Data processing method, device, electronic device and storage medium
By implementing the reorganization method of returned data in the DMA controller, the problems of data errors and low efficiency in PCI-e bus transmission are solved, and parallel reorganization and transmission of multiple types of data are realized, improving the efficiency and performance of data transmission.
Patent Information
- Application Number
- CN202111523062.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-13
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2041-12-13
AI Technical Summary
In the prior art, due to signal quality and external interference during the transmission of data on PCI-e bus, data errors, sharding, retransmission and other conditions may occur, resulting in low data transmission efficiency and poor performance, especially when the parallel transmission of multiple types of data is more obvious.
By implementing a data processing method in the DMA controller, it includes determining the corresponding read operation data packet and verification identification information based on the read return data, reading the return identification information of the return data, and recombining the return data based on the information to obtain the target data. This method can reduce the overflow and overwrite of read operations and realize parallel reorganization and transmission of multiple different types of data.
By reorganizing and transmitting various types of data read in parallel, the transmission pressure of overhead such as additional data type flag bits of the transmission data stream is reduced, transmission costs are saved, and data transmission efficiency and performance are improved.
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Figure CN114253718B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of network communication technology, and in particular to a data processing method, device, electronic device and storage medium. Background Art
[0002] The DMA (Direct Memory Access) controller is a key module in the PCI-e (PCI-Express, a universal bus specification) bus communication. It is a controller that connects the internal and external memories of the system. With the development of multi-core CPU (central processing unit) technology, the DMA data transmission performance and efficiency requirements between the system and peripherals through the PCI-e bus are higher. At the same time, with the development of technologies such as DPDK (Data Plane Development Kit) and virtualization, the original transmission data type has changed from a single format to a diversified type.
[0003] The PCI-e bus may cause data errors, fragmentation, and retransmissions due to signal quality and external interference. Therefore, when designing a DMA controller to receive data, it is necessary to reorganize and sort the data. If the data type is a single type, the data reorganization and sorting design is relatively easy to implement; if the data type is multiple types, the data reorganization and sorting design becomes complicated, resulting in low data transmission efficiency and poor performance. Summary of the invention
[0004] In view of this, an object of the embodiments of the present application is to provide a data processing method, device, electronic device and storage medium to improve the problem of low data transmission efficiency existing in the prior art.
[0005] In order to solve the above problems, in a first aspect, an embodiment of the present application provides a data processing method, including:
[0006] Determine a corresponding read operation data packet and verification identification information corresponding to the read operation data packet based on the read return data, wherein the return data is a data stream read in parallel;
[0007] Based on the verification identification information, reading the return identification information of the returned data;
[0008] The returned data is reorganized based on the returned identification information to obtain target data.
[0009] In the above implementation, by acquiring the read operation data packet and verification identification information of the data stream being read in parallel, the overflow when the read operation reads the return data and the coverage of the return data can be reduced based on the verification identification information. In the case of reducing the overflow of the parallel read operation, due to the various situations such as disordered fragments and disordered returns in the return data, it is necessary to reorganize the return data to obtain the target data, and then distribute the target data for subsequent processing. The return identification information returned by the return data to the processor can be read, and the return data stream can be reorganized based on the information contained in the return identification information to obtain the reorganized target data, so as to realize the parallel reorganization and transmission of multiple different types of data, reduce the transmission pressure of the overhead such as the additional data type flag bit of the transmission data stream, save the transmission cost, improve the efficiency of data transmission, and optimize the performance of data transmission.
[0010] Optionally, the return identification information includes a data type, a data sequence number, and a reorganization sequence number of the return data; and the reorganizing the return data based on the return identification information to obtain the target data includes:
[0011] Identifying a write status of the returned data;
[0012] Based on the data type and the write status, storing the returned data in a corresponding target partition;
[0013] Based on the data sequence number and the reorganization sequence number, determining whether the returned data is completely written into the target partition;
[0014] When the returned data is completely written into the target partition, complete identification information of the returned data is obtained;
[0015] The returned data is split based on the complete identification information and the data type to reorganize the returned data to obtain the corresponding target data.
[0016] In the above implementation, the return identification information of the return data returned to the processor includes the data type, data sequence number and reorganization sequence number of the return data. Based on the read data type, the return data is written, and the return data can be partitioned and stored. Based on the read data sequence number and reorganization sequence number, the integrity of the return data when it is written to the target partition is identified, and the write operation of the return data can be monitored, so that when the return data is completely written, the corresponding complete identification information is generated, and when it is detected that the return data has the corresponding complete identification information, the return data is shunted based on the complete identification information and the data type, and the return data is reorganized to obtain the reorganized target data, so that the target data is distributed and processed, and parallel processing of multiple types of target data is realized.
[0017] Optionally, judging whether the returned data is completely written into the target partition based on the data sequence number and the reorganization sequence number includes:
[0018] When the returned data is written into the target partition, determining the pre-state of the returned data based on the reorganized sequence number, and using the data sequence number as the write address of the pre-state;
[0019] Acquire a post-state after the returned data is written into the target partition;
[0020] Based on the pre-state and post-state, it is determined whether the returned data is completely written into the target partition, wherein when the pre-state is inconsistent with the post-state, the returned data is completely written into the target partition.
[0021] In the above implementation, when judging the integrity of the returned data when it is written into the target partition, the integrity can be judged based on the comparison between the pre-state when the returned data is written into the target partition and the post-state after the returned data is written into the target partition. The pre-state of the returned data is obtained by writing the reorganization sequence number, the written address is the data sequence number. When the pre-state is inconsistent with the post-state, the returned data stream is completely written into the target partition. It is possible to quickly and accurately judge whether the returned data is completely written into the target partition, providing a basis for the reorganization operation of the returned data.
[0022] Optionally, after determining the corresponding read operation data packet based on the read return data and the verification identification information corresponding to the read operation data packet, the method further includes:
[0023] Determine a storage address based on the verification identification information;
[0024] Based on the storage address, the return identification information of the returned data is saved in a corresponding read identification buffer area.
[0025] In the above implementation, after obtaining the return data packet and the corresponding verification identification information, since the types of return data read are large and can include multiple mixed data streams, in order to distinguish and identify the mixed data streams, the corresponding storage address can be determined by reading the verification identification information of the operation data packet, and the return identification information of the return data can be saved using the storage address as the address, and the return identification information is cached in the corresponding read identification buffer area, and the return identification information returned to the processor when the return data is read is cached, and the parallel read operations of multiple return data are distinguished and identified, thereby reducing the transmission pressure of the bus.
[0026] Optionally, the reading the return identification information of the returned data based on the verification identification information includes:
[0027] Extracting a read address based on the verification identification information;
[0028] Based on the read address, the read identification buffer area is read to obtain the corresponding return identification information.
[0029] In the above implementation, before the return data is reorganized, the verification identification information of the read operation data packet can be extracted to obtain the read address, and the read address is used as the read address to read the read identification buffer area to obtain the corresponding return identification information. Before the data is reorganized, the cached return identification information is read to obtain the corresponding return data and return identification information, providing a data source for the reorganization and diversion of the data.
[0030] Optionally, the determining a corresponding read operation data packet based on the read return data, and verification identification information corresponding to the read operation data packet, includes:
[0031] Obtaining a read request when reading the returned data;
[0032] Based on the read request, determining the read operation data packet corresponding to the returned data;
[0033] Based on the read request, the verification identification information corresponding to the read operation data packet is obtained.
[0034] In the above implementation, since the returned data is a data stream that is read in parallel, when a read operation is performed on the returned data, the read request when the returned data is read is obtained, and a read operation data packet of the bus transmission protocol of the extended bus standard corresponding to the returned data can be generated according to the read request. The verification identification information corresponding to the read operation data packet can also be obtained according to the number of read requests, wherein the verification identification information is identification information that is used continuously and cyclically, and is used to reduce overflow of parallel read operations.
[0035] Optionally, obtaining the verification identification information corresponding to the read operation data packet based on the read request includes:
[0036] Acquire initial verification identification information of the read operation data packet, wherein the initial verification identification information is used to determine whether the returned data is overwritten;
[0037] The initial verification identification information is updated based on the read request to obtain the verification identification information.
[0038] In the above implementation, when the bus signal quality of the extended bus standard is poor, the link layer may have a phenomenon of repeated retransmission during data transmission. Since the verification identification information is used cyclically, if the same verification identification information is used for a read operation when the previous verification identification information is not completely extracted, it will cause a read operation overflow. Therefore, by obtaining the initial verification identification information of the returned data, it is possible to judge whether the identification information is completely extracted on the basis of the initial verification identification information, thereby judging whether the returned data that has not been returned is read in advance, and judging whether the returned data will be overwritten in the reorganization operation, and updating the initial verification identification information based on the read request, and being able to reset the initial identification information to obtain the verification identification information, effectively reducing the read operation overflow and the repetition of the returned data being overwritten, and improving the accuracy of data transmission.
[0039] In a second aspect, an embodiment of the present application further provides a data processing device, the device comprising:
[0040] A parallel module, used to determine a corresponding read operation data packet and verification identification information corresponding to the read operation data packet based on the read return data, wherein the return data is a data stream read in parallel;
[0041] A reading module, used for reading the return identification information of the returned data based on the verification identification information;
[0042] The reorganization module is used to reorganize the returned data based on the returned identification information to obtain target data.
[0043] In the above implementation, one or more returned data are read in parallel by a parallel module, and the read operation data packet and verification identification information corresponding to the returned data are obtained, so as to reduce the overflow and coverage of the returned data when the read operation reads the returned data; the reading module is used to read based on the verification identification information to obtain the return identification information of the returned data; because there may be various situations such as disordered fragments and disordered returns in the returned data, the reorganization module is used to shunt and reorganize the returned data based on the return identification information to obtain the target data for distribution processing. It is possible to reorganize and transmit multiple different types of data in parallel, reduce the transmission pressure of the additional data type flag bit and other overheads of the transmission data stream, save transmission costs, improve the efficiency of data transmission, and optimize the performance of data transmission.
[0044] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores program instructions, and when the processor reads and runs the program instructions, it executes the steps in any implementation of the above-mentioned data processing method.
[0045] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer program instructions, and when the computer program instructions are read and executed by a processor, the steps in any implementation of the above-mentioned data processing method are executed.
[0046] In summary, the present application provides a data processing method, device, electronic device and storage medium, which can read multiple mixed return data streams in parallel, and reorganize the data streams according to the return identification information returned to the processor by the read data streams to obtain the target data after diversion, so as to reorganize and transmit multiple different types of data in parallel, reduce the transmission pressure of the additional data type flag bits and other overhead of the transmission data stream, save transmission costs, improve the efficiency of data transmission, and optimize the performance of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0048] Figure 1 A flowchart of a data processing method provided in an embodiment of the present application;
[0049] Figure 2 A detailed flow chart of step S3 provided in an embodiment of the present application;
[0050] Figure 3 A detailed flowchart of step S33 provided in an embodiment of the present application;
[0051] Figure 4 A flowchart of another data processing method provided in an embodiment of the present application;
[0052] Figure 5 A detailed flow chart of step S2 provided in an embodiment of the present application;
[0053] Figure 6 A detailed flow chart of step S1 provided in an embodiment of the present application;
[0054] Figure 7 A detailed flow chart of step S13 provided in an embodiment of the present application;
[0055] Figure 8 A schematic diagram of the module structure of a data processing device provided in an embodiment of the present application.
[0056] Icons: 400 - data processing device; 410 - parallel module; 420 - reading module; 430 - reorganization module. DETAILED DESCRIPTION
[0057] The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.
[0058] A DMA (Direct Memory Access) controller needs to support a variety of different data operations or data stream transmissions, such as Ethernet message transmission, various encrypted and decrypted data, compressed and decompressed data, AI (Artificial Intelligence) operation data, etc. In order to support multiple types of data operations in a DMA controller, the existing design technology is to add a data type field to the header of the data stream to identify and classify operations, occupying the transmission bandwidth of the data stream.
[0059] In some existing DMA controller design schemes, in order to handle data access of many AHB (Advanced High Performance Bus) slave devices, multiple DMA controllers need to be designed to handle AHB slave devices in a classified manner. Multiple DMA controllers are handled by request arbitration, design priority, interrupt response, etc. Once one DMA controller obtains control, it takes over the bus and releases the bus after completing data transmission.
[0060] In the prior art, DMA data access for each service is usually handled exclusively, relying on priority response requests, and using interrupts to notify the CPU (central processing unit) to respond to DMA data processing. Data access for each DMA channel is performed in a serial manner, and each DMA channel needs to design its own data buffer area to independently receive data from its own channel. Each DMA is responsible for its own type of data message, and cannot be processed uniformly. When there are many types of data, the data of mixed traffic cannot be effectively reorganized, resulting in low data transmission efficiency and poor performance.
[0061] Therefore, an embodiment of the present application provides a data processing method applied to a DMA controller. The DMA controller can be set in an electronic device with logical computing functions such as a server, a personal computer (PC), a tablet computer, a smart phone, a personal digital assistant (PDA), etc., and can perform parallel processing and effective reorganization of multiple mixed return data streams to obtain target data that can be distributed and processed.
[0062] Optionally, the electronic device may include a memory, a storage controller, a processor, a peripheral interface, an input / output unit, etc. The components and structure of the electronic device may be arranged according to actual conditions.
[0063] The above-mentioned memory, storage controller, processor, peripheral interface, input and output unit components are directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The above-mentioned processor is used to execute the executable module stored in the memory.
[0064] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory is used to store programs, and the processor executes the program after receiving the execution instruction. The method executed by the electronic device defined by the process disclosed in any embodiment of the present application can be applied to the processor or implemented by the processor.
[0065] The above-mentioned processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a CPU, a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0066] The above-mentioned peripheral interface couples various input / output devices to the processor and the memory. In some embodiments, the peripheral interface, the processor and the memory controller can be implemented in a single chip. In some other examples, they can be implemented by separate chips respectively.
[0067] The electronic device in this embodiment can be used to execute each step in each data processing method provided in the embodiment of the present application. The implementation process of the data processing method is described in detail below through several embodiments.
[0068] See also Figure 1 , Figure 1 A flowchart of a data processing method provided in an embodiment of the present application, the method may include the following steps:
[0069] Step S1, determining a corresponding read operation data packet and verification identification information corresponding to the read operation data packet based on the read return data.
[0070] Among them, the return data is a data stream that is read in parallel. When reading the return data, DMA read operations can be applied to multiple return data at the same time to read multiple mixed types of data streams in parallel, thereby improving the processing efficiency of the data stream. When reading the return data, a read operation data packet of the bus transmission protocol of the corresponding expansion bus standard can be generated, that is, the verification identification information in the PCI-e MRd TLP (Transaction Layer Packet) read operation data packet.
[0071] Optionally, the verification identification information can be defined as 8-bit wide data, and the verification identification information is identification information that can be used continuously and cyclically. Each time a read operation data packet is generated, the next continuous verification identification information is allocated to the read operation data packet. The TAG value of the verification identification information can be set to 32 or 64 for cyclic use to reduce the overflow of parallel read operations.
[0072] Optionally, when performing a read operation on the returned data, the read operation on the returned data may be read separately according to the data type of the returned data, the sequence number of the read operation, etc., so as to implement a parallel read operation of mixed-type data streams.
[0073] Step S2: based on the verification identification information, read the return identification information of the returned data.
[0074] According to the obtained verification identification information, the return identification information of the return data returned to the processor is read to obtain the relevant data of the return data, and on this basis, the reorganization operation of the return data is implemented.
[0075] Optionally, the return identification information includes multiple data such as data type, data sequence number (read seq number) and restructure number (restruct number). The definition format of the return identification information can be: data type [7: 0], read seq number [n: 0] and restructure number [m: 0], etc. Among them, the data type is used to classify the data stream type of the returned data. The data type can classify and determine the data stream types of 256 returned data at the same time; the data sequence number can be used as the cache base address of the returned data and number the returned data. The size of the data sequence number can be determined according to the size of the cache area; the restructure number is used to detect the restructure operation of the returned data. The restructure number can be updated with the cycle of the verification identification information. When the verification identification information is circulated, the restructure number can be correspondingly increased by 1. The restructure number can be set to 16 cycles, and then updated accordingly, that is, m is set to 3. The m value and the update cycle can also be modified and adjusted.
[0076] Step S3, reorganizing the returned data based on the returned identification information to obtain target data.
[0077] Among them, since there may be various situations such as fragmentation and disordered return in the returned data, when the CPU responds to the read operation, it can reorganize the returned data based on the obtained return identification information to reduce the situations of fragmentation and disordered return. The reorganization of the returned data can be achieved without adding the identification of the data type operation, which will not increase the data transmission pressure and transmission bandwidth overhead, and realize efficient data transmission between the data stream and the multi-core CPU.
[0078] exist Figure 1 In the illustrated embodiment, a plurality of different types of data can be reorganized and transmitted in parallel, reducing the transmission pressure of overhead such as additional data type flag bits of the transmission data stream, saving transmission costs, improving data transmission efficiency, and optimizing data transmission performance.
[0079] Optionally, see Figure 2 , Figure 2 A detailed flow chart of step S3 is provided in an embodiment of the present application. Step S3 may also include steps S31-S35.
[0080] Step S31, identifying the writing status of the returned data.
[0081] When the read return data is reorganized, the write status of the received return data can be identified to obtain the write status of the return data.
[0082] For example, when the return data is written, for different types of return data, the write address of each type of return data can be obtained using the mode of waddr=read seq number+lower Address, where lowerAddress is the lower address included in the completion data packet when writing is completed.
[0083] Step S32: based on the data type and the write status, store the returned data into the corresponding target partition.
[0084] Among them, according to the recognized write status of the received return data, based on the data type of the return data, the return data can be partitioned and stored in the corresponding target partition to distinguish and store multiple different types of mixed data streams.
[0085] Step S33: Based on the data sequence number and the reorganization sequence number, determine whether the returned data is completely written into the target partition.
[0086] The data sequence number and the reorganization sequence number can be used to judge the writing integrity of the returned data when it is written into the target partition, and the writing operation of the returned data can be monitored.
[0087] Step S34, when the returned data is completely written into the target partition, complete identification information of the returned data is obtained.
[0088] When it is determined that the returned data is completely written into the target partition, complete identification information representing that the returned data is completely written is generated to provide feedback that the writing status of the returned data is a complete writing operation.
[0089] Step S35: split the returned data based on the complete identification information and the data type to reorganize the returned data to obtain the corresponding target data.
[0090] Among them, when it is detected that the returned data has corresponding complete identification information, the returned data can be reorganized based on the complete identification information, and the returned data can be diverted based on the data type of the returned data to achieve reorganization of the returned data and obtain one or more reorganized target data.
[0091] It is worth noting that when the return data is diverted, the return data can be divided into multiple target data for different processing according to the data type, and the target data can also be distributed to the corresponding actual processing modules for processing, so as to process multiple types of data streams separately in parallel.
[0092] exist Figure 2 In the illustrated embodiment, the return data may be split and reassembled based on the data type, data sequence number and reassembly sequence number to obtain corresponding target data.
[0093] Optionally, see Figure 3 , Figure 3 A detailed flowchart of step S33 is provided for an embodiment of the present application. Step S33 may also include steps S331-S333.
[0094] Step S331, when the returned data is written into the target partition, the pre-state of the returned data is determined based on the reorganized sequence number, and the data sequence number is used as the write address of the pre-state.
[0095] When judging the integrity of the returned data when it is written into the target partition, the previous state of the returned data can be obtained before the returned data is written into the target area. The write operation, write address and other states of the returned data are identified, and when the returned data is written into the target area, the reorganized sequence number of the returned data is written into the previous state, and the data sequence number is written as the reorganized sequence number into the write address of the previous state to obtain the corresponding previous state.
[0096] Step S332, obtaining a post-state after the returned data is written into the target partition.
[0097] After the returned data is written into the target partition, the post-state of the returned data after writing into the target partition can be obtained based on the write operation, write address and other states of the returned data and the data stream written into the target partition.
[0098] Step S333: Based on the pre-state and post-state, determine whether the returned data is completely written into the target partition.
[0099] Among them, by comparing the obtained pre-state and post-state, it is possible to determine whether the returned data is completely written into the target partition. When the pre-state is inconsistent with the post-state, the returned data is completely written into the target partition. When the pre-state is consistent with the post-state, the returned data is not completely written into the target partition. Based on monitoring and comparing the pre-state of the return data stream writing state and the post-state after the data stream is written, the difficulty of data reorganization operation can be reduced, and it can also support the reorganization of multiple different types of mixed data.
[0100] Optionally, since there are multiple return data, or the return data includes multiple mixed data streams, a pre-state table and a post-state table can also be set up, and the obtained multiple pre-states and the corresponding multiple post-states are respectively added to the corresponding pre-state table and post-state table, so as to compare each pre-state and the corresponding post-state in the two tables, thereby improving the targetedness and accuracy of the comparison. In addition, in the two tables, the multiple pre-states can be compared with the corresponding post-states in sequence according to the sequence order of the data serial numbers of the multiple return data, thereby improving the orderliness of the comparison.
[0101] It is worth noting that after judging whether the returned data is completely written into the target partition, the multiple post-states in the post-state table can be updated, and the post-state can be updated with the corresponding multiple pre-states in the pre-state table to unify the pre-state table and the post-state table. It is possible to obtain whether the output of the returned data is completed from the two tables. When the pre-state table and the post-state table are consistent, the output of the returned data is completed, and the reorganization operation can be performed, which improves the efficiency and accuracy of obtaining the output state of the returned data.
[0102] exist Figure 3 In the illustrated embodiment, it is possible to quickly and accurately monitor and judge whether the returned data is completely written into the target partition, thereby providing a basis for the reorganization operation of the returned data.
[0103] Optionally, see Figure 4 , Figure 4A flowchart of another data processing method provided in an embodiment of the present application. After step S1, the method may further include steps Sa-Sb.
[0104] Step Sa, determining a storage address based on the verification identification information.
[0105] Among them, after obtaining the return data packet and the corresponding verification identification information, since the types of returned data read are large and can include multiple mixed data streams, in order to distinguish and identify the mixed data streams, when it is detected that the read operation generates a corresponding read operation data packet, the verification identification information corresponding to the read operation data packet can be used as the corresponding storage address.
[0106] Step Sb: based on the storage address, save the return identification information of the returned data to the corresponding read identification buffer area.
[0107] Among them, based on the obtained holding address, the return data can be returned to the processor, and the return identification information that identifies the read operation type can be cached to save it in the corresponding read identification buffer area. The read operation of the mixed data stream can be distinguished and identified by reading the return identification information in the identification buffer area, effectively reducing the bus transmission overhead of the extended bus standard.
[0108] Optionally, the returned identification information may include various data such as the data type of the returned data, a data sequence number, and a reassembly sequence number.
[0109] exist Figure 4 In the illustrated embodiment, the return identification information returned to the processor when the return data is read can be cached, and the parallel read operations of multiple return data can be distinguished and identified, thereby reducing the transmission pressure of the bus.
[0110] Optionally, see Figure 5 , Figure 5 A detailed flow chart of step S2 is provided in an embodiment of the present application. Step S2 may also include steps S21-S22.
[0111] Step S21, extracting a read address based on the verification identification information.
[0112] Before the returned data needs to be reorganized, the TAG value in the verification identification information of the read operation data packet can be extracted to obtain the read address, and the read address is used as the read address.
[0113] Step S22: based on the read address, read the read identification buffer area to obtain the corresponding return identification information.
[0114] Among them, reading is performed in the read identification buffer area based on the read address, and the return identification information cached in the read identification buffer area can be read to obtain various data such as the data type, data sequence number and reorganization sequence number of the returned data to support the reorganization operations of various types of complex data.
[0115] exist Figure 5 In the illustrated embodiment, the cached return identification information can be read before data reorganization to obtain corresponding return data and return identification information, thereby providing a data source for data reorganization and diversion.
[0116] Optionally, see Figure 6 , Figure 6 A detailed flowchart of step S1 is provided in an embodiment of the present application. Step S1 may also include steps S11-S13.
[0117] Step S11, obtaining a read request when reading the returned data.
[0118] When performing parallel read operations on the returned data, in order to obtain the corresponding read data packet and verification identification information, a read request for reading the returned data can be obtained, and the returned data can be read in parallel based on the read request, thereby improving the efficiency of the data read operation.
[0119] Step S12: determining the read operation data packet corresponding to the returned data based on the read request.
[0120] When a read request for returned data is detected, a read operation data packet corresponding to the returned data can be generated, and the read operation data packet includes relevant data when performing a read operation in a bus transmission protocol of the extended bus standard.
[0121] Step S13: based on the read request, obtaining the verification identification information corresponding to the read operation data packet.
[0122] After the corresponding read operation data packet is obtained, based on the read request, the verification identification information corresponding to the read operation data packet may also be obtained.
[0123] exist Figure 6 In the illustrated embodiment, it is possible to perform a parallel read operation on return data of multiple mixed data types, so as to obtain corresponding read operation data packets and verification identification information according to the read operation.
[0124] Optionally, see Figure 7 , Figure 7 A detailed flowchart diagram of step S13 is provided in an embodiment of the present application. Step S13 may also include steps S131-S132.
[0125] Step S131, obtaining initial verification identification information of the read operation data packet.
[0126] Among them, when the bus signal quality of the extended bus standard is poor, the link layer may have repeated retransmissions during data transmission. Since the verification identification information is used cyclically, if the same verification identification information is used for a read operation when the previous verification identification information is not completely extracted, it will cause a read operation overflow. In order to reduce the overflow of the read operation, the initial verification identification information of the read operation data packet can be obtained online. The initial verification identification information is used to determine whether the returned data is overwritten, and the judgment process may include: the initial verification identification information can determine whether the identification information is completely extracted, thereby determining whether the unreturned return data is read in advance, so as to determine whether the return data will be overwritten in the reorganization operation.
[0127] Step S132: updating the initial verification identification information based on the read request to obtain the verification identification information.
[0128] In order to reduce the situation where the returned data is overwritten during the reorganization and sorting due to overflow of the read operation, the update can be performed based on the initial verification identification information. Since the read request can include multiple request times, the TAG value of the initial verification identification information can be reset based on the request times to obtain the verification identification information, which can effectively reduce the duplication of data transmission.
[0129] Optionally, after the verification identification information is acquired, the verification identification information may also be fed back to the DMA of the parallel read operation to determine whether to use the verification identification information to re-match the corresponding read operation data packet.
[0130] exist Figure 7 In the illustrated embodiment, the initial verification identification information is updated based on the read request, and the initial identification information can be reset to obtain the verification identification information, which effectively reduces the read operation overflow and the duplication of the returned data being overwritten, and improves the accuracy of data transmission.
[0131] See also Figure 8 , Figure 8 A schematic diagram of a module structure of a data processing device provided in an embodiment of the present application, the data processing device 400 may include:
[0132] A parallel module 410 is used to determine a corresponding read operation data packet and verification identification information corresponding to the read operation data packet based on the read return data, wherein the return data is a data stream read in parallel;
[0133] A reading module 420, configured to read the return identification information of the returned data based on the verification identification information;
[0134] The reorganization module 430 is used to reorganize the returned data based on the returned identification information to obtain target data.
[0135] In an optional implementation, the reorganization module 430 may further include a partition storage submodule, a judgment submodule and a diversion submodule;
[0136] A partition storage submodule, used for identifying the write status of the returned data; based on the data type and the write status, storing the returned data in a corresponding target partition;
[0137] A judgment submodule, configured to judge whether the returned data is completely written into the target partition based on the data sequence number and the reorganization sequence number; and obtain complete identification information of the returned data when the returned data is completely written into the target partition;
[0138] The shunting submodule is used to shunt the return data based on the complete identification information and the data type, so as to reorganize the return data to obtain the corresponding target data.
[0139] In an optional implementation, the judgment submodule may further include a pre-unit, a post-unit and a comparison unit;
[0140] a pre-stage unit, configured to determine a pre-stage state of the returned data based on the reorganized sequence number when the returned data is written into the target partition, and use the data sequence number as a write address of the pre-stage state;
[0141] A post-unit, used for obtaining a post-state after the returned data is written into the target partition;
[0142] A comparison unit is used to determine whether the returned data is completely written into the target partition based on the pre-state and the post-state, wherein when the pre-state is inconsistent with the post-state, the returned data is completely written into the target partition.
[0143] In an optional implementation, the data processing device 400 may further include a cache module for determining a storage address based on the verification identification information; and based on the storage address, saving the return identification information of the returned data to a corresponding read identification buffer area.
[0144] In an optional implementation, the reading module 420 may further include an extraction submodule and a reading submodule;
[0145] An extraction submodule, used for extracting a read address based on the verification identification information;
[0146] The reading submodule is used to read the reading identification buffer area based on the reading address to obtain the corresponding return identification information.
[0147] In an optional implementation, the parallel module 410 may further include a request submodule and a read operation submodule;
[0148] A request submodule, used for obtaining a read request when reading the returned data;
[0149] The read operation submodule is used to determine the read operation data packet corresponding to the returned data based on the read request; and obtain the verification identification information corresponding to the read operation data packet based on the read request.
[0150] In an optional implementation, the read operation submodule further includes an initial unit and an update unit;
[0151] An initial unit, used for obtaining initial verification identification information of the read operation data packet, wherein the initial verification identification information is used for determining whether the returned data is overwritten;
[0152] An updating unit is used to update the initial verification identification information based on a read request to obtain the verification identification information.
[0153] Since the principle of solving the problem by the device in the embodiment of the present application is similar to that of the embodiment of the aforementioned data processing method, the implementation of the data processing device 400 in this embodiment can refer to the description in the embodiment of the aforementioned data processing method, and the repeated parts will not be repeated.
[0154] An embodiment of the present application also provides an electronic device, which includes a memory and a processor, wherein the memory stores program instructions, and when the processor reads and runs the program instructions, it executes the steps of any one of the data processing methods provided in this embodiment.
[0155] It should be understood that the electronic device may be a personal computer, a tablet computer, a smart phone, a personal digital assistant, or other electronic device with logic computing capabilities.
[0156] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer program instructions. When the computer program instructions are read and executed by a processor, the steps of any one of the data processing methods provided in the embodiment are executed.
[0157] In summary, the embodiments of the present application provide a data processing method, device, electronic device and storage medium, which can read multiple mixed return data streams in parallel, and reorganize the data streams according to the return identification information returned to the processor by the read data streams to obtain the target data after diversion, so as to reorganize and transmit multiple different types of data in parallel, reduce the transmission pressure of the additional data type flag bits and other overhead of the transmission data stream, save transmission costs, improve the efficiency of data transmission, and optimize the performance of data transmission.
[0158] In several embodiments provided in the present application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely schematic, for example, the block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices according to the multiple embodiments of the present application. In this regard, each box in the block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram, and the combination of the block diagrams, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.
[0159] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
[0160] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Therefore, this embodiment also provides a computer program instruction stored in a readable storage medium, and when the computer program instruction is read and executed by a processor, the steps in any method described in the block data storage method are executed. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RanDom Access Memory), disk or optical disk and other media that can store program codes.
[0161] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.
[0162] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
[0163] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
Claims
1. A data processing method, characterized in that: include: Determine a corresponding read operation data packet and verification identification information corresponding to the read operation data packet based on the read return data, wherein the return data is a data stream read in parallel; Based on the verification identification information, reading the return identification information of the returned data; Reorganize the returned data based on the returned identification information to obtain target data; The return identification information includes the data type, data sequence number and reorganization sequence number of the return data; the data sequence number includes a number determined according to the size of the buffer area of the return data, and the reorganization sequence number includes a sequence number updated based on the cycle of the verification identification information; the reorganization of the return data based on the return identification information to obtain the target data includes: identifying the write status of the return data; based on the data type and the write status, storing the return data in the corresponding target partition; based on the data sequence number and the reorganization sequence number, judging whether the return data is completely written to the target partition; when the return data is completely written to the target partition, obtaining the complete identification information of the return data; shunting the return data based on the complete identification information and the data type to reorganize the return data to obtain the corresponding target data; The method of judging whether the returned data is completely written into the target partition based on the data sequence number and the reorganization sequence number comprises: when the returned data is written into the target partition, determining a pre-state of the returned data based on the reorganization sequence number, and using the data sequence number as a write address of the pre-state; obtaining a post-state after the returned data is written into the target partition; judging whether the returned data is completely written into the target partition based on the pre-state and the post-state, wherein when the pre-state is inconsistent with the post-state, the returned data is completely written into the target partition.
2. The method according to claim 1, characterized in that After determining the corresponding read operation data packet based on the read return data and the verification identification information corresponding to the read operation data packet, the method further includes: Determine a storage address based on the verification identification information; Based on the storage address, the return identification information of the returned data is saved in a corresponding read identification buffer area.
3. The method according to claim 2, characterized in that The step of reading the return identification information of the returned data based on the verification identification information includes: Extracting a read address based on the verification identification information; Based on the read address, the read identification buffer area is read to obtain the corresponding return identification information.
4. The method according to claim 1, characterized in that: The determining of the corresponding read operation data packet based on the read return data, and the verification identification information corresponding to the read operation data packet, includes: Obtaining a read request when reading the returned data; Based on the read request, determining the read operation data packet corresponding to the returned data; Based on the read request, the verification identification information corresponding to the read operation data packet is obtained.
5. The method according to claim 4, characterized in that The obtaining, based on the read request, the verification identification information corresponding to the read operation data packet includes: Acquire initial verification identification information of the read operation data packet, wherein the initial verification identification information is used to determine whether the returned data is overwritten; The initial verification identification information is updated based on the read request to obtain the verification identification information.
6. A data processing device, characterized in that: The device comprises: A parallel module, used to determine a corresponding read operation data packet and verification identification information corresponding to the read operation data packet based on the read return data, wherein the return data is a data stream read in parallel; A reading module, used for reading the return identification information of the returned data based on the verification identification information; A reorganization module, used for reorganizing the returned data based on the returned identification information to obtain target data; Wherein, the return identification information includes the data type, data sequence number and reorganization sequence number of the return data; the data sequence number includes a number determined according to the size of the buffer area of the return data, and the reorganization sequence number includes a sequence number updated based on the cycle of the verification identification information; the reorganization module includes a partition storage submodule, a judgment submodule and a shunt submodule; the partition storage submodule is used to identify the write status of the return data; based on the data type and the write status, the return data is stored in the corresponding target partition; the judgment submodule is used to judge whether the return data is completely written to the target partition based on the data sequence number and the reorganization sequence number; when the return data is completely written to the target partition, the complete identification information of the return data is obtained; the shunt submodule is used to shunt the return data based on the complete identification information and the data type, so as to reorganize the return data and obtain the corresponding target data; The judgment submodule includes a pre-unit, a post-unit and a comparison unit; the pre-unit is used to determine the pre-state of the returned data based on the reorganized sequence number when the returned data is written into the target partition, and use the data sequence number as the write address of the pre-state; the post-unit is used to obtain the post-state of the returned data after writing into the target partition; the comparison unit is used to judge whether the returned data is completely written into the target partition based on the pre-state and the post-state, wherein when the pre-state is inconsistent with the post-state, the returned data is completely written into the target partition.
7. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores program instructions, and when the processor runs the program instructions, the steps in the method according to any one of claims 1 to 5 are executed.
8. A computer-readable storage medium, characterized in that: The readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the steps in the method according to any one of claims 1 to 5 are executed.
Citation Information
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