A method and apparatus for generating a register translation level file list file

Abstract

The application provides a method, system, device and storage medium for generating a register transfer level file list file, the method comprising: inputting a specific path of an application specific integrated circuit register transfer level file list file to import the application specific integrated circuit register transfer level file list file; comparing modules in the application specific integrated circuit register transfer level file list file with register transfer level circuit models in a feature module library to identify types of the modules in the application specific integrated circuit register transfer level file list file; in response to receiving clipping information input by a user, clipping a corresponding module type according to the clipping information and modifying a file list path; performing format conversion on the modified file list path and outputting a register transfer level file list file of an FPGA prototype according to the converted path. The application improves the work efficiency of generating a register transfer level file list file through automatic clipping and replacement.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of application specific integrated circuits, and more particularly, to a method, system, device and storage medium for generating a register transfer level file list file. BACKGROUND

[0002] FPGA(Field Programmable Gate Array, i.e. field programmable gate array) prototype is indispensable in ASIC(Application Specific Integrated Circuit, i.e. application specific integrated circuit) design and verification. Before the ASIC is manufactured, a lot of effort is spent on the verification work of the RTL(Register Transfer Level, i.e. register transfer level) code; in addition, the development of software also needs to start before the ASIC is back to the piece, and both of these two aspects of work need to use the FPGA prototype to provide a verification platform to simulate the behavior of the ASIC, to help hardware developers and software developers to improve the work efficiency.

[0003] Compared with front-end simulation or hardware simulation accelerator simulation, FPGA prototype verification has the following advantages: 1, the running speed of FPGA is closer to the real ASIC chip, which can cooperate with the software developer to develop the underlying software; 2, in addition to being able to develop software in advance, from the time cost, FPGA prototype can quickly build a hardware verification environment; 3, FPGA prototype can be easily connected to real interface peripherals, such as UART interface peripherals, I2C interface peripherals, QSPI Flash interface peripherals, JTAG interface peripherals, etc. commonly used in ASIC, which facilitates the function test and verification before the chip is manufactured.

[0004] Of course, as a substitute for ASIC, FPGA prototype also has many limitations, such as size limit, speed limit, power limit, structure limit, etc. The physical structure of ASIC and FPGA is different, ASIC is based on standard cell library, while FPGA is based on vendor-provided macro cell module (lookup table and flip-flop), which leads to that if FPGA prototype verification is to be performed, the ASIC code must be converted to be able to be transplanted to FPGA. This conversion is only a code level conversion, which replaces part of the code in ASIC with what can be implemented by FPGA, without changing the original function.

[0005] The RTL code file paths for ASIC designs are uniformly managed by the RTL file list file. All additions, deletions, and replacements of RTL module code files during the design process are synchronized to the RTL file list file. With the RTL file list file, ASIC designers can create an ASIC design project within their design tools. A unified RTL file list file is crucial for ASIC design and verification that requires team collaboration. An RTL file list file is indispensable for porting an ASIC design to an FPGA prototype. Currently, modifying the RTL file list file used to generate FPGA prototypes is labor-intensive and inefficient. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a method, system, computer device, and computer-readable storage medium for generating a register translation level file list. This invention automatically identifies and classifies RTL modules by reading the RTL file list of the ASIC, and can automatically perform RTL module trimming and replacement operations based on the identification results, thereby improving the efficiency of porting ASIC designs to FPGA prototypes.

[0007] To achieve the above objectives, one aspect of the present invention provides a method for generating a register translation level file list, comprising the following steps: inputting a specific path to an application-specific integrated circuit (ASIC) register translation level file list to import the ASIC register translation level file list; comparing the modules in the ASIC register translation level file list with register translation level circuit models in a feature module library to identify the type of each module in the ASIC register translation level file list; responding to receiving clipping information input by a user, clipping the corresponding module type according to the clipping information and modifying the file list path; and converting the format of the modified file list path and outputting the register translation level file list of the FPGA prototype according to the converted path.

[0008] In some implementations, modifying the file list paths includes: adding the file paths of the DUMMYRTL module and the FPGA IP module to the file list; adding the file path of the FPGA bidirectional I / O port control logic module to the file list; and adding the file path of the FPGA global clock with an enable pin to the file list.

[0009] In some implementations, the process of converting the modified file list path to a format includes converting the modified file list path to a file path in the syntax of a tool command language.

[0010] In some embodiments, the cutting module is configured to read type information in the cutting information, cut corresponding modules in the application specific integrated circuit register transfer level file list file according to the type information, and save a temporary file list copy.

[0011] In another aspect of the embodiments of the present application, a system for generating a register transfer level file list file is provided, which includes an input module configured to input a specific path of an application specific integrated circuit register transfer level file list file to import the application specific integrated circuit register transfer level file list file; a classification module configured to compare modules in the application specific integrated circuit register transfer level file list file with register transfer level circuit models in a feature module library to identify types of the modules in the application specific integrated circuit register transfer level file list file; a cutting module configured to cut corresponding module types according to cutting information received in response to a user input, and modify a file list path; and an output module configured to format convert the modified file list path, and output a register transfer level file list file of an FPGA prototype according to the converted path.

[0012] In some embodiments, the cutting module is configured to add file paths of DUMMY RTL modules and FPGA IP modules in the file list, add file paths of FPGA bidirectional IO port control logic modules in the file list, and add file paths of global clocks with enable terminals of FPGAs in the file list.

[0013] In some embodiments, the output module is configured to convert the modified file list path into a file path in a tool command language syntax.

[0014] In some embodiments, the cutting module is configured to read type information in the cutting information, cut corresponding modules in the application specific integrated circuit register transfer level file list file according to the type information, and save a temporary file list copy.

[0015] In yet another aspect of the embodiments of the present application, a computer device is provided, which includes at least one processor, and a memory storing computer instructions executable on the processor, which, when executed by the processor, implement steps of the above method.

[0016] In still another aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores a computer program executable by a processor to implement steps of the above method.

[0017] The application has the following beneficial technical effects: by reading the RTL file list file of the ASIC, the identification and classification of the RTL module are automatically performed, and the cutting and replacing operations of the RTL module can be automatically performed according to the identification result, thereby improving the work efficiency of the ASIC design to FPGA prototype transplantation. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained without creative labor on the basis of these drawings.

[0019] Figure 1 The schematic diagram of the embodiment of the method for generating the register transfer level file list file provided by the present application is shown.

[0020] Figure 2 The schematic diagram of the method for generating the register transfer level file list file provided by the present application is shown.

[0021] Figure 3 The schematic diagram of the embodiment of the system for generating the register transfer level file list file provided by the present application is shown.

[0022] Figure 4 The schematic diagram of the hardware structure of the embodiment of the computer device for generating the register transfer level file list file provided by the present application is shown.

[0023] Figure 5 The schematic diagram of the embodiment of the computer storage medium for generating the register transfer level file list file provided by the present application is shown. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will be further described in detail with specific embodiments and with reference to the drawings.

[0025] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same name different entities or different parameters, and it can be seen that "first" and "second" are only for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0026] The first aspect of the embodiments of the present application provides an embodiment of a method for generating a register transfer level file list file. Figure 1 The schematic diagram of the embodiment of the method for generating the register transfer level file list file provided by the present application is shown. As shown in the figure, Figure 1As shown, the embodiment of the present application comprises the following steps:

[0027] S1, input the specific path of the application specific integrated circuit register transfer level file list file to import the application specific integrated circuit register transfer level file list file;

[0028] S2, compare the modules in the application specific integrated circuit register transfer level file list file with the register transfer level circuit model in the feature module library to identify the type of each module in the application specific integrated circuit register transfer level file list file;

[0029] S3, in response to receiving the user inputted clipping information, clip the corresponding module type according to the clipping information, and modify the file list path; and

[0030] S4, format convert the modified file list path, and output the register transfer level file list file of the FPGA prototype according to the converted path.

[0031] ASIC, namely application specific integrated circuit, refers to an integrated circuit designed and manufactured according to the requirements of a specific user and the needs of a specific electronic system. FPGA prototype verification: a kind of ASIC verification method based on FPGA, which generally verifies the functions of ASIC as much as possible on the FPGA prototype before the ASIC flow sheet after the completion of the front-end RTL design and RTL simulation stage. File list: refers to the list of paths where all VHDL / Verilog HDL design files are located in an ASIC design. The design tool completes the construction of the entire design by reading the file list.

[0032] Figure 2 The architecture diagram for generating the register transfer level file list file is provided in the present application. In combination with Figure 2 The embodiment of the present application is described.

[0033] The specific path of the application specific integrated circuit register transfer level file list file is inputted to import the application specific integrated circuit register transfer level file list file. The FPGA prototype RTL file list file automatic generation script program (hereinafter referred to as automatic generation script program) is written by using Python language, and the RTL file list file of the ASIC is processed in an automatic manner. The feature module library is designed in the automatic generation script program, and the corresponding RTL circuit model is stored for each typical RTL module. The RTL circuit model can be added, deleted and maintained according to the actual needs of the project. Open the automatic generation script program, input the specific path of the ASIC RTL file list file, and import the ASIC RTL file list file.

[0034] The modules in the ASIC register transfer level file list file are compared with the register transfer level circuit models in the feature module library to identify the types of the modules in the ASIC register transfer level file list file. A module identification engine in the automatically generated script program compares the modules contained in the ASIC RTL file list file with the RTL circuit models in the feature module library to classify each module in the list and record the classification information.

[0035] In response to receiving the user inputted pruning information, the corresponding module type is pruned according to the pruning information, and the file list path is modified. A module pruning engine in the automatically generated script program prompts the user to select the modules to be pruned according to the classification information identified by the module identification engine.

[0036] In some embodiments, the modification of the file list path includes adding the file paths of the DUMMY RTL module and the FPGA IP module in the file list, adding the file path of the FPGA bidirectional IO port control logic module in the file list, and adding the file path of the FPGA global clock with an enable end in the file list. The automatically generated script program simultaneously calls the DUMMY RTL replacement module, the FPGA IP replacement module, the IO PAD replacement module, and the gated clock replacement module. The DUMMY RTL replacement module is called to add the file path of the DUMMY RTL module in the file list. The FPGA IP replacement module is called to add the file path of the FPGA IP module in the file list. The IO PAD replacement module is called to add the file path of the FPGA bidirectional IO port control logic module in the file list. The gated clock replacement module is called to add the file path of the FPGA global clock with an enable end in the file list.

[0037] DUMMY RTL module: refers to removing the functional logic blocks in a module in the RTL design, only keeping the input and output ports of the module, all input ports are suspended, and all output ports are set according to actual requirements. PLL: Phase Locked Loop, that is, a phase-locked loop, which is a feedback control circuit. The characteristics of the phase-locked loop are: using the reference signal input from outside, controlling the frequency and phase of the oscillation signal inside the loop. Because the phase-locked loop can realize automatic tracking of the output signal frequency to the input signal frequency, the phase-locked loop is usually used in closed-loop tracking circuits. IO PAD: an ASIC pin processing module, that is, the signal of the ASIC pin can be processed and sent to the internal ASIC, and the output signal of the internal ASIC can also be processed and sent to the ASIC pin. Input signal processing includes clock signal, reset signal, etc. Output signals include observation clock, interrupt, etc. The IOPAD module can control the level and drive current of the input and output signals, and also includes detection functions. Gated clock: a technology that turns off the clock in some parts of the ASIC design. Here, the "part" can be a single register, a module, a subsystem, or even the entire ASIC.

[0038] In some embodiments, the cutting of the corresponding module type according to the cutting information includes: reading type information in the cutting information, cutting the corresponding module in the application specific integrated circuit register transfer level file list file according to the type information, and saving a temporary file list copy. The module cutting engine in the automatically generated script program automatically cuts the module type selected by the user according to the input information of the user, and saves a temporary file list copy as an operation object for subsequent operations.

[0039] The modified file list path is converted in format, and a register transfer level file list file of an FPGA prototype is output according to the converted path.

[0040] In some embodiments, the format conversion of the modified file list path includes: converting the modified file list path into a file path in the form of a tool command language syntax. The syntax conversion engine in the automatically generated script program converts the modified file list path into a file path in the form of Tcl syntax. The automatically generated script saves the file path in the form of Tcl syntax, and outputs an RTL file list file of an FPGA prototype.

[0041] The embodiments of the application can automatically identify and classify RTL modules by reading an RTL file list file of an ASIC, and can automatically perform cutting and replacing operations on the RTL modules according to the identification results, thereby improving the work efficiency of porting an ASIC design to an FPGA prototype.

[0042] It should be particularly pointed out that each step in each embodiment of the above method of generating the register transfer level file list file can be crossed, replaced, added, deleted, and thus, these reasonable permutations and combinations of the method of generating the register transfer level file list file should also belong to the protection scope of the present application, and the protection scope of the present application should not be limited to the embodiments.

[0043] Based on the above purpose, a second aspect of the embodiment of the present application provides a system for generating a register transfer level file list file. As shown in Figure 3 The system 200 includes the following modules: an input module configured to input a specific path of an application specific integrated circuit register transfer level file list file to import the application specific integrated circuit register transfer level file list file; a classification module configured to compare modules in the application specific integrated circuit register transfer level file list file with register transfer level circuit models in a feature module library to identify types of the modules in the application specific integrated circuit register transfer level file list file; a clipping module configured to clip a corresponding module type according to clipping information input by a user in response to receiving the clipping information and modify a file list path; and an output module configured to format convert the modified file list path and output a register transfer level file list file of an FPGA prototype according to the converted path.

[0044] In some embodiments, the clipping module is configured to add file paths of DUMMY RTL modules and FPGA IP modules in the file list, add file paths of FPGA bidirectional IO port control logic modules in the file list, and add file paths of global clocks with enable terminals in the file list.

[0045] In some embodiments, the output module is configured to convert the modified file list path into a file path in a tool command language syntax form.

[0046] In some embodiments, the clipping module is configured to read type information in the clipping information, clip corresponding modules in the application specific integrated circuit register transfer level file list file according to the type information, and save a temporary file list copy.

[0047] Based on the above purpose, a third aspect of the embodiments of the present application provides a computer device, comprising: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executed by the processor to implement the following steps: S1, inputting a specific path of an application specific integrated circuit register transfer level file list file to import the application specific integrated circuit register transfer level file list file; S2, comparing modules in the application specific integrated circuit register transfer level file list file with register transfer level circuit models in a feature module library to identify types of the modules in the application specific integrated circuit register transfer level file list file; S3, in response to receiving clipping information input by a user, clipping a corresponding module type according to the clipping information, and modifying a file list path; and S4, format-converting the modified file list path, and outputting a register transfer level file list file of an FPGA prototype according to the converted path.

[0048] In some embodiments, the modifying the file list path comprises: adding file paths of DUMMYRTL modules and FPGA IP modules in the file list; adding a file path of a FPGA bidirectional IO port control logic module in the file list; and adding a file path of a global clock with an enable end in the FPGA in the file list.

[0049] In some embodiments, the format-converting the modified file list path comprises: converting the modified file list path into a file path in a tool command language syntax form.

[0050] In some embodiments, the clipping the corresponding module type according to the clipping information comprises: reading type information in the clipping information, clipping a corresponding module in the application specific integrated circuit register transfer level file list file according to the type information, and saving a temporary file list copy.

[0051] As shown in Figure 4 , it is a hardware structure schematic diagram of one embodiment of the computer device for generating the register transfer level file list file provided by the present application.

[0052] As shown in Figure 4 , the device comprises a processor 301 and a memory 302.

[0053] The processor 301 and the memory 302 can be connected through a bus or other means, Figure 4 for example, through a bus connection.

[0054] Memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for generating a register translation level file list in this embodiment. Processor 301 executes various server functions and data processing by running the non-volatile software programs, instructions, and modules stored in memory 302, thereby implementing the method for generating a register translation level file list.

[0055] Memory 302 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created using a method for generating a register translation level file list file, etc. Furthermore, memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory remotely located relative to processor 301, and these remote memories may be connected to a local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0056] One or more methods for generating register translation level file list files are stored in memory 302. When executed by processor 301, the method for generating register translation level file list files in any of the above method embodiments is executed.

[0057] Any embodiment of the computer device that performs the above-described method for generating a register translation level file list can achieve the same or similar effects as any of the foregoing method embodiments.

[0058] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs a method for generating a register translation level file list file.

[0059] like Figure 5 The diagram shown is a schematic representation of an embodiment of the computer storage medium for generating the register translation level file list file provided by the present invention. Figure 5 Taking the computer storage medium shown as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, performs the above method.

[0060] Finally, it needs to be explained that all or part of the processes in the above-mentioned embodiment methods can be implemented by a computer program to instruct relevant hardware to complete, and the program of the method of generating the register translation level file list file can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiment methods. The storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding any method embodiments.

[0061] The above is the exemplary embodiment disclosed by the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present application defined by the claims. The functions, steps and / or acts of the method claims described in the embodiments disclosed herein need not be performed in any particular order. In addition, although the elements of the embodiments disclosed by the present application can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to singular.

[0062] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that "and / or" as used herein refers to any and all possible combinations of one or more of the associated listed items.

[0063] The above-mentioned embodiment number of the embodiments disclosed by the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0064] It can be understood by those of ordinary skill in the art that all or part of the above-mentioned embodiments can be completed by hardware, or by a program to instruct relevant hardware, and the program can be stored in a computer readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0065] Those of ordinary skill in the art should understand that the above discussion of any embodiment is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present application (including the claims) is limited to these examples; under the idea of the embodiments of the present application, the above embodiments or technical features in different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail. Therefore, any omissions, modifications, equivalent replacements, improvements, etc. made in the spirit and principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A method for generating a register translation level file list, characterized in that, Includes the following steps: Enter the specific path to the ASIC register translation level file list file to import the ASIC register translation level file list file; The modules in the application-specific integrated circuit register translation level file list are compared with the register translation level circuit models in the feature module library to identify the type of each module in the application-specific integrated circuit register translation level file list; In response to receiving clipping information input by the user, the corresponding module type is clipped according to the clipping information, and the file list path is modified; as well as The modified file list path is formatted and the register conversion level file list of the FPGA prototype is output according to the converted path. The modification of the file list path includes: Add the file paths of the DUMMY RTL module and the FPGA IP module to the file list; Add the file path of the FPGA bidirectional I / O port control logic module to the file list; and Add the file path to the FPGA's global clock with enable pin to the file list.

2. The method according to claim 1, characterized in that, The process of converting the modified file list path to a new format includes: Convert the modified file list path into file path format using the tool command language syntax.

3. The method according to claim 1, characterized in that, The module types corresponding to the clipping information include: Read the type information in the trimming information, trim the corresponding module in the application-specific integrated circuit register conversion level file list file according to the type information, and save a temporary file list copy.

4. A system for generating a register translation level file list, characterized in that, include: The input module is configured to import the ASIC register translation level file list file by inputting the specific path of the ASIC register translation level file list file. The classification module is configured to compare the modules in the application-specific integrated circuit register translation level file list with the register translation level circuit models in the feature module library to identify the type of each module in the application-specific integrated circuit register translation level file list; The trimming module is configured to respond to received trimming information from the user, trim the corresponding module type according to the trimming information, and modify the file list path. as well as The output module is configured to convert the modified file list path into a new format and output the register conversion level file list of the FPGA prototype based on the converted path. The cropping module is configured to: Add the file paths of the DUMMY RTL module and the FPGA IP module to the file list; Add the file path of the FPGA bidirectional I / O port control logic module to the file list; and Add the file path to the FPGA's global clock with enable pin to the file list.

5. The system according to claim 4, characterized in that, The output module is configured to: Convert the modified file list path into file path format using the tool command language syntax.

6. The system according to claim 4, characterized in that, The cropping module is configured to: Read the type information in the trimming information, trim the corresponding module in the application-specific integrated circuit register conversion level file list file according to the type information, and save a temporary file list copy.

7. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-3.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-3.

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