Memory device and method of operation thereof

Abstract

A memory device with improved performance includes a plurality of memory cells programmed to one of a plurality of program states based on threshold voltage partitioning, and a plurality of page buffers coupled to the plurality of memory cells by a plurality of bit lines. Each page buffer of the plurality of page buffers includes a latch to store data sensed from a corresponding bit line of the plurality of bit lines, and each page buffer of the plurality of page buffers discharges the corresponding bit line when performing a latch set operation, the latch set operation including setting data stored in the latch in a verify operation for the plurality of program states.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0122030, filed on September 22, 2020, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments described herein relate to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0004] Storage devices store data under the control of host devices such as computers or smartphones. For example, such storage devices may include a memory device for storing data and a memory controller for controlling the memory device.

[0005] Memory devices are generally classified into volatile memory devices and non-volatile memory devices. Volatile memory devices store data only when powered on. When power is interrupted, the stored data is lost. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices retain data even when power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] The embodiments provide a memory device with improved performance and a method of operating the memory device.

[0008] According to one aspect of this disclosure, a memory device includes: a plurality of memory cells programmed to one of a plurality of programming states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells via a plurality of bit lines, wherein each of the plurality of page buffers includes a latch configured to store data sensed from a corresponding bit line of the plurality of bit lines, and each of the plurality of page buffers discharges the corresponding bit line when performing a latch setting operation, the latch setting operation including setting the data stored in the latch in the latch during a verification operation of the plurality of programming states.

[0009] According to another aspect of this disclosure, a page buffer coupled to a plurality of memory cells via bit lines includes: a latch configured to store data sensed from the bit lines; a latch setting circuit configured to perform a latch setting operation including setting the data stored in the latch during a verification operation of the plurality of memory cells; and a bit line controller configured to discharge the bit lines while the latch setting operation is being performed.

[0010] According to another aspect of this disclosure, a method for operating a memory device includes a plurality of memory cells programmed to one of a plurality of programming states divided based on a threshold voltage. The method includes: performing a latch setting operation, the latch setting operation including setting data stored in a latch; discharging bit lines connected to the plurality of memory cells during the execution of the latch setting operation; and pre-charging the bit lines based on whether the latch setting operation has been completed.

[0011] According to another aspect of this disclosure, an apparatus includes a page buffer and a controller coupled to the page buffer, the page buffer being coupled to a memory cell via a bit line, and the page buffer including a latch configured to store data sensed from the bit line. The controller is configured to generate a first signal, a second signal, and a third signal, the first signal for controlling the latch, the second signal for controlling a latch setting operation including setting data stored in the latch during a verification operation of the memory cell, and the third signal for discharging the bit line while the latch setting operation is being performed. Attached Figure Description

[0012] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0013] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals refer to similar elements.

[0014] Figure 1 An embodiment of a storage device is illustrated.

[0015] Figure 2 An embodiment of a memory device is illustrated.

[0016] Figure 3 An embodiment of a memory cell array is illustrated.

[0017] Figure 4 An embodiment of a memory block is illustrated.

[0018] Figure 5 Another embodiment of the memory block is illustrated.

[0019] Figure 6 Another embodiment of the memory block is illustrated.

[0020] Figure 7 The illustration shows an example of programming operations for a memory device.

[0021] Figure 8 An embodiment of a page buffer is illustrated.

[0022] Figure 9A and Figure 9B The illustration shows examples of latch setting operations and bit line discharge operations.

[0023] Figure 10A and Figure 10B Additional examples of latch setting operations and bit line discharge operations are illustrated.

[0024] Figure 11 The illustration shows an embodiment of the operation of pre-charging the bit line during the verification process.

[0025] Figure 12 The illustration shows an example of a bit line pre-charge operation during a read operation.

[0026] Figure 13 An embodiment of a method of operating a memory device is illustrated.

[0027] Figure 14 An embodiment of a method for discharging a bit line is illustrated.

[0028] Figure 15 Another embodiment of a method for discharging bit lines is illustrated.

[0029] Figure 16 An embodiment of a memory controller is illustrated.

[0030] Figure 17 An embodiment of a memory card system to which a storage device can be applied is illustrated.

[0031] Figure 18 An embodiment of a solid-state drive (SSD) system to which a storage device can be applied is illustrated.

[0032] Figure 19 An embodiment of a user system that can apply storage devices to it is illustrated. Detailed Implementation

[0033] The specific structural or functional descriptions disclosed herein are illustrative only and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0034] Figure 1 This diagram illustrates one embodiment of a storage device 50, which may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device 100. The storage device 50 may store data under the control of a host 300. Examples of host 300 include mobile phones, smartphones, MP3 players, laptops, desktop computers, game consoles, TVs, tablet PCs, and in-vehicle infotainment systems.

[0035] Depending on the communication standard or protocol of the host interface of host 300, storage device 50 can be manufactured as any of various types of storage devices. Examples of storage device 50 include: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), small form factor MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0036] Storage device 50 can be manufactured in any of a variety of package types. Examples include point-of-purchase (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0037] The memory device 100 stores data under the control of the memory controller 200. The memory device 100 may include at least one memory cell array, each of which includes a plurality of memory cells for storing data. For example, each memory cell may operate as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0038] Each memory cell array may include multiple memory blocks, where each memory block includes one or more memory cells. In one embodiment, one or more memory blocks within a memory block may include multiple pages. Each page may serve as a unit for storing data in the memory device 100 or for retrieving data stored in the memory device 100. A memory block may also serve as a unit for erasing data.

[0039] Examples of memory device 100 include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. For ease of description, the case where memory device 100 is NAND flash memory will be described.

[0040] Memory device 100 can receive a command CMD and an address ADDR from memory controller 200, and can then access the region selected by address ADDR in the memory cell array. Memory device 100 can then perform the operation indicated by command CMD on the region selected by address ADDR. For example, memory device 100 can perform write operations (e.g., programming operations), read operations, and erase operations. In a programming operation, memory device 100 can program data in the region selected by address ADDR. In a read operation, memory device 100 can read data from the region selected by address ADDR. In an erase operation, memory device 100 can erase data stored in the region selected by address ADDR.

[0041] The memory controller 200 can control the overall operation of the storage device 50. When power is applied to the storage device 50, the memory controller 200 can execute firmware (FW). When the storage device 100 is a flash memory device, the FW may include: a host interface layer (HIL) for controlling communication with the host 300, a flash translation layer (FTL) for controlling communication between the host and the storage device 100, and a flash interface layer (FIL) for controlling communication with the storage device 100.

[0042] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and then translate the LBA into a physical block address (PBA), which represents the address of a memory cell in the memory device 100 where data is to be stored. In one or more embodiments, the terms LBA and "logical address" or "logical address" may be used synonymously. Furthermore, PBA and "physical address" may be used synonymously.

[0043] In response to a request from host 300, memory controller 200 can control memory device 100 to perform programming, reading, erasing, or other operations. During a programming operation, memory controller 200 can provide programming commands, PBA, and / or data to memory device 100. During a reading operation, memory controller 200 can provide reading commands and / or PBA to memory device 100. During an erasing operation, memory controller 200 can provide erasing commands and / or PBA to memory device 100.

[0044] In one embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host 300, and can transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing read operations and programming operations accompanying wear leveling, read recycling, garbage collection, or other operations.

[0045] In one embodiment, the memory controller 200 can control at least two memory devices 100. For example, the memory controller 200 can control the memory devices according to an interleaving technique to improve operational performance. For example, the interleaving technique can be a technique for controlling the operation of at least two memory devices 100 to overlap with each other.

[0046] The host 300 can communicate with the storage device 50 using at least one of a variety of communication methods. Examples include Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0047] Figure 2 It is a diagram. Figure 1A diagram of one embodiment of the memory device 100 shown. (Refer to...) Figure 2 The memory device 100 may include at least one memory cell array 110, peripheral circuitry 120, and control logic 130.

[0048] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz, which are connected to row decoder 121 via corresponding row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLm. Each memory block BLK1 to BLKz includes multiple memory cells, which may be, for example, non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0049] Row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. For example, each memory cell in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0050] The peripheral circuit 120 can perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLm under the control of the control logic 130, or it can discharge the applied voltages.

[0051] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126. The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include ordinary word lines and dummy word lines. In another embodiment, the row lines RL may further include pipe select lines.

[0052] The row decoder 121 operates under the control of the control logic. The row decoder 121 receives the row address RADD from the control logic 130 and decodes the row address RADD. The row decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded address. Furthermore, the row decoder 121 can select at least one word line of the selected memory block to apply a voltage generated by the voltage generator 122 to at least one word line WL according to the decoded address.

[0053] For example, in a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and can apply a programming pass voltage (e.g., the programming pass voltage has a level lower than the programming voltage) to the unselected word line. In a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage (e.g., the verification pass voltage has a level higher than the verification voltage) to the unselected word line.

[0054] During a read operation, the line decoder 121 can apply a read voltage to the selected word line and can apply a read pass voltage (e.g., the read pass voltage has a higher level than the read voltage) to the unselected word line.

[0055] In one embodiment, the erase operation of memory device 100 is performed on a block-by-block basis. During the erase operation, row decoder 121 selects a memory block based on the decoded address. During the erase operation, row decoder 121 may apply a reference voltage (e.g., ground) to the word line connected to the selected memory block.

[0056] Voltage generator 122 operates under the control of control logic 130. Voltage generator 122 generates multiple voltages based on the external supply voltage provided to memory device 100. For example, the voltage generator may generate various operating voltages Vop used in programming, reading, and erasing operations in response to the operation signal OPSIG. In one embodiment, voltage generator 122 may generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, and / or another voltage under the control of control logic 130.

[0057] In one embodiment, voltage generator 122 can generate an internal supply voltage by adjusting an external supply voltage. The internal supply voltage can be used as the operating voltage of the memory device 100.

[0058] In one embodiment, voltage generator 122 can generate multiple voltages using either an external supply voltage or an internal supply voltage. For example, voltage generator 122 may include multiple pump capacitors for receiving the internal supply voltage, and voltage generator 122 can generate multiple voltages by selectively activating the multiple pump capacitors under the control of control logic 130. The multiple generated voltages can be provided to memory cell array 110 via row decoder 121.

[0059] Page buffer group 123 includes first page buffers to m-th page buffers PB1 to PBm. First page buffers to m-th page buffers PB1 to PBm are respectively connected to memory cell array 110 via first bit lines to m-th bit lines BL1 to BLm. First bit lines to m-th bit lines BL1 to BLm operate under the control of control logic 130. For example, first bit lines to m-th bit lines BL1 to BLm can operate in response to the page buffer control signal PBSIGNALS. In one embodiment, first page buffers to m-th page buffers PB1 to PBm can temporarily store data received via first bit lines to m-th bit lines BL1 to BLm, or the voltage or current of bit lines BL1 to BLm can be sensed during read or verification operations.

[0060] During programming, page buffers PB1 to PBm (from the first page buffer to the m-th page buffer) can, for example, transfer data DATA received via input / output circuit 125 to the selected memory cell via first bit lines to m-th bit lines BL1 to BLm. This can occur when a programming voltage is applied to the selected word line. The memory cell of the selected page is programmed based on the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. Threshold voltages of memory cells connected to bit lines to which a programming disable voltage (e.g., supply voltage) is applied can be maintained. During programming verification, page buffers PB1 to PBm (from the first page buffer to the m-th page buffer) can read page data from the selected memory cell via first bit lines to m-th bit lines BL1 to BLm.

[0061] During the read operation, the first page buffer to the m-th page buffer PB1 to PBm read data DATA from the memory cell of the selected page through the first bit line to the m-th bit line BL1 to BLm, and under the control of the column decoder 124, output the read data DATA to the input / output circuit 125.

[0062] During the erase operation, the first page buffer to the m-th page buffer PB1 to PBm can float the first bit line to the m-th bit line BL1 to BLm.

[0063] The column decoder 124 can communicate data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can communicate data with the first page buffer to the m-th page buffers PB1 to PBm via the data line DL, or it can communicate data with the input / output circuitry 125 via the column line CL.

[0064] Input / output circuit 125 can transfer data from a reference circuit. Figure 1 The memory controller 200 described herein receives commands CMD and addresses ADDR and passes them to control logic 130, or may exchange data DATA with column decoder 124.

[0065] During a read or verification operation, the sensing circuit 126 can generate a reference current in response to the enable bit VRYBIT signal, and can output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0066] In response to the command CMD and address ADDR, control logic 130 can control peripheral circuitry 120 by outputting the operation signal OPSIG, the row address RADD, the page buffer control signal PBSIGNALS, and the enable bit VRYBIT. Furthermore, in response to the pass signal PASS or the failure signal FAIL, control logic 130 can determine whether the verification operation has passed or failed.

[0067] Figure 3 It is a diagram. Figure 2 A diagram of one embodiment of the memory cell array 110 shown. (Refer to...) Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz, each of which may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells may be arranged along predetermined directions (e.g., +X, +Y, and +Z directions). (Refer to...) Figure 4 and Figure 5 An example describing the structure of each memory block.

[0068] Figure 4 This is a circuit diagram illustrating one embodiment of the memory block BLKa, which can represent... Figure 3 The image shows one or more memory blocks from BLK1 to BLKz. (Reference) Figure 4 The memory block BLKa may include multiple memory cell strings CS11 to CS1m and CS21 to CS2m.

[0069] In one embodiment, each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m can be formed into a predetermined shape, such as a "U" shape. In the memory block BLKa, m memory cell strings are arranged in the row direction (i.e., the +X direction). Figure 4 The illustration shows two strings of memory cells arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it should be understood that three strings of memory cells can be arranged in the column direction.

[0070] Each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell to an nth memory cell MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0071] The select transistors SST and DST, and the memory cells MC1 to MCn, can have structures similar to each other. In one embodiment, each select transistor in the select transistors SST and DST, and each memory cell in the memory cells MC1 to MCn, may include a channel layer, a tunnel insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each memory cell string. In one embodiment, pillars for providing at least one of the channel layer, tunnel insulating layer, charge storage layer, or barrier insulating layer may be provided in each memory cell string.

[0072] The source select transistor SST of each memory cell string is connected between the common source line CSL and memory cells MC1 to MCp. In one embodiment, the source select transistors of memory cell strings arranged in the same row are connected to source select lines extending in the row direction. The source select transistors of memory cell strings arranged in different rows are connected to different source select lines. Figure 4 In the first row, the source select transistors of memory cell strings CS11 to CS1m are connected to the first source select line SSL1. The source select transistors of memory cell strings CS21 to CS2m in the second row are connected to the second source select line SSL2. In one embodiment, the source select transistors of memory cell strings CS11 to CS1m and CS21 to CS2m can be connected to a single source select line.

[0073] The first to nth memory cells MC1 to MCn of each memory cell string are connected between the source selection transistor SST and the drain selection transistor DST. The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in opposite directions in the +Z direction and connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and connected in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are connected via the channel transistor PT. The gate electrodes of the first memory cell to the nth memory cell MC1 to MCn of each memory cell string are respectively connected to the first word line to the nth word line WL1 to WLn.

[0074] The gate of the pipe transistor PT in each memory cell string is connected to the pipe line PL.

[0075] The drain select transistor (DST) of each memory cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Memory cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of memory cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of memory cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0076] Memory cells arranged in the column direction are connected in a string to bit lines extending in the column direction. Figure 4 In the diagram, memory cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. Memory cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0077] In a row-oriented memory cell string, memory cells connected to the same word line constitute a page. For example, memory cells in the memory cell strings CS11 to CS1m in the first row connected to the first word line WL1 constitute one page. Memory cells in the memory cell strings CS21 to CS2m in the second row connected to the first word line WL1 constitute another page. When either drain select line DSL1 or DSL2 is selected, a memory cell string arranged in a row direction can be selected. When any word line WL1 to WLn is selected, a page can be selected from the selected memory cell string.

[0078] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines to the m-th bit lines BL1 to BLm. Furthermore, memory cell strings with even-numbered addresses in the row-directed memory cell strings CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, respectively. Conversely, memory cell strings with odd-numbered addresses in the row-directed memory cell strings CS11 to CS1m or CS21m to CS2m can be connected to the odd-numbered bit lines, respectively.

[0079] In one embodiment, at least one of the memory cells MC1 to MCn from the first memory cell to the nth memory cell can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. In one embodiment, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKa can be improved, but the size of the memory block BLKa may increase. When the number of dummy memory cells decreases, the size of the memory block BLKa decreases, but the operational reliability of the memory block BLKa may deteriorate.

[0080] To effectively control at least one dummy memory cell, the dummy memory cell can have a predetermined threshold voltage. Before or after an erase operation on memory block BLKa, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation, threshold voltage control for the dummy memory cell is applied to the voltage of the dummy word line connected to the corresponding dummy memory cell, such that the dummy memory cell can have a predetermined threshold voltage.

[0081] Figure 5 This is a circuit diagram illustrating one embodiment of the memory block BLKb, which can represent... Figure 3The memory blocks BLK1 to BLKz are shown in the diagram. (Reference) Figure 5 The memory block BLKb may include multiple memory cell strings CS11' to CS1m' and CS21' to CS2m', each of which may extend along the +Z direction. Each of the multiple memory cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first memory cells to nth memory cells MC1 to MCn, and at least one drain selection transistor DST, which are stacked on a substrate beneath the memory block BLKb.

[0082] The source select transistor SST of each memory cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of memory cell strings arranged in the same row are connected to the same source select line. The source select transistors of memory cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of memory cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In one embodiment, the source select transistors of memory cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a common source select line.

[0083] The first memory cell to the nth memory cell MC1 to MCn of each memory cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gate electrodes of the first memory cell to the nth memory cell MC1 to MCn are respectively connected to the first word line to the nth word line WL1 to WLn.

[0084] The drain select transistor (DST) of each memory cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of memory cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of memory cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of memory cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0085] As a result, besides from Figure 5 Each memory cell string in the array excludes the pipe transistor PT. Figure 5 The memory block BLKb can have the same as Figure 4 The circuitry is similar to that of the memory block BLKa.

[0086] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided in place of the first bit lines to the m-th bit lines BL1 to BLm. Furthermore, memory cell strings with even-numbered addresses in the row-direction memory cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines respectively. Conversely, memory cell strings with odd-numbered addresses in the row-direction memory cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines respectively.

[0087] In one embodiment, at least one of the memory cells MC1 to MCn from the first memory cell to the nth memory cell can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. In one embodiment, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKb can be improved, but the size of the memory block BLKb may increase. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases, but the operational reliability of the memory block BLKb may deteriorate.

[0088] To effectively control at least one dummy memory cell, the dummy memory cell can have a predetermined threshold voltage. Before or after an erase operation on memory block BLKb, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation, threshold voltage control for the dummy memory cell is applied to the voltage of the dummy word line connected to the corresponding dummy memory cell, such that the dummy memory cell can have a predetermined threshold voltage.

[0089] Figure 6 This is a circuit diagram illustrating one embodiment of the memory block BLKi, which can represent... Figure 3 The memory blocks BLK1 to BLKz are shown in the diagram. (Reference) Figure 6In a memory block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). For example, a memory block BLKi can include multiple memory cell strings ST connected between bit lines BL1 to BLm and a common source line (CSL). Bit lines BL1 to BLm can be individually connected to memory cell strings ST, and the common source line (CSL) can be collectively connected to memory cell strings ST. Memory cell strings ST can be configured identically to each other. For illustrative purposes, as an example, a memory cell string ST connected to the first bit line BL1 will be described.

[0090] A memory cell string ST may include a source select transistor SST, multiple memory cells MC1 to MC16, and a drain select transistor DST, which are connected in series between a common source line CSL and a first bit line BL1. A memory cell string ST may include at least one drain select transistor DST, and a memory cell string ST may include source select transistors (e.g., the number of source select transistors is greater than the number of source select transistors SST shown in the figure, and the number of memory cells is greater than the number of memory cells MC1 to MC16 shown in the figure).

[0091] The source of the source-select transistor SST can be connected to the common source line SL, and the drain of the drain-select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source-select transistor SST and the drain-select transistor DST. The gate of the source-select transistor SST in different memory cell strings ST can be connected to the source-select line SSL. The gate of the drain-select transistor DST in different memory cell strings ST can be connected to the drain-select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16.

[0092] A group of memory cells connected to the same word line in different memory cell strings ST can be called a physical page PG. Therefore, a physical page PG corresponding to the number of word lines WL1 to WL16 can be included in a memory block BLKi.

[0093] In one embodiment, a memory cell may store one bit of data. In this case, the memory cell may be referred to as a single-level cell (SLC). A physical page (PG) may store one logical page (LPG) of data. An LPG of data may include data bits corresponding to the number of cells in a physical page (PG). In one embodiment, a memory cell may store two or more bits of data. In this case, a physical page (PG) may store two or more LPGs of data.

[0094] Figure 7 It is a diagram. Figure 2 A diagram illustrating one embodiment of the programming operation of the memory device. Figure 7 For ease of description, it is assumed that the memory cell is a multi-level cell (MLC) that stores 2 bits of data. However, the scope of this disclosure is not limited to this, and the memory cell may be a three-level cell (TLC) that stores 3 bits of data or a four-level cell (QLC) that stores 4 bits of data. The number of data bits stored by the memory cell may be one or more.

[0095] By executing one or more programming cycles PL1 to PLn, a memory device can program selected memory cells to have a threshold voltage corresponding to one of a plurality of programming states P1, P2, and P3. Each programming cycle PL1 to PLn may include a programming voltage application step PGM Step and a programming verification step Verify Step. The programming voltage application step PGM Step includes applying a programming voltage to a selected word line connected to the selected memory cell, and the programming verification step Verify Step includes determining whether the memory cell has been programmed by applying a verification voltage.

[0096] For example, when executing the first programming cycle PL1, a first verification voltage to a third verification voltage V_vfy1 to V_vfy3 can be applied sequentially to verify the programming state of the selected memory cell after the first programming pulse Vpgm1 is applied. Verification of the memory cell (whose target programming state is the first programming state P1) can be performed using the first verification voltage V_vfy1. Verification of the memory cell (whose target programming state is the second programming state P2) can be performed using the second verification voltage V_vfy2. Verification of the memory cell (whose target programming state is the third programming state P3) can be performed using the third verification voltage V_vfy3.

[0097] It can be determined that the memory cell that passes verification by each of the verification voltages V_vfy1 to V_vfy3 has a target programming state. Subsequently, in the second programming cycle PL2, the memory cell can be disabled for programming. For example, starting from the second programming cycle PL2, a programming disable voltage can be applied to the bit line connected to the verified memory cell.

[0098] A second programming pulse Vpgm2 (e.g., a voltage ΔVpgm higher than the first programming pulse Vpgm1) can be applied to the selected word line to program memory cells other than those that are disabled for programming, in the second programming cycle PL2. Subsequently, a verification operation can be performed in a similar or identical manner to the first programming cycle PL1. For example, successful verification may include a memory cell being read as an off-cell by the corresponding verification voltage.

[0099] As described above, when a memory device programs an MLC that stores 2 bits of data, the memory device can verify the memory cell having the corresponding programming state as the target programming state by using the first verification voltage to the third verification voltage V_vfy1 to V_vfy3.

[0100] In the verification operation, a verification voltage can be applied to the selected word line, which is the word line connected to the selected memory cell, and Figure 2 The page buffer shown can determine whether a memory cell passes verification based on the current or voltage flowing through the bit lines connected to the selected memory cell.

[0101] When the verification operation for the first programming state is completed, the voltage level of the bit line connected to the memory cell programmed to the first programming state can be increased. Therefore, during the verification operation for the second programming state, when the bit line connected to the memory cell programmed to the second programming state is precharged, the performance of the precharge operation may degrade due to the coupling effect with the bit line having an increased voltage level.

[0102] Therefore, according to one embodiment, the bit line can be discharged during the latch setting operation, thereby improving the performance of the bit line pre-charge operation during the verification operation.

[0103] Figure 8 It is a diagram. Figure 2 The circuit diagram shown is of one embodiment of the page buffer. Figure 8 The page buffer PB shown can be Figure 2 Any of the page buffers PB1 to PBm shown. Figure 2 The page buffers PB1 to PBm shown can be designed to have similar structures to each other.

[0104] refer to Figure 8 The page buffer PB may include a latch 810, a bit line controller 820, and latch setting circuitry 830. The latch 810 may store data sensed from the bit line BL and may include a a-th transistor Ta, a b-th transistor Tb, a c-th transistor Tc, and inverters IV1 and IV2. In one embodiment, the a-th transistor Ta, the b-th transistor Tb, and the c-th transistor Tc may be implemented, for example, using NMOS transistors. In another embodiment, one or more of these transistors may be implemented with different conductivity types.

[0105] Inverters IV1 and IV2 can be connected in reverse parallel between nodes QS and QS_N. Transistor Ta (a) can be connected between node QS and node NDa (a) to electrically connect nodes QS and NDa (a) in response to the reset signal SRST. Transistor Tb (b) can be connected between node QS_N and node NDa (a) to electrically connect nodes QS_N and NDa (a) in response to the set signal SSET. Transistor Tc (c) can be connected between node NDa (a) and the ground supply VSS, and can be switched on according to the potential of the sensing node SO to electrically connect node NDa (a) and the ground supply VSS.

[0106] For example, when the sensing node SO is precharged to a high level, and the reset signal SRST is applied to the a-th transistor Ta at a logic high level, nodes QS and QS_N are initialized to logic low and logic high levels, respectively. Furthermore, when the sensing node SO is precharged to a high level, and the set signal SSET is applied to the b-th transistor Tb at a logic high level, nodes QS and QS_N are set to logic high and logic low levels, respectively.

[0107] During the programming cycle, latch 810 can latch verification data during the verification operation. For example, when the potential level of the sensing node SO is changed during the verification operation, latch 810 generates and latches verification data based on the potential level of the sensing node SO. For example, when the threshold voltage of the target memory cell connected to the bit line BL is lower than the verification voltage, the target memory cell is turned on. Therefore, the potential level of the sensing node SO is discharged.

[0108] When the threshold voltage of the target memory cell connected to bit line BL is higher than the verification voltage, the target memory cell is turned off. Therefore, the potential level of the sensing node SO is maintained at the pre-charge level (supply voltage level). The a-th transistor Ta is turned on in response to the reset signal SRST, and the c-th transistor Tc is turned on or off based on the potential level of the sensing node SO, causing latch 810 to latch the verification data. For example, when latch 810 latches verification data corresponding to failure as the result of the verification operation, node QS has a first logic level (e.g., high). When latch 810 latches verification data corresponding to success as the result of the verification operation, node QS has a second logic level (e.g., low).

[0109] After the verification operation, latch 810 can transmit the latched verification data to the sensing node SO during the current sensing operation.

[0110] During programming operations, based on the potential of node QS, bit line controller 820 controls the potential level of bit line BL to either a programming enable level or a programming disable level. Furthermore, bit line controller 820 controls the potential level of sensing node SO based on the amount of current in bit line BL, which changes according to the programming state of the memory cell connected to bit line BL. This can occur during sensing operations, either during a read operation or a verification operation.

[0111] Bit line controller 820 may include a first transistor T1, a second transistor T2, and a third transistor T3. In one embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be implemented using NMOS transistors. In another embodiment, one or more of these transistors may be implemented using different conductivity types.

[0112] A first transistor T1 can be connected between a first node ND1 and a common sensing node CSO, the first node ND1 being connected to the bit line BL. The first transistor T1 electrically connects the first node ND1 and the common sensing node CSO in response to the page buffer sensing signal PB_SENSE.

[0113] The second transistor T2 can be connected between the second node ND2 and the common sensing node CSO, with the second node ND2 connected to the supply voltage VDD. The second transistor T2 can supply the supply voltage VDD provided through the d-th transistor Td to the common sensing node CSO in response to the control signal SA_CSOC.

[0114] The third transistor T3 can be connected between the first node ND1 and the ground power supply VSS. The third transistor T3 can apply the ground power supply VSS to the first node ND1 in response to the bit line discharge signal BL_DIS.

[0115] The d-th transistor Td is connected in series between the supply voltage VDD and the second node ND2, and can be turned on in response to node QS of latch 810. In one embodiment, the d-th transistor Td can be implemented using a PMOS transistor. In another embodiment, the d-th transistor Td can be implemented using transistors of a different conductivity type.

[0116] The e-th transistor Te is connected between bit line BL and the first node ND1, and is electrically connected to bit line BL and the first node ND1 in response to the bit line select signal SEL_BL. In one embodiment, the e-th transistor Te can be implemented using an NMOS transistor. In another embodiment, the e-th transistor Te can be implemented using transistors of a different conductivity type.

[0117] In one embodiment, while a latch setting operation is being performed to set the data stored in latch 810, bit line controller 820 may discharge bit line BL. Furthermore, in one embodiment, bit line controller 820 may pre-charge bit line BL when the latch setting operation is complete.

[0118] The latch setting circuit 830 can set the data stored in the latch 810 during a verification operation of multiple memory cells. The latch setting circuit 830 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. In one embodiment, the fourth transistor T4 and the fifth transistor T5 may be implemented using PMOS transistors. Alternatively, the sixth transistor T6 and the seventh transistor T7 may be implemented using NMOS transistors. In another embodiment, one or more of these transistors may be implemented as transistors of different conductivity types.

[0119] The fourth transistor T4 can be connected between the sensing node SO and the supply voltage VDD. The fourth transistor T4 can apply the supply voltage VDD to the sensing node SO in response to the sensing node precharge signal PRECHSO_N.

[0120] The fifth transistor T5 can be connected between the sensing node SO and the second node ND2. The fifth transistor T5 can be turned on in response to the precharge signal SA_PRECH_N.

[0121] The sixth transistor T6 can be connected between the sensing node SO and the common sensing node CSO. The sixth transistor T6 can electrically connect the sensing node SO and the common sensing node CSO in response to the sensing signal SA_SENSE.

[0122] The seventh transistor T7 can be connected between the common sensing node CSO and the node QS of the latch 810. The seventh transistor T7 electrically connects the sensing node CSO and the node QS in response to the discharge signal SA_DISCH.

[0123] In one embodiment, latch setting circuitry 830 can perform a latch setting operation during a verification operation on a plurality of memory cells. In one embodiment, the latch setting operation can include storing a first logic value in latch 810 of each page buffer connected to a bit line on which a verification operation for a second programming state is to be performed. The verification operation for the second programming state can be performed after the verification operation for the first programming state is completed. Furthermore, the latch setting operation can include storing an inverted first logic value in latch 810 of each page buffer connected to a bit line on which a verification operation for the second programming state is not performed.

[0124] In the verification operation of the second programming state, performed after the verification operation of the first programming state, a latch setting operation can be performed before the bit line pre-charge operation. For example, when the page buffer PB is connected to the memory cell on which the verification operation of the programming state is to be performed, the latch setting circuit 830 can set a first value (e.g., 1) to node QS_N of latch 810. When the page buffer PB is not connected to the memory cell on which the verification operation of the programming state is to be performed, the latch setting circuit 830 can set a second value (e.g., 0) to node QS_N of latch 810.

[0125] Figure 9A This is a circuit diagram illustrating one embodiment of a page buffer used to perform latch setting operations and bit line discharge operations. Figure 9B This is a waveform diagram illustrating the latch setting operation and the operation of discharging the bit line according to one embodiment. Figure 9A The page buffer shown can be Figure 8 The page buffer PB is shown in the figure.

[0126] exist Figure 9B In the process, during time periods T0 to T1, the latch setup operation QS set up and the operation BL Discharge for discharging the bit line during the verification operation are performed, and during time periods T1 to T2, the operation BL Precharge for precharging the bit line during the verification operation can be performed.

[0127] During time periods T0 to T1, the page buffer PB can perform a latch setup operation QS. In one embodiment, the page buffer PB can turn off the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. For example, the page buffer PB can increase the precharge signal SA_PRECH_N applied to the fifth transistor T5 to the turn-off voltage. Furthermore, the page buffer PB can decrease the sensing signal SA_SENSE and the discharge signal SA_DISCH applied to the sixth transistor T6 and the seventh transistor T7, respectively, to the turn-off voltage.

[0128] In one embodiment, the page buffer PB can perform a latch setup operation QS by applying a supply voltage VDD to the sensing node SO via the fourth transistor T4, and can pass the supply voltage VDD to node QS of latch 810 via the sensing node SO. For example, the page buffer PB can reduce the sensing node precharge signal PRECHSO_N applied to the fourth transistor T4 to the turn-on voltage. The page buffer PB can apply the supply voltage VDD to the sensing node SO according to the sensing node precharge signal PRECHSO_N. Furthermore, the page buffer PB can pass the supply voltage VDD to node QS of latch 810 via the sensing node SO, and can set the value of node QS_N to 1 based on the supply voltage VDD.

[0129] Furthermore, during the latch set-up operation QS, the page buffer PB can discharge the bit line BL. In one embodiment, the page buffer PB can turn off the first transistor T1 and discharge the bit line BL by applying a ground power supply VSS to the first node ND1 via the third transistor T3. For example, the page buffer PB can decrease the page buffer sensing signal PB_SENSE applied to the first transistor T1 to the turn-off voltage. Additionally, the page buffer PB can increase the bit line discharge signal BL_DIS applied to the third transistor T3 to the turn-on voltage. The page buffer PB can discharge the bit line BL by applying a ground power supply VSS to the first node ND1 connected to the bit line BL according to the bit line discharge signal BL_DIS.

[0130] During time intervals T1 to T2, the page buffer PB can precharge the bit line BL. For example, after the latch set-up operation QS and the bit line discharge operation BL Discharge are completed, the page buffer PB can precharge the bit line. (See reference...) Figure 11 A detailed description of an embodiment of the operation BL Precharge for precharging the bit line.

[0131] Therefore, according to one embodiment, performing the latch setting operation and the bit line discharge operation simultaneously improves the performance of the bit line discharge operation during the verification operation.

[0132] Figure 10A This is a circuit diagram illustrating one embodiment of a page buffer on which latch setting operations and bit line discharge operations are performed during a verification operation. Figure 10B This is an example of a waveform diagram illustrating the latch setting operation and the bit line discharge operation during the verification operation. Figure 10A and Figure 10B In the process, the BL Discharge operation, which discharges the bit line, can be combined with... Figure 9A and Figure 9B The operation shown is different from BL Discharge. Furthermore, Figure 10A The page buffer shown can be Figure 8 The page buffer PB is shown in the figure.

[0133] exist Figure 10B During time periods T0 to T1, the latch setup operation (QS set up) and the bit line discharge operation (BL Discharge) can be performed. During time periods T1 to T2, the bit line precharge operation (BL Precharge) can be performed during the verification operation.

[0134] During time periods T0 to T1, the page buffer PB can perform a latch setup operation QS. In one embodiment, the page buffer PB can turn off the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. For example, the page buffer PB can increase the precharge signal SA_PRECH_N applied to the fifth transistor T5 to the turn-off voltage. Furthermore, the page buffer PB can decrease the sensing signal SA_SENSE and the discharge signal SA_DISCH applied to the sixth transistor T6 and the seventh transistor T7, respectively, to the turn-off voltage.

[0135] In one embodiment, the page buffer PB can perform a latch setup operation QS by applying a supply voltage VDD to the sensing node SO via the fourth transistor T4, and can pass the supply voltage VDD to node QS of latch 810 via the sensing node SO. For example, the page buffer PB can reduce the sensing node precharge signal PRECHSO_N applied to the fourth transistor T4 to the turn-on voltage. The page buffer PB can apply the supply voltage VDD to the sensing node SO based on the sensing node precharge signal PRECHSO_N. Furthermore, the page buffer PB can pass the supply voltage VDD to node QS of latch 810 via the sensing node SO, and can set the value of node QS_N to "1" based on the supply voltage VDD.

[0136] Furthermore, during the latch setup operation QS, the page buffer PB can discharge the bit line BL. In one embodiment, the page buffer PB can turn off the second transistor T2 and discharge the bit line BL by applying a ground power supply VSS to the first node ND1 via the third transistor T3. For example, the page buffer PB can decrease the control signal SA_CSOC applied to the second transistor T2 to the turn-off voltage. Additionally, the page buffer PB can increase the bit line discharge signal BL_DIS applied to the third transistor T3 to the turn-on voltage. The page buffer PB can discharge the bit line BL by applying a ground power supply VSS to the first node ND1 connected to the bit line BL according to the bit line discharge signal BL_DIS.

[0137] During time intervals T1 to T2, the page buffer PB can precharge the bit line BL. For example, after the latch set-up operation QS and the bit line discharge operation BL Discharge are completed, the page buffer PB can precharge the bit line. (See reference...) Figure 11 An example of the operation BL Precharge, which describes the pre-charging of the bit line.

[0138] Therefore, according to one embodiment, performing the latch setting operation and the bit line discharge operation simultaneously improves the performance of the bit line discharge operation during the verification operation.

[0139] Figure 11 This is a circuit diagram illustrating the operation of pre-charging a bit line during a verification operation according to one embodiment. Figure 11 The page buffer PB shown can be Figure 8 The page buffer PB is shown in the figure.

[0140] refer to Figure 11After the latch setup operation and the bit line discharge operation are completed, the page buffer PB can precharge the bit line. In one embodiment, the page buffer PB can precharge the bit line BL using a first transistor T1 and a second transistor T2 via a first precharge path BL. In another embodiment, the page buffer PB can turn off a third transistor T3. Furthermore, the page buffer PB can precharge the bit line BL by applying a supply voltage VDD to the first node ND1 via the first transistor T1 and the second transistor T2.

[0141] For example, the page buffer PB can reduce the bit line discharge signal BL_DIS applied to the third transistor T3 to the turn-off voltage. Furthermore, the page buffer PB can increase the page buffer sensing signal PB_SENSE and the control signal SA_CSOC (which are applied to the first transistor T1 and the second transistor T2, respectively) to the turn-on voltage. The page buffer PB can precharge the bit line BL by providing the supply voltage VDD supplied via the d-th transistor Td to the bit line BL through the common sensing node CSO and the first node ND1.

[0142] Figure 12 This is a circuit diagram illustrating the operation of precharging a bit line during a read operation according to one embodiment. Figure 12 The page buffer shown can be Figure 2 Any one of the page buffers PB1 to PBm shown. Furthermore, in Figure 12 In this context, the control signal SA_CSOC1 applied to the second transistor T2 can be equal to the reference signal. Figure 11 SA_CSOC is described.

[0143] refer to Figure 12 The page buffer PB may include an eighth transistor T8 connected between the supply voltage VDD and the common sensing node CSO. The eighth transistor T8 may supply the supply voltage VDD to the common sensing node CSO in response to the control signal SA_CSOC2.

[0144] In one embodiment, during the verification operation of multiple memory cells, the page buffer PB can precharge the bit line BL using a first transistor T1 and a second transistor T2 via a first precharge path BL Precharge path 1. In another embodiment, the page buffer PB can turn off a third transistor T3 and an eighth transistor T8. Furthermore, the page buffer PB can precharge the bit line BL by applying a supply voltage VDD to the first node ND1 via the first transistor T1 and the second transistor T2.

[0145] In one embodiment, during a read operation on multiple memory cells, the page buffer PB can use the first transistor T1 and the eighth transistor T8 to precharge the bit line BL via the second precharge path BL Precharge path 2.

[0146] In one embodiment, during a read operation on multiple memory cells, the page buffer PB can turn off the second transistor T2 and the third transistor T3. Furthermore, the page buffer PB can precharge the bit line BL by applying a supply voltage VDD to the first node ND1 via the first transistor T1 and the eighth transistor T8. For example, the page buffer PB can reduce the control signal SA_CSOC1 and the bit line discharge signal BL_DIS, respectively, applied to the second transistor T2 and the third transistor T3, to the turn-off voltage. Additionally, the page buffer PB can increase the page buffer sensing signal PB_SENSE and the control signal SA_CSOC2, respectively, applied to the first transistor T1 and the eighth transistor T8, to the turn-on voltage. The page buffer PB can precharge the bit line BL by providing the supply voltage VDD, supplied via the eighth transistor T8, to the bit line BL via the common sensing node CSO and the first node ND1.

[0147] Therefore, according to one embodiment, the precharge paths in the verification operation and the read operation are set to be different from each other, so that the read operation can be performed smoothly even when the latch is insufficient.

[0148] Figure 13 This is a flowchart illustrating an operation method of a memory device according to one embodiment. For example, Figure 13 The operation method shown can be provided by Figure 2 The memory device 100 shown is executed.

[0149] refer to Figure 13 In operation S1301, the memory device 100 can perform a latch setting operation to set the data stored in the latch.

[0150] In operation S1303, when performing a latch setting operation, the memory device 100 can discharge multiple bit lines connected to multiple memory cells.

[0151] In operation S1305, memory device 100 can determine whether the latch setting operation has been completed. If, based on the determination result in operation S1305, the latch setting operation has not been completed, memory device 100 can perform the latch setting operation until the latch setting operation is completed. If, based on the determination result in operation S1305, the latch setting operation is completed, then in operation S1307, memory device 100 can precharge multiple bit lines.

[0152] Figure 14 This is a flowchart illustrating a method for discharging a bit line according to one embodiment. For example, Figure 14 The method shown can be derived from Figure 2 The memory device 100 shown is executed.

[0153] refer to Figure 14 In operation S1401, memory device 100 can turn off the transistor connected between the node connected to the multiple bit lines and the common sensing node. In operation S1403, memory device 100 can apply a reference (e.g., ground) power supply to the node connected to the multiple bit lines using the transistor connected between the node connected to the multiple bit lines and the ground power supply.

[0154] Figure 15 This is a flowchart illustrating a method for discharging a bit line according to one embodiment. For example, Figure 15 The method shown can be derived from Figure 2 The memory device 100 shown executes, and can be with Figure 14 The methods shown are different from those used for discharging bit lines.

[0155] refer to Figure 15 In operation S1501, memory device 100 may turn off the transistor connected between the node connected to the supply voltage and the common sensing node. In operation S1503, memory device 100 may apply a reference (e.g., ground) power supply to the node connected to the plurality of bit lines. The reference power supply may be connected to the plurality of bit lines via a transistor connected between the node connected to the plurality of bit lines and the ground power supply.

[0156] According to one embodiment, an apparatus may include a controller connected to at least one page buffer. The at least one page buffer may be connected to a memory cell via one or more corresponding bit lines. The controller is configured to generate a first signal, a second signal, and a third signal, the first signal controlling a latch to store data sensed from the bit lines, the second signal controlling a latch setting operation including setting data stored in the latch during a verification operation of the memory cell, and the third signal discharging the bit lines while the latch setting operation is being performed. The latch, latch setting operation, and discharging operation may be latches, latch setting operations, and discharging operations described with respect to any embodiment described herein. Therefore, the first to third signals may be embodiments described herein (including, but not limited to, embodiments described herein). Figures 8 to 12Any control signal, command, or instruction described in the embodiments herein. For example, the apparatus may be a memory device, a host, a page buffer, or any other circuitry or logic described herein.

[0157] Figure 16 It is a diagram. Figure 1 A diagram illustrating one embodiment of the memory controller. (Reference) Figure 1 and Figure 16 The memory controller 200 may include a processor 220, RAM 230, error correction circuitry 240, ROM 260, host interface 270, and flash memory interface 280.

[0158] The processor 220 can control the overall operation of the memory controller 200.

[0159] For example, RAM 230 can be used as a buffer memory, cache memory, working memory, etc. of memory controller 200.

[0160] Error correction circuitry 240 can perform error correction. In one embodiment, error correction circuitry 240 can perform error correction code (ECC) encoding on data to be written to a memory device via flash interface 280. ECC-decoded data can be transmitted to the memory device via flash interface 280. Error correction circuitry 240 can also perform ECC decoding on data received from the memory device via flash interface 280. As an example, error correction circuitry 240 can be included as a component of flash interface 280.

[0161] ROM 260 can store various forms of information to support the operation of memory controller 200. This information can be stored, for example, in the form of firmware.

[0162] The memory controller 200 can communicate with external devices (e.g., host 300, application processor, etc.) via host interface 270. The memory controller 200 can communicate with the memory device 100 via flash interface 280. The memory controller 200 can transmit commands (CMD), addresses (ADDR), control signals (CTRL), and / or other information to the memory device 100 via flash interface 280, and can also receive data (DATA). Flash interface 280 may include, for example, a NAND interface.

[0163] Figure 17 This is a block diagram illustrating a memory card system for use with a storage device according to one embodiment. (Reference) Figure 17 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0164] Memory controller 2100 is connected to memory device 2200 to access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can serve as an interface between memory device 2200 and host computer. Memory controller 2100 drives firmware for controlling memory device 2200 and can be configured with reference to... Figure 1 The memory controller 200 described is implemented in a similar or identical manner. In one embodiment, it can be implemented in a manner similar to that described in the reference. Figure 2 The memory device 2200 is implemented in a similar or identical manner to the memory device 100 described.

[0165] The memory controller 2100 may include various components such as random access memory (RAM), processing unit, host interface, memory interface and ECC circuitry.

[0166] The memory controller 2100 can communicate with external devices via connector 2300. In one embodiment, the memory controller 2100 can communicate with external devices (e.g., a host) according to one or more communication protocols. Examples include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. Exemplarily, connector 2300 can be defined by at least one of the various communication protocols described above.

[0167] The memory device 2200 can be implemented using a variety of non-volatile memory devices. Examples include electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0168] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. Examples of memory cards include PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, and eMMC), SD cards (SD, miniSD, microSD, and SDHC), and universal flash memory (UFS).

[0169] Figure 18 This is a block diagram illustrating a solid-state drive (SSD) system to which a storage device can be applied, according to one embodiment. Reference Figure 18 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0170] In one embodiment, the SSD controller 3210 can be used as a reference. Figure 1 The memory controller 200 is described. The SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG can be a signal based on the interface between the host 3100 and the SSD 3200. The signal SIG can be a signal defined by at least one interface, examples of which include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0171] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power PWR input from host 3100 and can charge the power PWR. When the power supply from host 3100 deviates from a predetermined state (e.g., becomes unstable or does not conform to the desired waveform), auxiliary power supply 3230 can provide power to SSD 3200. Auxiliary power supply 3230 can be located within or outside of SSD 3200. In one embodiment, auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0172] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, and / or may temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 may include one or more types of volatile memory. Examples include DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0173] Figure 19 This is a block diagram illustrating a user system to which a storage device can be applied, according to one embodiment. (Reference) Figure 19 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0174] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include a controller for controlling components, interfaces, graphics engines, etc., included in user system 4000. In one embodiment, application processor 4100 may be provided as a system-on-chip (SoC).

[0175] For example, memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory or non-volatile random access memory, such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, and non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, application processor 4100 and memory module 4200 may be provided as a single semiconductor package (e.g., a stacked package (POP)).

[0176] Network module 4300 can communicate with one or more external devices and can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0177] Storage module 4400 can store, for example, data received from application processor 4100. In one embodiment, storage module 4400 can transfer the data stored therein to application processor 4100. In one embodiment, storage module 4400 can be implemented using a non-volatile semiconductor memory device. Examples include phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. For example, storage module 4400 can be provided, for example, as a removable drive, such as a memory card of user system 4000 or an external drive.

[0178] For example, the storage module 4400 may include a plurality of non-volatile memory devices, which can be used in conjunction with a reference. Figure 1 The memory device 100 described operates in a similar or identical manner. In one embodiment, the memory module 4400 can operate in a manner similar to or the same as described. Figure 1 The storage devices operate in a similar or identical manner to the 50 other storage devices.

[0179] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. User interface 4500 may include one or more user input interfaces. Examples include a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include one or more user output interfaces. Examples include liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0180] According to one or more embodiments of the foregoing embodiments, a memory device and a method for operating the memory device are provided, the memory device and the method having improved performance in terms of reliability, efficiency and / or other operational properties.

[0181] As used herein, the terms “connection” and “coupling” can include a direct connection between two elements or an indirect connection between two elements. An indirect connection can include a situation where one or more elements are connected between two elements.

[0182] The methods, processes, and / or operations described herein can be performed by code or instructions that will be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be any of the elements described herein or other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can transform a computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0183] The controllers, processors, interfaces, calibration circuits, decoders, generators, logic, and other signal generation and signal processing features of the embodiments disclosed herein can be implemented, for example, with non-transient logic that may include hardware, software, or both hardware and software. When implemented at least partially in hardware, the controllers, processors, interfaces, calibration circuits, decoders, generators, logic, and other signal generation and signal processing features can be, for example, any of a variety of integrated circuits, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, systems-on-a-chip (SoCs), microprocessors, or other types of processing or control circuitry.

Claims

1. A memory device, comprising: Multiple memory cells are programmed into one of multiple programming states based on a threshold voltage. as well as Multiple page buffers are coupled to the multiple memory cells via multiple bit lines. Each of the plurality of page buffers includes a latch that stores data sensed from a corresponding bit line among the plurality of bit lines, and during a latch setting operation, each of the plurality of page buffers discharges the corresponding bit line, the latch setting operation including setting the data stored in the latch during a verification operation of the plurality of programming states.

2. The memory device of claim 1, wherein each of the plurality of page buffers comprises: A first transistor is connected between a common sensing node and a first node, the first node being connected to the corresponding bit line; A second transistor is connected between the common sensing node and the second node, and the second node is connected to the power supply voltage. as well as The third transistor is connected between the first node and the reference power supply.

3. The memory device of claim 2, wherein when the corresponding bit line is discharged, each of the plurality of page buffers turns off the first transistor and applies the reference power supply to the first node through the third transistor.

4. The memory device of claim 2, wherein when the corresponding bit line is discharged, each of the plurality of page buffers turns off the second transistor and applies the reference power supply to the first node through the third transistor.

5. The memory device of claim 2, wherein each of the plurality of page buffers further comprises: A fourth transistor is connected between the sensing node and the supply voltage; A fifth transistor is connected between the sensing node and the second node; A sixth transistor is connected between the sensing node and the common sensing node; as well as A seventh transistor is connected between the common sensing node and the latch node.

6. The memory device of claim 5, wherein when the latch setting operation is performed, each of the plurality of page buffers turns off the fifth transistor, the sixth transistor, and the seventh transistor, applies the supply voltage to the sensing node through the fourth transistor, and transmits the supply voltage to the node of the latch through the sensing node.

7. The memory device of claim 1, wherein the latch setting operation is an operation of storing a first logic value in a corresponding latch of a page buffer connected to a bit line during a verification operation of a second programming state of the plurality of programming states, the verification operation of the second programming state being performed on that bit line, and the verification operation of the second programming state being performed after the verification operation of the first programming state of the plurality of programming states is completed.

8. The memory device of claim 2, wherein after the latch setting operation is completed, each of the plurality of page buffers precharges the corresponding bit line.

9. The memory device of claim 8, wherein when the plurality of bit lines are precharged, each of the plurality of page buffers turns off the third transistor and applies the supply voltage to the first node through the first transistor and the second transistor.

10. The memory device of claim 2, wherein each of the plurality of page buffers further comprises an eighth transistor connected between the supply voltage and the common sensing node, and When a read operation is performed on the plurality of memory cells, each of the plurality of page buffers precharges the plurality of bit lines by turning off the second transistor and the third transistor and applying the supply voltage to the first node via the first transistor and the eighth transistor.

11. A page buffer, the page buffer being coupled to a plurality of memory cells via bit lines, the page buffer comprising: A latch that stores data sensed from the bit line; A latch setting circuit performs a latch setting operation, which includes setting data stored in the latch during a verification operation of the plurality of memory cells; as well as The bit line controller discharges the bit line while the latch setting operation is being performed.

12. The page buffer of claim 11, wherein the bit line controller comprises: A first transistor is connected between a common sensing node and a first node, the first node being connected to the bit line; A second transistor is connected between the common sensing node and the second node, and the second node is connected to the power supply voltage. as well as The third transistor is connected between the first node and the reference power supply.

13. The page buffer of claim 12, wherein the bit line controller discharges the bit line by turning off the first transistor and applying the reference power supply to the first node via the third transistor.

14. The page buffer of claim 12, wherein the bit line controller discharges the bit line by turning off the second transistor and applying the reference power supply to the first node via the third transistor.

15. The page buffer of claim 12, wherein the latch setting circuitry comprises: A fourth transistor is connected between the sensing node and the supply voltage; A fifth transistor is connected between the sensing node and the second node; A sixth transistor is connected between the sensing node and the common sensing node; as well as A seventh transistor is connected between the common sensing node and the latch node.

16. The page buffer of claim 15, wherein the latch setting circuit performs the latch setting operation by turning off the fifth transistor, the sixth transistor, and the seventh transistor, applying the supply voltage to the sensing node via the fourth transistor, and transmitting the supply voltage to the latch node via the sensing node.

17. The page buffer of claim 11, wherein after the latch setting operation is completed, the bit line controller precharges the bit line.

18. A method for operating a memory device, the memory device comprising a plurality of memory cells programmed to one of a plurality of programming states divided based on a threshold voltage, the method comprising: Perform a latch setting operation, which includes setting data stored in the latch during the verification operation of the plurality of programming states; When performing the latch setting operation, the bit lines connected to the plurality of memory cells are discharged; as well as Precharge the bit line based on whether the latch setting operation has been completed.

19. The method of claim 18, wherein the discharge of the bit line comprises: Turn off the first transistor connected between the common sensing node and the first node, the first node being connected to the bit line; as well as The reference power supply is applied to the first node via a second transistor connected between the reference power supply and the first node.

20. The method of claim 18, wherein the discharge of the bit line comprises: Turn off the third transistor connected between the common sensing node and the second node, the second node being connected to the supply voltage; as well as A reference power supply is applied to the first node connected to the bit line via a fourth transistor connected between the first node and the reference power supply.

Images