Read retry threshold optimization system and method conditioned on previous reads

Abstract

A memory system is disclosed. The memory system includes a memory device and a controller. The controller optimizes read retry thresholds of the memory device using one or more previous reads and a condition. The controller determines a read level table based on the condition indicative of a state of the memory device and selects an entry among a plurality of entries in the selected read level table based on a historical read threshold. For the selected entry, the controller: determines failed bits of data associated with a plurality of read operations to a plurality of cells using a plurality of read retry thresholds; and determines an order of the plurality of read retry thresholds based on a determination of the failed bits.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a scheme for optimizing a read retry threshold in a memory system. BACKGROUND

[0002] The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having a memory device (i.e., a data storage device). The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic device.

[0003] Because a memory system using a memory device does not have moving parts, it provides excellent stability, durability, high information access speed, and low power consumption. Examples of the memory system having such advantages include a universal serial bus (USB) memory device, a memory card having various interfaces such as universal flash storage (UFS), and a solid state drive (SSD). The memory system can perform a read operation using various read biases, levels, or thresholds (e.g., a read retry threshold). SUMMARY

[0004] Aspects of the present invention include a memory system and a method for optimizing a read retry threshold based on one or more previous reads and conditions of the memory system.

[0005] In an aspect, a memory system includes a memory device having a plurality of cells and a controller. The controller: determines a read level table based on a condition indicative of a state of the memory device, the read level table including a plurality of entries, each entry including a set of read thresholds, the set of read thresholds including a history read threshold and a plurality of read retry thresholds; and selects an entry among the plurality of entries of the selected read level table based on the history read threshold. For the selected entry, the controller: determines failed bits of data associated with a plurality of read operations to the plurality of cells using the plurality of read retry thresholds; and determines an order of the plurality of read retry thresholds based on the determination of the failed bits.

[0006] In another aspect, a method for operating a memory system, the memory system including a memory device and a controller, the memory device including a plurality of cells, includes determining a read level table based on a condition indicative of a state of the memory device, the read level table including a plurality of entries, each entry including a set of read thresholds, the set of read thresholds including a history read threshold and a plurality of read retry thresholds; and selecting an entry among the plurality of entries of the selected read level table based on the history read threshold. For the selected entry, the method includes determining failed bits of data associated with a plurality of read operations to the plurality of cells using the plurality of read retry thresholds; and determining an order of the plurality of read retry thresholds based on the determination of the failed bits.

[0007] In yet another aspect, a memory system includes a memory device having a plurality of cells and a controller. The controller determines a read level table based on a condition indicative of a state of the memory device, the read level table including a plurality of entries, each entry including a set of read thresholds, the set of read thresholds including a history read threshold and a plurality of read retry thresholds. The controller determines whether the history read threshold is included in a set of default read thresholds, the set of default read thresholds corresponding to a plurality of history read thresholds in the plurality of entries. The controller determines whether the condition corresponds to any one of a plurality of defined conditions. When it is determined that the history read threshold is included in the set of default read thresholds and the condition corresponds to any one of the plurality of defined conditions, the controller selects an entry among the plurality of entries in the selected read level table based on the history read threshold. For the selected entry, the controller: determines failed bits of data associated with a plurality of read operations to the plurality of cells using the plurality of read retry thresholds; and determines an order of the plurality of read retry thresholds based on the determination of the failed bits.

[0008] Other aspects of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram illustrating a data processing system according to an embodiment of the present application.

[0010] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the present application.

[0011] Figure 3 is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present application.

[0012] Figure 4 is a graph illustrating a state distribution of different types of cells of a memory device.

[0013] Figure 5 is a graph illustrating a memory system according to an embodiment of the present disclosure.

[0014] Figure 6 is a diagram illustrating an example of Gray coding for a three-layer cell (TLC).

[0015] Figure 7 is a diagram illustrating a state distribution of a page of a three-layer cell (TLC).

[0016] Figure 8A is a diagram illustrating a read level table.

[0017] Figure 8B and Figure 8C is a diagram illustrating a read level table according to an embodiment of the present application.

[0018] Figure 9 is a diagram illustrating an operation of selecting a read retry threshold according to an embodiment of the present application.

[0019] Figure 10 is a flow diagram illustrating a read retry threshold operation of a memory device.

[0020] Figures 11 to 13 is a diagram illustrating a scheme for determining a selection order of a read retry threshold according to an embodiment of the present application.

[0021] Figure 14 is a flow diagram illustrating a scheme for determining a selection order of a read retry threshold according to an embodiment of the present application.

[0022] Figure 15 is a chart illustrating a performance comparison between a fixed read retry threshold selection scheme and a selection operation of a read retry threshold according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] Various embodiments will be described in detail below with reference to the drawings. The present application may, however, be embodied in different forms and thus should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. Further, reference to "an embodiment," "another embodiment," etc., in this disclosure does not necessarily refer to the same embodiment, and different embodiments can include different features. Like reference numerals in the drawings and in the description below mean the same element throughout.

[0024] The present application can be implemented in numerous ways, including as a process; an apparatus; a system; a computer program product (which can be implemented on a computer-readable storage medium); and / or as a processor, such as a processor configured to fetch and execute instructions. Typically, steps of disclosed processes can be performed in a different order, unless otherwise specified. Components described as being adapted to perform a task, such as a processor or a memory, can be implemented as a general component temporarily configured to perform the task at a given time or as a specific component manufactured to perform the task. As used herein, the term "processor" and the like refers to one or more devices, circuits, and / or processing cores adapted to process data, such as computer program instructions.

[0025] A detailed description of embodiments of the present application is provided below along with accompanying figures that illustrate the aspects of the present application. The present application is described in connection with these embodiments, but is not limited to any embodiment. The scope of the application is limited only by the claims. Numerous alternatives, modifications and equivalents of the present application are encompassed by the scope of the claims. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. The present application can be practiced without some or all of these specific details. In other instances, well known

[0026] Figure 1 is a block diagram illustrating a data processing system 2 according to an embodiment of the present application.

[0027] Referring to Figure 1 The data processing system 2 can include a host device 5 and a memory system 10. The memory system 10 can receive a request from the host device 5 and operate in response to the received request. For example, the memory system 10 can store data to be accessed by the host device 5.

[0028] The host device 5 can be implemented with any one of various electronic devices. In various embodiments, the host device 5 can include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 can include a portable electronic device such as a mobile phone, a smart phone, an electronic book, an MP3 player, a portable multimedia player (PMP), and / or a portable game machine.

[0029] The memory system 10 can be implemented with any one of various storage devices such as a solid state drive (SSD) and a memory card. In various embodiments, the memory system 10 can be provided as one of various components in an electronic device such as a computer, an ultra mobile personal computer (PC) (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an electronic book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, and one of various electronic devices of a home network, one of various electronic devices of a computer network, one of electronic devices of a telematics network, or one of various components of a computing system.

[0030] The memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control overall operations of the semiconductor memory device 200.

[0031] The semiconductor memory device 200 can perform one or more erase operations, program operations, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive a command CMD, an address ADDR, and data DATA through input / output lines. The semiconductor memory device 200 can receive power PWR through a power supply line and a control signal CTRL through a control line. The control signal CTRL can include a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals, according to the design and configuration of the memory system 10.

[0032] The memory controller 100 and the semiconductor memory device 200 can be integrated in a single semiconductor device such as a solid state drive (SSD). The SSD can include a storage device for storing data therein. When the memory system 10 is used in the SSD, the operating speed of a host device (e.g., the host device 5 of FIG. 1) coupled to the memory system 10 can be significantly improved. Figure 1

[0033] ​The memory controller 100 and the semiconductor memory device 200 can be integrated in a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be so integrated to configure a Personal Computer (PC) card of Personal Computer Memory Card International Association (PCMCIA), a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a MultiMediaCard (MMC), a Reduced Size MMC (RS-MMC), a micro-sized version of MMC (micro- MMC), a Secure Digital (SD) card, a mini Secure Digital (mini-SD) card, a micro Secure Digital (micro-SD) card, a High Capacity Secure Digital (SDHC), and / or a Universal Flash Storage (UFS).

[0034] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the present application. For example, Figure 2 The memory system of Figure 1 The memory system 10 illustrated in FIG. 1.

[0035] Referring to Figure 2 The memory system 10 can include a controller 100 and a memory device 200. The memory system 10 can operate in response to a request from a host device (e.g., the host device 5 of Figure 1 The memory system 10 can store data to be accessed by the host device.

[0036] The memory device 200 can store data to be accessed by the host device.

[0037] The memory device 200 can be implemented with a volatile memory device such as Dynamic Random Access Memory (DRAM) and / or Static Random Access Memory (SRAM) or a non-volatile memory device such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Ferroelectric Random Access Memory (FRAM), Phase-Change RAM (PRAM), Magneto-resistive RAM (MRAM), and / or Resistive RAM (RRAM).

[0038] The controller 100 can control storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device and can store data provided from the host device into the memory device 200.

[0039] The controller 100 can include a storage 110, a control component 120, an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150 coupled through a bus 160, and the control component 120 can be implemented as a processor such as a central processing unit (CPU).

[0040] The storage 110 can serve as a working memory of the memory system 10 and the controller 100, and store data for driving the memory system 10 and the controller 100. When the controller 100 controls the operation of the memory device 200, the storage 110 can store data used by the controller 100 and the memory device 200 for operations such as a read operation, a write operation, a program operation, and an erase operation.

[0041] The storage 110 can be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage 110 can store data used by the host device in the memory device 200 for read and write operations. To store data, the storage 110 can include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, etc.

[0042] The control component 120 can control general operations of the memory system 10 in response to a corresponding request from the host device, and in particular, write and read operations with respect to the memory device 200. The control component 120 can drive firmware called a flash translation layer (FTL) to control general operations of the memory system 10. For example, the FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. The L2P mapping is referred to as a logical block address (LBA).

[0043] During a read operation, the ECC component 130 can detect and correct errors in data read from the memory device 200. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 can not correct the error bits, but can output an error correction failure signal indicating a failure to correct the error bits.

[0044] In various embodiments, the ECC component 130 can perform error correction operations based on encoding modulation such as Low-Density Parity-Check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, turbo product code (TPC), Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM), or block coded modulation (BCM). However, error correction is not limited to these techniques. Thus, the ECC component 130 can include any and all circuitry, systems, or devices suitable for error correction operations.

[0045] The host interface 140 can communicate with a host device through one or more of various interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advance Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and / or Integrated Drive Electronics (IDE).

[0046] The memory interface 150 can provide an interface between the controller 100 and the memory device 200 to allow the controller 100 to control the memory device 200 in response to a request from the host device. The memory interface 150 can generate a control signal for the memory device 200 and process data under the control of the control component 120. When the memory device 200 is a flash memory such as NAND flash memory, the memory interface 150 can generate a control signal for the memory and process data under the control of the control component 120.

[0047] The memory device 200 can include a memory cell array 210, a control circuit 220, a voltage generating circuit 230, a row decoder 240, a page buffer array 250 which can be in the form of an array of page buffers, a column decoder 260, and an input and output (input / output) circuit 270. The memory cell array 210 can include a plurality of memory blocks 211 which can store data. The voltage generating circuit 230, the row decoder 240, the page buffer array 250, the column decoder 260, and the input / output circuit 270 can form a peripheral circuit for the memory cell array 210. The peripheral circuit can perform a program operation, a read operation, or an erase operation on the memory cell array 210. The control circuit 220 can control the peripheral circuit.

[0048] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as an erase voltage and a pass voltage.

[0049] The row decoder 240 can be in electrical communication with the voltage generation circuit 230 and the plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220, and transmit an operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0050] The page buffer array 250 can be coupled to the memory cell array 210 through bit lines BL (shown in FIG. 1) and word lines WL (shown in FIG. 1). The page buffer array 250 can pre-charge the bit lines BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, transmit and receive data to and from the selected memory block in programming and reading operations, or temporarily store the transmitted data. Figure 3

[0051] The column decoder 260 can transmit and receive data to and from the page buffer array 250, and can transmit and receive data to and from the input / output circuit 270.

[0052] The input / output circuit 270 can transmit a command and an address received from an external device (e.g., the memory controller 100 of FIG. 1) to the control circuit 220, transmit data from the external device to the column decoder 260, or output data from the column decoder 260 to the external device through various lines. Figure 1

[0053] The control circuit 220 can control the peripheral circuit in response to the command and the address.

[0054] Figure 3 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present application. For example, the memory block of FIG. 1 can be any one of the memory blocks 211 of the memory cell array 210 shown in FIG. 1. Figure 3 Figure 2

[0055] Referring to FIG. 2, Figure 3 the exemplary memory block 211 can include a plurality of word lines WLO to WLn-1, a drain select line DSL, and a source select line SSL coupled to the row decoder 240. These lines can be arranged in parallel with a plurality of word lines between the DSL and the SSL.

[0056] ​​​​The example memory block 211 can further include a plurality of cell strings 221 coupled to bit lines BL0 through BLm-1, respectively. Each column of cell strings can include one or more drain select transistors DST and one or more source select transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, a plurality of memory cells or memory cell transistors MC0 through MCn-1 can be coupled in series between the select transistors DST and SST. Each of the memory cells can be formed as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, or a quad-level cell (QLC) storing 4 bits of data.

[0057] The source of the SST in each cell string can be coupled to a common source line CSL, and the drain of each DST can be coupled to a respective bit line. The gate of the SST in a cell string can be coupled to the SSL, and the gate of the DST in a cell string can be coupled to the DSL. The gates of the memory cells on a cell string can be coupled to a respective word line. That is, the gate of memory cell MC0 is coupled to a respective word line WL0, the gate of memory cell MC1 is coupled to a respective word line WL1, and so on. A group of memory cells coupled to a particular word line can be referred to as a physical page. Thus, the number of physical pages in the memory block 211 can correspond to the number of word lines.

[0058] The page buffer array 250 can include a plurality of page buffers 251 coupled to the bit lines BL0 through BLm-1. The page buffers 251 can operate in response to page buffer control signals. For example, during a read operation or a verify operation, the page buffers 251 can temporarily store data received through the bit lines BL0 through BLm-1 or sense the voltage or current of the bit lines.

[0059] In some embodiments, the memory block 211 can include NAND-type flash memory cells. However, the memory block 211 is not limited to this type of cell, but can include NOR-type flash memory cells. The memory cell array 210 can be implemented as a hybrid flash memory combining two or more types of memory cells, or one-NAND flash memory in which a controller is embedded inside a memory chip.

[0060] Figure 4 is a graph illustrating a distribution of states or program voltage (PV) levels of different types of cells of a memory device.

[0061] As described above, each of the memory cells can be implemented with a particular type of cell such as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, or a quad-level cell (QLC) storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required. Figure 4 The states of each of these types of cells are shown.

[0062] An SLC can include two states P0 and P1. P0 can represent an erased state and P1 can represent a programmed state. Because an SLC can be set to one of two different states, each SLC can program or store 1 bit according to a set encoding method. An MLC can include four states P0, P1, P2, and P3. Among these states, P0 can represent an erased state and P1 through P3 can represent programmed states. Because an MLC can be set to one of four different states, each MLC can program or store two bits according to a set encoding method. A TLC can include eight states P0 through P7. Among these states, P0 can represent an erased state and P1 through P7 can represent programmed states. Because a TLC can be set to one of eight different states, each TLC can program or store three bits according to a set encoding method. A QLC can include sixteen states P0 through P15. Among these states, P0 can represent an erased state and P1 through P15 can represent programmed states. Because a QLC can be set to one of sixteen different states, each QLC can program or store four bits according to a set encoding method.

[0063] Figure 5 is a diagram illustrating a memory system 10 according to an embodiment of the present disclosure.

[0064] Referring to Figure 5 The memory system 10 includes a controller 100 and a memory device 200. The memory device 200 can include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged as Figure 3The illustrated array is arranged in rows and columns. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are connected to a bit line (e.g., BL0). These word lines and bit lines are used for read operations and write operations. During a write operation, the data to be written ("1" or "0") is provided to the bit line when the word line is asserted. During a read operation, the word line is again asserted and then the threshold voltage of each cell can be obtained from the bit line. Multiple pages can share memory cells coupled to the same word line. When the memory cells are implemented with MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented with TLC, the multiple pages include a MSB page, a center significant bit (CSB) page, and a LSB page. When the memory cells are implemented with QLC, the multiple pages include a MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page, and a LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) in order to increase the capacity of the memory system 10, such as an SSD.

[0065] Figure 6 is a diagram illustrating an example of Gray encoding for triple level cell (TLC).

[0066] Referring to Figure 6 TLC can be programmed using Gray encoding. As described above, TLC can have 8 programming states, including an erase state E (or PV0) and first through seventh programming states PV1-PV7. The erase state E (or PV0) can correspond to "110". The first programming state PV1 can correspond to "011". The second programming state PV2 can correspond to "001". The third programming state PV3 can correspond to "000". The fourth programming state PV4 can correspond to "010". The fifth programming state PV5 can correspond to "110". The sixth programming state PV6 can correspond to "100". The seventh programming state PV7 can correspond to "101".

[0067] In TLC, as Figure 7As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds are a first threshold VT0 and a second threshold VT4. The first threshold VT0 distinguishes between erase state E and first programming state PV1. The second threshold VT4 distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds are a first threshold VT1, a second threshold VT3, and a third threshold VT5. The first threshold VT1 distinguishes between first programming state PV1 and second programming state PV2. The second threshold VT3 distinguishes between third programming state PV3 and fourth programming state PV4. The third threshold VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds are a first threshold VT2 and a second threshold VT6. The first threshold VT2 distinguishes between second programming state PV2 and third programming state PV3. The second threshold VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0068] Re-reference Figure 5 The controller 100 may include a read processor 510, a decoder 520, and a read threshold optimizer 530. These components may be provided by... Figure 2 The control component 120 or its internal components (i.e., firmware (FW)) are used to implement this. Although in Figure 5 Not shown, but the controller 100 and memory device 200 may include, for example... Figure 2 The various other components shown.

[0069] The read processor 510 can respond to data from the host (e.g., Figure 1 The read processor 510 controls read operations on the memory device 200 based on read requests from the host device 5). The read processor 510 can control read operations based on various read thresholds. The decoder 520 can decode the data associated with the read operation.

[0070] In some embodiments, the read processor 510 can use a selected read threshold from a set read level table to control read operations on memory cells. In some embodiments, the read level table may include multiple read thresholds, and the selected read threshold may include a default read threshold. Figure 7 As shown, when performing a read operation on the MSB page of a TLC, the selection of read thresholds can include a pair of first read thresholds and second read thresholds [VT0, VT4]. The first read threshold VT0 is used to distinguish between the erase state (i.e., E) and the first programming state (i.e., PV1), and the second read threshold VT4 is used to distinguish between the fourth programming state (i.e., PV4) and the fifth programming state (i.e., PV5). Figure 7As shown, when a read operation is performed on an LSB page of the TLC, the selection of the read threshold can include a pair of first and second read thresholds [VT2, VT6]. The first read threshold VT2 is used to distinguish between the second program state (i.e., PV2) and the third program state (i.e., PV3), and the second read threshold VT6 is used to distinguish between the sixth program state (i.e., PV6) and the seventh program state (i.e., PV7).

[0071] From the decoding result of the decoder 520, it can be determined whether the read operation using the selected read threshold from the read threshold set is successful or failed. When the read operation using the selected read threshold fails, the read processor 510 can use a read retry threshold to control one or more read retry operations for the memory cell. In some embodiments, read retry involves performing 5 different read attempts with different but static read threshold settings.

[0072] In general, the memory cells of the memory device 200 gradually wear out due to program-erase (P / E) cycles, and the default read threshold is not optimal under all retention and read disturbance conditions. When the number of bit errors in a page to be read exceeds the error correction capability (i.e., error correction code (ECC) correction capability) of the error correction scheme in the decoder, additional read attempts are needed for data recovery to successfully decode the page with different read threshold biases. The first two steps of data recovery involve performing a historical (or history) read and a high priority read (i.e., read retry read). The successful read threshold associated with the last successful decode is tracked and maintained in a set of historical read thresholds, and the historical read threshold is used in the first step of the additional read attempts. If the decode fails after using the historical read threshold, multiple other read attempts (i.e., high priority read or HRR) are made. The high priority read thresholds are static; that is, the order of the high priority read thresholds used for read retry is predetermined and does not change during the lifetime of the memory system (e.g., SSD).

[0073] Accordingly, unlike using a fixed HRR order, various embodiments provide a read retry threshold optimization scheme that is able to obtain the optimal HRR for each of all possible historical read thresholds given the conditions of the memory system (i.e., NAND conditions). The read retry threshold optimization scheme can improve the read quality of service (QoS) of the memory system without changing the memory system hardware.

[0074] Referring back to Figure 5 , the controller 100 can include a read level table. For example, the read level table can be used to determine the read threshold to use for a read operation based on the read level of the memory cell. Figure 2implemented within the storage device 110. The read level table can store a plurality of read thresholds (e.g., K read thresholds RR0to RR K ), and can include a plurality of entries (e.g., K entries as shown in Figure 8A ). Each entry can correspond to each of the plurality of read thresholds, and include a set of read thresholds among the plurality of read thresholds. Each entry can include a history read threshold and a plurality of read retry thresholds. Note that the plurality of read retry thresholds in this and the following text indicates HRRs unless specifically defined. For example, as shown in Figure 8B , each entry can include 5 different read thresholds, including one read threshold as a history read threshold and 4 read thresholds as HRRs.

[0075] As described above, a static HRR ordering scheme can generally be used for read retry operations. According to the static HRR ordering scheme, the order of the plurality of read retry thresholds in each entry of the read level table is fixed. Figure 9 An example of a static HRR ordering scheme for two different conditions of a memory system (e.g., a TLC NAND SSD) is shown in

[0076] In the example shown in Figure 9 , it is assumed that there are two conditions: condition 1 (1K, LSB) and condition 2 (11K, LSB). 1K and 11K represent the number of erase / write (EW) cycles that occur when the HRR ordering scheme is applied, and LSB (i.e., least significant bit) represents the type of TLC page to be read. Under both conditions, it is assumed that there are 10 pages denoted by letters a to j, and only 3 different read biases {RR0, RR1, RR2} are available. The circles around the pages represent the RR iSuccessfully decoded pages. Under both conditions, pages {a,b,c,d} read through read threshold RR1 can be successfully decoded. Under condition 1, pages {e,f,g} read through read threshold RR0 can be successfully decoded, and pages {h,j} read through read threshold RR2 can be successfully decoded. Under condition 2, pages {c,d,e} read through read threshold RR0 can be successfully decoded, and pages {a,g,f} read through read threshold RR2 can be successfully decoded. Given a historical read threshold HR = RR1, the optimal read retry threshold HRR after HR differs for different conditions. Under condition 1, the optimal HRR set is ordered as [RR0, RR2]. Under condition 2, the optimal HRR set is ordered as [RR2, RR0]. The main reason for this difference is the different correlation between the number of pages that RR can correct under these conditions. Therefore, for at least one of these conditions, any static HRR ordering is suboptimal.

[0077] The read threshold optimizer 530 can execute optimal, non-static HRR sorting schemes. Figure 8B The results of the optimal HRR sorting scheme are shown in the figure.

[0078] exist Figure 8B In the example shown, there is a read level table HRR-LUT for condition (c). (c) The read level meter includes 50 entries. Each entry can correspond to each of multiple read thresholds and includes a set of read thresholds. The entries in the first row include the historical read threshold RR0 and the entries in the order RR. 10 RR 22 RR 49 and RR 42 Multiple read retry thresholds (i.e., HRR). The entries in the second row include the historical read threshold RR1 and the RR-ordered thresholds. 49 RR 44 RR 27 and RR 47 Multiple read retry thresholds. The entries in the third row include the historical read threshold RR2 and the sequence RR... 22 RR 49 RR 42 and RR 27 Multiple read retry thresholds. The entry in line 50 includes the historical read threshold RR. 49 The order is RR5, RR 18 RR 49 and RR 42 Multiple read retry thresholds are defined. Therefore, the read threshold optimizer 530 can determine different orders of read retry thresholds for different entries in the read level meter.

[0079] In some embodiments, the controller 100 can include a plurality of read level tables corresponding to a plurality of conditions, respectively. In Figure 8C In the illustrated example, the controller 100 can include L read level tables HRR-LUT1 through HRR-LUT L where L is an integer of 2 or greater. Each read level table can correspond to a particular condition. As an example and without any limitation, the following elements can be used to configure individual conditions: an accumulated erase / write (EW) cycle, a single page read (SPRD) cycle, and a type of page associated with a plurality of cells. That is, each condition can be a particular value from one or more of these condition elements. For example, the EW cycle values can be represented as EW = {1, 1k, 5k, 9k,..., ew max}. Similarly, the SPRD cycle values can be SPRD = {0, 500k,..., sprd max}. For TLC NAND cells, the page types include a most significant bit (MSB) page, a center significant bit (CSB) page, and a least significant bit (LSB) page. For QLC NAND cells, the page types include a MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page, and a LSB page. Thus, many different conditions can be configured by selecting particular values from one or more of the condition elements to cover a range of changes that can occur during the lifetime of a memory device (e.g., NAND).

[0080] The read threshold optimizer 530 can select a read level table among the plurality of read level tables based on a condition indicative of a state of the memory device. Further, the read threshold optimizer 530 can select an entry among a plurality of entries in the selected read level table based on a previous historical (historical) read threshold. In other words, the selected entry corresponds to the previous historical read threshold. Then, the read threshold optimizer 530 can count failed bits of data associated with a plurality of read operations on a plurality of cells using the plurality of read retry thresholds for a plurality of read thresholds (i.e., HRRs) of the selected entry.

[0081] Further, the read threshold optimizer 530 can determine an order of the plurality of read retry thresholds based on their failed bit counts. In some embodiments, the read threshold optimizer 530 can determine the order of the plurality of read retry thresholds by arranging the plurality of read retry thresholds in an ascending order of the failed bit counts. Referring to Figure 11 This determination operation is described in detail.

[0082] The state of the memory device can not be precisely defined by any combination of the values of the condition elements defined above. In this case, an extrapolation interpolation method is performed. That is, the read threshold optimizer 530 can determine two conditions among the possible conditions closest to the state of the memory device, select two read level tables corresponding to the two conditions, and interpolate between the two read level tables to generate an interpolated read level table. Refer to Figure 12 The interpolation operation is described in detail. Further, the read threshold optimizer 530 can perform the operations of selecting entries, counting fail bits, and determining the order of the plurality of read thresholds using the interpolated read level table described above.

[0083] In connection with generating the interpolated read level table, the previous history read threshold is extrapolated. In this case, the read threshold optimizer 530 can determine a set distance (e.g., Euclidean distance) between the previous history read threshold and each of the set of the plurality of read thresholds, and select a read threshold having the smallest distance among the set of the plurality of read thresholds. Refer to Figure 13 The determination operation is described in detail. Further, the read threshold optimizer 530 can determine entries with the selected read threshold as the history read threshold, and perform the operations of selecting entries, counting fail bits, and determining the order of the plurality of read thresholds described above.

[0084] Figure 10 is a flowchart illustrating a read retry threshold optimization operation 1000 according to an embodiment of the present application. The read retry threshold optimization operation 1000 can be performed by the read threshold optimizer 530 of the controller 100 in Figure 5 .

[0085] Refer to Figure 10 , at operation 1010, the read threshold optimizer 530 can select a read level table among the plurality of read level tables based on a condition indicating a state of the memory device. At operation 1020, the read threshold optimizer 530 can select an entry among a plurality of entries in the selected read level table based on a previous history read threshold.

[0086] For the selected entry, operations 1030 and 1040 can be performed. At operation 1030, the read threshold optimizer 530 can count fail bits for data associated with a plurality of read operations on a plurality of cells using a plurality of read retry thresholds. At operation 1040, the read threshold optimizer 530 can determine an order of the plurality of read retry thresholds based on the counting result of the fail bits. In some embodiments, the read threshold optimizer 530 can determine the order of the plurality of read retry thresholds by arranging the plurality of read retry thresholds in an ascending order of the fail bit counts.

[0087] As described above, the read threshold optimizer 530 can determine the order of each of the read retry thresholds (i.e., HRRs) according to one or more previous read attempts, current NAND conditions, and ECC correction capability. When a read operation is performed using the first read retry threshold (i.e., one HRR), the previous read attempts include read operations using the historical read threshold. When a read operation is performed using each of the remaining read retry thresholds, the previous read attempts include read operations using the historical read threshold and one or more previous read retry thresholds. Specifically, embodiments provide a Bayesian optimization algorithm to find the optimal HRR by considering i) all previous read attempts including the historical read, ii) ECC correction capability, and iii) NAND conditions. Refer to Figure 11 The algorithm is described. In addition, embodiments provide an algorithm to reduce the storage requirement of the HRRs determined by the Bayesian optimization algorithm. Refer to Figure 12 The algorithm is described. In addition, embodiments provide an algorithm to allow arbitrary historical read values to be used as inputs to the Bayesian optimization algorithm. Refer to Figure 13 The algorithm is described. The above algorithms can be combined and used as a read strategy called a smart RR read scheme. This read scheme significantly improves read latency by finding the optimal HRRs from the Bayesian optimization algorithm with a small additional storage cost.

[0088] Figure 11 and Figure 13 is a diagram illustrating a scheme (i.e., an optimal HRR ordering scheme) for determining the order of selecting read retry thresholds according to embodiments of the present application. The scheme can be performed by the read threshold optimizer 530 of the controller 100 implemented with firmware in Figure 5 In the following description, RR denotes a historical threshold, HRR denotes a read retry threshold, and a read threshold is sometimes also referred to as a read bias or level or voltage.

[0089] Refer to Figure 11 , the read threshold optimizer 530 can input information (conditions c, S RR , CC th ), perform operations of steps 1 to 5, and output HRRs c In Figure 11 , various information including input information is shown, which are defined as shown in the following List 1:

[0090] List 1:

[0091]

[0092] The read threshold optimizer 530 can collect a set S cAnd for the set S belonging to all possible RRs RR Historical read threshold RR H Perform steps 1 through 5.

[0093] In step 1, the read threshold optimizer 530 can read the set S of bias voltages from the default read threshold. RR Excluding historical read threshold RR H (Right now, To obtain S RR In the example shown in Figure 8, when the default read bias set includes {RR0, RR1, RR2, ..., RR...} 49 Furthermore, when the historical read bias is RR0, set S can be determined. RR Including {RR1, RR2, RR3, ..., RR 49}. When the default read bias set includes {RR0, RR1, RR... 2， ……, RR 49 Furthermore, when the historical read bias is RR1, set S can be determined. RR Including {RR0, RR2, RR3, ..., RR 49}

[0094] In step 2, the threshold optimizer 530 can be read using the equation This determines the set of available pages within the set of all pages under condition c. In this equation, S... c It is the set of available pages under condition c, and S success This indicates those belonging to set S c The page makes it accessible via the historical read threshold RR. H When reading, the corresponding failure bit count (FBC) is less than or equal to the ECC correction capability threshold (CC). th In other words, S success This indicates those that pass the historical read threshold RR H When reading, the page can be successfully decoded by the decoder.

[0095] In step 3, through the equation HRR c (RR H ) = RR H The read threshold optimizer 530 can be set for a given historical read threshold RR. H The optimal HRR order for condition c.

[0096] In step 4, the threshold optimizer 530 can be read using the equation Find RR *In this equation, P(FBC≤CC th |S c ) represents the probability that the failure bit count (FBC) is less than the ECC correction capability when the pages in the set S c are read with the read bias RR. In other words, P(FBC≤CC th |S c ) represents that the decoder can correct the pages if they are read with the read bias RR. In this way, the read threshold optimizer 530 can find the read bias RR (i.e., RR th ) having the highest decoding success opportunity (i.e., P(FBC≤CC c |S * )) among all the RR belonging to the set of default read biases.

[0097] Further, the read threshold optimizer 530 can append (or add) the read bias having the highest decoding success opportunity among the set of default read biases to the optimal HRR set. Hereinafter, the read threshold optimizer 530 can perform an operation of finding the read bias having the highest decoding success opportunity among the remaining read biases in the set of default read biases. The finding operation of the remaining read biases can be performed iteratively when it is determined that the condition in step 5 is satisfied.

[0098] In step 5, the read threshold optimizer 530 can determine whether at least one of the following two conditions is satisfied: (1) |HRR c (RR H )| > t; or (2) |S| is small. |HRR c (RR H )| represents the number of HRRs obtained from the Bayesian optimization algorithm under the condition c when the historical read threshold is RR H . t is t c , which represents the number of HRRs obtained from the Bayesian optimization algorithm. |S| represents the size of S c , which represents the set of remaining pages that have not been decoded by the decoder under the condition c. When one of the above two conditions is satisfied, i.e., all HRRs have been found or the number of remaining pages (e.g., 100) is small, the iterative operation of step 4 is stopped.

[0099] By the algorithm of Figure 11 , a read level table as shown in Figure 8B is configured. In Figure 8BWhen the historical read threshold RR0 in the first row is selected, a plurality of read retry thresholds can be used to perform a plurality of read operations. A fail bit can be obtained by decoding data associated with the plurality of read operations. An order of the plurality of read retry thresholds can be determined based on the fail bit count. In some embodiments, the plurality of read retry thresholds can be arranged in ascending order of the fail bit count. For example, the plurality of read retry thresholds can be arranged in the order of RR0→RR1→RR2→...→RRn. This ordering indicates that RR0has the highest decoding success chance among the plurality of read retry thresholds. 10 22 49 42 10 49 44 27 47 22 49 42 27 49 18 49 42

[0100] As described above, the Bayesian optimization algorithm generates HRR c for a condition c. In practice, it is infeasible to store HRR c for all possible NAND (i.e., memory device) conditions. This problem can be solved by storing HRR c for a selected set of conditions. As described above, the set of conditions needs to cover most of the variations that can occur in various dimensions of NAND development. Each NAND condition is (or can be approximated as) a combination of the number of erase / write (EW) cycles, the number of single page read (SPRD) cycles, and the page type (LCM). Thus, as shown in List 2, each of the conditions can include an array of values:

[0101] List 2:

[0102]

[0103] Referring to List 2, a selected set of conditions C can be defined as shown in List 3. ​​​​​​​​​​​​​​​​​

[0104] List 3:

[0105]

[0106] HRR given all conditions for c e C c , the read threshold optimizer 530 can use an interpolation scheme as shown in Figure 12 to obtain the optimal HRR for the missing condition . In other words, when a condition c' does not correspond to any of the defined condition combinations, the read threshold optimizer 530 can determine the two conditions c1, c2among the defined conditions that are closest to this condition c'.

[0107] Further, the read threshold optimizer 530 can select the two read level tables corresponding to the two conditions. In addition, the read threshold optimizer 530 can interpolate the two read level tables , generate an interpolated read level table, and use the interpolated read level table to execute the Bayesian optimization algorithm in Figure 11 . In some embodiments, the interpolation can be done with a linear or non-linear function; it depends on the size of the missing condition c' and the neighboring conditions c1, c2e C.

[0108] As mentioned above, Figure 11 the Bayesian optimization algorithm in RR generates the optimal HRR when the historical read threshold belongs to the set of default read biases (S RR ). Although the historical read bias starts from one of the default read biases, as the NAND evolves, the historical read bias can take any voltage value that does not necessarily belong to the default read biases S c . As such, if there is no HRR c (HR) in the table HRR c . In this case, the read threshold optimizer 530 can use an algorithm as shown in Figure 13 to find the default RR index that is closest to the current HR.

[0109] Referring to Figure 13 , VT HR (lcm) denotes the historical read voltage for the page type (lcm). For TLC cells, the page types can be {LSB page, CSB page, MSB page} and the historical read voltage has 7 up-shift values. Among the 7 read voltages, 2 read voltages are used for the LSB page, 2 read voltages are used for the MSB page, and 3 read voltages are used for the CSB page.

[0110] Given VT HR (lcm), the read threshold optimizer 530 can compute the optimal HRR for all RR e RRdefault distance d(VT HR (lcm)-, VT RR (lcm)). The historical read voltage (HR) can not belong to the set of S RR . For each RR i (e.g., S RR there are 50 available default read voltages), the read threshold optimizer 530 can calculate the set distance (d) between the historical read voltage of the page type lcm (i.e., VT HR (lcm)) and the RR of the page type lcm (i.e., i Among all the calculated distances, the read threshold optimizer 530 can find the index of the minimum distance (i). The Euclidean distance or any other suitable type of distance that can provide good estimation can be used.

[0111] As described above, when the historical read threshold is not included in the set of default read thresholds (which corresponds to the plurality of historical read thresholds in the plurality of entries of the read level table), the read threshold optimizer 530 can determine the set distance between the historical read threshold and each of the plurality of read thresholds, and select the historical read threshold having the minimum distance among the set of default read thresholds. Then, the read threshold optimizer 530 can perform the Bayesian optimization algorithm in Figure 11 using the selected read level table.

[0112] Figure 14 is a flowchart illustrating a scheme 1400 for determining the order of selecting read retry thresholds according to an embodiment of the present application.

[0113] Referring to Figure 14 , the scheme 1400 obtains a practical algorithm for using the optimal HRR for a specific condition in combination with all the previous algorithms in Figures 11 to 13 . For the scheme 1400, input information including a condition and a historical read threshold is provided at operation 1405. Operation 1410 can be selectively performed. After operation 1410 is performed, operation 1420 or operation 1430 can be performed according to the result of operation 1415. At operation 1415, it is determined whether there is a read level table corresponding to the specific condition. After operation 1420 or operation 1430 is performed, operation 1440 can be performed. Operation 1410 corresponds to the algorithm of Figure 13 . Operation 1420 corresponds to the algorithm of Figure 12 . Operation 1430 and operation 1440 correspond to the algorithm of Figure 11 . At operation 1440, the order of read retry thresholds HRR is determined based on the failed bit count, and the order of HRR is output.

[0114] Figure 15 is a graph showing a performance comparison between a read operation using a static read retry threshold selection scheme (i.e., a static read operation) and a read operation using an intelligent RR algorithm (i.e., an intelligent read operation) according to an embodiment of the present application.

[0115] Referring to Figure 15 , the x-axis represents program / erase cycles (PEC) and the y-axis represents latency (us). The average latency of the intelligent read operation (1530) is shown compared to the static read operations (1510, 1520). In the read operation 1510, the set of read thresholds for all conditions (i.e., different program / erase cycles) is fixed. The order of the read thresholds is as follows: RR H , RR0, RR1, RR2, RR3, RR4, …, RR 10 . The set of read thresholds does not change with the condition and is not dependent on the history read thresholds RR H . In the read operation 1520, the set of read thresholds does not change with the condition and is not dependent on the history read thresholds RR H . The simulation results indicate that the intelligent read operation reduces read latency and improves quality of service (QoS).

[0116] As described above, embodiments provide a scheme that is capable of obtaining an optimal read retry threshold (i.e., HRR) among all possible history read thresholds for a given condition (i.e., NAND condition) of a memory system. The read retry threshold optimization scheme can improve the read quality of service (QoS) of the memory system without changing the hardware of the memory system.

[0117] While the foregoing embodiments have been shown and described in considerable detail for the purposes of clarity and understanding, the present application is not limited to the provided details. As will be appreciated by a person skilled in the art, there are many alternatives that can be implemented to carry out the present application as understood from the foregoing disclosure. Accordingly, the disclosed embodiments are to be considered illustrative and not restrictive. The present application is intended to cover all alternatives, modifications and equivalents thereof falling within the scope of the claims.

Claims

1. A memory system, comprising: a memory device including a plurality of cells; and a controller coupled to the memory device and: selecting a read level table based on a condition, the condition indicative of a state of the memory device, the read level table including a plurality of entries, each entry including a set of read thresholds, the set of read thresholds including a history read threshold and a plurality of read retry thresholds; selecting an entry among the plurality of entries in the selected read level table based on the history read threshold; for the selected entry, using the plurality of read retry thresholds to determine failed bits of data associated with a plurality of read operations to the plurality of cells; and for the selected entry, determining an order of the plurality of read retry thresholds based on the determination of the failed bits.

2. The memory system of claim 1, wherein the condition includes a combination of an erase / write cycle value array (EW cycle value array), a single page read cycle value array (SPRD cycle value array), and a value of a type of page associated with the plurality of cells.

3. The memory system of claim 1, wherein the controller: determines the order of the plurality of read retry thresholds to be an ascending order of failed bit counts.

4. The memory system of claim 1, wherein the controller: determines two conditions closest to the condition when the condition does not correspond to any of a plurality of defined conditions; selects two read level tables corresponding to the two conditions; and uses the two read level tables to perform selecting an entry, determining failed bits, and determining an order of read thresholds.

5. The memory system of claim 4, wherein the controller: performs interpolation on the two read level tables to generate an interpolated read level table, and uses the interpolated read level table to perform selecting an entry, determining failed bits, and determining the order of the plurality of read thresholds.

6. The memory system of claim 1, wherein the controller: determines a set distance between the history read threshold and each of a plurality of read thresholds when the history read threshold is not included in a set of default read thresholds corresponding to the plurality of history read thresholds in the plurality of entries; and selects a history read threshold with a smallest distance among the set of default read thresholds.

7. The memory system of claim 6, wherein the controller: determines an entry with the selected read threshold as a history read threshold, counts failed bits and determines an order of the plurality of read thresholds.

8. The memory system of claim 6, wherein the set distance includes a Euclidean distance.

9. A method of operating a memory system, the memory system including a memory device and a controller, the memory device including a plurality of cells, the method comprising: selecting a read level table based on a condition, the condition indicative of a state of the memory device, the read level table including a plurality of entries, each entry including a set of read thresholds, the set of read thresholds including a history read threshold and a plurality of read retry thresholds; selecting an entry among the plurality of entries in the selected read level table based on the history read threshold; for the selected entry, using the plurality of read retry thresholds to determine failed bits of data associated with a plurality of read operations to the plurality of cells; and for the selected entry, determining an order of the plurality of read retry thresholds based on the determination of the failed bits. selecting an entry among a plurality of entries in a selected read level table based on the historical read threshold; for the selected entry, using the plurality of read retry thresholds to determine failed bits of data associated with a plurality of read operations to a plurality of cells; and for the selected entry, determining an order of the plurality of read retry thresholds based on the determination of the failed bits.

10. The method of claim 9, wherein the condition comprises a combination of an erase / write cycle value array (EW cycle value array), a single page read cycle value array (SPRD cycle value array), and a value of a type of a page associated with the plurality of cells.

11. The method of claim 9, wherein determining the order of the plurality of read retry thresholds comprises: determining the order of the plurality of read retry thresholds to be an ascending order of failed bit counts.

12. The method of claim 9, further comprising: when the condition does not correspond to any of a plurality of defined conditions, determining two conditions closest to the condition; selecting two read level tables corresponding to the two conditions; and using the two read level tables to perform selecting an entry, determining failed bits, and determining an order of a plurality of read thresholds.

13. The method of claim 12, further comprising: performing interpolation on the two read level tables to generate an interpolated read level table, and using the interpolated read level table to perform selecting an entry, determining failed bits, and determining the order of the plurality of read thresholds.

14. The method of claim 9, further comprising: when the historical read threshold is not included in a set of default read thresholds corresponding to a plurality of historical read thresholds in the plurality of entries, determining a set distance between the historical read threshold and each of a plurality of read thresholds; and selecting a historical read threshold with a smallest distance among the set of default read thresholds.

15. The method of claim 14, further comprising: using the selected read threshold as a historical read threshold to determine an entry, counting failed bits and determining an order of the plurality of read thresholds.

16. The method of claim 14, wherein the set distance comprises a Euclidean distance.

17. A memory system, comprising: a memory device comprising a plurality of cells; and a controller coupled to the memory device and: selecting a read level table based on a condition, the condition indicative of a state of the memory device, the read level table comprising a plurality of entries, each entry comprising a set of read thresholds, the set of read thresholds comprising a historical read threshold and a plurality of read retry thresholds; determining whether the historical read threshold is included in a set of default read thresholds, the set of default read thresholds corresponding to a plurality of historical read thresholds in the plurality of entries; determining whether the condition corresponds to any of a plurality of defined conditions; when it is determined that the historical read threshold is included in the set of default read thresholds and the condition corresponds to any one of the plurality of defined conditions, selecting an entry among a plurality of entries in a selected read level table based on the historical read threshold; for the selected entry, using the plurality of read retry thresholds to determine failed bits of data associated with a plurality of read operations to the plurality of cells; and for the selected entry, determining an order of the plurality of read retry thresholds based on the determination of the failed bits.

18. The memory system of claim 17, wherein the condition comprises a combination of an erase / write cycle value array (EW cycle value array), a single page read cycle value array (SPRD cycle value array), and a value of a type of page associated with the plurality of cells, wherein the controller: determines the order of the plurality of read retry thresholds to be an ascending order of failed bit counts.

19. The memory system of claim 17, wherein the controller: when the condition does not correspond to any one of a plurality of defined conditions, determines two conditions closest to the condition; selects two read level tables corresponding to the two conditions; and performs interpolation on the two read level tables to generate an interpolated read level table, and uses the interpolated read level table to perform selecting an entry, determining failed bits, and determining an order of a plurality of read thresholds.

20. The memory system of claim 17, wherein the controller: when it is determined that the historical read threshold is not included in the set of default read thresholds, determines a set distance between the historical read threshold and each of a plurality of read thresholds; selects a historical read threshold with a smallest distance among the set of default read thresholds; determines an entry with the selected read threshold as a historical read threshold; and counts failed bits and determines an order of the plurality of read thresholds.

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