Electronic fuse circuit
By introducing a multi-mode latch circuit and logic circuit group into the electronic fuse circuit, the commonality of normal mode and burning mode can be achieved, which solves the problems of circuit area and complexity in traditional memory, and realizes circuit area saving and design simplification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-09-24
- Publication Date
- 2026-04-03
AI Technical Summary
In traditional memory devices, electronic fuse circuits require a large number of latching circuits and complex logic decoders, which leads to increased circuit area and design complexity, especially in high-density memories.
A multi-mode latch circuit and logic circuit group are adopted to achieve sharing between normal mode and burning mode, reduce the use of latch circuit, and replace complex decoder with simple logic circuit, and share comparator circuit to save circuit area.
By sharing latch circuits and simplifying logic design, the circuit area and design complexity are reduced, and the space utilization efficiency of the memory is improved.
Smart Images
Figure CN114255814B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to electronic fuse circuits, and more particularly to electronic fuse circuits that can share circuitry to save circuit area. Background Technology
[0002] Traditional memories include electronic fuse circuits with redundant memory cells. These circuits record the addresses of damaged memory cells and use them to determine whether the memory cell to be accessed is damaged, deciding whether to replace it with a redundant memory cell. However, traditional memory devices typically require a large number of latches to temporarily store the selection signal when selecting the electronic fuse to write to, and also require a decoder with complex logic design. With technological advancements, memory cell density is increasing, leading to a corresponding increase in the number of redundant memory cells and electronic fuses, and consequently, a greater need for latches and decoders, thus increasing the space required for the memory. Summary of the Invention
[0003] The purpose of this invention is to provide an electronic fuse circuit that can share circuitry to save circuit area.
[0004] This invention provides an electronic fuse circuit, comprising: an electronic fuse group including multiple electronic fuse segments, each of the multiple electronic fuse segments including multiple electronic fuses; a multi-mode latch circuit for receiving an input signal in a burn-in mode to generate a first output signal, and receiving a comparison address in a normal mode to generate a second output signal; a first logic circuit group for receiving a first portion of bits of the first output signal in the burn-in mode to generate a control signal; and a second logic circuit group for receiving a second portion of bits of the first output signal and the control signal in the burn-in mode to generate a selection signal to select which of the multiple electronic fuse segments will be activated.
[0005] According to the foregoing embodiments, the present invention can share the latch circuit in both normal mode and burning mode, and the logic circuit used in the present invention can share the circuit with the comparator circuit in the prior art, thus reducing the area required for the circuit. Furthermore, the present invention replaces the decoder in the prior art with a simpler logic circuit, thus reducing the complexity of the circuit design.
[0006] According to the foregoing embodiments, the present invention can share the latch circuit in both normal mode and burning mode, and the logic circuit used in the present invention can share the circuit with the comparator circuit in the prior art, thus reducing the area required for the circuit. Furthermore, the present invention replaces the decoder in the prior art with a simpler logic circuit, thus reducing the complexity of the circuit design. Attached Figure Description
[0007] Figure 1 A block diagram of an electronic fuse circuit according to an embodiment of the present invention is shown.
[0008] Figure 2 A circuit diagram of an electronic fuse according to an embodiment of the present invention is shown.
[0009] Figure 3 A block diagram of a multi-mode latching circuit in an electronic fuse circuit according to an embodiment of the present invention is shown.
[0010] Figure 4 A block diagram of a first logic circuit group and a second logic circuit group in an electronic fuse circuit according to an embodiment of the present invention is shown.
[0011] Figure 5 A block diagram of an electronic fuse circuit according to another embodiment of the present invention is shown.
[0012] Figure 6 A detailed circuit diagram of a multi-mode latching circuit in an electronic fuse circuit according to an embodiment of the present invention is shown.
[0013] Figure 7 Detailed circuit diagrams of the first logic circuit group and the second logic circuit group in the electronic fuse circuit according to an embodiment of the present invention are shown. Detailed Implementation
[0014] The concept of the present invention will be described below with reference to different embodiments. Please note that the terms "first," "second," etc., and related descriptions in the following description are used only to identify different elements or signals and are not intended to limit their order. Furthermore, the number of bits received and the bit order of each circuit may vary depending on the specific circuit.
[0015] Figure 1 A block diagram of an electronic fuse circuit according to an embodiment of the present invention is shown. Figure 1As shown, the electronic fuse circuit 100 includes a multi-mode latch circuit ML, a first logic circuit group LG_1, a second logic circuit group LG_2, and an electronic fuse group EG. The first logic circuit group LG_1 includes at least one first logic circuit LG_11-LG_1n (not shown), and the second logic circuit group LG_1 includes at least one second logic circuit LG_21-LG_2n (not shown). The electronic fuse group EG includes multiple electronic fuse segments ES_1, ES_2…ES_n, each of which contains multiple electronic fuses (not shown in this figure). The multi-mode latch circuit ML is used to receive the serial input signal IO in burn-in mode to generate a first output signal OS_1 in parallel output, and to receive the serial input comparison address AD in normal mode to generate a second output signal OS_2 in parallel output. The first logic circuit group LG_1 receives a first portion of the bits of the first output signal OS_1 in burn-in mode to generate a control signal R0N. In burn-in mode, the second logic circuit group LG_2 receives the second part of the bits of the first output signal OS_1 and the control signal R0N to generate the selection signal EN to select which electronic fuse segment in the electronic fuse group EG will be activated. In one embodiment, the first logic circuit group LG_1 can be used in normal mode to compare the second output signal OS_2 with the error address FA (i.e., the address of the corrupted memory cell) stored in the electronic fuse group EG to determine whether the address to be compared AD is an error address, so as to perform the replacement of redundant memory cells.
[0016] Figure 2 A block diagram of an electronic fuse assembly EG according to an embodiment of the present invention is shown. Figure 2 As shown, the electronic fuse group EG includes i-bit bit determination circuits EG_1-EG_i. The burning signal circuit 201 in the bit determination circuit EG_1 receives the first switch signal CS_1, the second switch signal CS_2, and... Figure 1 The selection signal EN is generated by the second logic circuit group LG_2. The first switch signal CS_1 and the second switch signal CS_2 can be generated by different circuits based on the input signal IO. For example, the first switch signal CS_1 and the second switch signal CS_2 can be generated by the circuit disclosed in US Patent No. US10629282, but the present invention is not limited thereto. The selection signal EN is the enable signal of the bit determination circuit EG_1, which determines whether the bit determination circuit EG_1 is enabled or not.
[0017] When the bit determination circuit EG_1 is enabled, the first switch signal CS_1 and the second switch signal CS_2 generate the burn-in signal BS_1. Figure 2In the example, if the logic value of the burn signal BS_1 is 0, the burn switch BM_1 is turned on, causing the fuse f1 to be burned, thus changing the error address FA.
[0018] The bit-determining circuit EG_i has the same circuit structure as the bit-determining circuit EG_1. However, note that in the following examples, according to... Figure 2 The example signal and data logic values shown can be understood by those skilled in the art to be modified according to the circuit structure of the electronic fuse circuit EG to achieve the same function.
[0019] Figure 3 A block diagram of a multi-mode latch circuit ML in an electronic fuse circuit according to an embodiment of the present invention is shown. Figure 3 As shown, Figure 1 The multi-mode latch circuit ML in the middle includes Figure 3 The system contains multiple multiplexers MUX_1-MUX_n and multiple latching circuits La_1-La_n. Multiplexers MUX_1-MUX_n receive different bits IO[0]-IO[n] of the serial input signal IO in burn-in mode and output these bits to latching circuits La_1-La_n respectively. In normal mode, they receive different bits AD[0]-AD[n] of the serial input address AD to be compared and output these bits to latching circuits La_1-La_n respectively. Latching circuits La_1-La_n generate different bits OS_1[0]-OS1[m] of the first output signal OS_1 based on the different bits IO[0]-IO[n] of the input signal IO in burn-in mode, and generate different bits of the second output signal OS_2[0]-OS_2[n] based on the different bits AD1-AD[n] of the address AD to be compared in normal mode.
[0020] In one embodiment, the first output signal OS_1 is an m-bit signal output in parallel, and the second output signal OS_2 is an n-bit signal output in parallel, where m and n are both positive integers and m is less than n. In this case, in the burning mode, the latching circuits La_1-La_n can enable only m multiplexers and latching circuits, or still generate bits OS_1[0]-OS1[n], but only the components corresponding to bits OS_1[0]-OS1[m] are enabled in the subsequent first and second logic circuits. Such variations should be included within the scope of this invention.
[0021] Figure 4 A block diagram illustrating the first logic circuit group LG_1 and the second logic circuit group LG_2 in an electronic fuse circuit according to an embodiment of the present invention is shown. Figure 4 As shown, Figure 1The first logic circuit group LG_1 shown contains n first logic circuits LG_11-LG1n, while Figure 1 The second logic circuit group LG_2 shown contains n second logic circuits LG_21-LG2n. The first logic circuits LG_11-LG1n each receive a portion of the first output signal OS_1 (bits OS_1B1), while the second logic circuits LG_21-LG2n each receive the remaining portion of the first output signal OS_1 (bits OS_1B2). The second logic circuits LG_21-LG2n generate different selection signals EN_1-EN_n based on OS_1B2 and the corresponding control signals R0N_1-R0N_n.
[0022] To explain in detail the operation of the electronic fuse circuit of the present invention in the burning mode, Figure 5 Taking two first logic circuits LG_11, LG21, and LG1, two second logic circuits LG_21 and LG_22, and two electronic fuse sections ES_1 and ES_2 as examples, the following explanation is provided. Other first logic circuits, second logic circuits, and electronic fuse sections can also operate in the same way. In this embodiment, the remaining bits OS_1_B2 of the first output signal OS_1 are AN[1:2]. Therefore, after decoding AN[1:2], the second logic circuits LG_21 and LG_22 will each generate a 4-bit selection signal EN. That is, the selection signals EN_1 and EN_2 are 4-bit signals output in parallel. Corresponding to the number of bits of the selection signals EN_1 and EN_2, each of the electronic fuse sections ES_1-ES_2 will be divided into four electronic fuse blocks EB_1-EB_4. Therefore, the selection signal EN_1 is used to select which electronic fuse blocks EB_1-EB_4 in electronic fuse segment ES_1 are enabled, while the selection signal EN_2 is used to select which electronic fuse blocks EB_1-EB_4 in electronic fuse segment ES_2 are enabled. In this embodiment, each of the electronic fuse blocks EB_1-EB_4 contains 11 electronic fuses (not shown). For example, if electronic fuse block EB_1 is enabled by selection signal EN_1[0], the fuses in that block will be burned in, generating an error address FA.
[0023] In addition, in burn-in mode, Figure 5Each electronic fuse segment ES_1 and ES_2 in the circuit has a unique identification code RRID_1 and RRID_2. In this embodiment, the first logic circuit LG_11 receives the first part of the first output signal OS_1, bits OS_1B1 (e.g., AN[3:12]), and compares it with the identification code RRID_1 to generate a control signal RON_1. The first logic circuit LG_12 receives the first part of the first output signal OS_1 and compares it with the identification code RRID_2 to generate a control signal RON_2. When the control signal RON_1 = 1, it indicates that the first part of the first output signal OS_1, bits OS_1B1, is the same as the identification code RRID_1, that is, Figure 1 The input signal IO specifies that the electronic fuse section ES_1 should be activated. Similarly, when the control signal R0N_2 = 1, it indicates... Figure 1 The input signal IO specifies that the electronic fuse segment ES_2 should be activated. After confirming which electronic fuse segment ES_1 or ES_2 should be activated, the second logic circuits LG_21 and LG_22 then decode the second part of the first output signal OS_1, bits OS_1_B2 (e.g., AN[1:2]), and generate a 4-bit selection signal (EN_2[0:3]) to select one of the enable electronic fuse blocks EB_1-EB_4.
[0024] Figure 6 A detailed circuit diagram of the first logic circuit LG_11 in the electronic fuse circuit according to an embodiment of the present invention is shown. Figure 7 A detailed circuit diagram of the second logic circuit LG_21 in the electronic fuse circuit according to an embodiment of the present invention is shown. However, please note that... Figure 6 and Figure 7 The circuit structure shown is for illustrative purposes only and is not intended to limit the invention. Those skilled in the art will be able to interpret the foregoing description. Figure 6 and Figure 7 Modifications to the circuit structure shown to achieve the same function should be included within the scope of this invention. Furthermore, in Figure 6 and Figure 7 The relevant description only uses the first logic circuit LG_11 and the second logic circuit LG_21 as examples, but other first logic circuits and second logic circuits may contain the same circuit structure.
[0025] like Figure 6As shown, the first logic circuit LG_11 contains multiple logic units (XOR gates XOR_1-XOR_10 in this example). These logic units receive different bits (e.g., AN[9:12]) of the first output signal OS_1 in parallel in burn-in mode to generate the control signal RON. In normal mode, they receive different bits (e.g., AN[3:12]) of the second output signal OS_2 in parallel, as well as the error addresses F[3:8] and C[9:12] stored in the electronic fuse group EG, to compare whether the address to be compared AD is an error address FA. In this embodiment, the signal C[9:12] also incorporates the comparison result of the aforementioned identification code RRID. If the address to be compared AD is an error address FA, a redundant memory cell replacement operation will be performed.
[0026] In this embodiment, all XOR gates XOR_1-XOR_10 are enabled for comparison operations in normal mode; however, only XOR gates XOR_1-XOR_4 are enabled for generating the control signal RON in burn-in mode. In other words, the first logic circuit LG_11 disclosed in this invention can be used in both normal and burn-in modes, thus saving circuit area.
[0027] Please see Figure 7 For simplicity, only the generation circuit of EN_1[0] is shown. The second logic unit LG_21 includes NOR gates NOR_1-NOR_2, NAND gates NA_3-NA_4, and inverters IV_1-IV_3. NOR gate NOR_1 serves as a receiving logic unit to sequentially receive the aforementioned second part of bits AN[1:2] and their inverted signals. NAND gate NA_4 and inverters IV_2-IV_3 form a first path, which receives the output of the receiving NOR gate NOR_1 in normal mode to select which electronic fuse segment in the first figure to use. NOR gate NOR_2, NAND gate NA_3, and inverter IV_1 form a second path, which receives the control signal R0N_1 and the output of NOR gate NOR_1 in burn-in mode to generate the selection signal EN_1[0] to control whether to start the electronic fuse block EB_1. Signal BNEF is used to enable the first and second paths respectively. Similarly, the second logic circuit LG_21 disclosed in this invention can be used in both normal mode and burn-in mode, thus saving circuit area.
[0028] According to the foregoing embodiments, the present invention can share the latch circuit in both normal mode and burning mode, and the logic circuit used in the present invention can share the circuit with the comparator circuit in the prior art, thus reducing the area required for the circuit. Furthermore, the present invention replaces the decoder in the prior art with a simpler logic circuit, thus reducing the complexity of the circuit design.
[0029] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.
[0030] [Symbol Explanation]
[0031] 100 Electronic fuse circuit
[0032] 201 Burn-in signal circuit
[0033] 203 Logic Circuits
[0034] ML multi-mode latch circuit
[0035] LG_1 First Logic Circuit Group
[0036] LG_2 Second Logic Circuit Group EG Electronic Fuse Group EB_1, EB_2, EB_3, EB_4 Electronic Fuse Blocks ES_1, ES_2, ES_n Electronic Fuse Segments BM_1 Burn-in Switch f1 Fuse M_1 Switching Element MUX_1-MUX_n Multiplexer La_1-La_n Latch Circuit LG_11-LG_1n First Logic Circuit LG_21-LG_2n Second Logic Circuit XOR_1-XOR_10 XOR Gate XNOR_1-XNOR_4 XNOR Gate NA_1, NA_2, NA_3, NA_4 NAND Gate NOR_1, NOR_2 NOR Gate IV_1, IV_2, IV_3 Inverter
Claims
1. An electronic fuse circuit, comprising: An electronic fuse assembly includes multiple electronic fuse segments, and each of the multiple electronic fuse segments includes multiple electronic fuses; A multi-mode latch circuit is used to receive an input signal in burn-in mode to generate a first output signal, and to receive the address to be compared in normal mode to generate a second output signal. The input signal used in the burn-in mode is different from the address to be compared used in the normal mode; The first logic circuit group receives a first portion of bits of the first output signal in the burn-in mode to generate a control signal. as well as The second logic circuit group receives a second portion of the bits of the first output signal and the control signal in the burn-in mode to generate a selection signal (En) to select which of the plurality of electronic fuse segments will be activated.
2. The electronic fuse circuit according to claim 1, wherein the first output signal is an m-bit signal transmitted in parallel, and the second output signal is an n-bit signal transmitted in parallel, where m and n are both positive integers and m is less than n.
3. The electronic fuse circuit according to claim 1, wherein the number of bits in the first part of the bits is greater than the number of bits in the second part of the bits.
4. The electronic fuse circuit according to claim 1, wherein the first logic circuit group in the normal mode is used to compare the address to be compared with at least one erroneous address stored in the electronic fuse group to determine whether the address to be compared is the erroneous address.
5. The electronic fuse circuit of claim 1, wherein the first logic circuit group further receives an identification code and compares the first portion of bits with the identification code to generate the control signal, wherein each of the plurality of electronic fuse segments has a unique identification code.
6. The electronic fuse circuit according to claim 5, wherein the first logic circuit group comprises a plurality of first logic circuits, each of the first logic circuits comprising: Multiple logic units, wherein the multiple logic units receive different bits of the first portion of bits in parallel in the burn-in mode to generate the control signal, and receive different bits of the second output signal and the error address stored in the electronic fuse group in parallel in the normal mode; At least one of the plurality of logic units further receives the comparison result of the first portion of bits and the identification code.
7. The electronic fuse circuit according to claim 1, wherein the multi-mode latch circuit comprises: At least one latching circuit is configured to generate different bits of the first output signal based on different bits of the input signal in the burn-in mode, and to generate different bits of the second output signal based on different bits of the address to be compared in the normal mode; and At least one multiplexer is configured to receive the plurality of different bits of the input signal in the burning mode and output one of the plurality of different bits of the input signal to the latching circuit, and to receive the plurality of different bits of the address to be compared in the normal mode and output one of the plurality of different bits of the address to be compared to the latching circuit.
8. The electronic fuse circuit according to claim 1, wherein the first logic circuit group comprises a plurality of first logic circuits, each of the first logic circuits comprising: Multiple logic units, in the burn-in mode, receive different bits of the first portion of bits in parallel to generate the control signal, and in the normal mode, receive different bits of the second output signal in parallel as well as the error address stored in the electronic fuse group.
9. The electronic fuse circuit of claim 8, wherein only a portion of the plurality of logic units generate the control signal in the burn-in mode, but all of the plurality of logic units receive the plurality of different bits of the second output signal and the error address in the normal mode.
10. The electronic fuse circuit according to claim 1, wherein the second logic circuit group comprises a plurality of second logic circuits, each of the second logic circuits comprising: A receiving logic unit is used to receive the second part of the bits and the inverted signal of the second part of the bits; In the first path, the output of the receiving logic unit is received in the normal mode to select which of the plurality of electronic fuse segments to use; The second path involves receiving the control signal and the output of the receiving logic unit in the burn-in mode to generate the selection signal.
Citation Information
Patent Citations
E-fuse circuit
US10629282B1
Redundancy circuit in semiconductor memory device
CN1855300A
Redundancy circuit
KR1020030077839A