Semiconductor device

Abstract

An embodiment provides a semiconductor device capable of reducing noise. The semiconductor device (100) according to the embodiment includes: an IC chip having a first terminal and a second terminal on a first surface; and a first silicon capacitor facing the first surface of the IC chip and having a first electrode electrically connected to the first terminal through a first conductive member and a second electrode electrically connected to the second terminal through a second conductive member on a second surface facing the first surface.

Description

[0001] This application incorporates the entire contents of the base application by reference thereto. This application claims priority based on Japanese Patent Application No. 2020-153215 (filing date: September 11, 2020) as the base application. This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0002] The embodiment relates to a semiconductor device. Background Art

[0003] Conventionally, a technique for reducing noise in a semiconductor device using a capacitor has been known. Summary of the Invention

[0004] The embodiment provides a semiconductor device capable of reducing noise.

[0005] The semiconductor device according to the embodiment includes: an IC chip having a first terminal and a second terminal on a first surface; and a first silicon capacitor facing the first surface of the IC chip and having a first electrode electrically connected to the first terminal through a first conductive member and a second electrode electrically connected to the second terminal through a second conductive member on a second surface facing the first surface. Brief Description of the Drawings

[0006] Figure 1 It is a top view showing a semiconductor device according to a first embodiment.

[0007] Figure 2 It is Figure 1 a cross-sectional view taken along line A - A' of

[0008] Figure 3 It is a top view showing an IC chip of a semiconductor device according to a first embodiment.

[0009] Figure 4 It is a circuit diagram of a semiconductor device according to a first embodiment.

[0010] Figure 5 It is a top view showing an IC chip and a silicon capacitor of a semiconductor device according to a first embodiment.

[0011] Figure 6 It is Figure 2 a cross-sectional view showing an enlarged area surrounded by a double-dashed line B of

[0012] Figure 7 It is a top view showing a semiconductor device according to a second embodiment.

[0013] Figure 8 It is a circuit diagram of a semiconductor device according to a second embodiment.

[0014] Figure 9 It is a top view of an IC chip and a silicon capacitor in a semiconductor device according to the third embodiment.

[0015] Figure 10 (a) in Figure 9 is a cross-sectional view taken along the C-C' line of Figure 10 (b) in is a cross-sectional view showing the current path and the direction of the magnetic field.

[0016] Figure 11 It is a top view of a semiconductor device according to the fourth embodiment.

[0017] Figure 12 is Figure 11 a cross-sectional view taken along the D-D' line of

[0018] Figure 13 It is a top view of an IC chip, a first silicon capacitor, and a second silicon capacitor in a semiconductor device according to the fourth embodiment.

[0019] Figure 14 It is a circuit diagram of a semiconductor device according to the fourth embodiment.

[0020] Figure 15 It is a top view of a modification example of a first silicon capacitor and a second silicon capacitor in a semiconductor device according to the fourth embodiment.

[0021] Figure 16 It is a cross-sectional view of a semiconductor device according to the fifth embodiment.

[0022] Figure 17 It is a top view of a semiconductor device according to the sixth embodiment.

[0023] Figure 18 is Figure 17 a cross-sectional view taken along the E-E' line of

[0024] Figure 19 It is a top view of a semiconductor device according to the seventh embodiment.

[0025] Figure 20 is Figure 19 a cross-sectional view taken along the F-F' line of

[0026] Figure 21 It is a top view of a semiconductor device according to the eighth embodiment.

[0027] Figure 22 is Figure 21 a cross-sectional view taken along the G-G' line of Detailed Embodiments

[0028] <First Embodiment>

[0029] First, the first embodiment will be described.

[0030] Figure 1 is a top view showing the semiconductor device according to the present embodiment.

[0031] Figure 2 is Figure 1 a cross-sectional view taken along line A-A' of

[0032] If reference is made to Figure 1 and Figure 2 for a brief description, the semiconductor device 100 according to the present embodiment includes a die pad 110, an IC chip 120, a silicon capacitor 130, a plurality of wires 140, and a sealing member 150. Among them, in Figure 1 the sealing member 150 is shown by a double-dashed line for easy understanding of the internal structure of the semiconductor device 100.

[0033] Hereinafter, each part of the semiconductor device 100 will be described in detail. Hereinafter, an XYZ orthogonal coordinate system is used for easy understanding of the description. The direction from the die pad 110 toward the IC chip is set as the "Z direction". One direction orthogonal to the Z direction is set as the "X direction". One direction orthogonal to the Z direction and the X direction is set as the "Y direction". In addition, hereinafter, for easy understanding of the description, the Z direction is set as "upward" and the opposite direction of the Z direction is set as "downward", but the upward and downward directions are independent of the direction of gravity.

[0034] The die pad 110 has a flat plate shape. The die pad 110 is made of a metal material such as a copper alloy or an iron alloy.

[0035] Figure 3 is a top view showing the IC chip of the semiconductor device according to the present embodiment.

[0036] Figure 4 is a circuit diagram of the semiconductor device according to the present embodiment.

[0037] The IC chip 120 is disposed on the die pad 110 and is electrically connected to the die pad 110. The IC chip 120 generally has an approximately rectangular flat plate shape. However, the shape of the IC chip is not limited to the above shape.

[0038] As shown in Figure 4 the IC chip 120 is a driver IC that controls the driving of the motor M in the present embodiment, that is, an MCD (Motor control driver) chip, and is mounted on a vehicle such as an automobile. However, the type of the IC chip 120 is not limited to the above type.

[0039] The IC chip 120 includes a control circuit 121 that controls the driving of the motor M. The control circuit 121 includes a logic circuit 122 and a switching circuit 123, etc.

[0040] The logic circuit 122 has a first terminal 122a connected to the first power supply V1 and a second terminal 122b electrically connected to the ground GND. The first terminal 122a and the second terminal 122b are, for example, pad electrodes as Figure 3 shown, and are provided on the upper surface 120a of the IC chip 120.

[0041] Here, "the first terminal 122a and the second terminal 122b are provided on the upper surface 120a of the IC chip 120" means that, as Figure 2 shown, at least a part of the first terminal 122a and the second terminal 122b is exposed from other components constituting the IC chip 120 on the side of the upper surface 120a of the IC chip 120. Therefore, the first terminal 122a and the second terminal 122b can be configured such that their upper surfaces are flush with the upper surface 120a of the IC chip 120, or can be configured to protrude from the upper surface 120a. In the present embodiment, a protective layer 125 is provided on the uppermost layer of the IC chip 120. Moreover, the upper surfaces of the first terminal 122a and the second terminal 122b are substantially flush with the upper surface of the protective layer 125, and together with the upper surface of the protective layer 125, constitute the upper surface 120a of the IC chip 120. However, the first terminal and the second terminal can also protrude upward from the protective layer, and the protective layer can also not be provided on the uppermost layer of the IC chip and the first terminal and the second terminal can protrude from the upper surface of the IC chip.

[0042] The switching circuit 123, as Figure 4 shown, switches the on and off of the motor M according to the output signal of the logic circuit 122.

[0043] In addition, as Figure 3 shown, a first pad electrode 124a, a second pad electrode 124b, a third pad electrode 124c, a fourth pad electrode 124d, and a fifth pad electrode 124e are provided on the upper surface 120a of the IC chip 120.

[0044] The first pad electrode 124a is, as Figure 4 shown, electrically connected to the first terminal 122a within the IC chip 120. The second pad electrode 124b is electrically connected to the second terminal 122b within the IC chip 120. The third pad electrode 124c, the fourth pad electrode 124d, and the fifth pad electrode 124e are electrically connected to the switching circuit 123 within the IC chip 120.

[0045] In addition, although other electrode pads are also provided on the upper surface of the IC chip 120, detailed descriptions and illustrations thereof are omitted. In addition, the positions and shapes of the first terminal, the second terminal, the first pad electrode, the second pad electrode, the third pad electrode, the fourth pad electrode, and the fifth pad electrode are not particularly limited to Figure 1 the positions and shapes shown.

[0046] Figure 5 FIG. is a top view of the IC chip and the silicon capacitor of the semiconductor layer device according to the present embodiment.

[0047] Figure 6 is Figure 2 a cross-sectional view showing an enlarged view of the region surrounded by the two-dot chain line B.

[0048] The silicon capacitor 130 is disposed to face the upper surface 120a of the IC chip 120. In the present embodiment, the silicon capacitor 130 is disposed directly above the logic circuit 122 of the IC chip 120. The shape of the silicon capacitor 130 is generally a substantially rectangular flat plate shape in the present embodiment. However, the shape of the silicon capacitor is not limited to the above shape.

[0049] As shown in Figure 6 the silicon capacitor 130 has a substrate 131, a first conductive layer 132, a dielectric layer 133, a second conductive layer 134, a first internal electrode 135, a second internal electrode 136, an insulating layer 137, a protective layer 137s, a first external electrode 138 (first electrode), and a second external electrode 139 (second electrode).

[0050] The substrate 131 is made of, for example, silicon or the like. A channel 131a is provided in the substrate 131, which is recessed upward from the lower surface.

[0051] The second conductive layer 134 is disposed under the substrate 131. The second conductive layer 134 is made of, for example, silicon doped with impurities. A plurality of channels 134a are provided in a portion of the second conductive layer 134 located in the channel 131a, which are recessed upward from the lower surface.

[0052] The dielectric layer 133 is disposed under the surface of each channel 134a and the region around each channel 134a on the lower surface of the second conductive layer 134. The dielectric layer 133 is made of, for example, silicon oxide or silicon nitride. In Figure 6 an example in which the dielectric layer is a single layer is described, but the dielectric layer may also be two or more layers.

[0053] The first conductive layer 132 is provided to fill the portion below the dielectric layer 133 inside each channel 134a. Additionally, the first conductive layer 132 is provided under the portion protruding from each channel 134a in the dielectric layer 133. The first conductive layer 132 is formed of, for example, doped polysilicon or the like.

[0054] The first internal electrode 135 is disposed directly below the first conductive layer 132 and is connected to the first conductive layer 132. The second internal electrode 136 is formed of a metal material such as copper, for example.

[0055] The second internal electrode 136 is disposed directly below the second conductive layer 134 and is connected to the second conductive layer 134. The second internal electrode 136 is disposed directly below the region of the substrate 131 where the channel 131a is not provided. The second internal electrode 136 is formed of, for example, the same material as the first internal electrode 135.

[0056] The insulating layer 137 covers the first conductive layer 132, the dielectric layer 133, and the second conductive layer 134. Additionally, the insulating layer 137 covers a part of the first internal electrode 135 and a part of the second internal electrode 136. The insulating layer 137 is formed of, for example, silicon oxide or silicon nitride, etc. The protective layer 137s covers the lower surface of the insulating layer 137.

[0057] The first opening 137a and the second opening 137b are provided in the insulating layer 137 and the protective layer 137s. Another part of the first internal electrode 135 is exposed from the first opening 137a. Another part of the second internal electrode 136 is exposed from the second opening 137b.

[0058] The first external electrode 138 is the positive electrode in the present embodiment. The second external electrode 139 is the negative electrode in the present embodiment. The first external electrode 138 and the second external electrode 139 are provided on the lower surface 130b of the silicon capacitor 130.

[0059] Here, "the first external electrode 138 and the second external electrode 139 are provided on the lower surface 130b of the silicon capacitor 130" means that at least a part of the first external electrode 138 and the second external electrode 139 is exposed from other components constituting the silicon capacitor 130 on the lower surface 130b side. Therefore, the first external electrode 138 and the second external electrode 139 can be configured such that their lower surfaces are flush with the lower surface 130b of the silicon capacitor 130, or can be configured to protrude from the lower surface 130b.

[0060] In the present embodiment, a protective layer 137s is provided on the lowermost layer of the silicon capacitor 130. Moreover, the lower surfaces of the first external electrode 138 and the second external electrode 139 are substantially flush with the lower surface of the protective layer 137s, and together with the lower surface of the protective layer 137s, they form the lower surface 130b of the silicon capacitor 130. However, the first external electrode and the second external electrode may protrude downward beyond the protective layer, or the protective layer may not be provided on the lowermost layer of the silicon capacitor, and the first external electrode and the second external electrode may protrude from the lower surface of the silicon capacitor.

[0061] The first external electrode 138 is provided directly below the first internal electrode 135 and directly above the first terminal 122a of the logic circuit 122. The first external electrode 138 is disposed in the first opening 137a. The upper end of the first external electrode 138 is connected to the first internal electrode 135 via the first opening 137a. The lower end of the first external electrode 138 is connected to the first terminal 122a via the first bump 161 (first conductive member). The first external electrode 138 is made of a metal material such as copper, for example. The first bump 161 is made of solder or the like, for example. In addition, in the present embodiment, an example in which the first conductive member is the first bump 161 has been described, but the specific configuration of the shape, position, and material of the first conductive member is not particularly limited as long as the first external electrode and the first terminal can be electrically connected.

[0062] The second external electrode 139 is provided directly below the second internal electrode 136 and directly above the second terminal 122b of the logic circuit 122. The second external electrode 139 is disposed in the second opening 137b. The upper end of the second external electrode 139 is connected to the second internal electrode 136 via the second opening 137b. The lower end of the second external electrode 139 is connected to the second terminal 122b via the second bump 162 (second conductive member). The second external electrode 139 is made of the same material as the first external electrode 138, for example. The second bump 162 is made of solder or the like, for example. In addition, in the present embodiment, an example in which the second conductive member is the second bump 162 has been described, but the specific configuration of the shape, position, and material of the second conductive member is not particularly limited as long as the second electrode and the second terminal can be electrically connected.

[0063] In this way, the first external electrode 138 of the silicon capacitor 130 is electrically connected to the first terminal 122a of the logic circuit 122 that is the noise generation source, and the second external electrode 139 is electrically connected to the second terminal 122b of the logic circuit 122. Since the silicon capacitor 130 functions in such a way as to repeatedly charge and discharge to eliminate the high-frequency noise generated by the logic circuit 122, it is possible to suppress the propagation of high-frequency noise from the logic circuit 122 to the first power supply V1 and the ground GND that are the connection targets of the logic circuit 122. In addition, the silicon capacitor may be connected to other circuits within the IC chip instead of the logic circuit.

[0064] The closer the silicon capacitor 130 is to the logic circuit 122 that is the noise generation source, the easier it is to suppress noise through the silicon capacitor 130. In the present embodiment, the first terminal 122a and the second terminal 122b are provided on the upper surface 120a of the IC chip 120. Moreover, the first external electrode 138 and the second external electrode 139 are provided on the lower surface 130b of the silicon capacitor 130 that faces the upper surface 120a. Moreover, the first external electrode 138 is connected to the first terminal 122a through the first bump 161, and the second external electrode 139 is connected to the second terminal 122b through the second bump 162. Therefore, the silicon capacitor 130 can be brought close to the logic circuit 122.

[0065] In addition, as described above, the silicon capacitor 130 is a capacitor in which the substrate 131, the first conductive layer 132, the dielectric layer 133, and the second conductive layer 134 contain silicon. In this way, since the silicon capacitor 130 contains silicon in the same way as the IC chip 120, it is easy to follow the deformation of the IC chip 120 in the case where the IC chip 120 is deformed or the like. In addition, the silicon capacitor 130 has excellent adhesion to the sealing member 150. Therefore, by using the silicon capacitor 130 as a capacitor, the reliability of the semiconductor device 100 can be improved.

[0066] Multiple wires 140 are arranged around the die pad 110 as Figure 1 and Figure 2 shown. The multiple wires 140 are separated from each other. In addition, the multiple wires 140 are separated from the die pad 110. Each wire 140 is made of the same material as the die pad 110. Hereinafter, five of the multiple wires 140 will also be referred to as the "first wire 141", the "second wire 142", the "third wire 143", the "fourth wire 144", and the "fifth wire 145".

[0067] The first wire 141 is electrically connected to the first pad electrode 124a of the IC chip 120 via the first bonding wire 171 as Figure 1 shown. The second wire 142 is electrically connected to the second pad electrode 124b of the IC chip 120 via the second bonding wire 172.

[0068] The first wire 141, as Figure 4 shown, is electrically connected to the first power supply V1, for example, when the semiconductor device 100 is in use. The second wire 142 is electrically connected to the ground GND, for example, when the semiconductor device 100 is in use. Therefore, the silicon capacitor 130 can suppress the propagation of noise from the logic circuit 122 to connection targets such as the first power supply V1 or the ground GND.

[0069] The third wire 143, as Figure 1 shown, is electrically connected to the third pad electrode 124c of the IC chip 120 via the third bonding wire 173. The fourth wire 144 is electrically connected to the fourth pad electrode 124d of the IC chip 120 via the fourth bonding wire 174. The fifth wire 145 is electrically connected to the fifth pad electrode 124e of the IC chip 120 via the fifth bonding wire 175.

[0070] The third wire 143, as Figure 4 shown, is connected to the second power supply V2, for example, when the semiconductor device 100 is in use. The fourth wire 144 is connected to the ground GND, for example, when the semiconductor device 100 is in use. The fifth wire 145 is connected to the motor M, for example, when the semiconductor device 100 is in use.

[0071] In addition, regarding the specific configurations such as the shape, position, and material of each wire, as long as the IC chip can be electrically connected to connection targets outside the semiconductor device such as the ground or power supply, there is no particular limitation. In addition, the wiring components used for the electrical connection between each wire and the IC chip are not particularly limited to bonding wires. In addition, other wires 140 other than the above-mentioned five wires 140 are also connected to the IC chip 120 via bonding wires, and detailed descriptions and illustrations are omitted here.

[0072] The sealing member 150, as Figure 1 and Figure 2 shown, seals the IC chip 120 and the silicon capacitor 130. In addition, the sealing member 150 covers a part of the die pad 110 and a part of each wire 140, exposing the other part of the die pad 110 and the other part of each wire 140. Specifically, in the present embodiment, the sealing member 150 covers the upper surface of the die pad 110 and the upper surfaces of the plurality of wires 140. In addition, the sealing member 150 is provided in the gaps between the die pad 110 and the plurality of wires 140, and in the gaps between adjacent wires 140. The sealing member 150 is not particularly limited and is made of a resin material such as a thermosetting resin, for example. However, regarding the specific configurations such as the shape and material of the sealing member, as long as the IC chip 120 and the silicon capacitor 130 can be sealed, there is no particular limitation.

[0073] Next, the effects of the present embodiment will be described.

[0074] The semiconductor device 100 according to the present embodiment includes an IC chip 120 and a silicon capacitor 130. The IC chip 120 has a first terminal 122a and a second terminal 122b on its upper surface 120a. The silicon capacitor 130 faces the upper surface 120a of the IC chip 120. The silicon capacitor 130 has a first external electrode 138 electrically connected to the first terminal 122a through a first bump 161 and a second external electrode 139 electrically connected to the second terminal 122b through a second bump 162 on its lower surface 130b facing the upper surface 120a.

[0075] In such a semiconductor device 100, the silicon capacitor 130 can suppress the propagation of noise from the IC chip 120 to the connection target of the IC chip. In particular, the silicon capacitor 130 faces the upper surface 120a of the IC chip 120 and is electrically connected to the IC chip 120 via the first bump 161 and the second bump 162. Therefore, the silicon capacitor 130 can be brought close to the IC chip. As a result, the noise propagated from the IC chip 120 to the connection target can be efficiently suppressed. In summary, a semiconductor device 100 capable of reducing noise can be provided.

[0076] In addition, in the semiconductor device 100 according to the present embodiment, the silicon capacitor 130 is used as a capacitor. Since the silicon capacitor 130 contains silicon as well as the IC chip 120, it is likely to follow the deformation of the IC chip 120 in the case where the IC chip 120 is deformed or the like. Therefore, the reliability of the semiconductor device 100 can be improved.

[0077] In addition, the semiconductor device 100 according to the present embodiment further includes a die pad 110, a first wire 141, a second wire 142, and a sealing member 150. The IC chip 120 is provided on the die pad 110. The first wire 141 is electrically connected to the first terminal 122a. The second wire 142 is electrically connected to the second terminal 122b. The sealing member 150 seals the IC chip 120 and the silicon capacitor 130. In such a semiconductor device 100, it is possible to suppress the propagation of noise from the IC chip 120 to the connection targets of the first wire 141 and the second wire 142 during the use of the semiconductor device 100. In addition, by sealing the IC chip 120 and the silicon capacitor 130 with the sealing member 150, the connection between the IC chip 120 and the silicon capacitor 130 can be made firm. As a result, the reliability of the semiconductor device 100 can be improved.

[0078] In addition, the IC chip 120 also has a logic circuit 122 electrically connected to the first terminal 122a and the second terminal 122b. The silicon capacitor 130 is located directly above the logic circuit 122. Therefore, the silicon capacitor 130 can be close to the logic circuit 122 which is the noise generation source. Thus, the propagation of noise from the IC chip 120 to the connection target can be efficiently suppressed.

[0079] <Second Embodiment>

[0080] Next, the second embodiment will be described.

[0081] Figure 7 It is a top view of the semiconductor device according to this embodiment.

[0082] Figure 8 It is a circuit diagram of the semiconductor device according to this embodiment.

[0083] The semiconductor device 200 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that it further includes a first inductor 281 and a second inductor 282.

[0084] In the following description, as a principle, only the differences from the first embodiment will be described. The matters other than those described below are the same as those in the first embodiment.

[0085] The first inductor 281 and the second inductor 282 are disposed on the die pad 110. The first inductor 281 and the second inductor 282 are sealed by the sealing member 150.

[0086] The first inductor 281 has a pair of terminals 281a, 281b. The terminal 281a is electrically connected to the first pad electrode 124a via the bonding wire 276. The terminal 281b is electrically connected to the first wire 141 via the bonding wire 277. As Figure 8 shown, the first pad electrode 124a is electrically connected to the first terminal 122a of the logic circuit 122 of the IC chip 120. Therefore, the first inductor 281 is electrically connected to the first terminal 122a of the logic circuit 122 and the first wire 141.

[0087] The second inductor 282, as Figure 7 shown, has a pair of terminals 282a, 282b. The terminal 282a is electrically connected to the second pad electrode 124b via the bonding wire 278. The terminal 282b is electrically connected to the second wire 142 via the bonding wire 279. As Figure 8 shown, the second pad electrode 124b is electrically connected to the second terminal 122b of the logic circuit 122 of the IC chip 120. Therefore, the second inductor 282 is electrically connected to the second terminal 122b of the logic circuit 122 and the second wire 142.

[0088] In this embodiment, an example in which wire bonding is used for the electrical connection between each inductor and the IC chip has been described. However, regarding the specific configuration of the shape, position, material, etc. of the wiring component used for the electrical connection between each inductor and the IC chip, as long as each inductor can be electrically connected to the IC chip, there is no particular limitation. Similarly, in this embodiment, an example in which wire bonding is used for the electrical connection between each inductor and each wire has been described. However, regarding the specific configuration of the shape, position, material, etc. of the wiring component used for the electrical connection between each inductor and each wire, as long as each inductor can be electrically connected to each wire, there is no particular limitation.

[0089] As described above, the semiconductor device 200 according to this embodiment further includes a first inductor 281 that is electrically connected to the first terminal 122a and the first wire 141 and is sealed by the sealing member 150. Therefore, it is possible to suppress the propagation of high-frequency noise from the IC chip 120 to the first power supply V1 or the like that is the connection target of the first wire 141 by the self-induction action of the first inductor 281.

[0090] In addition, the semiconductor device 200 according to this embodiment further includes a second inductor 282 that is electrically connected to the second terminal 122b and the second wire 142 and is sealed by the sealing member 150. Therefore, it is possible to suppress the propagation of high-frequency noise from the IC chip 120 to the ground GND or the like that is the connection target of the second wire 142 by the self-induction action of the second inductor 282. In addition, it is possible to suppress the propagation of noise to other circuits sharing the ground GND.

[0091] Furthermore, in this embodiment, an example in which two inductors are provided in the semiconductor device has been described. However, when inductors are provided in the semiconductor device, the number of inductors provided is not limited to the above number.

[0092] <Third Embodiment>

[0093] Next, the third embodiment will be described.

[0094] Figure 9 It is a top view showing an IC chip and a silicon capacitor in the semiconductor device according to this embodiment.

[0095] Figure 10 (a) in Figure 9 is a cross-sectional view taken along the C-C' line of Figure 10 (b) in is a cross-sectional view showing the current path and the direction of the magnetic field.

[0096] The semiconductor device 300 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that a third terminal 322c is further provided for the IC chip 120 and in the structure of the silicon capacitor 330.

[0097] A third terminal 322c is further provided on the upper surface 120a of the IC chip 120. The second terminal 122b is located between the first terminal 122a and the third terminal 322c. The third terminal 322c is electrically connected to the logic circuit 122 within the IC chip 120.

[0098] The silicon capacitor 330, as shown in (a) of Figure 10 , has a substrate 331, a first conductive layer 332, a dielectric layer 333, a second conductive layer 334, two first internal electrodes 335a and 335b, a second internal electrode 336, an insulating layer 337, a protective layer 337s, a first external electrode 338, and a second external electrode 339.

[0099] Two channels 331a and 331b that are recessed upward from the lower surface are provided in the substrate 331.

[0100] The second conductive layer 334 is provided under the substrate 331. A plurality of channels 334a that are recessed upward from the lower surface are provided in a portion of the second conductive layer 334 that is within the channel 331a. In addition, a plurality of channels 334b that are recessed upward are provided in a portion of the second conductive layer 334 that is within the channel 331b.

[0101] The dielectric layer 333 has a first portion 333a and a second portion 333b. The first portion 333a is provided under the surfaces of the respective channels 334a and the regions around the respective channels 334a on the lower surface of the second conductive layer 334. The second portion 333b is provided under the surfaces of the respective channels 334b and the regions around the respective channels 334b on the lower surface of the second conductive layer 334.

[0102] The first conductive layer 332 has a first portion 332a and a second portion 332b. The first portion 332a is provided to fill the portion below the dielectric layer 333 within the respective channels 334a. In addition, the first portion 332a is provided under the portions of the dielectric layer 333 that protrude from the respective channels 334a. In addition, the second portion 332b is provided to fill the portion below the dielectric layer 333 within the respective channels 334b. In addition, the second portion 332b is provided under the portions of the dielectric layer 333 that protrude from the respective channels 334b.

[0103] The first internal electrode 335a is disposed directly below the first portion 332a of the first conductive layer 332 and is connected to the first portion 332a. The first internal electrode 335b is disposed directly below the second portion 332b of the first conductive layer 332 and is connected to the second portion 332b. The second internal electrode 336 is disposed between the two first internal electrodes 335a and 335b and is connected to the second conductive layer 334.

[0104] The insulating layer 337 covers the first conductive layer 332, the dielectric layer 333, and the second conductive layer 334. In addition, the insulating layer 337 covers a part of each of the first internal electrodes 335a and 335b and a part of the second internal electrode 336. The protective layer 337s covers the lower surface of the insulating layer 337.

[0105] The first opening 337a, the second opening 337b, and the third opening 337c are provided in the insulating layer 337 and the protective layer 337s. Another part of the first internal electrode 335a is exposed from the first opening 337a. Another part of the second internal electrode 336 is exposed from the second opening 337b. Another part of the first internal electrode 335b is exposed from the third opening 337c.

[0106] The first external electrode 338 is the positive electrode in the present embodiment. As Figure 9 shown, it has a first portion 338a, a second portion 338b, and a connecting portion 338c.

[0107] The first portion 338a is disposed in the first opening 337a as shown in (a) of Figure 10 . The first portion 338a is disposed directly below the first internal electrode 335a and directly above the first terminal 122a of the logic circuit 122 of the IC chip 120. The first portion 338a is connected to the first internal electrode 335a via the first opening 337a. The lower end of the first portion 338a is connected to the first terminal 122a via the first bump 161. The first portion 338a extends in the X direction as shown in Figure 9 .

[0108] The second portion 338b is disposed in the third opening 337c as shown in (a) of Figure 10 . The second portion 338b is disposed directly below the first internal electrode 335b and directly above the third terminal 322c of the logic circuit 122 of the IC chip 120. The second portion 338b is connected to the first internal electrode 335b via the third opening 337c. The lower end of the second portion 338b is connected to the third terminal 322c via the third bump 363. The second portion 338b is as shown in Figure 9As shown, it extends in the X direction. In addition, in the present embodiment, an example in which the second part 338b of the first external electrode 338 is electrically connected to the third terminal 322c by the third bump 363 has been described. However, regarding the specific configuration such as the shape and material of the conductive component used for the electrical connection between the second part of the first external electrode and the third terminal, as long as the second part of the first external electrode can be electrically connected to the third terminal, it is not limited to the above description.

[0109] The connecting portion 338c is connected to the first part 338a and the second part 338b. The connecting portion 338c extends in the Y direction. In addition, the connecting portion 338c may not be provided.

[0110] The second external electrode 339 is the negative electrode in the present embodiment. The second external electrode 339 has a third part 339a located between the first part 338a and the second part 338b. The third part 339a extends in the X direction.

[0111] The third part 339a is disposed in the second opening 337b as shown in (a) of Figure 10 . The third part 339a is provided directly below the second internal electrode 336 and directly above the second terminal 122b of the logic circuit 122 of the IC chip 120. The third part 339a is connected to the second internal electrode 336 via the second opening 337b. The lower end of the third part 339a is connected to the second terminal 122b via the second bump 162. The third part 339a extends in the X direction as shown in Figure 9 .

[0112] In this way, the silicon capacitor 330 has two sets of parts, namely, a part formed by the combination of the first part 338a and the third part 339a and a part formed by the combination of the second part 338b and the third part 339a.

[0113] As shown by the arrow I1 in (b) of Figure 10 , within the silicon capacitor 330, current flows from the third part 339a of the second external electrode 339 toward the first part 338a of the first external electrode 338. Moreover, as shown by the arrow I2, current flows from the first part 338a of the first external electrode 338 toward the first terminal 122a of the IC chip 120. In the IC chip 120, as shown by the arrow I3, current flows from the first terminal 122a toward the second terminal 122b. Moreover, as shown by the arrow I4, current flows from the second terminal 122b toward the third part 339a of the second external electrode 339 of the silicon capacitor 330. Therefore, a current loop IR1 is formed as shown by the arrows I1, I2, I3, and I4.

[0114] Similarly, as indicated by arrow I5, within the silicon capacitor 330, current flows from the third part 339a of the second external electrode 339 toward the second part 338b of the first external electrode 338. Further, as indicated by arrow I6, current flows from the second part 338b of the first external electrode 338 toward the third terminal 322c of the IC chip 120. In the IC chip 120, as indicated by arrow I7, current flows from the third terminal 322c toward the second terminal 122b. Further, as indicated by arrow I8, current flows from the second terminal 122b toward the third part 339b of the second external electrode 339 of the silicon capacitor 330. Accordingly, a current loop IR2 is formed as indicated by arrows I5, I6, I7, and I8.

[0115] As described above, as Figure 9 shown, the direction of the current loop IR1 is opposite to the direction of the current loop IR2. Among them, in Figure 9 , the current flowing within the silicon capacitor 330 is indicated by a solid arrow, and the current flowing within the IC chip 120 is indicated by a double-dashed arrow. The same applies in Figure 13 and Figure 15 described later. Therefore, the direction of the magnetic field H1 generated by the current loop IR1 is opposite to the direction of the magnetic field H2 generated by the current loop IR2. Accordingly, the two magnetic fields H1 and H2 are easily canceled out.

[0116] As described above, in the semiconductor device 300 according to the present embodiment, the third terminal 322c is provided on the upper surface 120a of the IC chip 120, and the second terminal 122b is disposed between the first terminal 122a and the third terminal 322c. Further, the first external electrode 338 has a first part 338a electrically connected to the first terminal 122a and a second part 338b electrically connected to the third terminal 322c, and the second external electrode 339 has a third part 339a located between the first part 338a and the second part 338b and electrically connected to the second terminal 122b. Accordingly, the direction of the current loop IR1 flowing through the first part 338a of the first external electrode 338, the third part 339a of the second external electrode 339, the second terminal 122b, and the first terminal 122a is opposite to the direction of the current loop IR2 flowing through the second part 338b of the first external electrode 338, the third part 339a of the second external electrode 339, the second terminal 122b, and the third terminal 322c. Therefore, the direction of the magnetic field H1 generated by the current loop IR1 is opposite to the direction of the magnetic field H2 generated by the current loop IR2. As a result, the two magnetic fields H1 and H2 are easily canceled out. As a result, the electromagnetic noise radiated from the IC chip 120 can be reduced.

[0117] Among them, in the above-described embodiment, the case where the first external electrode 338 is the positive electrode and the second external electrode 339 is the negative electrode has been described. However, it is also possible that the first external electrode is the negative electrode and the second external electrode is the positive electrode. That is, the negative electrode can have two parts, and at least a part of the positive electrode is provided between them. In addition, in the above-described embodiment, an example in which the silicon capacitor 330 has two sets of parts, namely, a part formed by the combination of the first part 338a and the third part 339a and a part formed by the combination of the second part 338b and the third part 339a, has been described. However, the silicon capacitor can also have four or more and an even number of sets.

[0118] <Fourth Embodiment>

[0119] Next, the fourth embodiment will be described.

[0120] Figure 11 It is a top view showing the semiconductor device according to this embodiment.

[0121] Figure 12 is Figure 11 a cross-sectional view taken along the line D-D' of

[0122] Figure 13 It is a top view showing the IC chip, the first silicon capacitor, and the second silicon capacitor of the semiconductor device according to this embodiment.

[0123] Figure 14 It is a circuit diagram of the semiconductor device according to this embodiment.

[0124] The semiconductor device 400 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that it further includes a silicon capacitor 430 in addition to the silicon capacitor 130. Hereinafter, the silicon capacitor 130 will be referred to as the "first silicon capacitor 130". In addition, the silicon capacitor 430 will be referred to as the "second silicon capacitor 430".

[0125] The switching circuit 123 of the IC chip 120 has a fourth terminal 423a and a fifth terminal 423b as shown in Figure 12 and Figure 13 The fourth terminal 423a and the fifth terminal 423b are, for example, pad electrodes provided on the upper surface 120a of the IC chip 120.

[0126] The third pad electrode 124c of the IC chip 120 is electrically connected to the fifth terminal 423b within the IC chip 120 as shown in Figure 14 The fourth pad electrode 124d is electrically connected to the fourth terminal 423a within the IC chip 120.

[0127] The second silicon capacitor 430 is as shown in Figure 13As shown, it is disposed on the upper surface 120a of the IC chip 120 and directly above the switching circuit 123.

[0128] Since the structure of the second silicon capacitor 430 is the same as that of the first silicon capacitor 130, a detailed description thereof is omitted. Hereinafter, the component corresponding to the first external electrode 138 of the first silicon capacitor 130 in the second silicon capacitor 430 will be referred to as the "third external electrode 438". In addition, the component corresponding to the second external electrode 139 of the first silicon capacitor 130 in the second silicon capacitor 430 will be referred to as the "fourth external electrode 439". In the present embodiment, the third external electrode 438 is the positive electrode and the fourth external electrode 439 is the negative electrode. As Figure 12 shown, similar to the first silicon capacitor 130, the third external electrode 438 and the fourth external electrode 439 are disposed on the lower surface 430b of the second silicon capacitor 430.

[0129] The third external electrode 438 is disposed directly above the fourth terminal 423a and is electrically connected to the fourth terminal 423a via a fourth bump 471 (fourth conductive member). The fourth external electrode 439 is disposed directly above the fifth terminal 423b and is electrically connected to the fifth terminal 423b via a fifth bump 472 (fifth conductive member). In addition, in the present embodiment, an example in which the fourth conductive member is the fourth bump 471 is described. However, for the specific configuration of the shape and material of the fourth conductive member, etc., as long as the third external electrode of the second silicon capacitor can be electrically connected to the fourth terminal of the IC chip, there is no particular limitation. In addition, in the present embodiment, an example in which the fifth conductive member is the fifth bump 472 is described. However, for the specific configuration of the shape and material of the fifth conductive member, etc., as long as the fourth external electrode of the second silicon capacitor can be electrically connected to the fifth terminal of the IC chip, there is no particular limitation.

[0130] As Figure 14 shown, in the present embodiment, the third wire 143 electrically connected to the third pad electrode 124c is connected to the ground GND during the use of the semiconductor device 100. In addition, the fourth wire 144 electrically connected to the fourth pad electrode 124d is connected to the second power supply V2 during the use of the semiconductor device 100. Therefore, the second silicon capacitor 430 can suppress the propagation of high-frequency noise from the switching circuit 123 to connection targets such as the second power supply V2 or the ground GND.

[0131] In addition, in the present embodiment, as Figure 13As shown, the direction from the first external electrode 138 toward the second external electrode 139 is opposite to the direction from the third external electrode 438 toward the fourth external electrode 439. Therefore, the direction of the current loop IR41 of the current flowing in the logic circuit 122 and the first silicon capacitor 130 is opposite to the direction of the current loop IR42 of the current flowing in the switch circuit 123 and the second silicon capacitor 430. As a result, the orientation of the magnetic field H41 generated by the current loop IR41 is opposite to the orientation of the magnetic field H42 generated by the current loop IR42, and the two magnetic fields H41 and H42 are easily canceled out. Therefore, the electromagnetic noise radiated from the IC chip 120 can be reduced.

[0132] As described above, in the semiconductor device 400 according to the present embodiment, the IC chip 120 further has a fourth terminal 423a and a fifth terminal 423b on the upper surface 120a. The semiconductor device 400 further includes a second silicon capacitor 430. The second silicon capacitor 430 is disposed to face the upper surface 120a. The second silicon capacitor 430 has a third external electrode 438 electrically connected to the fourth terminal 423a through a fourth bump 471 and a fourth external electrode 439 electrically connected to the fifth terminal 423b through a fifth bump 472 on the lower surface 430b facing the upper surface 120a. Therefore, the second silicon capacitor 430 can suppress the propagation of noise from the IC chip 120 to the connection target.

[0133] In addition, the IC chip 120 further has a switch circuit 123 electrically connected to the fourth terminal 423a and the fifth terminal 423b. The second silicon capacitor 430 is located directly above the switch circuit 123. Therefore, the second silicon capacitor 430 can be brought close to the switch circuit 123 which is the noise generation source. As a result, the propagation of noise from the IC chip 120 to the connection target can be suppressed efficiently.

[0134] In addition, the first external electrode 138 and the third external electrode 438 are positive electrodes, and the second external electrode 139 and the fourth external electrode 439 are negative electrodes. Moreover, the direction from the first external electrode 138 toward the second external electrode 139 is opposite to the direction from the third external electrode 438 toward the fourth external electrode 439. Therefore, the direction of the current loop IR41 of the current flowing in the first silicon capacitor 130 and the logic circuit 122 is opposite to the direction of the current loop IR41 of the current flowing in the second silicon capacitor 430 and the logic circuit 122. As a result, the orientation of the magnetic field H41 generated by the current loop IR41 is opposite to the orientation of the magnetic field H42 generated by the current loop IR42. As a result, the two magnetic fields H41 and H42 are easily canceled out. As a result, the electromagnetic noise radiated from the IC chip 120 can be reduced.

[0135] Figure 15 It is a top view showing modified examples of the IC chip, the first silicon capacitor, and the second silicon capacitor in the semiconductor device according to the present embodiment.

[0136] On the upper surface 120a of the IC chip 120, a third terminal 322c electrically connected to the logic circuit 122 can be provided in the same manner as in the third embodiment. In addition, a sixth terminal 423c electrically connected to the switch circuit 123 can also be provided on the upper surface 120a of the IC chip 120. The fourth terminal 423a is located between the fifth terminal 423b and the sixth terminal 423c.

[0137] Moreover, a first silicon capacitor 330 having the same configuration as the silicon capacitor 330 in the third embodiment can be provided on the logic circuit 122. Thus, in the same manner as in the third embodiment, current loops IR1 and IR2 in which two currents flow in opposite directions are generated. In addition, magnetic fields H1 and H2 in opposite directions are generated by the two current loops IR1 and IR2.

[0138] In addition, a second silicon capacitor 430s can be provided on the switch circuit 123. The structures of the positive electrode and the negative electrode of the second silicon capacitor 430s are opposite to those of the first silicon capacitor 330. The fourth external electrode 439s corresponding to the negative electrode has a first part 439a and a second part 439b, and the third external electrode 438s corresponding to the positive electrode has a third part 438a disposed between the first part 439a and the second part 439b. In the fourth external electrode 439s, the first part 439a and the second part 439b are connected by a connecting portion 439c.

[0139] The third part 438a of the third external electrode 438s is electrically connected to the fourth terminal 423a. The first part 439a of the fourth external electrode 439s is electrically connected to the fifth terminal 423b. The second part 439b of the fourth external electrode 439s is electrically connected to the sixth terminal 423c.

[0140] Thus, a current loop IR43 flowing through the third part 438a of the third external electrode 438s, the first part 439a of the fourth external electrode 439s, the fifth terminal 423b, and the fourth terminal 423a is generated. In addition, a current loop IR44 flowing through the third part 438a of the third external electrode 438s, the second part 439b of the fourth external electrode 439s, the sixth terminal 423c, and the fourth terminal 423a is generated. Magnetic fields H43 and H44 in opposite directions are generated by the two current loops IR43 and IR44.

[0141] Since the two magnetic fields H1 and H2 are oriented in opposite directions, they are easily canceled out. Additionally, since the two magnetic fields H43 and H44 are oriented in opposite directions, they are easily canceled out. Moreover, since the two magnetic fields H1 and H44 are oriented in opposite directions, they are easily canceled out. Also, since the two magnetic fields H2 and H43 are oriented in opposite directions, they are easily canceled out. Therefore, the electromagnetic noise radiated from the IC chip 120 can be reduced.

[0142] <Fifth Embodiment>

[0143] Next, the fifth embodiment will be described.

[0144] Figure 16 It is a cross-sectional view showing the semiconductor device according to this embodiment.

[0145] The semiconductor device 500 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that a silicon capacitor 530 is provided between the die pad 110 and the IC chip 520.

[0146] In the IC chip 520, the first terminal 522a and the second terminal 522b of the logic circuit 122 are provided on the lower surface 520b. Among them, Figure 16 in the bottom layer of the IC chip 520, a protective film 525 is provided, and the lower surfaces of the first terminal 522a and the second terminal 522b are substantially on the same plane as the lower surface of the protective film 525. However, the first terminal and the second terminal may also protrude downward from the lower surface of the protective film, or the IC chip may not have a protective film in the bottom layer and the first terminal and the second terminal may protrude downward from the lower surface of the IC chip.

[0147] The silicon capacitor 530 is configured in the same manner as the silicon capacitor 130 in the first embodiment, except that the first external electrode 138 and the second external electrode 139 are arranged upward. The first external electrode 138 of the silicon capacitor 530 is connected to the first terminal 522a provided on the lower surface 520b of the IC chip through the first bump 161. The second external electrode 139 of the silicon capacitor 530 is connected to the second terminal 522b provided on the lower surface 520b of the IC chip through the second bump 162.

[0148] As described above, in the semiconductor device 500 according to the present embodiment, the silicon capacitor 530 is disposed between the die pad 110 and the IC chip 520. In such a configuration, it is also possible to suppress the propagation of noise to the connection target of the IC chip 520 during the use of the semiconductor device 500 by the silicon capacitor 530. Further, in such a case, the IC chip 520 can be electrically connected to the die pad 110 through wiring components such as wire bonding. In addition, an insulating component may be provided between the silicon capacitor 530 and the die pad 110.

[0149] <Sixth Embodiment>

[0150] Next, the sixth embodiment will be described.

[0151] Figure 17 is a top view showing the semiconductor device according to the present embodiment.

[0152] Figure 18 is Figure 17 a cross-sectional view taken along line E-E' of

[0153] The semiconductor device 600 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in that the silicon capacitor 630 is provided on the die pad 110.

[0154] As Figure 17 shown, in a top view, the logic circuit 122 is located between the center C1 of the IC chip 120 and the silicon capacitor 630. Here, the center C1 of the IC chip 120 is located at the intersection of the diagonals of the IC chip 120.

[0155] The silicon capacitor 630 is, as Figure 17 and Figure 18 shown, except that the first external electrode 138 and the second external electrode 139 face upward and are configured to be adjacent to the IC chip 120 on the die pad 110, is configured in the same manner as the silicon capacitor 130 in the first embodiment. The sealing member 150 seals the silicon capacitor 630.

[0156] The first external electrode 138 of the silicon capacitor 630 is electrically connected to the first terminal 122a via the first wire bond 671 (first wiring component). As Figure 17 shown, the second external electrode 139 of the silicon capacitor 630 is electrically connected to the second terminal 122b via the second wire bond 672 (second wiring component). Further, in the present embodiment, an example in which the first wiring component and the second wiring component are wire bonds is described, but for the specific configurations such as the shape, position, and material of the first wiring component and the second wiring component, as long as the silicon capacitor can be electrically connected to the IC chip, there is no particular limitation.

[0157] As described above, the semiconductor device 600 according to the present embodiment includes a die pad 110, an IC chip 120, a silicon capacitor 630, a first wire 141, a second wire 142, and a sealing member 150. The IC chip 120 is disposed on the die pad 110 and has a first terminal 122a and a second terminal 122b. The silicon capacitor 630 has a first external electrode 638 electrically connected to the first terminal 122a via a first bonding wire 671 and a second external electrode 639 electrically connected to the second terminal 122b via a second bonding wire 672. The first wire 141 is electrically connected to the first terminal 122a. The second wire 142 is electrically connected to the second terminal 122b. The sealing member 150 seals the IC chip 120 and the silicon capacitor 630.

[0158] In this way, the silicon capacitor 630 is disposed on the die pad 110 and can also be electrically connected to the IC chip 120 through the bonding wires 671 and 672. In such a configuration, it is also possible to suppress noise propagation to the connection target of the IC chip 120 when the semiconductor device 100 is in use by the silicon capacitor 630.

[0159] In particular, the IC chip 120 and the silicon capacitor 630 are disposed on the die pad 110, and the silicon capacitor 630 is connected to the IC chip 120 through the bonding wires 671 and 672. Therefore, compared with a configuration in which the IC chip and the silicon capacitor are disposed on a substrate and the IC chip and the silicon capacitor are electrically connected via the wiring of the substrate, the semiconductor device 600 according to the present embodiment can be manufactured more easily because there is no need to provide wiring on the substrate.

[0160] In addition, the first bonding wire 671 may not be directly connected to the first terminal 122a but may be connected to the first pad electrode 124a. Similarly, the second bonding wire 672 may not be directly connected to the second terminal 122b but may be connected to the second pad electrode 124b.

[0161] <Seventh Embodiment>

[0162] Next, the seventh embodiment will be described.

[0163] Figure 19 is a top view showing the semiconductor device according to the present embodiment.

[0164] Figure 20 is Figure 19 a cross-sectional view taken along line F - F' of

[0165] The semiconductor device 700 according to this embodiment is different from the semiconductor device 600 according to the sixth embodiment in that it includes two silicon capacitors 731 and 732, and the two silicon capacitors 731 and 732 are arranged on the IC chip 120. Hereinafter, the silicon capacitor 731 will be referred to as the "first silicon capacitor 731", and the silicon capacitor 732 will be referred to as the "second silicon capacitor 732".

[0166] In the following description, as a principle, only the differences from the sixth embodiment will be described. Matters other than those described below are the same as those in the sixth embodiment.

[0167] The first silicon capacitor 731 is arranged on the IC chip 120 as Figure 20 shown. On the upper surface of the first silicon capacitor 731, as Figure 19 shown, a first external electrode 731a and a second external electrode 731b are provided. The first external electrode 731a is connected to the first terminal 122a of the IC chip 120 via a first bonding wire 871. The second external electrode 731b is connected to the second terminal 122b of the IC chip 120 via a second bonding wire 872.

[0168] The second silicon capacitor 732 is arranged on the first silicon capacitor 731 as Figure 20 shown. The second silicon capacitor 732 is configured in the same manner as the silicon capacitor 130, except that a third external electrode 732a corresponding to the first external electrode 138 and a fourth external electrode 732b corresponding to the second external electrode 139 are arranged upward.

[0169] The third external electrode 732a is electrically connected to the first external electrode 731a via a bonding wire 873. The fourth external electrode 732b is electrically connected to the second external electrode 731b via a bonding wire 874. The sealing member 150 seals the first silicon capacitor 731 and the second silicon capacitor 732.

[0170] As described above, in the semiconductor device 700 according to this embodiment, the first silicon capacitor 731 is arranged on the IC chip 120. In such a semiconductor device 700, noise can also be suppressed from spreading to the connection target of the IC chip 120 during the use of the semiconductor device 700 by the first silicon capacitor 731.

[0171] In addition, the semiconductor device 700 according to this embodiment further includes a second silicon capacitor 732 arranged on the first silicon capacitor 731 and having a third external electrode 732a electrically connected to the first external electrode 731a and a fourth external electrode 732b electrically connected to the second external electrode 731b. By arranging the first silicon capacitor 731 and the second silicon capacitor 732 in this way, the combined capacitance of the capacitors can be increased.

[0172] <Eighth Embodiment>

[0173] Next, the eighth embodiment will be described.

[0174] Figure 21 is a top view showing the semiconductor device according to this embodiment.

[0175] Figure 22 is Figure 21 a cross-sectional view taken along line G-G' of

[0176] The semiconductor device 800 according to this embodiment is different from the semiconductor device 600 according to the sixth embodiment in that the silicon capacitor 830 is disposed between the die pad 110 and the IC chip 120.

[0177] The silicon capacitor 830 is configured in the same manner as the silicon capacitor 130 in the first embodiment, except that the area of the silicon capacitor 830 is larger than the area of the IC chip 120 in a top view and the first external electrode 838 and the second external electrode 839 are disposed between the die pad 110 and the IC chip 120 in an upward direction. The first external electrode 838 of the silicon capacitor 830 is electrically connected to the first terminal 122a of the IC chip 120 via the first bonding wire 871. The second external electrode 839 of the silicon capacitor 830 is electrically connected to the second terminal 122b of the IC chip 120 via the second bonding wire 872. Herein, the IC chip 120 can be electrically connected to the die pad 110 via a bonding wire, for example.

[0178] As described above, in the semiconductor device 800 according to this embodiment, the silicon capacitor 830 is provided between the IC chip 120 and the die pad 110. In such a semiconductor device 800, noise propagation to the connection target of the IC chip 120 can also be suppressed by the silicon capacitor 830.

[0179] In addition, in such a semiconductor device 800, the area of the silicon capacitor 830 in a top view can be made larger than the area of the IC chip 120. Therefore, the capacitance of the silicon capacitor 830 can be increased.

[0180] As described above, a plurality of embodiments have been described, but the respective configurations described in these embodiments can be appropriately combined. For example, one or more inductors can be provided in the semiconductor device 600 according to the sixth embodiment as in the second embodiment. In addition, for example, the silicon capacitor 630 in the semiconductor device 600 according to the sixth embodiment can be configured as the silicon capacitor 330 in the third embodiment.

[0181] As described above, the embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, it includes: an IC chip having a first terminal, a second terminal, and a third terminal on a first surface, and the second terminal is disposed between the first terminal and the third terminal; and a first silicon capacitor facing the first surface of the IC chip and having a first electrode and a second electrode on a second surface facing the first surface, the first electrode has a first portion electrically connected to the first terminal through a first conductive member and a second portion electrically connected to the third terminal through a third conductive member, the second electrode has a third portion located between the first portion and the second portion and electrically connected to the second terminal through a second conductive member.

2. The semiconductor device according to claim 1, characterized in that, it further includes: a die pad, on which the IC chip is disposed; a first wire electrically connected to the first terminal; a second wire electrically connected to the second terminal; and a sealing member for sealing the IC chip and the first silicon capacitor.

3. The semiconductor device according to claim 2, characterized in that, it further includes an inductor electrically connected to the first terminal and the first wire and sealed by the sealing member.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, the IC chip further has a first circuit electrically connected to the first terminal and the second terminal, and the first silicon capacitor is located directly above the first circuit.

5. A semiconductor device, characterized in that, it includes: an IC chip having a first terminal, a second terminal, a fourth terminal, and a fifth terminal on a first surface; a first silicon capacitor facing the first surface of the IC chip and having a first electrode electrically connected to the first terminal through a first conductive member and a second electrode electrically connected to the second terminal through a second conductive member on a second surface facing the first surface; and a second silicon capacitor facing the first surface and having a third electrode connected to the fourth terminal through a fourth conductive member and a fourth electrode connected to the fifth terminal through a fifth conductive member on a third surface facing the first surface, the first electrode and the third electrode are one of a positive electrode and a negative electrode, the second electrode and the fourth electrode are the other of the positive electrode and the negative electrode, and the direction from the first electrode to the second electrode is opposite to the direction from the third electrode to the fourth electrode.

6. The semiconductor device according to claim 5, characterized in that, the IC chip further has a second circuit electrically connected to the fourth terminal and the fifth terminal, and the second silicon capacitor is located directly above the second circuit.

7. A semiconductor device, characterized in that, it includes: a die pad; an IC chip disposed on the die pad and having a first terminal and a second terminal; a first silicon capacitor having a first electrode electrically connected to the first terminal through a first wiring member and a second electrode electrically connected to the second terminal through a second wiring member; A second silicon capacitor is disposed on the first silicon capacitor and has a third electrode electrically connected to the first electrode and a fourth electrode electrically connected to the second electrode; A first wire is electrically connected to the first terminal; A second wire is electrically connected to the second terminal; And A sealing member seals the IC chip and the first silicon capacitor.

8. The semiconductor device according to claim 7, wherein, the first silicon capacitor is disposed on the die pad.

9. The semiconductor device according to claim 8, wherein, the IC chip further has a first circuit electrically connected to the first terminal and the second terminal, and the first circuit is located between the center of the IC chip and the first silicon capacitor in a top view.

10. The semiconductor device according to claim 7, wherein, the first silicon capacitor is disposed on the IC chip.

11. The semiconductor device according to claim 7, wherein, the first silicon capacitor is disposed between the IC chip and the die pad.

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