A semiconductor device and a method of manufacturing the same

Abstract

The present application provides a semiconductor device and a manufacturing method thereof. A substrate is provided, on which a first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked. A gate dielectric layer and a gate structure that surround the channel layer in the horizontal direction are provided around the channel layer. A spacer layer is formed on the outer sidewall of the gate structure. The gate structure is etched to reduce the thickness of the gate structure, a sacrificial structure covering the gate structure is formed, and a covering layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. In this way, the sacrificial structure is located outside the second source-drain layer and inside the spacer layer. Then, the covering layer is etched to obtain a first contact hole penetrating the sacrificial structure, the sacrificial structure at the bottom of the first contact hole is removed to form a gap below the first contact hole, and a first contact structure is formed in the first contact hole and the gap, realizing self-alignment between the bottom of the first contact structure and the gate structure, and improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] A vertical transistor is a transistor in which a source electrode, a channel, and a drain electrode are stacked longitudinally. Such a transistor has good device characteristics, such as good electrostatic characteristics, good control of the short-channel effect, and a small subthreshold waveguide to reduce power consumption, etc., and can further expand the device or increase the integration density of an integrated circuit. However, the current manufacturing process of vertical transistors causes reliability problems in vertical transistors. Summary of the Invention

[0003] In view of this, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, to achieve self-alignment of the gate contact and the gate, and improve the reliability of the device.

[0004] An embodiment of the present application provides a manufacturing method of a semiconductor device, including:

[0005] Providing a substrate; on the substrate, there are a first source-drain layer, a channel layer, and a second source-drain layer stacked in sequence; around the channel layer, there are a gate dielectric layer and a gate structure surrounding the channel layer in the horizontal direction, the gate structure has a first part extending in the horizontal direction and a second part extending upward outside the first part, and the second part is outside the second source-drain layer;

[0006] Forming a spacer layer on the outer sidewall of the gate structure;

[0007] Etching the gate structure to reduce the longitudinal dimension of the gate structure;

[0008] Forming a sacrificial structure covering the gate structure, and a covering layer covering the second source-drain layer, the sacrificial structure, and the spacer layer;

[0009] Etching the covering layer to obtain a first contact hole penetrating to the sacrificial structure, removing the sacrificial structure at the bottom of the first contact hole, and forming a gap below the first contact hole;

[0010] Forming a first contact structure in the first contact hole and the gap.

[0011] Optionally, a first dielectric layer surrounding the first source / drain layer is formed on the sidewalls of the first source / drain layer, and a second dielectric layer surrounding the second source / drain layer is formed on the sidewalls of the second source / drain layer; the sidewalls of the channel layer have a first recessed area relative to the first dielectric layer and the second dielectric layer; a gate dielectric layer and a gate structure are formed in the first recessed area, and before the spacer layer is formed on the outer sidewalls of the gate structure, the second portion extends upward to the sidewalls of the second dielectric layer.

[0012] Optionally, the gate structure further includes a third portion extending downward, and the third portion extends to the sidewalls of the first dielectric layer.

[0013] Optionally, the first dielectric layer and the second dielectric layer are formed through the following steps:

[0014] After etching the sequentially stacked first source / drain layer, channel layer, and second source / drain layer to achieve patterning, the channel layer is etched from the sidewalls of the channel layer, so that the sidewalls of the channel layer have a third recessed area relative to the first source / drain layer and the second source / drain layer;

[0015] A dummy gate structure is formed in the first recessed area;

[0016] The first source / drain layer and the second source / drain layer are etched from the sidewalls of the first source / drain layer and the sidewalls of the second source / drain layer, so that the sidewalls of the first source / drain layer have a fourth recessed area relative to the dummy gate structure, and the sidewalls of the second source / drain layer have a fifth recessed area relative to the dummy gate structure;

[0017] A first dielectric layer is formed in the fourth recessed area, and a second dielectric layer is formed in the fifth recessed area.

[0018] Optionally, the sidewalls of the channel layer have a second recessed area relative to the first source / drain layer and the second source / drain layer, a gate dielectric layer and a gate structure are formed in the second recessed area, before the spacer layer is formed on the outer sidewalls of the gate structure, the gate structure extends to the sidewalls of the second source / drain layer, and the bottom surface of the gate structure is higher than the top surface of the first source / drain layer; before forming the sacrificial structure covering the gate structure, the method further includes: forming an isolation layer on the sidewalls of the second source / drain layer.

[0019] Optionally, the method further includes:

[0020] Etching the covering layer to obtain a second contact hole penetrating to the second source / drain layer;

[0021] Forming a second contact structure in the second contact hole.

[0022] Optionally, the sacrificial structure is removed by wet etching.

[0023] An embodiment of the present application provides a semiconductor device, including:

[0024] A first source / drain layer, a channel layer, and a second source / drain layer stacked in sequence on a substrate;

[0025] A gate dielectric layer and a gate structure that laterally surround the channel layer; the gate structure extends in the horizontal direction;

[0026] A first contact structure connected to the gate structure; the first contact structure includes a fourth part connected to the gate structure and a fifth part connected to the fourth part in the longitudinal direction, and the lateral dimensions of the fourth part and the fifth part are different;

[0027] A spacer layer located on the outer sidewalls of the gate structure and the fourth part.

[0028] Optionally, a first dielectric layer surrounding the first source / drain layer is formed on the sidewall of the first source / drain layer, and a second dielectric layer surrounding the second source / drain layer is formed on the sidewall of the second source / drain layer; the sidewall of the channel layer has a first recessed area relative to the first dielectric layer and the second dielectric layer; a gate dielectric layer and a gate structure are formed in the first recessed area, and the fourth part is located on the sidewall of the second dielectric layer.

[0029] Optionally, the sidewall of the channel layer has a second recessed area relative to the first source / drain layer and the second source / drain layer, a gate dielectric layer and a gate structure are formed in the second recessed area, the fourth part is located on the sidewall of the second dielectric layer, and the bottom surface of the gate structure is higher than the top surface of the first source / drain layer; an isolation layer is formed between the second source / drain layer and the fourth part.

[0030] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. A substrate is provided, on which a first source / drain layer, a channel layer, and a second source / drain layer are sequentially stacked. A gate dielectric layer and a gate structure that surround the channel layer in the horizontal direction are provided around the channel layer. The gate structure has a first portion extending in the horizontal direction and a second portion extending upward around the first portion. The second portion is outside the second source / drain layer. A spacer layer is formed on the outer sidewall of the gate structure, the gate structure is etched to reduce the thickness of the gate structure, a sacrificial structure covering the gate structure is formed, and a covering layer covering the second source / drain layer, the sacrificial structure, and the spacer layer is formed. In this way, the sacrificial structure is located outside the second source / drain layer and inside the spacer layer. Then, the covering layer is etched to obtain a first contact hole penetrating the sacrificial structure, the sacrificial structure at the bottom of the first contact hole is removed to form a gap below the first contact hole, and a first contact structure is formed in the first contact hole and the gap. During the formation of the first contact structure, the spacer layer can limit the position of the first contact structure, making the bottom of the first contact structure self-aligned with the gate structure, improving the contact quality between the first contact structure and the gate structure, enhancing the reliability of the device, and reducing the precision required for the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0033] Figures 2A - 33 It is a schematic structural diagram of a semiconductor device in the manufacturing method. DETAILED DESCRIPTION

[0034] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will provide a detailed description of the specific embodiments of the present application with reference to the drawings.

[0035] Many specific details are set forth in the following description to facilitate a thorough understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0036] Secondly, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual manufacturing, three-dimensional spatial dimensions including length, width, and depth should be included.

[0037] A vertical transistor is a transistor in which a source electrode, a channel, and a drain electrode are stacked longitudinally. Such a transistor has good device characteristics, such as good electrostatic characteristics, good control of the short-channel effect, and a small subthreshold waveguide to reduce power consumption, etc., and can further expand the device or increase the integration density of an integrated circuit. However, the current manufacturing process of vertical transistors causes reliability problems in vertical transistors. In fact, there are alignment problems between the current gate contact and the gate structure. How to achieve self-alignment of the gate contact and the gate structure, while reducing costs and ensuring the reliability of the transistor, is an important issue in this field.

[0038] Based on this, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof. A substrate is provided, and a first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. A gate dielectric layer and a gate structure that surround the channel layer in the horizontal direction are provided outside the channel layer. The gate structure has a first portion extending in the horizontal direction and a second portion extending upward outside the first portion. The second portion is outside the second source-drain layer. A spacer layer is formed on the outer sidewall of the gate structure, the gate structure is etched to reduce the thickness of the gate structure, a sacrificial structure covering the gate structure is formed, and a covering layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. In this way, the sacrificial structure is located outside the second source-drain layer and inside the spacer layer. Then, the covering layer is etched to obtain a first contact hole penetrating the sacrificial structure, the sacrificial structure at the bottom of the first contact hole is removed to form a gap below the first contact hole, and a first contact structure is formed in the first contact hole and the gap. During the formation of the first contact structure, the spacer layer can limit the position of the first contact structure, making the bottom of the first contact structure self-aligned with the gate structure, improving the contact quality between the first contact structure and the gate structure, improving the reliability of the device, and reducing the precision required by the manufacturing process.

[0039] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the drawings.

[0040] Refer to Figure 1 As shown, it is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present application. Refer to Figures 2A - 33 As the schematic structural diagram of the semiconductor device in this manufacturing method. Specifically, this manufacturing method includes:

[0041] S101, provide a substrate 100. Refer toFigures 2A - 12B , Figures 21 - 24 as shown.

[0042] In an embodiment of the present application, the substrate 100 is a semiconductor substrate, which may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator), or a GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., may also be a stacked structure, such as Si / SiGe, etc., may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. In this embodiment, the substrate 100 is a silicon substrate, which is used to support the device structure thereon.

[0043] Referring to Figure 2A and Figure 2B as shown, where Figure 2A is a top view of the semiconductor device, Figure 2B is a cross-sectional view of the semiconductor device along the AA direction. In the substrate 100, there may be a well region 101, which is obtained by doping the substrate 100. In an N-type FET, the well region 101 may have a P-type doping element, for example, the well region 101 is doped with B or In, etc., and the doping concentration may be 1e17 - 2e19 / cm 3 ; in a P-type FET, the well region 101 may have an N-type doping element, for example, the well region 101 is doped with As or P, etc., and the doping concentration may be 1e17 - 2e19 / cm 3 . The well region 101 can be formed into the required shape by ion implantation and thermal annealing. The well region 101 can isolate the substrate 100 and the semiconductor device thereon, preventing the semiconductor device from leaking current through the substrate 100.

[0044] On the substrate 100, there are sequentially stacked a first source / drain layer 110, a channel layer 120, and a second source / drain layer 130. One of the first source / drain layer 110 and the second source / drain layer 130 serves as the source electrode, and the other serves as the drain electrode. Specifically, a first source / drain layer 110 covering the substrate 100, a channel layer 120 covering the first source / drain layer 110, and a second source / drain layer 130 covering the channel layer 120 can be formed on the substrate 100 first. Referring to Figure 3 as shown, which is a cross-sectional view of the semiconductor structure along the AA direction, and then the second source / drain layer 130, the channel layer 120, and the first source / drain layer 110 are etched to form the required shapes of the first source / drain layer 110, the channel layer 120, and the second source / drain layer 130, realizing the patterning of the first source / drain layer 110, the channel layer 120, and the second source / drain layer 130. Referring to Figure 4A , Figure 4B and Figure 5 as shown.Figure 4A The top view of another semiconductor device provided by the embodiment of the present application Figure 4B is Figure 4A the cross-sectional view of the semiconductor device along the AA direction

[0045] During specific implementation, an epitaxy (EPI) technology can be used to form a first semiconductor layer covering the substrate 100 on the substrate 100, and the first semiconductor is doped to obtain a first source / drain layer 110. Among them, the material of the first semiconductor layer can be silicon, and the doping method can be in-situ doping. In a P-type FET, the doping element can be a P-type element, such as B or In, etc., and the doping concentration range is 1e18 - 2e20 / cm 3 ; in an N-type FET, the doping element can be an N-type element, such as As or P, etc., and the doping concentration range is 1e18 - 1e21 / cm 3 . The thickness range of the first source / drain layer 110 is 10nm - 50nm

[0046] During specific implementation, an epitaxy technology can be used to form a channel layer 120 covering the first source / drain layer 110. The channel layer 120 can be doped or undoped. Among them, the material of the channel layer 120 is silicon germanium, and the molecular number of germanium accounts for 10 - 40% of the total molecular number. The thickness of the channel layer 120 defines the longitudinal channel length and also limits the gate length to a certain extent, which is used to control the electrical characteristics of the device, such as the short channel effect, etc. The thickness range of the channel layer 120 is 10 - 100nm

[0047] During specific implementation, an epitaxy technology can be used to form a second semiconductor layer covering the channel layer 120, and the second semiconductor layer is doped to obtain a second source / drain layer 130. Among them, the material of the second semiconductor layer is silicon, and the doping method can be in-situ doping. In a P-type FET, the doping element can be a P-type doping element, such as B or In, etc., and the doping concentration range is 1e18 - 2e20 / cm 3 ; in an N-type FET, the doping element can be an N-type element, such as As or P, etc., and the doping concentration range is 1e18 - 1e21 / cm 3 . The thickness range of the first source / drain layer 110 is 10nm - 50nm

[0048] It should be noted that in a MOS device, the first source / drain layer 110 and the second source / drain layer 130 can be doped with the same type of doping element, while in a tunneling field-effect transistor (TFET), the first source / drain layer 110 and the second source / drain layer 130 can be doped with opposite types of doping elements

[0049] In the embodiments of the present application, a dielectric layer may further be formed on the second source / drain layer 130. The dielectric layer may protect the second source / drain layer 130 and may also serve as a hard mask for subsequent etching of the second source / drain layer 130, the channel layer 120, and the first source / drain layer 110. Specifically, the dielectric layer may include a protective layer 141 and a hard mask layer 142 on the protective layer 141. The protective layer 141 is used to protect the second source / drain layer 130 and may also serve as an etch stop layer for the hard mask layer 142. The material of the protective layer 141 may be an oxide, such as a thermal oxide, and its thickness range may be 2 - 5 nm, which is obtained by thermally oxidizing the surface of the second source / drain layer 130. The material of the hard mask layer 142 may be a nitride or a low dielectric constant (low-k) material. The low-k material may be, for example, a silicon carbide-based material, etc. The thickness range of the hard mask layer 142 may be 10 nm - 100 nm.

[0050] Reference Figure 4A and Figure 4B As shown, a patterned photoresist layer 143 may be formed on the dielectric layer. The lateral dimension of the photoresist layer 143 may be smaller than the lateral dimension of the well region 101, so that the formed functional film layer is limited within the well region 101 to ensure the reliability of the device. On the Figure 4B basis, the pattern of the photoresist layer 143 is transferred to the dielectric layer, and the second source / drain layer 130, the channel layer 120, and the first source / drain layer 110 are etched using the patterned dielectric layer as a mask to obtain the desired shapes of the second source / drain layer 130, the channel layer 120, and the first source / drain layer 110. Reference Figure 5 is shown. Of course, the substrate 100 within the well region 101 may also be etched to further improve the reliability of the device.

[0051] After etching the second source / drain layer 130, the channel layer 120, and the first source / drain layer 110, the photoresist layer 143 may be removed, and a shallow trench isolation (STI) structure 102 is formed on the substrate 100 for isolating different devices. In the case where the substrate 100 within the well region 101 is etched, the shallow trench isolation structure 102 may surround the sidewalls of the well region 101 under the first source / drain layer 110 for isolating different well regions 101. The shallow trench isolation structure 102 may cover all the sidewalls of the well region 101 or may cover the lower half of the sidewalls of the well region 101. Reference Figure 6A , Figure 6B and Figure 6C are shown, where Figure 6A is a three-dimensional structure diagram of the semiconductor device, Figure 6B is Figure 6A a cross-sectional view of the semiconductor device in Figure 6C along the AA direction, Figure 6A and is a cross-sectional view of the semiconductor device in Figure 6A along the BB direction.

[0052] In some scenarios, the shallow trench isolation structure 102 can also cover the sidewalls of the first source / drain layer 110 for protecting the first source / drain layer 110 and for isolating the first source / drain layer 110 from other film layers, such as a semiconductor layer or a conductor layer.

[0053] The shallow trench isolation structure 102 can be obtained through a deposition process and an etching process. Specifically, an isolation material can be deposited, and then the isolation material located on the surface of the dielectric layer can be etched away. The isolation material located on the sidewalls of the second source / drain layer 130, the channel layer 120, and the first source / drain layer 110 can be etched away. The isolation material on the substrate 100 can be planarized. When it is necessary to retain the isolation material on the sidewalls of the first source / drain layer 110, the isolation material on the sidewalls of the first source / drain layer 110 can be not etched. The ways of etching away the isolation material can include wet etching, vapor etching, vapor HF, etc.

[0054] After the shallow trench isolation structure 102 is formed, the gate dielectric layer 151 and the gate structure 150 around the channel layer 120 can be formed. The formed gate dielectric layer 151 and gate structure 150 surround the channel layer 120 in the horizontal direction. The gate structure 150 can have a first part extending in the horizontal direction and a second part extending upward around the first part. The second part can be located around the second source / drain layer 130.

[0055] The embodiments of the present application provide two structures: In the first structure, a first dielectric layer 111 surrounding the first source / drain layer 110 is formed on the sidewalls of the first source / drain layer 110, a second dielectric layer 131 surrounding the second source / drain layer 130 is formed on the sidewalls of the second source / drain layer 130, and the sidewalls of the channel layer 120 have a first recessed area relative to the first dielectric layer 111 and the second dielectric layer 131. The gate dielectric layer 151 and the gate structure 150 are formed in the first recessed area; In the second structure, the sidewalls of the channel layer 120 have a second recessed area relative to the first source / drain layer 110 and the second source / drain layer 130. The gate dielectric layer 151 and the gate structure 150 are formed in the second recessed area. The following will respectively elaborate on these two structures in detail.

[0056] In the first structure, a second dielectric layer 131 is formed around the second source / drain layer 130. Then, the second part of the gate structure 150 can extend to the sidewall of the second dielectric layer 131, and the second dielectric layer 131 isolates the second source / drain layer 130 after the second part. Since the first dielectric layer 111 is provided around the first source / drain layer 110, the shallow trench isolation structure 102 can not cover the sidewalls of the first source / drain layer 110. And since the first dielectric layer 111 covers the first source / drain layer 110, the gate structure 150 can also have a third part extending downward, and the third part extends to the sidewall of the first dielectric layer 111. The first dielectric layer 111 isolates the third part and the first source / drain layer 110.

[0057] In the formation process of the first structure, the first dielectric layer 111 surrounding the first source / drain layer 110 and the second dielectric layer 131 surrounding the second source / drain layer 130 can be formed first, and then the gate dielectric layer 151 and the gate structure 150 are formed in the first recessed region of the channel layer 120 with respect to the first dielectric layer 111 and the second dielectric layer 131.

[0058] Wherein, the first dielectric layer 111 and the second dielectric layer 131 can be formed through the following steps:

[0059] After etching the sequentially stacked first source / drain layer 110, channel layer 120, and second source / drain layer 130 to achieve patterning, the channel layer 120 is etched from the sidewalls of the channel layer 120, so that the sidewalls of the channel layer 120 have a third recessed region with respect to the first source / drain layer 110 and the second source / drain layer 130. Refer to Figure 7A 、 Figure 7B and Figure 7C shown, wherein Figure 7A is a three-dimensional structure schematic diagram of another semiconductor structure provided by an embodiment of the present application, Figure 7B is Figure 7A a cross-sectional view of the semiconductor structure in Figure 7C along the AA direction, Figure 7A is a cross-sectional view of the semiconductor structure in

[0060] Specifically, after etching the sequentially stacked first source / drain layer 110, channel layer 120, and second source / drain layer 130 to achieve patterning, since the first source / drain layer 110, channel layer 120, and second source / drain layer 130 are etched using the same hard mask layer 142, the sidewalls of the obtained first source / drain layer 110, second source / drain layer 130, and channel layer 120 are substantially flush. Then, the channel layer 120 is etched from the sidewalls of the channel layer 120 to reduce the lateral dimension of the channel layer 120. The etching dimension of the channel layer 120 is mainly used to define the lateral dimension and current amount of the device. The larger the remaining lateral dimension of the channel layer 120, the larger the current amount in the longitudinal channel formed in the channel layer 120, and the corresponding larger the lateral dimension of the device. The etching of the channel layer 120 can use atomic layer etching to achieve good etching control of the channel shape.

[0061] After that, a dummy gate structure 121 is formed in the third recessed region. Refer to Figure 8A and Figure 8B shown, wherein Figure 8A is a cross-sectional view of the semiconductor structure along the AA direction, Figure 8BA cross-sectional view of the semiconductor structure along the BB direction. The dummy gate structure 121 fills the third recessed region. The outer sidewalls of the dummy gate structure 121 can be flush with the sidewalls of the first source / drain layer 110 and the sidewalls of the second source / drain layer 130, so as to protect the channel layer 120 surrounded by the dummy gate structure 121 by using the dummy gate structure 121. The dummy gate structure 121 can be nitrogen oxide or silicon carbide, etc. The material of the dummy gate structure 121 is different from that of the hard mask layer 142, so that they can be removed separately.

[0062] After that, the first source / drain layer 110 and the second source / drain layer 130 are etched from the sidewalls of the first source / drain layer 110 and the sidewalls of the second source / drain layer 130, so that the sidewall of the first source / drain layer 110 has a fourth recessed region relative to the dummy gate structure 121, and the sidewall of the second source / drain layer 130 has a fifth recessed region relative to the dummy gate structure 121. Refer to Figure 9A and Figure 9B as shown, where Figure 9A is a cross-sectional view of the semiconductor structure along the AA direction, Figure 9B is a cross-sectional view of the semiconductor structure along the BB direction. During the etching process of the first source / drain layer 110 and the second source / drain layer 130, if the channel layer 120 is not exposed, the channel layer 120 will not be damaged. After the lateral etching of the first source / drain layer 110 and the second source / drain layer 130, the sidewall of the first source / drain layer 110 can be flush with the sidewall of the channel layer 120, and the sidewall of the second source / drain layer 130 can also be flush with the sidewall of the channel layer 120. Of course, there may still be a recessed region on the sidewall of the channel layer 120 relative to the first source / drain layer 110, and there may still be a recessed region on the sidewall of the channel layer 120 relative to the second source / drain layer 130. The lateral etching of the first source / drain layer 110 and the second source / drain layer 130 can reduce the overlap capacitance between the source / drain and the gate. After etching, the lateral dimensions of the first source / drain layer 110 and the second source / drain layer 130 become smaller. When etching the first source / drain layer 110, the well region 101 under the first source / drain layer 110 can be etched simultaneously to reduce the lateral dimension of the top of the well region 101.

[0063] After that, a first dielectric layer 111 is formed in the fourth recessed region, and a second dielectric layer 131 is formed in the fifth recessed region. Refer to Figure 10A and Figure 10B as shown, where Figure 10A is a cross-sectional view of the semiconductor structure along the AA direction, Figure 10BA cross-sectional view of the semiconductor structure along the BB direction. The first dielectric layer 111 and the second dielectric layer 131 can both be oxide layers. The first dielectric layer 111 and the second dielectric layer 131 can be formed by the same process and have different names due to their different positions. Specifically, an oxide can be deposited and then etched back to expose the dummy gate structure 121, resulting in the first dielectric layer 111 and the second dielectric layer 131. The first dielectric layer 111 can extend laterally onto the shallow trench isolation structure 102. The upper surface of the first dielectric layer 111 is lower than the bottom surface of the dummy gate structure 121. The upper surface of the first dielectric layer 111 outside the fourth recessed area can be lower than the upper surface of the first dielectric layer 111 inside the fourth recessed area. The second dielectric layer 131 is formed in the fifth recessed area. Among them, the material of the first dielectric layer 111 and the material of the shallow trench isolation structure 102 can be the same. Since they are formed at different times, in order to distinguish the two, they are separated by a dotted line in the figure. The material of the second dielectric layer 131 and the material of the protective layer 141 can be the same. Since they are formed at different times, in order to distinguish the two, they are separated by a dotted line in the figure.

[0064] Among them, after forming the first dielectric layer 111 and the second dielectric layer 131, forming the gate dielectric layer 151 and the gate structure 150 in the first recessed area can be achieved through the following steps:

[0065] Remove the dummy gate structure 121 in the first recessed area. When removing the dummy gate structure 121, the hard mask layer 142 can not be etched. Then, a gate dielectric layer 151 covering the surface of the first recessed area is formed in the first recessed area. The gate dielectric layer 151 covers the upper surface of the first source / drain layer 110, the sidewalls of the channel layer 120, and the lower surface of the second source / drain layer 130 in the first recessed area. Specifically, a gate dielectric material layer can be deposited and then etched to retain only the gate dielectric material layer in the first recessed area as the gate dielectric layer 151. The material of the gate dielectric layer 151 is a high-k dielectric layer.

[0066] After that, the gate structure 150 is formed. Specifically, a gate material 150' can be deposited. The formed gate material 150' is located in the first recessed area and also outside the first recessed area. Refer to Figure 11A and Figure 11B , where Figure 11A is a cross-sectional view of the semiconductor structure along the AA direction, Figure 11B is a cross-sectional view of the semiconductor structure along the BB direction. The gate material 150' is etched to obtain the gate structure 150. The gate dielectric layer 151 is disposed between the channel layer 120 and the gate structure 150. The formed gate structure 150 surrounds the channel layer 120 in the horizontal direction. The gate structure 150 can have a first part extending in the horizontal direction and a second part extending upward around the first part. The second part can be located around the second source / drain layer 130. Refer toFigure 12A and Figure 12B as shown, where Figure 12A is a cross-sectional view of the semiconductor structure along the AA direction, Figure 12B is a cross-sectional view of the semiconductor structure along the BB direction. The gate structure 150 may further have a third part extending downward, and the third part extends to the sidewall of the first dielectric layer 111, and the first dielectric layer 111 isolates the third part from the first source / drain layer 110. In addition, the second part of the gate structure 150 may further extend to the sidewall of the hard mask layer 142, that is, the upper surface of the second part may be higher than the upper surface of the second source / drain layer 130.

[0067] In the second structure, the sidewall of the channel layer 120 has a second recessed area relative to the first source / drain layer 110 and the second source / drain layer 130. When no dielectric layer is provided on the sidewall of the first source / drain layer 110 and the gate structure 150 does not extend to the sidewall of the first source / drain layer 110, the bottom surface of the gate structure 150 is higher than the top surface of the first source / drain layer 110 to isolate the gate structure 150 from the first source / drain layer 110. In the embodiments of the present application, after etching the sequentially stacked first source / drain layer 110, channel layer 120, and second source / drain layer 130 to achieve patterning, a shallow trench isolation structure 102 may be formed. The shallow trench isolation structure 102 may cover the sidewall of the first source / drain layer 110 to prevent the subsequently formed gate structure 150 from contacting the sidewall of the first source / drain layer 110. Refer to Figure 21 as shown, Figure 21 which is a cross-sectional view of the semiconductor structure along the AA direction.

[0068] After that, the channel layer 120 may be etched from the sidewall of the channel layer 120 so that the sidewall of the channel layer 120 has a second recessed area relative to the first source / drain layer 110 and the second source / drain layer 130. Refer to Figure 22A and Figure 22B as shown, Figure 22A which is a cross-sectional view of the semiconductor structure along the AA direction, Figure 22B and is a cross-sectional view of the semiconductor structure along the BB direction. The etching of the channel layer 120 refers to the foregoing description and will not be elaborated here. After etching the channel layer 120 to obtain the second recessed area, a gate dielectric layer 151 may be formed in the second recessed area. The formation of the gate dielectric layer 151 refers to the foregoing description and will not be elaborated here.

[0069] After that, the gate structure 150 may be formed. Specifically, the gate material 150' may be deposited first, and the formed gate material 150' is located in the first recessed area and also outside the first recessed area. Refer to Figure 23A and Figure 23B as shown, Figure 23A which is a cross-sectional view of the semiconductor structure along the AA direction, Figure 23BA cross-sectional view of the semiconductor structure along the BB direction. Since the shallow trench isolation structure 102 can cover the sidewalls of the first source / drain layer 110, the gate material 150' is not disposed on the sidewalls of the first source / drain layer 110. The gate material 150' is etched to obtain the gate structure 150. The gate dielectric layer 151 is disposed between the channel layer 120 and the gate structure 150. The formed gate structure 150 surrounds the channel layer 120 in the horizontal direction. The gate structure 150 may have a first portion extending in the horizontal direction and a second portion extending upward around the first portion. The second portion may be located around the second source / drain layer 130. Refer to Figure 24 as shown, wherein Figure 24 is a cross-sectional view of the semiconductor structure along the AA direction. The gate structure 150 extends to the sidewall of the second source / drain layer 130, and the bottom surface of the gate structure 150 is higher than the top surface of the first source / drain layer 110. In addition, the second portion of the gate structure 150 may further extend to the sidewall of the hard mask layer 142, that is, the upper surface of the second portion may be higher than the upper surface of the second source / drain layer 130.

[0070] S102, a spacer layer 152 is formed on the outer sidewall of the gate structure 150. Refer to Figure 13A 、 Figure 13B and Figure 25 as shown.

[0071] In an embodiment of the present application, after the gate structure 150 is formed, a spacer layer 152 may be formed on the outer sidewall of the gate structure 150. The spacer layer 152 may be formed by a deposition and etching process. When the gate structure 150 surrounds the channel layer 120, the spacer layer 152 may surround the gate structure 150 and form a ring in the horizontal direction. The material of the spacer layer 152 may be nitrogen oxide. The lateral dimension range of the spacer layer 152 may be 5 nm - 50 nm. The spacer layer 152 is formed along the outer sidewall of the gate structure 150. The gate structure 150 defines the position and the inner sidewall of the spacer layer 152. The longitudinal dimension of the spacer layer 152 may be the same as the longitudinal dimension of the gate structure 150, or may be slightly smaller than the longitudinal dimension of the gate structure 150.

[0072] In the first structure, the semiconductor structure after the spacer layer 152 is formed may be referred to Figure 13A and Figure 13B as shown, wherein Figure 13A is a cross-sectional view of the semiconductor structure along the AA direction, Figure 13B is a cross-sectional view of the semiconductor structure along the BB direction; in the second structure, the semiconductor structure after the spacer layer 152 is formed may be referred to Figure 25 as shown, wherein Figure 25 is a cross-sectional view of the semiconductor structure along the AA direction.

[0073] S103, etch the gate structure 150 to reduce the longitudinal dimension of the gate structure 150, as shown in reference Figure 14 and Figure 26 shown.

[0074] After forming the spacer layer 152, the gate structure 150 can be etched to reduce the longitudinal dimension of the gate structure 150. The top surface of the etched gate structure 150 is higher than the upper surface of the gate dielectric layer 151 on the first source / drain layer 110, so as to keep the overall structure of the gate structure 150.

[0075] In the first structure, the top surface of the gate structure 150 can be lower than the lower surface of the gate dielectric layer 151 under the second source / drain layer 130. The semiconductor structure after etching the gate structure 150 can be referred to Figure 14 shown, where Figure 14 is a cross-sectional view of the semiconductor structure along the AA direction. The top surface of the gate structure 150 can also be higher than the lower surface of the second source / drain layer 130. Since the sidewall of the second source / drain layer 130 is formed with a second dielectric layer 131, the part of the gate structure 150 higher than the lower surface of the second source / drain layer 130 is separated from the second source / drain layer 130 by the second dielectric layer 131.

[0076] In the second structure, the top surface of the gate structure 150 is lower than the lower surface of the gate dielectric layer 151 under the second source / drain layer 130. The semiconductor structure after etching the gate structure 150 can be referred to Figure 26 shown, where Figure 26 is a cross-sectional view of the semiconductor structure along the AA direction. The top surface of the gate structure 150 can also be higher than the lower surface of the gate dielectric layer 151 under the second source / drain layer 130 and lower than the upper surface of the gate dielectric layer 151 under the second source / drain layer 130, because no dielectric layer is provided on the sidewall of the second source / drain layer 130, and the gate structure 150 and the second source / drain layer 130 cannot be in direct contact.

[0077] S104, form a sacrificial structure 154 covering the gate structure 150, and a capping layer 160 covering the second source / drain layer 130, the sacrificial structure 154 and the spacer layer 152, as shown in reference Figure 15 、 Figure 16 、 Figure 27 、 Figure 28 and Figure 29 shown.

[0078] In the embodiment of the present application, after etching the gate structure 150, a sacrificial structure 154 covering the gate structure 150 can be formed. The sacrificial structure 154 is disposed above the gate structure 150 and between the second source / drain layer 130 and the spacer layer 152. In the horizontal direction, the sacrificial structure 154 can be ring-shaped. The material of the sacrificial structure 154 can be nitride. The sacrificial structure 154 can be formed by a deposition process and an etching process. While forming the sacrificial structure 154, a third dielectric layer 153 made of the same material as the sacrificial structure 154 can be formed in an area outside the spacer layer 152. When the material of the sacrificial structure 154 is consistent with the material of the hard mask layer 142, the hard mask layer 142 can be removed simultaneously during the process of forming the sacrificial structure 154.

[0079] In the first structure, the semiconductor device after forming the sacrificial structure 154 can refer to Figure 15 As shown, Figure 15 The sectional view of the semiconductor structure along the AA direction is shown. The sacrificial structure 154 is formed above the gate structure 150 and is located between the second dielectric layer 131 and the spacer layer 152 . The third dielectric layer 153 made of the same material as the sacrificial structure 154 is located on the first dielectric layer 111 .

[0080] In the second structure, before forming the sacrificial layer, an isolation layer 156 may be formed on the sidewall of the second source / drain layer 130. The isolation layer 156 located on the sidewall of the second source / drain layer 130 is used to isolate the second source / drain layer 130 from the first contact structure 163 formed subsequently. The material of the isolation layer 156 may be a high-k dielectric material, such as an oxide. The lateral size of the isolation layer 156 ranges from 3 nm to 15 nm. The semiconductor device after forming the isolation layer 156 can refer to Figure 27 As shown, Figure 27 1 is a cross-sectional view of the semiconductor structure along the AA direction, wherein the isolation layer 156 can be provided on the sidewalls of the second source / drain layer 130 and the sidewalls of the hard mask layer 142. Of course, during the process of forming the isolation layer 156, the isolation layer 156 can also be provided on the sidewalls of the detection layer. After forming the isolation layer 156, a sacrificial structure 154 can be formed on the gate structure 150. The semiconductor device after forming the sacrificial structure 154 can refer to Figure 28 As shown, Figure 28 1 is a cross-sectional view of the semiconductor structure along line AA, wherein a sacrificial structure 154 is formed above the gate structure 150 , and the sacrificial structure 154 is located between two isolation layers 156 .

[0081] In the embodiments of the present application, after forming the sacrificial structure 154, a capping layer 160 covering the second source / drain layer 130, the sacrificial structure 154, and the spacer layer 152 may be formed. The material of the capping layer 160 may be an oxide, such as silicon oxide. The capping layer 160 may be formed by a deposition process and an etching process, and the upper surface of the capping layer 160 may be a flat surface.

[0082] In the first structure, the semiconductor device after forming the capping layer 160 may be referred to Figure 16 as shown Figure 16 which is a cross-sectional view of the semiconductor structure along the AA direction, and the capping layer 160 covers the protective layer 141, the sacrificial layer, the spacer layer 152, and the third dielectric layer 153.

[0083] In the second structure, the semiconductor device after forming the capping layer 160 may be referred to Figure 29 as shown Figure 29 which is a cross-sectional view of the semiconductor structure along the AA direction, and the capping layer 160 covers the protective layer 141, the sacrificial layer, the spacer layer 152, the isolation layer 156, and the third dielectric layer 153.

[0084] S105, etch the capping layer 160 to obtain a first contact hole 161 penetrating through to the sacrificial structure 154, remove the sacrificial structure 154 at the bottom of the first contact hole 161, and form a gap 162 below the first contact hole 161, refer to Figure 17 、 Figure 18 、 Figure 30 and Figure 31 as shown.

[0085] In the embodiments of the present application, after forming the capping layer 160, the capping layer 160 may be etched to obtain a first contact hole 161 penetrating through to the sacrificial structure 154, and the bottom of the first contact hole 161 is the top of the sacrificial structure 154. The etching of the first contact hole 161 may use the sacrificial structure 154 as an etch stop layer, or may over-etch part of the sacrificial structure 154. The first contact hole 161 may be formed by anisotropic dry etching.

[0086] In the first structure, the semiconductor device after forming the first contact hole 161 may be referred to Figure 17 as shown Figure 17 which is a cross-sectional view of the semiconductor structure along the AA direction. In the second structure, the semiconductor device after forming the first contact hole 161 may be referred to Figure 30 as shown Figure 30 which is a cross-sectional view of the semiconductor structure along the AA direction.

[0087] In the embodiment of the present application, after the first contact hole 161 is formed, the sacrificial structure 154 at the bottom of the first contact hole 161 can be removed to form a gap 162 under the first contact hole 161, and the gap 162 exposes the gate structure 150 under the sacrificial structure 154. When the sacrificial structure 154 is a ring structure in the horizontal direction, all of the sacrificial structure 154 can be removed, and the formed gap 162 is a ring structure in the horizontal direction. At this time, the lateral dimension of the gap 162 is larger than the lateral dimension of the first contact hole 161. When the sacrificial structure 154 is a ring structure in the horizontal direction, only the sacrificial structure 154 under the first contact hole 161 can be removed, and the sacrificial structure 154 at other positions can be retained, and the formed gap 162 is a hollow column. At this time, the lateral dimension of the gap 162 can be larger than the lateral dimension of the first contact hole 161 or smaller than the lateral dimension of the first contact hole 161. The sacrificial structure 154 can be removed by wet etching, and the wet etching has less damage to the gate structure 150 under the sacrificial structure 154, which is beneficial to improving the device quality. Compared with forming the first contact hole 161 penetrating through to the gate structure 150 by dry etching, this method has less damage to the gate structure 150.

[0088] In the first structure, the semiconductor device after removing the sacrificial structure 154 to form the gap 162 can be referred to Figure 18 as shown Figure 18 in the cross-sectional view of the semiconductor structure along the AA direction, where the lateral dimension of the gap 162 is larger than the lateral dimension of the first contact hole 161. In the second structure, the semiconductor device after removing the sacrificial structure 154 to form the gap 162 can be referred to Figure 31 as shown Figure 31 in the cross-sectional view of the semiconductor structure along the AA direction, where the lateral dimension of the gap 162 is larger than the lateral dimension of the first contact hole 161.

[0089] S106, form a first contact structure 163 in the first contact hole 161 and the gap 162, refer to Figure 19 , Figure 20 , Figure 32 and Figure 33 as shown.

[0090] After removing the sacrificial structure 154 under the first contact hole 161 to form the gap 162 under the first contact hole 161, a first contact structure 163 can be formed in the first contact hole 161 and the gap 162. Since the gap 162 exposes the gate structure 150, the first contact structure 163 formed in the first contact hole 161 and the gap 162 is electrically connected to the gate structure 150, and the gate structure 150 can be led out to the top of the covering layer 160. The first contact structure 163 serves as a gate contact structure. The first contact structure 163 can be obtained by depositing and etching a conductor material.

[0091] Among them, the first contact structure 163 in the gap 162 can be used as the fourth part, and the first contact structure 163 in the first contact hole 161 can be used as the fifth part. That is, the first contact structure 163 can include a fourth part and a fifth part in the longitudinal direction. The fourth part is located below and contacts the gate structure 150, while the fifth part is located above the fourth part and contacts the fourth part. When the gap 162 is a ring-shaped structure in the horizontal direction, the fourth part is a ring-shaped structure in the horizontal direction, and at this time, the lateral dimension of the fourth part is larger than that of the fifth part; when the gap 162 is a hollow column, the lateral dimension of the fourth part can be larger than that of the fifth part or smaller than that of the fifth part.

[0092] In the first structure, the semiconductor device after forming the first contact structure 163 can be referred to Figure 19 as shown in Figure 19 which is a cross-sectional view of the semiconductor structure along the AA direction, where the lateral dimension of the lower part of the first contact structure 163 is larger than that of the upper part of the first contact structure 163. In the second structure, the semiconductor device after forming the first contact structure 163 can be referred to Figure 32 as shown in Figure 32 which is a cross-sectional view of the semiconductor structure along the AA direction, where the lateral dimension of the lower part of the first contact structure 163 is larger than that of the upper part of the first contact structure 163.

[0093] In the embodiments of the present application, the covering layer 160 can also be etched to obtain a second contact hole penetrating to the second source / drain layer 130, and a second contact structure 164 is formed in the second contact hole. When the second source / drain layer 130 is used as the drain, the second contact structure 164 serves as the drain contact structure. The second contact structure 164 can be obtained by depositing and etching a conductor material. The first contact structure 163 can be formed before the second contact structure 164 or after the second contact structure 164.

[0094] In the first structure, the semiconductor device after forming the second contact structure 164 can be referred to Figure 20 as shown in Figure 20 which is a cross-sectional view of the semiconductor structure along the AA direction. In the second structure, the semiconductor device after forming the second contact structure 164 can be referred to Figure 33 as shown in Figure 33 which is a cross-sectional view of the semiconductor structure along the AA direction.

[0095] An embodiment of the present application provides a method for manufacturing a semiconductor device. A substrate is provided, on which a first source / drain layer, a channel layer, and a second source / drain layer are sequentially stacked. A gate dielectric layer and a gate structure that surround the channel layer in the horizontal direction are provided around the channel layer. The gate structure has a first portion extending in the horizontal direction and a second portion extending upward around the first portion. The second portion is outside the second source / drain layer. A spacer layer is formed on the outer sidewall of the gate structure. The gate structure is etched to reduce the thickness of the gate structure, a sacrificial structure covering the gate structure is formed, and a capping layer covering the second source / drain layer, the sacrificial structure, and the spacer layer is formed. In this way, the sacrificial structure is located outside the second source / drain layer and inside the spacer layer. Then, the capping layer is etched to obtain a first contact hole penetrating the sacrificial structure, the sacrificial structure at the bottom of the first contact hole is removed to form a gap below the first contact hole, and a first contact structure is formed in the first contact hole and the gap. During the formation of the first contact structure, the spacer layer can limit the position of the first contact structure, making the bottom of the first contact structure self-aligned with the gate structure, improving the contact quality between the first contact structure and the gate structure, and improving the reliability of the device.

[0096] Based on the method for manufacturing a semiconductor device provided by the embodiment of the present application, the embodiment of the present application further provides a semiconductor structure. Refer to Figure 20 and Figure 33 As shown, which is a schematic structural diagram of the semiconductor device provided by the embodiment of the present application. The semiconductor structure includes:

[0097] The first source / drain layer, the channel layer, and the second source / drain layer sequentially stacked on the substrate;

[0098] The gate dielectric layer and the gate structure that surround the channel layer in the transverse direction; the gate structure extends in the horizontal direction;

[0099] The first contact structure connected to the gate structure; the first contact structure longitudinally includes a fourth portion connected to the gate structure and a fifth portion connected to the fourth portion, and the lateral dimensions of the fourth portion and the fifth portion are different;

[0100] The spacer layer located on the outer sidewall of the gate structure and the outer sidewall of the fourth portion.

[0101] Optionally, a first dielectric layer surrounding the first source / drain layer is formed on the sidewall of the first source / drain layer, and a second dielectric layer surrounding the second source / drain layer is formed on the sidewall of the second source / drain layer; the sidewall of the channel layer has a first recessed area relative to the first dielectric layer and the second dielectric layer; the gate dielectric layer and the gate structure are formed in the first recessed area, and the fourth portion is located on the sidewall of the second dielectric layer.

[0102] Optionally, the sidewalls of the channel layer have a second recessed area relative to the first source / drain layer and the second source / drain layer. A gate dielectric layer and a gate structure are formed in the second recessed area. The fourth portion is located on the sidewall of the second dielectric layer, and the bottom surface of the gate structure is higher than the top surface of the first source / drain layer. An isolation layer is formed between the second source / drain layer and the fourth portion.

[0103] An embodiment of the present application provides a semiconductor device, including a first source / drain layer, a channel layer, and a second source / drain layer that are sequentially stacked on a substrate. The periphery of the channel layer has a gate dielectric layer and a gate structure that surround the channel layer in the horizontal direction. The gate structure has a first portion extending in the horizontal direction and a second portion extending upward around the first portion. The second portion is outside the second source / drain layer and laterally surrounds the channel layer, the gate dielectric layer, and the gate structure; the gate structure extends in the horizontal direction; a first contact structure connected to the gate structure; the first contact structure includes a fourth portion connected to the gate structure and a fifth portion connected to the fourth portion in the longitudinal direction, and the lateral dimensions of the fourth portion and the fifth portion are different; a spacer layer located on the outer sidewall of the gate structure and the outer sidewall of the fourth portion. During the formation of the first contact structure, the spacer layer can limit the position of the first contact structure, making the bottom of the first contact structure and the gate structure self-aligned, improving the contact quality between the first contact structure and the gate structure, improving the reliability of the device, and reducing the precision required for the manufacturing process.

[0104] When introducing the elements of the various embodiments of the present application, the articles "a", "an", "this", and "the" are all intended to mean that there is one or more elements. The words "comprising", "including", and "having" are all inclusive and mean that there may be other elements in addition to the listed elements.

[0105] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0106] The above is only the preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the protection of the technical solution of the present application.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, Comprising: Providing a substrate; A first source / drain layer, a channel layer, and a second source / drain layer are sequentially stacked on the substrate; A gate dielectric layer and a gate structure that surround the channel layer in the horizontal direction are provided around the channel layer. The gate structure has a first portion extending in the horizontal direction and a second portion extending upward around the first portion. The second portion is outside the second source / drain layer; Forming a spacer layer on the outer sidewall of the gate structure; Etching the gate structure to reduce the longitudinal dimension of the gate structure; Forming a sacrificial structure covering the gate structure, and a covering layer covering the second source / drain layer, the sacrificial structure, and the spacer layer; Etching the covering layer to obtain a first contact hole penetrating to the sacrificial structure, removing the sacrificial structure at the bottom of the first contact hole, and forming a gap below the first contact hole; Forming a first contact structure in the first contact hole and the gap; 2. The method according to claim 1, characterized in that, A first dielectric layer surrounding the first source / drain layer is formed on the sidewall of the first source / drain layer, and a second dielectric layer surrounding the second source / drain layer is formed on the sidewall of the second source / drain layer; a first recessed area exists on the sidewall of the channel layer relative to the first dielectric layer and the second dielectric layer; a gate dielectric layer and a gate structure are formed in the first recessed area. Before forming the spacer layer on the outer sidewall of the gate structure, the second portion extends upward to the sidewall of the second dielectric layer; 3. The method according to claim 2, wherein The gate structure further includes a third portion extending downward, and the third portion extends to the sidewall of the first dielectric layer; 4. The method according to claim 2, wherein The first dielectric layer and the second dielectric layer are formed through the following steps: After etching the sequentially stacked first source / drain layer, channel layer, and second source / drain layer to achieve patterning, etching the channel layer from the sidewall of the channel layer so that a third recessed area exists on the sidewall of the channel layer relative to the first source / drain layer and the second source / drain layer; Forming a dummy gate structure in the first recessed area; Etching the first source / drain layer and the second source / drain layer from the sidewall of the first source / drain layer and the sidewall of the second source / drain layer so that a fourth recessed area exists on the sidewall of the first source / drain layer relative to the dummy gate structure, and a fifth recessed area exists on the sidewall of the second source / drain layer relative to the dummy gate structure; Forming a first dielectric layer in the fourth recessed area and a second dielectric layer in the fifth recessed area; 5. The method according to claim 1, characterized in that, A second recessed area exists on the sidewall of the channel layer relative to the first source / drain layer and the second source / drain layer. A gate dielectric layer and a gate structure are formed in the second recessed area. Before forming the spacer layer on the outer sidewall of the gate structure, the gate structure extends to the sidewall of the second source / drain layer, and the bottom surface of the gate structure is higher than the top surface of the first source / drain layer; Before forming the sacrificial structure covering the gate structure, the method further includes: forming an isolation layer on the sidewall of the second source / drain layer; 6. The method according to any one of claims 1-5, characterized in that, The method further includes: Etching the covering layer to obtain a second contact hole penetrating to the second source / drain layer; Forming a second contact structure in the second contact hole; 7. The method according to any one of claims 1-5, characterized in that, The sacrificial structure is removed by wet etching; 8. A semiconductor device, characterized in that, Comprising: A first source / drain layer, a channel layer, and a second source / drain layer stacked in sequence on a substrate; A gate dielectric layer and a gate structure that laterally surround the channel layer; the gate structure extends in the horizontal direction; A first contact structure connected to the gate structure; the first contact structure longitudinally includes a fourth portion connected to the gate structure and a fifth portion connected to the fourth portion, and the lateral dimensions of the fourth portion and the fifth portion are different; A spacer layer located on the outer sidewall of the gate structure and the outer sidewall of the fourth portion.

9. The semiconductor device according to claim 8, wherein, A first dielectric layer surrounding the first source / drain layer is formed on the sidewall of the first source / drain layer, and a second dielectric layer surrounding the second source / drain layer is formed on the sidewall of the second source / drain layer; the sidewall of the channel layer has a first recessed region relative to the first dielectric layer and the second dielectric layer; a gate dielectric layer and a gate structure are formed in the first recessed region, and the fourth portion is located on the sidewall of the second dielectric layer.

10. The semiconductor device according to claim 8, wherein, A second dielectric layer surrounding the second source / drain layer is formed on the sidewall of the second source / drain layer; the sidewall of the channel layer has a second recessed region relative to the first source / drain layer and the second source / drain layer, a gate dielectric layer and a gate structure are formed in the second recessed region, the fourth portion is located on the sidewall of the second dielectric layer, and the bottom surface of the gate structure is higher than the top surface of the first source / drain layer; an isolation layer is formed between the second source / drain layer and the fourth portion.

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