Oscillator and chip

Abstract

The embodiment of the present application provides an oscillator and a chip, and belongs to the technical field of electronic circuits. The oscillator comprises a current generating circuit, a comparator circuit and an oscillation circuit. The current generating circuit is used for generating a first reference current and a second reference current, and providing a reference voltage signal according to the first reference current. The oscillation circuit comprises a capacitor. The comparator circuit is connected between the capacitor and the current generating circuit, and outputs a high or low level according to the size relationship between the reference voltage signal and the voltage signal of the capacitor, so as to control the capacitor to discharge or be charged by the second reference current flowing through the comparator circuit. The oscillator and the chip can reduce the current branch, and achieve the purpose of reducing power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to an oscillator and chip. Background Technology

[0002] In power management chips and mixed-signal integrated circuit systems, oscillators are essential circuits. Oscillator circuits provide clock signals for very large-scale integrated circuit systems and also serve as the core unit for synchronous driving of power modules.

[0003] Relaxation oscillators have a relatively simple circuit architecture, can be highly integrated on a chip system, and are widely used in power management signals and mixed-signal circuits. For example... Figure 1 The diagram shows the basic structure of a traditional relaxation oscillator circuit. The circuit principle is briefly described as follows: A constant current source CM1 flows through the load resistor R to generate a reference voltage signal VREF. A constant current source CM2 charges capacitor C, forming the VRAMP signal. Signals VRAMP and VREF are input to the positive and negative terminals of comparator CMP, respectively. After level discrimination by the comparator, a high / low level control signal VCLK is output. This signal is then processed by a buffer stage circuit BUF to control the NMOS transistor MN to turn on or off, causing the capacitor voltage VRAMP to rise or fall rapidly.

[0004] The power consumption of a circuit is calculated by multiplying the voltage by the current in that branch. Figure 1 It can be seen that the current branches are CM1, CM2, the comparator power supply current, and the buffer stage BUF branch current. With so many current branches, the system power consumption is high. Summary of the Invention

[0005] The purpose of this invention is to provide an oscillator and chip that can reduce current branches and thus reduce power consumption.

[0006] To achieve the above objectives, embodiments of the present invention provide an oscillator comprising: a current generating circuit, a comparator circuit, and an oscillation circuit. The current generating circuit generates a first reference current and a second reference current, and provides a reference voltage signal based on the first reference current. The oscillation circuit includes a capacitor. The comparator circuit is connected between the capacitor and the current generating circuit, and outputs a high or low level based on the magnitude relationship between the reference voltage signal and the voltage signal of the capacitor, to control the capacitor to discharge or to charge the capacitor by the second reference current flowing through the comparator circuit.

[0007] Preferably, when the comparator circuit outputs a high level, the capacitor discharges; when the comparator circuit outputs a low level, the capacitor is charged by the second reference current flowing through the comparator circuit.

[0008] Preferably, the current generating circuit includes: a first NMOS transistor, an amplifier, and a current mirror connected to a power supply terminal. The current mirror includes a first branch and a second branch. The first reference current flows through the first branch, and the second reference current flows through the second branch. The drain of the first NMOS transistor is connected to the first branch, the gate is connected to the amplifier, and the source is connected to the negative input terminal of the amplifier. The amplifier and the first NMOS transistor form a negative feedback loop, so that the voltage at the negative input terminal of the amplifier is equal to the reference voltage at the positive input terminal of the amplifier.

[0009] Preferably, the current generating circuit further includes: a first resistor, one end of which is connected to the source of the first NMOS transistor, the other end of which is grounded, and the voltage at the negative input terminal of the amplifier is the product of the first reference current and the first resistor.

[0010] Preferably, the oscillator further includes: a level shifting circuit connected to the comparator circuit and the current generating circuit, used to level shift and adjust the reference voltage signal and the voltage signal of the capacitor, and output a first voltage signal corresponding to the reference voltage signal and a second voltage signal corresponding to the voltage signal of the capacitor to the comparator circuit.

[0011] Preferably, the level shifting circuit includes: a second NMOS transistor, a third NMOS transistor, a first constant current source, and a second constant current source, wherein the gate of the second NMOS transistor receives the reference voltage signal, the source is connected to the first constant current source and outputs the first voltage signal, and the drain is connected to the power supply terminal; the gate of the third NMOS transistor receives the voltage signal of the capacitor, the source is connected to the second constant current source and outputs the second voltage signal, and the drain is connected to the power supply terminal.

[0012] Preferably, the comparator circuit includes a plurality of MOSFETs to receive the first voltage signal and the second voltage signal, and outputs a low level when the first voltage signal is greater than the second voltage signal, and outputs a high level when the first voltage signal is less than the second voltage signal.

[0013] Preferably, the plurality of MOS transistors includes: a first PMOS transistor, a second PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein the sources of the first PMOS transistor and the second PMOS transistor are connected to the current generating circuit to receive the second reference current; the gate of the first PMOS transistor is connected to the source of the second NMOS transistor to receive the first voltage signal; the gate of the second PMOS transistor is connected to the source of the third NMOS transistor to receive the second voltage signal; the drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor; the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor and is also connected to the drain of the fifth NMOS transistor; and the sources of the fourth NMOS transistor and the fifth NMOS transistor are connected to the capacitor.

[0014] Preferably, the oscillation circuit further includes a buffer circuit and a sixth NMOS transistor, wherein the buffer circuit is also connected to the gate of the sixth NMOS transistor; the source and drain of the sixth NMOS transistor are connected to the two ends of the capacitor, and are used to turn off when the comparator circuit outputs a high level to discharge the capacitor; and to turn on when the comparator circuit outputs a low level to charge the capacitor.

[0015] This invention also provides a chip that includes the oscillator described above.

[0016] By employing the above technical solutions, the oscillator and chip provided by this invention reduce the power supply current of the comparator branch using the current reuse principle, thereby achieving low power consumption for the entire system.

[0017] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 This is a schematic diagram of an existing oscillator circuit;

[0020] Figure 2 This is a schematic diagram of the structure of an oscillator provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a current generating circuit provided in an embodiment of the present invention;

[0022] Figure 4This is a schematic diagram of a level shifting circuit provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of a comparator circuit package provided in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of an oscillator provided in another embodiment of the present invention;

[0025] Figure 7 This is a timing waveform diagram provided in an embodiment of the present invention.

[0026] Explanation of reference numerals in the attached figures

[0027] 101 Current Generating Circuit 102 Comparator Circuit

[0028] 103 Oscillating Circuit Detailed Implementation

[0029] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0030] Figure 2 This is a schematic diagram of the structure of an oscillator provided in an embodiment of the present invention. Figure 2 As shown, the oscillator includes a current generating circuit 101, a comparator circuit 102, and an oscillation circuit 103. The current generating circuit 101 generates a first reference current and a second reference current IC, and provides a reference voltage signal VREF based on the first reference current. The oscillation circuit 103 includes a capacitor C. The comparator circuit 102 is connected between the capacitor C and the current generating circuit 101, and outputs a high or low level according to the relationship between the reference voltage signal VREF and the voltage signal of the capacitor C, so as to control the capacitor C to discharge or be charged by the second reference current IC flowing through the comparator circuit 102.

[0031] For example, the current generating circuit 101 can generate a first reference current (not shown in the figure), which can be processed to generate a reference voltage signal VREF. The current generating circuit 101 can also generate a second reference current IC, which can first pass through the comparator circuit 102 and then through the capacitor C in the oscillation circuit 103. The voltage across capacitor C forms a voltage signal VRAMP. VREF and VRAMP are input to the comparator circuit 102 for comparison, thereby causing the comparator circuit 102 to output a high or low level to the oscillation circuit 103. The oscillation circuit 103 controls the charging and discharging of capacitor C according to the high or low level, continuously changing the value of VRAMP. For example, preferably, when the comparator circuit 102 outputs a high level, capacitor C discharges to gradually decrease VRAMP until the comparator circuit 102 outputs a low level. When the comparator circuit 102 outputs a low level, the second reference current IC flowing through the comparator circuit 102 charges capacitor C to gradually increase VRAMP until the comparator circuit 102 outputs a high level. This cycle is repeated to complete the oscillation. In this embodiment of the invention, the capacitors C in the current generating circuit 101, comparator circuit 102 and oscillation circuit 103 are stacked in the same branch. The capacitors C in the comparator circuit 102 and oscillation circuit 103 reuse the second reference current IC, so as not to generate new branch current and reduce additional power consumption.

[0032] Figure 3 This is a schematic diagram of a current generating circuit 101 provided in an embodiment of the present invention. Figure 3 As shown, the current generating circuit 101 includes: a first NMOS transistor, an amplifier AMP, and a current mirror connected to the power supply terminal ADD. The current mirror includes a first branch and a second branch. The first reference current IB flows through the first branch, and the second reference current IC flows through the second branch. The drain of the first NMOS transistor is connected to the first branch, the gate is connected to the amplifier AMP, and the source is connected to the negative input terminal of the amplifier AMP. The amplifier AMP and the first NMOS transistor form a loop negative feedback, so that the voltage at the negative input terminal of the amplifier AMP is equal to the reference voltage VREF at the positive input terminal of the amplifier AMP.

[0033] The current mirror consists of four PMOS transistors, M3-M6, such as... Figure 3 As shown. It is understandable that... Figure 3The current mirror structure is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. In this embodiment, the second reference current IC flows through the second branch composed of M4 and M6. The first reference current IB flows through the first branch composed of M3 and M5. Connected to the first branch is the first NMOS transistor M2, which, together with the amplifier AMP, forms a loop negative feedback structure, such that the voltage at the negative input terminal of the amplifier AMP is equal to the reference voltage VREF at the positive input terminal of the amplifier.

[0034] More specifically, the present invention provides a structure that can achieve the above requirements, namely, the current generating circuit 101 further includes: a first resistor RT, one end of the first resistor RT being connected to the source of the first NMOS transistor, the other end of the first resistor RT being grounded, and the voltage at the negative input terminal of the amplifier AMP being the product of the first reference current IB and the first resistor RT, as shown in the following formula:

[0035]

[0036] Furthermore, given the known relationship between the second reference current IC and the first reference current IB, the relationship between the second reference current IC and the first resistor RT and the reference voltage VREF can also be determined. For example, assuming that the second reference current IC is N times the first reference current IB, the relationship is as follows:

[0037] IC = N × IB

[0038]

[0039] Thus, in fact, with the first resistor RT fixed, the magnitude of the reference voltage VREF can be determined by the generated first reference current IB and second reference current IC.

[0040] Figure 4 This is a schematic diagram of a level shifting circuit provided in an embodiment of the present invention. Figure 4 As shown, the oscillator also includes a level shifting circuit, which is connected to the comparator circuit 102 and the current generation circuit 101. The level shifting circuit is used to adjust the reference voltage signal VREF and the voltage signal VRAMP of the capacitor C, and outputs a first voltage signal VIN corresponding to the reference voltage signal and a second voltage signal VIP corresponding to the voltage signal of the capacitor C to the comparator circuit 102.

[0041] For example, since the comparator circuit 102, current generation circuit 101, and capacitor C are stacked in this invention and share a single current, the voltage at the end connected to capacitor C should be equal to the voltage VRAMP of capacitor C (the structure of comparator circuit 102 is described in detail below). Unlike the usual method where VSS is ground, VRAMP is used as ground, which is equivalent to raising the voltage level. In order for the MOSFETs in comparator circuit 102 to operate normally in the saturation region, a PMOS pair that can conduct without a very high voltage is required. Therefore, this invention preferably includes a level shifting circuit to shift the reference voltage signal VREF and the voltage signal VRAMP of capacitor C downwards, outputting a first voltage signal VIN and a second voltage signal VIP.

[0042] Specifically, the level shifting circuit includes: a second NMOS transistor ML1, a third NMOS transistor ML2, a first constant current source, and a second constant current source. The gate of the second NMOS transistor ML1 receives the reference voltage signal VREF, its source is connected to the first constant current source and outputs the first voltage signal VIN, and its drain is connected to the power supply terminal. The gate of the third NMOS transistor ML2 receives the voltage signal VRAMP from the capacitor C, its source is connected to the second constant current source and outputs the second voltage signal VIP, and its drain is connected to the power supply terminal. It is understood that the level shifting circuit of this invention is only a preferred example and is not intended to limit the invention. This level shifting circuit has a simple structure and generates extremely low losses.

[0043] Figure 5 This is a schematic diagram of a comparator circuit 102 package provided in an embodiment of the present invention. Figure 5 As shown, the comparator circuit 102 includes a plurality of MOSFETs to receive the first voltage signal VIN and the second voltage signal VIP, and outputs a low level when the first voltage signal VIN is greater than the second voltage signal VIP, and outputs a high level when the first voltage signal VIN is less than the second voltage signal VIP.

[0044] For example, as described above, the comparator circuit 102 uses a structure with multiple MOSFETs. The uppermost terminal is connected to the drain of M4 in the current generation circuit 101, labeled V1, so the tail current of the comparator circuit 102 is IC. The lowermost terminal needs to be connected to capacitor C, and the voltage is the voltage signal VRAMP of capacitor C.

[0045] Preferably, the plurality of MOS transistors includes: a first PMOS transistor MC6, a second PMOS transistor MC5, a fourth NMOS transistor MC7, and a fifth NMOS transistor MC8, wherein the sources of the first PMOS transistor MC6 and the second PMOS transistor MC5 are connected to the current generating circuit 101 to receive the second reference current IC; the gate of the first PMOS transistor MC6 is connected to the source of the second NMOS transistor ML1 to receive the first voltage signal VIN; the gate of the second PMOS transistor MC5 is connected to the source of the third NMOS transistor ML2 to receive the second voltage signal VIP; the drain of the first PMOS transistor MC6 is connected to the drain of the fourth NMOS transistor MC7; the drain of the second PMOS transistor MC5 is connected to the drain of the fifth NMOS transistor; the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor MC8 and to the drain of the fifth NMOS transistor MC8; and the sources of the fourth NMOS transistor MC7 and the fifth NMOS transistor MC8 are connected to the capacitor C.

[0046] The comparator outputs a low level when the first voltage signal VIN is greater than the second voltage signal VIP, and outputs a high level when the first voltage signal VIN is less than the second voltage signal VIP.

[0047] Figure 6 This is a schematic diagram of the structure of an oscillator provided in another embodiment of the present invention. Figure 6 As shown, this embodiment provides an overall schematic diagram of the oscillator (the level shifting circuit is not shown for clarity; the level shifting circuit should be connected according to the connection relationship described above). Figure 6 (in the middle). The oscillation circuit 103 further includes a buffer circuit BUF and a sixth NMOS transistor M1. The buffer circuit BUF is also connected to the gate of the sixth NMOS transistor M1. The source and drain of the sixth NMOS transistor M1 are connected to the two ends of the capacitor C, and are used to turn off when the comparator circuit 102 outputs a high level, so as to discharge the capacitor C; and to turn on when the comparator circuit 102 outputs a low level, so as to charge the capacitor C.

[0048] For example, the second reference current IC gradually fills the capacitor C, causing VRAMP to gradually increase and exceed VREF. At this time, the comparator circuit 102 outputs a high level. After being buffered by the buffer circuit BUF, the sixth NMOS transistor M1 is turned off, and the capacitor C is short-circuited and discharged, gradually decreasing VRAMP. When VRAMP is less than VREF, the comparator circuit 102 outputs a low level. After being buffered by the buffer circuit BUF, the sixth NMOS transistor M1 is turned on, and the capacitor C is charged by the second reference current IC flowing through the comparator circuit 102. VRAMP gradually increases again until it exceeds VREF, causing the comparator circuit 102 to output a high level. This cycle repeats to complete the oscillation.

[0049] Figure 7 This is a timing waveform diagram provided in an embodiment of the present invention. For example... Figure 7 As shown, this embodiment provides the oscillator operation as described above. Assuming the charging time of capacitor C is TRAMP, the comparator delay is TCOMP, the buffer circuit BUF delay is TBUF, and the reset time of capacitor C is TRST, then the oscillator period expression is as follows:

[0050] Where W / L is the width-to-length ratio.

[0051] Ttot = TRAMP + TCOMP + TBUF + TRST, where Ttot is the clock period of the oscillator.

[0052] like Figure 7 As shown, VIN and VIP are the output results of VREF and VRAMP shifted down by one VTH by the level shifting circuit. After VIN and VIP are compared by comparator circuit 102, the output result is buffered by the buffer circuit BUF to generate the VCLK signal to control the on / off state of M1.

[0053] This invention also provides a chip that includes the oscillator described above. Its embodiments are similar to those of the oscillator described above, and will not be repeated here.

[0054] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0055] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An oscillator, characterized in that, The oscillator includes: The circuit consists of a current generating circuit, a comparator circuit, and an oscillator circuit. The current generating circuit is used to generate a first reference current and a second reference current, and to provide a reference voltage signal based on the first reference current; The oscillation circuit includes a capacitor; The comparator circuit is connected between the capacitor and the current generating circuit, and outputs a high or low level according to the relationship between the reference voltage signal and the voltage signal of the capacitor, so as to control the capacitor to discharge or charge the capacitor by the second reference current flowing through the comparator circuit. In this circuit, the capacitors in the current generation circuit, comparator circuit, and oscillation circuit are stacked in the same branch, and the capacitors in the comparator circuit and oscillation circuit reuse the second reference current.

2. The oscillator according to claim 1, characterized in that, When the comparator circuit outputs a high level, the capacitor discharges; when the comparator circuit outputs a low level, the capacitor is charged by the second reference current flowing through the comparator circuit.

3. The oscillator according to claim 1, characterized in that, The current generating circuit includes: The first NMOS transistor, the amplifier, and the current mirror connected to the power supply are included. The current mirror includes a first branch and a second branch. The first reference current flows through the first branch, and the second reference current flows through the second branch. The drain of the first NMOS transistor is connected to the first branch, the gate is connected to the amplifier, and the source is connected to the negative input terminal of the amplifier. The amplifier and the first NMOS transistor form a loop negative feedback, so that the voltage at the negative input terminal of the amplifier is equal to the reference voltage at the positive input terminal of the amplifier.

4. The oscillator according to claim 3, characterized in that, The current generating circuit further includes: The first resistor has one end connected to the source of the first NMOS transistor and the other end grounded. The voltage at the negative input terminal of the amplifier is the product of the first reference current and the first resistor.

5. The oscillator according to claim 1, characterized in that, The oscillator also includes: A level shifting circuit, connected to the comparator circuit and the current generating circuit, is used to level shift and adjust the reference voltage signal and the voltage signal of the capacitor, and output a first voltage signal corresponding to the reference voltage signal and a second voltage signal corresponding to the voltage signal of the capacitor to the comparator circuit.

6. The oscillator according to claim 5, characterized in that, The level shifting circuit includes: The system comprises a second NMOS transistor, a third NMOS transistor, a first constant current source, and a second constant current source, wherein the gate of the second NMOS transistor receives the reference voltage signal, the source is connected to the first constant current source and outputs the first voltage signal, and the drain is connected to the power supply terminal; the gate of the third NMOS transistor receives the voltage signal from the capacitor, the source is connected to the second constant current source and outputs the second voltage signal, and the drain is connected to the power supply terminal.

7. The oscillator according to claim 5, characterized in that, The comparator circuit includes multiple MOSFETs to receive the first voltage signal and the second voltage signal, and outputs a low level when the first voltage signal is greater than the second voltage signal, and outputs a high level when the first voltage signal is less than the second voltage signal.

8. The oscillator according to claim 7, characterized in that, The plurality of MOSFETs include: The first PMOS transistor, the second PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor, among which, The sources of the first PMOS transistor and the second PMOS transistor are connected to the current generating circuit to receive the second reference current. The gate of the first PMOS transistor is connected to the source of the second NMOS transistor to receive the first voltage signal. The gate of the second PMOS transistor is connected to the source of the third NMOS transistor to receive the second voltage signal. The drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor and to the drain of the fifth NMOS transistor, and the sources of the fourth and fifth NMOS transistors are connected to the capacitor.

9. The oscillator according to claim 7, characterized in that, The oscillation circuit also includes: The buffer circuit and the sixth NMOS transistor, among which, The buffer circuit is also connected to the gate of the sixth NMOS transistor; The source and drain of the sixth NMOS transistor are connected to the two ends of the capacitor, and are used to turn off when the comparator circuit outputs a high level to discharge the capacitor; and to turn on when the comparator circuit outputs a low level to charge the capacitor.

10. A chip, characterized in that, The chip includes the oscillator as described in any one of claims 1-9.

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