A single clock controlled high-speed comparator circuit

Abstract

The present invention discloses a single-clock controlled high-speed comparator circuit, which can meet the high-speed application environment requirements of the comparator while reducing power consumption and input noise. The comparator circuit includes a dynamic amplification circuit module, a comparison decision circuit module, and an output register module. The input end of the dynamic amplification circuit module is connected to the clock signal CLK, and the output end of the dynamic amplification circuit module is connected to the comparison decision circuit module and the output register module in sequence. The dynamic amplification circuit module includes several control units, each composed of several MOS transistors. The input voltage signal is amplified by charging and discharging the control units. The comparison decision circuit module includes a cross-coupled inverter pair for providing a positive feedback structure and further amplifying and isolating the signal output by the dynamic amplification circuit. The output register module includes a latch for temporarily storing the output signal.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converters and comparators, and in particular to a single-clock controlled high-speed comparator circuit. Background Art

[0002] A comparator is a core module in high-speed, high-precision analog-to-digital converters (ADCs). It amplifies the difference between two analog voltages to a "1" or "0" in the digital voltage domain to obtain the input voltage. The comparator is directly involved in the ADC's quantization process, and its performance is directly related to the ADC's conversion results.

[0003] One way to implement a comparator is to achieve a high gain through cascading open-loop amplifiers, thereby amplifying the input signal into the digital domain. However, this cascade structure requires the same gain, which is achieved primarily by increasing the bandwidth of the entire amplifier. Increasing the amplifier bandwidth increases the speed of the entire comparator, but it also increases the power consumption of the entire comparator. Furthermore, the output swing of the back-end amplifier stage is large, requiring sufficient time to accommodate large output changes. This increases the current of the entire high-speed comparator, making it impossible to meet the design requirements of a high-speed, low-power ADC.

[0004] Another way to implement a comparator is to use positive feedback to amplify input information in a short period of time. The positive feedback is provided by two cross-coupled amplifiers and requires two non-overlapping clocks for amplification and reset control, that is, discharge and charging control. During the discharge process, the existing discharge path only has the input path, which limits the operating speed of the entire comparator. During the comparison process and reset, the change in the output voltage is coupled to the input through the parasitic capacitance of the transistor, thereby interfering with the input signal, introducing noise, and causing comparison errors. Summary of the Invention

[0005] In order to solve the problem that traditional comparators require large currents to meet the application environment requirements of high-speed analog-to-digital converter circuits, resulting in high power consumption, and the problem that the output of the high-speed comparator is quickly coupled to the input end through parasitic capacitance, which easily interferes with the input signal, introduces noise, and causes comparison errors, the present invention provides a single-clock controlled high-speed comparator circuit, which can meet the high-speed application environment requirements of the comparator while reducing power consumption and input noise.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A single-clock controlled high-speed comparator circuit includes a dynamic amplification circuit module, a comparison and decision circuit module, and an output register module. The input end of the dynamic amplification circuit module is connected to a clock signal CLK, and the output end of the dynamic amplification circuit module is connected to the comparison and decision circuit module and the output register module in sequence.

[0008] The dynamic amplification circuit module includes several control units, each of which is composed of several MOS tubes. The input voltage signal is amplified by charging and discharging the control units.

[0009] The comparison and decision circuit module includes a cross-coupled inverter pair for providing a positive feedback structure and further amplifying and isolating the signal output by the dynamic amplification circuit;

[0010] The output register module includes a latch for temporarily storing the output signal.

[0011] It is further characterized in that

[0012] The control unit in the dynamic amplification circuit module includes a first switch control unit, an input control unit, a charging control unit, and an inverter. The input end of the first switch control unit is connected to the clock signal CLK, and the output end of the switch control unit is connected to the input control unit, the charging control unit, and the inverter in sequence; the first switch control unit is used to control the clock signal CLK, the input control unit is used to control the input of the clock signal CLK, the charging control unit is used to control the charging and discharging of the entire dynamic amplification circuit module, and the inverter is used to implement signal inversion control;

[0013] Furthermore, the comparison and decision circuit module also includes an intermediate transmission stage and a decision acceleration unit. The input end of the intermediate transmission stage is connected to the output signals N3 and N4 in the dynamic amplification circuit. The output end of the intermediate transmission stage is sequentially connected to the cross-coupled inverter pair and the decision acceleration unit. The intermediate transmission stage is used to amplify the output signals N3 and N4 once. The cross-coupled inverter pair is used to amplify and isolate the signal output by the intermediate transmission stage again. The decision acceleration unit includes a tail current source and a pulse distribution control unit. The tail current source is used to provide current to the cross-coupled inverter pair. The pulse distribution control unit is used to distribute the pulse signal.

[0014] Furthermore, the register in the output register module includes: a first signal conditioning unit and a second signal conditioning unit, the input ends of the first signal conditioning unit and the second signal conditioning unit are respectively connected to the output signals N5 and N6, and the output ends are respectively connected to the output signals DN and D, the first signal conditioning unit includes a plurality of first inverters connected in series and a first NAND gate, the second signal conditioning unit includes a plurality of second inverters connected in series and a second NAND gate, the output of the first NAND gate is connected to the input port 1 of the second NAND gate, and the output end of the second NAND gate is connected to the input port 1 of the first NAND gate;

[0015] Furthermore, the high-speed comparator circuit also includes a clock circuit, which includes a delay unit, an inverter and an AND gate. The delay unit, the third inverter and the AND gate are connected in series in sequence. The input port 1 of the third inverter is connected to the first clock signal end of the clock circuit. The output of the AND gate is the second clock signal end of the clock circuit. The first clock signal end outputs a clock signal CLK, and the second clock signal end outputs a clock signal CLK1.

[0016] The above-mentioned structure of the present invention can achieve the following beneficial effects: the high-speed comparator circuit includes a dynamic amplification circuit module and a comparison and decision circuit module. The dynamic amplification circuit module includes a plurality of control units composed of MOS transistors. The comparison and decision circuit module includes a cross-coupled inverter pair. Dynamic amplification of the input voltage signal is achieved through charging and discharging of the control unit. The cross-coupled inverter pair provides a positive feedback structure for amplifying the signal output by the dynamic amplification circuit to a digital domain voltage range. The current of the dynamic amplification circuit module and the comparison and decision circuit module is provided by triggering the corresponding current by short-term clock signals CLK and CLK1, eliminating the need for long-term continuous current supply, thereby reducing power consumption.

[0017] The comparison decision circuit module in the high-speed comparator circuit includes a cross-coupled inverter pair. The cross-coupled inverter pair is composed of two cross-couplers, which has the function of isolating the input and output, cutting off the direct coupling path from the output to the input, thereby reducing the kickback noise at the input and reducing the comparison error of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit principle diagram of the present invention;

[0019] Figure 2 This is a simulation timing diagram of the clock signal of the present invention.

[0020] Figure 3 This is a simulation waveform diagram of the high-speed comparator of the present invention. DETAILED DESCRIPTION

[0021] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0022] Conventional comparator signal amplification methods include two approaches: one uses cascaded open-loop amplifiers to achieve a high gain, thereby amplifying the input signal to the digital domain; the other utilizes positive feedback to amplify the input information in a short period of time. However, in the first approach, the same gain of the cascaded structure is achieved by increasing the bandwidth of the entire amplifier. This increased bandwidth improves the speed and power consumption of the entire comparator, and requires a long period of continuous current supply to meet the large output swing requirements of the back-end amplifier stage. This increased current increases the power consumption of the high-speed comparator. In the other approach, during the comparison process and reset of the high-speed comparator, changes in the output voltage are coupled to the input through the parasitic capacitance of the transistor, thereby interfering with the input signal, introducing noise, and causing comparison errors.

[0023] In order to solve the problems of high power consumption, input susceptibility to noise interference, and large comparison error in the above-mentioned high-speed comparator, a specific embodiment of a single-clock controlled high-speed comparator circuit is provided below. Figure 1 The high-speed comparator includes a dynamic amplification circuit module 1, a comparison and decision circuit module 2, and an output register module 3. The input end of the dynamic amplification circuit module 1 is connected to the clock signal CLK, and the output end of the dynamic amplification circuit module 1 is connected to the comparison and decision circuit module 2 and the output register module 3 in sequence. The dynamic amplification circuit module 1 includes a plurality of control units, each composed of a plurality of MOS transistors, and amplifies the input voltage signal through the charging and discharging of the control units. The comparison and decision circuit module 2 includes a cross-coupled inverter pair for providing a positive feedback structure and further amplifying and isolating the signal output by the dynamic amplification circuit. The output register module 3 includes a latch for temporarily storing the output signal.

[0024] The control unit in the dynamic amplification circuit module 1 includes a first switch control unit, an input control unit, a charging control unit, and an inverter. The first switch control unit includes a tail current MOS tube Mtail, the input control unit includes symmetrically connected MOS tubes MN1 and MN2, the charging control unit includes symmetrically connected MOS tubes MP1 and MP2, the inverter includes a first inverter and a second inverter, the first inverter includes MOS tubes MP3 and MN3, the second inverter includes MOS tubes MP4 and MN4, the base of the tail current MOS tube Mtail is connected to the clock signal CLK, the source of the tail current MOS tube Mtail is connected to the voltage source VSS, the drain of the tail current MOS tube Mtail is connected to the source of the MOS tubes MN1 and MN2 respectively, and the base of the MOS tubes MN1 and MN2 is connected to the clock signal CLK. A group of input signals INP and INN are connected, the drain of the MOS transistor MN1 is respectively connected to the source of the MOS transistor MP1 and the bases of the MOS transistors MP3 and MN3, the drain of the MOS transistor MN2 is respectively connected to the source of the MOS transistor MP2 and the bases of the MOS transistors MP4 and MN4, the bases of the MOS transistors MP1 and MP2 are connected, the drains of the MOS transistors MP1 and MP2 are respectively connected to the sources of the MOS transistors MP3 and MP4 and the voltage source VDD, the sources of the MOS transistors MN3 and MN4 are respectively connected to the voltage source VSS, the drains of the MOS transistors MP4 and MN4 are connected, and then a signal N3 is output, and the output signal N3 is connected to the first input terminal of the comparison and decision module, the drains of the MOS transistors MP3 and MN3 are connected, and then a signal N4 is output, and the output signal N4 is connected to the second input terminal of the comparison and decision module.

[0025] In this dynamic amplifier circuit module 1, the input transistor pair, namely MOS transistors MN1 and MN2, the tail current MOS transistor Mtail, and the charge control transistors, namely MOS transistors MP1 and MP2, are controlled by an input clock signal CLK, which switches MOS transistors MP1 and MP2 on and off, thereby controlling the charging of signal nodes N1 and N2 to a high level. This clock signal also controls the on and off of the tail current MOS transistor Mtail. When the clock signal CLK is low, the comparator enters a reset phase, the charge control transistors MP1 and MP2 are turned on, the tail current MOS transistor Mtail is turned off, and the signal nodes N1 and N2 are pulled high. This also indicates the absence of quiescent current, thus avoiding the quiescent current consumption state that could be caused by two clock controls. When the clock signal CLK is high, the comparator enters the normal working stage, the charging control tubes MP1 and MP2 are turned off, and the tail current MOS tube Mtail is turned on. At this time, the signal nodes N1 and N2 (the signal nodes are nodes of voltage signals) form a branch to the ground and start to discharge to the ground. The discharge speed is determined by the current of the tail current MOS tube Mtail and the parasitic capacitance at the signal nodes N1 and N2. The speed is I tail / C N1(2)The input pair plays the role of current distribution, forming a voltage difference ΔV at the N1 and N2 nodes. N1(2) , which is equivalent to amplifying the difference of the input signals. This voltage difference is further amplified by the inverters (which are push-pull inverting amplifiers) formed by MOS transistors MP3, MP4 and MN3, MN4, and transmitted to the comparison and decision module in the form of output signals N3 and N4.

[0026] The comparison decision circuit module 2 also includes an intermediate transmission stage and a decision acceleration unit. The intermediate transmission stage includes MOS transistors MP7 and MP8. The cross-coupled inverter includes MOS transistors MP5, MN5, MP6, and MN6. The decision acceleration unit includes MOS transistors MN7 to MN12. The sources of the MOS transistors MP7, MP8, MN5, and MN6 are all connected to the voltage source VDD. The bases of the MOS transistors MP7, MN11, and MN7 are connected to the output signal N3. The bases of the MOS transistors MP8, MN11, and MN8 are connected to the output signal N4. The MOS transistor MN7 The sources of the MOS transistors MN11, MN8, and MN12 are all connected to the voltage source VSS. The drain of the MOS transistor MN11 is connected to the source of the MOS transistor MN9. The drains of the MOS transistors MN9, MP7, MP5, and MN5 are connected to the bases of the MOS transistors MP6 and MN6 and output the signal N6. The drains of the MOS transistors MP6, MN6, MP8, and MP10 are connected to the bases of the MOS transistors MP5 and MN5 and output the signal N5. The source of the MOS transistor MN6 is connected to the drain of the MOS transistor MN8. The bases of the MOS transistors MN9 and MN10 are respectively connected to the clock signal CLK1.

[0027] The charge and discharge structure in the dynamic amplifier circuit module 1 amplifies the output voltage difference signal ΔV N1(2) After further amplification by the push-pull inverting amplifier, it is transmitted to the cross-coupled inverter pair by the MOS transistors MP7 and MP8 in the intermediate transmission stage for amplification. At the same time, the push-pull inverting amplifier and the MOS transistors MP7 and MP8 have the function of isolating the input signal from the output signal, thereby achieving the attenuation of the output coupling to the input noise and improving the accuracy of the comparator. The MOS transistors MN7 and MN8 in the decision acceleration unit control the tail current source of the comparison decision module. The MOS transistors MN7 and MN8 are turned on and provide current to the cross-coupled inverter pair through the voltage source VSS. In the normal working stage of the comparator, that is, when CLK1 is at a high level, a corresponding short-time pulse signal is distributed to increase the power supply current of the cross-coupled inverter pair, thereby speeding up the comparison decision circuit. The short-time pulse signal is realized by controlling the clock signal through the delay unit (the delay unit generates a delay on the signal link through the inverter), the inverter and the AND logic gate. The specific timing diagram of the clock circuit is shown in FIG. Figure 2As shown, in the positive feedback amplification stage, the pulse signal can turn on the MOS transistors MN9 and MN10, and then turn on the MOS transistors MN9, MN11 and MN10, MN12, so that the current of the positive feedback structure is increased, and the charging speed of the load capacitor is accelerated. The charging speed is calculated as follows: (I MN7(8) +I MN11(12) ) / C N5(6) When the output signals N5 and N6 are stable, the acceleration pulse control signal ends and returns to a low level, and the MOS tubes MN9, MN10 and MN11, MN12 are turned off, so no unnecessary current consumption is generated.

[0028] The registers in the output register module 3 include: a first signal conditioning unit and a second signal conditioning unit. The inputs of the first and second signal conditioning units are connected to output signals N5 and N6, respectively, and their outputs are connected to output signals DN and D, respectively. The output signals DN and D are connected to the parasitic capacitance and input capacitance of the next-stage circuit. The first signal conditioning unit includes several first inverters 31 connected in series and a first NAND gate. The second signal conditioning unit includes several second inverters 32 connected in series and a second NAND gate. The output of the first NAND gate is connected to input port 1 of the second NAND gate, and the output of the second NAND gate is connected to input port 1 of the first NAND gate. The sizes of the two-stage inverters (i.e., the first inverter 31 and the second inverter 32) are increased in a 1:3 ratio, ensuring strong drive capability while meeting minimum delay time to facilitate subsequent processing of the comparison result of the comparator.

[0029] See Figure 1 The high-speed comparator circuit also includes a clock circuit 4, which includes a delay unit 41, a third inverter 42 and an AND gate. The delay unit, the third inverter and the AND gate are connected in series in sequence. The input terminal 1 of the third inverter is connected to the first clock signal terminal of the clock circuit. The output of the AND gate is the second clock signal terminal of the clock circuit. The first clock signal terminal outputs the clock signal CLK, and the second clock signal terminal outputs the clock signal CLK1. The clock signal of the high-speed comparator is controlled by a single clock, that is, by Figure 2The clock signals CLK and CLK1 generated by the clock circuit shown in the figure are controlled by a single clock, which reduces the introduction of redundant clock signals, compared to the deviation effect of two-phase clock control. This avoids the need to consider the influence of parasitic parameters on phase delay in the transmission path in subsequent designs. A short control pulse signal is generated by the delay unit and digital gate circuit to reduce the charging time of the parasitic capacitance and input capacitance of the next-stage circuit when the comparison and decision circuit module 2 outputs the signal, thereby accelerating the supply of tail current to the comparison and decision circuit module 2, thereby further accelerating the amplification speed of the positive feedback structure. After the short pulse signal ends, the relevant transistors are controlled to turn off, avoiding the increase of excess transient current and the loss of power consumption, thereby reducing power consumption.

[0030] The above high-speed comparator circuit is applied to a high-speed ADC. The input signal INN is a 0.6V voltage, and the input signal INP is a sinusoidal voltage signal with a frequency of 500MHz and an amplitude of 500mV. When CLK is low, it is the reset stage of the dynamic comparator. When CLK is high, it is the normal working stage of the dynamic comparator. If INN is greater than INP at this time, the comparison result, that is, the output signal D outputs a low level. If INN is less than INP, the output signal D outputs a high level. Figure 3 (a). The simulation waveform of the high-speed comparator is as follows Figure 3 As shown, Figure 3 In the figure, the horizontal axis represents time and the vertical axis represents voltage value. Figure 3 (a) represents the digital code output by the comparator, where 1.2V is the high level and 0V is the low level. Figure 3 The two lines A and B in (b) represent the input signals INP and INN respectively. Figure 3 (c) represents the clock control signal required by the above-mentioned high-speed comparator. When operating at a 10 GHz control clock, the high-speed, low-power comparator consumes only 709.44 uW of power (i.e., consumes 591.2 uA of power supply current). When operating at a 2 GHz control clock, the high-speed, low-power comparator consumes only 159.6 uW of power (i.e., consumes 133 uA of power supply current).

[0031] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. A single-clock controlled high-speed comparator circuit, comprising a dynamic amplification circuit module, a comparison decision circuit module, and an output register module, characterized in that: The input end of the dynamic amplifying circuit module is connected to the clock signal CLK, and the output end of the dynamic amplifying circuit module is connected to the comparison decision circuit module and the output register module in sequence; The dynamic amplification circuit module includes several control units, each of which is composed of several MOS tubes. The input voltage signal is amplified by charging and discharging the control units. The comparison and decision circuit module includes a cross-coupled inverter pair for providing a positive feedback structure and further amplifying and isolating the signal output by the dynamic amplification circuit; The output register module includes a latch for temporarily storing the output signal; The comparison and decision circuit module further includes an intermediate transmission stage and a decision acceleration unit. The input end of the intermediate transmission stage is connected to the output signals N3 and N4 in the dynamic amplification circuit. The output end of the intermediate transmission stage is sequentially connected to the cross-coupled inverter pair and the decision acceleration unit. The intermediate transmission stage is used to amplify the output signals N3 and N4 once. The cross-coupled inverter pair is used to amplify and isolate the signal output by the intermediate transmission stage again. The decision acceleration unit includes a tail current source and a pulse distribution control unit. The tail current source is used to provide current to the cross-coupled inverter pair. The pulse distribution control unit is used to distribute pulse signals. The intermediate transmission stage includes MOS transistors MP7 and MP8, the cross-coupled inverter includes MOS transistors MP5, MN5, MP6, and MN6, and the decision acceleration unit includes MOS transistors MN7 to MN12. The sources of the MOS transistors MP7, MP8, MP5, and MP6 are all connected to the voltage source VDD, the bases of the MOS transistors MP7, MN11, and MN7 are connected to the output signal N3, the bases of the MOS transistors MP8, MN11, and MN8 are connected to the output signal N4, and the MOS transistors MN7, MN12 are connected to the output signal N5. The sources of the MOS transistors MN11, MN8, and MN12 are all connected to the voltage source VSS. The drain of the MOS transistor MN11 is connected to the source of the MOS transistor MN9. The drains of the MOS transistors MN9, MP7, MP5, and MN5 are connected to the bases of the MOS transistors MP6 and MN6 and output the signal N6. The drains of the MOS transistors MP6, MN6, MP8, and MP10 are connected to the bases of the MOS transistors MP5 and MN5 and output the signal N5. The source of the MOS transistor MN6 is connected to the drain of the MOS transistor MN8. The bases of the MOS transistors MN9 and MN10 are respectively connected to the clock signal CLK1. The high-speed comparator circuit also includes a clock circuit, which includes a delay unit, an inverter and an AND gate. The delay unit, the third inverter and the AND gate are connected in series in sequence. The input port 1 of the delay unit is connected to the first clock signal terminal of the clock circuit. The output of the AND gate is the second clock signal terminal of the clock circuit. The first clock signal terminal outputs a clock signal CLK, and the second clock signal terminal outputs a clock signal CLK1.

2. The single-clock controlled high-speed comparator circuit according to claim 1, wherein: The control unit in the dynamic amplification circuit includes a first switch control unit, an input control unit, a charging control unit, and an inverter, wherein the input end of the first switch control unit is connected to the clock signal CLK, and the output end of the switch control unit is connected to the input control unit, the charging control unit, and the inverter in sequence; The first switch control unit is controlled by the clock signal CLK, the input control unit is used to input the input signal INP and the input signal INN, the charging control unit is used to control the charging and discharging of the entire dynamic amplification circuit module, and the inverter is used to implement signal inversion control.

3. The single-clock controlled high-speed comparator circuit according to claim 2, wherein: The first switch control unit includes a tail current MOS transistor Mtail, the input control unit includes symmetrically connected MOS transistors MN1 and MN2, the charging control unit includes symmetrically connected MOS transistors MP1 and MP2, the inverter includes a first inverter and a second inverter, the first inverter includes MOS transistors MP3 and MN3, the second inverter includes MOS transistors MP4 and MN4, the base of the tail current MOS transistor Mtail is connected to the clock signal CLK, the source of the tail current MOS transistor Mtail is connected to the voltage source VSS, the drain of the tail current MOS transistor Mtail is respectively connected to the sources of the MOS transistors MN1 and MN2, the bases of the MOS transistors MN1 and MN2 are connected to a group of input signals INP and INN, the drain of the MOS transistor MN1 is respectively connected to the source of the MOS transistor MP1 and the bases of the MOS transistors MP3 and MN3, the MOS transistors The drain of the S transistor MN2 is respectively connected to the source of the MOS transistor MP2 and the bases of the MOS transistors MP4 and MN4. The bases of the MOS transistors MP1 and MP2 are connected. The drains of the MOS transistors MP1 and MP2 are respectively connected to the sources of the MOS transistors MP3 and MP4 and the voltage source VDD. The sources of the MOS transistors MN3 and MN4 are respectively connected to the voltage source VSS. The drains of the MOS transistors MP4 and MN4 are connected to output a signal N3, and the output signal N3 is connected to the first input terminal of the comparison and decision circuit module. The drains of the MOS transistors MP3 and MN3 are connected to output a signal N4, and the output signal N4 is connected to the second input terminal of the comparison and decision circuit module.

4. The single-clock controlled high-speed comparator circuit according to claim 1, wherein: The registers in the output register module include: a first signal adjustment unit and a second signal adjustment unit, the input ends of the first signal adjustment unit and the second signal adjustment unit are respectively connected to the output signals N5 and N6, and the output ends are respectively connected to the output signals DN and D, the first signal adjustment unit includes a plurality of first inverters connected in series and a first NAND gate, the second signal adjustment unit includes a plurality of second inverters connected in series and a second NAND gate, the output of the first NAND gate is connected to the input port 1 of the second NAND gate, and the output end of the second NAND gate is connected to the input port 1 of the first NAND gate.

Images