Comparing circuit with adaptive comparison mechanism and its operation method

Abstract

The present application relates to a comparison circuit with adaptive comparison mechanism and its operation method. A comparison circuit with adaptive comparison mechanism. The comparator is enabled by an enable signal in an enabled state in a comparison phase, and compares a first voltage and a second voltage to generate a comparison result. A comparison judgment circuit respectively sets a phase indication signal in an incomplete comparison phase state and a completed comparison phase state before and after the comparison result is generated. A time accumulation circuit starts accumulating an accumulated time when the enable signal is in the enabled state, and stops accumulating when the phase indication signal is in the completed comparison phase state to generate a comparison time. A decision circuit counts the comparison time in the comparison phase to generate a preset threshold time, and further directly sets a preset comparison result as the comparison result when the accumulated time exceeds the preset threshold time and the comparison result has not been generated in the comparison phase.

Description

TECHNICAL FIELD

[0001] The present application relates to a comparison circuit technology, and in particular, to a comparison circuit with adaptive comparison mechanism and a method of operating the same. BACKGROUND

[0002] A comparison circuit is a circuit used to compare a plurality of signals, and can be applied in different types of circuits. For example, the comparison circuit can be applied in an analog-to-digital conversion circuit for converting a continuous analog signal or a physical quantity (usually a voltage) into a digital signal. In a continuous ramp analog-to-digital conversion circuit, different configurations of a digital-to-analog circuit and operation of the comparison circuit are required to process and compare the input analog signal, so as to achieve the purpose of tracking the input signal. However, the comparison time of the comparison circuit is often affected by factors such as temperature, process, voltage, etc., and thus varies. When the comparison time is unstable, the performance of the comparison circuit will be affected. SUMMARY

[0003] In view of the problems of the prior art, one object of the present application is to provide a comparison circuit with adaptive comparison mechanism and a method of operating the same, so as to improve the prior art.

[0004] The present application includes a comparison circuit with adaptive comparison mechanism, comprising a comparator, a comparison judgment circuit, a time accumulation circuit, and a decision circuit. The comparator is enabled by an enable signal in an enabled state in a comparison phase, and compares a first voltage and a second voltage to generate a comparison result. The comparison judgment circuit makes a phase indication signal in a comparison phase incomplete state before the comparison result is generated in the comparison phase, and makes the phase indication signal in a comparison phase complete state after the comparison result is generated. The time accumulation circuit starts accumulating an accumulated time when the enable signal is in the enabled state, and stops accumulating to generate a comparison time when the phase indication signal is in the comparison phase complete state. The decision circuit counts the comparison time in the comparison phase to generate a preset threshold time, and further directly sets a preset comparison result as the comparison result when the accumulated time exceeds the preset threshold time and the comparison result has not been generated in the comparison phase.

[0005] The present invention also includes a method for operating a comparator circuit with an adaptive comparison mechanism, comprising: enabling a comparator by an enable signal in an enabled state during a comparison phase, comparing a first voltage and a second voltage to generate a comparison result; setting a stage indicator signal in an incomplete comparison phase state before the comparison result is generated by a comparison determination circuit, and setting the stage indicator signal in a completed comparison phase state after the comparison result is generated; starting a time accumulation circuit to accumulate time when the enable signal is in an enabled state, and stopping accumulation when the stage indicator signal is in a completed comparison phase state to generate a comparison time; and setting a determination circuit to statistically analyze the comparison time during the comparison phase to generate a preset threshold time, and further determining that if the accumulated time exceeds the preset threshold time and the comparison result has not yet been generated during the comparison phase, directly setting the preset comparison result as the comparison result.

[0006] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0007] [ Figure 1A This diagram shows a block diagram of a comparison circuit with an adaptive comparison mechanism according to one embodiment of the present invention.

[0008] [ Figure 1B This diagram illustrates a block diagram of an analog-to-digital converter circuit including a comparator circuit, according to one embodiment of the present invention.

[0009] [ Figure 2 The diagram shows a circuit diagram of a time accumulation circuit in one embodiment of the present invention.

[0010] [ Figure 3 This diagram shows a flowchart of a comparison circuit operation method with an adaptive comparison mechanism according to an embodiment of the present invention.

[0011] [ Figure 4 This diagram illustrates a flowchart of a comparator circuit operation method when applied to an analog-to-digital converter circuit, according to an embodiment of the present invention; and

[0012] [ Figure 5 The diagram illustrates a flowchart of a comparison circuit operation method when the comparison circuit is applied to an analog-to-digital conversion circuit, according to another embodiment of the present invention. Detailed Implementation

[0013] One objective of this invention is to provide a comparison circuit and its operation method with an adaptive comparison mechanism. By statistically analyzing the comparison time of the comparator to set a preset threshold time, and when the cumulative operation time of the comparator exceeds the preset threshold time without producing a comparison result, the preset comparison result is directly set as the comparison result, thus avoiding the situation where the comparison time is too long and a comparison result cannot be produced in a long time.

[0014] Referring to Figure 1A and Figure 1B . Figure 1A A block diagram of a comparison circuit 100 with an adaptive comparison mechanism is shown in one embodiment of the present application. Figure 1B A block diagram of an analog-to-digital conversion circuit 150 including the comparison circuit 100 is shown in one embodiment of the present application.

[0015] The comparison circuit 100 includes a comparator 110, a comparison judgment circuit 120, a time accumulation circuit 130, and a decision circuit 140.

[0016] The comparator 110 compares the first voltage Va and the second voltage Vb in a comparison phase to generate a comparison result CR. The comparison time from the start of comparison to the generation of the comparison result CR in each comparison phase is not a constant value but varies with factors such as temperature, voltage, process, etc. When the comparison time is too long and the comparator 110 still fails to generate the comparison result CR, a processing mechanism is needed to avoid the instability of the system caused by the above situation.

[0017] Therefore, the comparison judgment circuit 120, the time accumulation circuit 130, and the decision circuit 140 will operate to count the comparison time of the comparator 110 and set a preset threshold time. When the accumulated comparison time of the comparator 110 in each comparison phase exceeds the preset threshold time, the preset comparison result is directly set as the comparison result CR.

[0018] In one embodiment, the comparison circuit 100 can be applied to the analog-to-digital conversion circuit 150 as shown in Figure 1B The operation of each circuit element in the analog-to-digital conversion circuit 100 and the implementation of the application of the comparison circuit 100 will be described in more detail below.

[0019] The analog-to-digital conversion circuit 150 includes the comparison circuit 100, a digital-to-analog conversion circuit 160, and a control circuit 170.

[0020] In operation, the digital-to-analog conversion circuit 160 samples and outputs the first voltage Va and the second voltage Vb for each analog-to-digital conversion. The comparator 110 compares the first voltage Va and the second voltage Vb to generate the comparison result CR, and the control circuit 170 generates a digital code DC according to the comparison result CR to switch the configuration of the digital-to-analog conversion circuit 160.

[0021] The digital-to-analog conversion circuit 160, the comparator 110, and the control circuit 170 form a loop, and the above-mentioned procedures are repeated in multiple comparison stages. The control circuit 170 outputs a corresponding digital code DC as a digital output signal DOUT when a difference between the first voltage Va and the second voltage Vb is less than a preset level. In an embodiment, the difference is an amount of a least significant bit (LSB).

[0022] The digital-to-analog conversion circuit 160 samples the positive input voltage Vip and the negative input voltage Vin, and outputs the first voltage Va and the second voltage Vb.

[0023] In an embodiment, the digital-to-analog conversion circuit 160 can include, for example but not limited to, a positive capacitor array, a negative capacitor array, and a switching circuit (not shown), and the positive capacitor array and the negative capacitor array can be connected to an analog signal source through switches Sip and Sin, respectively. When the switches Sip and Sin are enabled, the positive capacitor array and the negative capacitor array receive the positive input voltage Vip and the negative input voltage Vin, respectively.

[0024] When the switches Sip and Sin are disabled, the positive capacitor array and the negative capacitor array are disconnected from the analog signal source to complete sampling. The switching circuit switches the configuration of the positive capacitor array and the negative capacitor array by receiving the digital code DC in each comparison stage, and thus outputs different first voltage Va and second voltage Vb.

[0025] The comparator 110 is enabled by the enable signal EN in an enabled state in each comparison stage, and compares the first voltage Va and the second voltage Vb to generate a comparison result CR, respectively.

[0026] In an embodiment, the enable signal EN can be generated by a logic circuit (not shown). The logic circuit can perform logical operations according to, for example but not limited to, a signal indicating that sampling is completed, a signal indicating that the comparator 110 has not completed comparison, and a signal indicating that analog-to-digital conversion has not been completed, and thus generate the enable signal EN in an enabled state. Therefore, the comparator 110 can be enabled when the digital-to-analog conversion circuit 160 completes sampling, the comparator 110 has not generated a comparison result CR, and there is an unfinished comparison stage.

[0027] In addition, when the digital-to-analog conversion circuit 160 has not yet completed sampling, the comparator 110 has generated a comparison result CR, or all comparison stages have been completed so that the analog-to-digital conversion has been completed, the aforementioned logic circuit can generate an enable signal EN in the disable state according to the relevant signals to disable the comparator 110. Thus, the comparator 110 will operate repeatedly according to the enable signal EN in the enable state and the disable state in each comparison stage after sampling is completed until all comparison stages are performed and the analog-to-digital conversion is completed.

[0028] It should be noted that the above-mentioned generation of the enable signal EN is only an example. When the comparison circuit 100 is applied to other types of circuits, the enable signal EN can be generated in different ways. However, the present application is not limited thereto.

[0029] In an embodiment, the comparator 110 compares the first voltage Va and the second voltage Vb and generates two output results OR1 and OR2. The comparison result CR indicates that the comparator 110 has confirmed that one of the first voltage Va and the second voltage Vb is greater than the other and generates the comparison result CR when one of the output results OR1 and OR2 is in the high state and the other is in the low state. On the contrary, when the output results OR1 and OR2 both show the low state, it indicates that the comparator 110 cannot confirm which of the first voltage Va and the second voltage Vb is greater and has not generated the comparison result CR.

[0030] It should be noted that the above-mentioned form of the comparison result CR generated by the comparator 110 is only an example. In other embodiments, the comparator 110 can also generate other forms of signals or signal combinations as the comparison result CR.

[0031] The control circuit 170 switches the configuration of the digital-to-analog conversion circuit 160 according to a set of digital codes DC in each comparison stage according to the comparison result CR, and outputs the corresponding digital code DC as the digital output signal DOUT when the difference between the first voltage Va and the second voltage Vb is less than the preset level.

[0032] The comparison judgment circuit 120 is electrically coupled to the comparator 110 and makes the stage indication signal TIS in the comparison stage incomplete state before the comparison result CR is generated in each comparison stage, and makes the stage indication signal TIS in the comparison stage complete state after the comparison result CR is generated.

[0033] In one embodiment, the comparison judging circuit 120 receives the two output results OR1 and OR2 generated by the comparator 110, and judges whether the comparison result CR is generated or not. For example, the comparison judging circuit 120 can be implemented by an exclusive OR (XOR) gate, so as to make the stage indication signal TIS in the comparison stage incomplete state when both of the output results OR1 and OR2 are in low state (the comparison result CR has not been generated), and make the stage indication signal TIS in the comparison stage complete state when one of the output results OR1 and OR2 is in high state and the other is in low state (the comparison result CR has been generated).

[0034] The time accumulation circuit 130 starts to accumulate the accumulation time AT when the enable signal EN is in the enable state, and stops the accumulation to generate the comparison time RT when the stage indication signal TIS is in the comparison stage complete state.

[0035] Please refer to Figure 2 . Figure 2 A circuit diagram of the time accumulation circuit 130 in one embodiment of the present application is shown. The time accumulation circuit 130 comprises a delay circuit 200 and a flip-flop circuit 210.

[0036] The delay circuit 200 comprises a plurality of delay units DU1-DU N which are connected in series, and are configured to transmit the enable signal EN. In one embodiment, the delay units DU1-DU N each comprise an even number of inverters which are connected in series, so as to make each delay unit DU1-DU N continuously transmit the enable signal EN in the enable state. In the present embodiment, two inverters IV1 and IV2 which are connected in series are taken as an example for illustration. However, the present application is not limited thereto.

[0037] The flip-flop circuit 210 comprises a plurality of flip-flop D-type positive and negative inverters DFT1-DFT N+1 which are connected in series. The flip-flop D-type positive and negative inverters DFT1-DFT N+1 each comprise an input terminal D, an output terminal Q and a clock input terminal CK.

[0038] The input terminal D of the first flip-flop D-type positive and negative inverter DFT1 directly receives the enable signal EN, and the input terminals D of the other flip-flop D-type positive and negative inverters DFT2-DFT N are electrically coupled to one of the delay units DU1-DU N respectively, so as to receive the enable signal EN transmitted by one of the delay units DU1-DU N . In the present embodiment, the number of the flip-flop D-type positive and negative inverters DFT2-DFT N+1 is one more than the number of the delay units DU1-DU N . The clock input terminal CK receives the stage indication signal TIS.

[0039] In one embodiment, the delay units DU1-DU N reset their delay outputs DO to low whenever the comparator 110 initiates a comparison. In one embodiment, the delay units DU1-DU N may reset their outputs DO by, for example, but not limited to, a pulse signal (not shown) generated according to the enable signal EN. The outputs DO of the delay units DU1-DU N pass the enable signal EN in the enabled state in sequence while the comparison is in progress, and the accumulated time AT will be determined according to the number of delay units that have completed passing the enable signal EN in the enabled state.

[0040] The outputs Q of the flip-flops DFT1-DFT N output the signal at the input D when the stage indication signal TIS is in the comparison stage completion state.

[0041] Thus, the comparison time RT can be determined by the number of flip-flops DFT that output the enable signal EN in the enabled state, and this number is related to the total delay time length of the delay units that have passed the enable signal EN in the enabled state.

[0042] For example, after it is known that the number of flip-flops DFT that output the enable signal EN in the enabled state is 5, it can be further known that the number of delay units that have passed the enable signal EN in the enabled state is 4. The total delay time length of these delay units can be obtained by multiplying the unit delay time length of one delay unit by the number of delay units, and taken as the comparison time RT. In one numerical example, the unit delay time length of one delay unit is 0.1-0.2 nanoseconds. Taking 0.1 nanoseconds as an example, the total delay time length of 4 delay units is 0.4 nanoseconds.

[0043] The determination circuit 140 is electrically coupled to the delay outputs DO of the delay units DU1-DU N and obtains the accumulated time AT according to the number of delay outputs DO that output the enable signal EN in the enabled state. Also, the determination circuit 140 is electrically coupled to the outputs Q of the flip-flops DFT1-DFT N and obtains the comparison time RT according to the number of outputs Q that output the enable signal EN in the enabled state.

[0044] The decision circuit 140 calculates the comparison time RT in each comparison stage to generate the preset threshold time TT. In more detail, the decision circuit 140 records the comparison time RT in each analog-to-digital conversion corresponding to different comparison stages, and calculates the average of the comparison time RT by, for example but not limited to, averaging. The decision circuit 140 thus knows the average comparison time RT of each comparison stage to generate the comparison result CR, and sets the threshold time TT accordingly.

[0045] In different embodiments, the decision circuit 140 can directly set the average comparison time RT as the threshold time TT, or increase the average comparison time RT by a preset value and set it as the threshold time TT. Moreover, the decision circuit 140 can store the threshold time TT in a storage circuit (not shown) disposed inside or outside the decision circuit 140.

[0046] The decision circuit 140 further directly sets a preset comparison result DR as the comparison result CR when the accumulated time AT exceeds the preset threshold time TT and the comparison result CR has not been generated in each comparison stage.

[0047] In more detail, when the comparator 110 generates the comparison result CR before the accumulated time AT exceeds the preset threshold time TT, the control circuit 170 switches the configuration of the digital-to-analog conversion circuit 160 according to the comparison result CR in digital code DC. When the comparator 110 does not generate the comparison result CR even after the accumulated time AT exceeds the preset threshold time TT, the decision circuit 140 sets the preset comparison result DR as the comparison result CR, and the control circuit 170 switches the configuration of the digital-to-analog conversion circuit 160 according to the preset comparison result DR in digital code DC.

[0048] In an embodiment, the preset comparison result DR causes the control circuit 170 to determine that one of the first voltage Va and the second voltage Vb is greater than the other. In more detail, the decision circuit 140 can also generate the preset comparison result DR with two preset output results, one of which is high and the other of which is low.

[0049] By the above mechanism, the analog-to-digital conversion circuit 150 can avoid the situation that the comparison time of the comparator 110 is too long and the comparison result CR is not generated in time.

[0050] In an embodiment, the decision circuit 140 can generate corresponding preset threshold times TT corresponding to different environmental conditions, and determine according to the corresponding preset threshold times TT when different environmental conditions are detected. Each environmental condition can correspond to a process corner.

[0051] For example, operating voltage, ambient temperature, and process drifts are environmental conditions that can cause variations in the speed of P-type and N-type devices. When the environmental conditions correspond to a process corner of "Fast-Fast (FF)", the P-type and N-type devices have faster speeds. At this time, the preset threshold time TT generated by the decision circuit 140 in statistics of the comparison time RT of the same comparison stage is smaller. When the environmental conditions correspond to a process corner of "Slow-Slow (SS)", the P-type and N-type devices have slower speeds. At this time, the preset threshold time TT generated by the decision circuit 140 in statistics of the comparison time RT of the same comparison stage is larger.

[0052] It should be noted that the above-mentioned environmental conditions are only an example. In other embodiments, the environmental conditions can be set according to other environmental parameters.

[0053] Therefore, the decision circuit 140 can detect the voltage, temperature, or other environmental conditions corresponding to the comparison circuit 100 according to, for example, but not limited to, the environmental parameter detection circuit (not shown) set in the comparison circuit 100, and then determine whether the accumulated time AT of the comparison performed by the comparator 110 is too long according to the corresponding preset threshold time TT, and set the preset comparison result DR as the comparison result CR when the accumulated time AT exceeds the preset threshold time TT.

[0054] Therefore, the comparison circuit with adaptive comparison mechanism of the present application can set the preset threshold time by counting the comparison time of the comparator, and directly set the preset comparison result as the comparison result when the accumulated time of the operation of the comparator exceeds the preset threshold time without generating the comparison result, thereby avoiding the situation that the comparison time is too long and the comparison result cannot be generated in time.

[0055] It should be noted that the above-mentioned circuit structure and the number of elements included in each circuit are only an example. In different embodiments, the circuit structure and the number of elements can be adjusted according to actual needs without affecting the efficiency. Moreover, the above-mentioned logic circuit and the high and low of the related state are also only an example. Other logic circuits can also be used without affecting the efficiency, or the operation can be performed according to the opposite state. Moreover, the comparison circuit 100 can be applied to other circuits other than the analog-to-digital conversion circuit 150. The present application is not limited to the above-mentioned embodiments.

[0056] Please refer to Figure 3 . Figure 3 A flowchart of a method 300 for operating a comparison circuit with adaptive comparison mechanism is shown in an embodiment of the present application.

[0057] In addition to the above-mentioned device, the present application further discloses a method 300 for operating a comparison circuit with adaptive comparison mechanism, which is applied to, for example, but not limited to Figure 1Aone of the comparison circuit operation methods 300 is implemented as Figure 3 as shown, comprising the following steps.

[0058] At step S310, the comparator 110 is enabled by the enable signal EN in the comparison phase to compare the first voltage Va and the second voltage Vb to generate a comparison result.

[0059] At step S320, the comparison determination circuit 120 is enabled by the enable signal EN in the comparison phase to generate a comparison result CR, and the phase indication signal TIS is in the comparison phase incomplete state before the comparison result is generated, and the phase indication signal TIS is in the comparison phase complete state after the comparison result is generated.

[0060] At step S330, the time accumulation circuit 130 starts to accumulate the accumulation time AT when the enable signal EN is in the enable state, and stops the accumulation to generate a comparison time RT when the phase indication signal TIS is in the comparison phase complete state.

[0061] At step S340, the determination circuit 140 determines the comparison time RT in the comparison phase to generate a preset threshold time, and further determines that the accumulation time AT exceeds the preset threshold time and the comparison result CR has not been generated in the comparison phase, and directly sets the preset comparison result DR as the comparison result CR.

[0062] Please refer to Figure 4 . Figure 4 The flowchart of the comparison circuit operation method 400 when the comparison circuit 100 is applied to the analog-to-digital conversion circuit 150 in one embodiment of the present application is shown. The comparison circuit operation method 400 comprises the following steps.

[0063] At step S410, the digital-to-analog conversion circuit 160 samples the positive input voltage Vip and the negative input voltage Vin to output the first voltage Va and the second voltage Vb.

[0064] At step S420, the comparator 110 is enabled by the enable signal EN in each comparison phase to compare the first voltage Va and the second voltage Vb.

[0065] At step S430, the time accumulation circuit 130 starts to accumulate the accumulation time AT when the enable signal EN is in the enable state.

[0066] At step S440, it is determined whether the comparison result CR is generated.

[0067] At step S450, the comparison and judgment circuit 120 locates the stage indication signal TIS at the comparison stage incomplete state before the comparison result CR is generated. The flow will return to step S330 to accumulate the accumulated time AT by the time accumulation circuit 130.

[0068] At step S460, the comparison and judgment circuit 120 locates the stage indication signal TIS at the comparison stage complete state after the comparison result CR is generated, and the time accumulation circuit 130 stops the accumulation to generate the comparison time RT when the stage indication signal TIS is located at the comparison stage complete state.

[0069] At step S470, it is judged whether the difference between the first voltage Va and the second voltage Vb is less than the preset level.

[0070] At step S480, when the difference between the first voltage Va and the second voltage Vb is not less than the preset level, the control circuit 170 switches the configuration of the digital to analog conversion circuit 160 according to the comparison result CR in the digital code DC.

[0071] At step S490, the decision circuit 140 counts the comparison time RT to generate the preset threshold time. The flow will return to step S320 to continue the comparison of the next comparison stage. It should be noted that in an embodiment, the decision circuit 140 can count the past comparison time RT every time a new comparison time RT is obtained. In other embodiments, the decision circuit 140 can also accumulate a certain number of comparison times RT before counting.

[0072] At step S495, when the difference between the first voltage Va and the second voltage Vb is less than the preset level, the control circuit 170 outputs the corresponding digital code DC as the digital output signal DOUT.

[0073] Please refer to Figure 5 . Figure 5 A flowchart of a comparison circuit operation method 500 applied to the analog to digital conversion circuit 150 is shown in another embodiment of the present application. The comparison circuit operation method 500 includes the following steps.

[0074] At step S510, the digital to analog conversion circuit 160 is enabled to sample the positive input voltage Vip and the negative input voltage Vin to output the first voltage Va and the second voltage Vb.

[0075] At step S520, the comparator 110 is enabled by the enable signal EN located at the enable state in each comparison stage to compare the first voltage Va and the second voltage Vb, respectively.

[0076] At step S530, the time accumulation circuit 130 starts to accumulate the accumulated time AT when the enable signal EN is located at the enable state.

[0077] At step S540, it is determined whether the comparison result CR is generated.

[0078] At step S550, when the comparison result CR is not generated, it is determined whether the accumulated time AT exceeds the preset threshold time. When the accumulated time AT does not exceed the preset threshold time, the flow returns to step S430 to accumulate the accumulated time AT by the time accumulation circuit 130.

[0079] At step S560, when the accumulated time AT exceeds the preset threshold time, the decision circuit 140 directly sets the preset comparison result DR as the comparison result CR.

[0080] At step S570, when the flow determines that the comparison result CR is generated at step S440, or the decision circuit 140 directly sets the preset comparison result DR as the comparison result CR at step S460, it is determined whether the difference between the first voltage Va and the second voltage Vb is less than the preset level.

[0081] At step S580, when the difference between the first voltage Va and the second voltage Vb is not less than the preset level, the control circuit 170 switches the configuration of the digital-to-analog conversion circuit 160 according to the comparison result CR by the digital code DC. The flow returns to step S520 to continue the comparison of the next comparison stage.

[0082] At step S590, when the difference between the first voltage Va and the second voltage Vb is less than the preset level, the control circuit 170 outputs the corresponding digital code DC as the digital output signal DOUT.

[0083] In an embodiment, Figure 3 the analog-to-digital conversion method 300 and Figure 4 the analog-to-digital conversion method 400 can be selectively and independently performed at different stages, or simultaneously.

[0084] It is noted that the above-described embodiments are only examples. In other embodiments, those skilled in the art can make changes without departing from the spirit of the present application.

[0085] In summary, the comparison circuit with adaptive comparison mechanism and the operation method thereof in the present application can set the preset threshold time by counting the comparison time of the comparator, and directly set the preset comparison result as the comparison result when the accumulated time of the comparator operation exceeds the preset threshold time and the comparison result is not generated, thereby avoiding the situation that the comparison time is too long and the comparison result is not generated.

[0086] Although the present application has been described in terms of the embodiments thereof, those skilled in the art will be in position to appreciate that the technical features of the present application can be changed or substituted, according to the technical spirits of the present application, without departing from the scope of the present application. In other words, the scope of the patent protection of the present application should be defined by the scope of the patent application as set forth in the specification.

[0087] SYMBOL DESCRIPTION

[0088] 100: comparison circuit

[0089] 110: comparator

[0090] 120: comparison determining circuit

[0091] 130: time accumulating circuit

[0092] 140: determining circuit

[0093] 150: analog-digital converting circuit

[0094] 160: digital-analog converting circuit

[0095] 170: control circuit

[0096] 200: delay circuit

[0097] 210: flip-flop circuit

[0098] 300: comparison circuit operation method

[0099] S310-S340: steps

[0100] 400: comparison circuit operation method

[0101] S410-S495: steps

[0102] 500: comparison circuit operation method

[0103] S510-S590: steps

[0104] AT: accumulated time

[0105] CK: clock input terminal

[0106] CR: comparison result

[0107] D: input terminal

[0108] DC: digital code

[0109] DFT1-DFT: flip-flop D-type N+1 : flip-flop D-type

[0110] DO: delay output terminal

[0111] DOUT: digital output signal

[0112] DU1~DU N : delay unit

[0113] EN: enable signal

[0114] IV1, IV2: inverter

[0115] OR1, OR2: output result

[0116] Q: output terminal

[0117] RT: comparison time

[0118] Sip, Sin: switch

[0119] TIS: stage indication signal

[0120] TT: preset threshold time

[0121] Va: first voltage

[0122] Vb: second voltage

[0123] Vip: positive input voltage

[0124] Vin: negative input voltage

Claims

1. A comparison circuit with adaptive comparison mechanism, comprising: a comparator configured to compare a first voltage and a second voltage to generate a comparison result in a comparison phase enabled by an enable signal in an enabled state; a comparison decision circuit configured to set a phase indication signal in an incomplete comparison phase state before the comparison result is generated in the comparison phase, and set the phase indication signal in a complete comparison phase state after the comparison result is generated in the comparison phase; a time accumulation circuit configured to start accumulating an accumulated time when the enable signal is in the enabled state, and stop accumulating to generate a comparison time when the phase indication signal is in the complete comparison phase state; and a decision circuit configured to count the comparison time in the comparison phase to generate a preset threshold time, and further set a preset comparison result as the comparison result when the accumulated time exceeds the preset threshold time and the comparison result has not been generated in the comparison phase.

2. The comparison circuit of claim 1, wherein the decision circuit generates corresponding preset threshold times corresponding to different environmental conditions, and judges according to the corresponding preset threshold times when detecting different environmental conditions.

3. The comparison circuit of claim 2, wherein the different environmental conditions correspond to different process corners.

4. The comparison circuit of claim 1, wherein the time accumulation circuit comprises: a delay circuit comprising a plurality of delay units connected in series, configured to pass the enable signal; a flip-flop circuit comprising a plurality of flip-flop D-type positive and negative inverters connected in series, each comprising: an input end, wherein a first one of the plurality of flip-flop D-type positive and negative inverters is configured to directly receive the enable signal, and the other flip-flop D-type positive and negative inverters are respectively electrically coupled to one of the plurality of delay units to receive the enable signal passed by the one of the plurality of delay units; an output end; and a clock input end configured to receive the phase indication signal; and wherein the output end of each of the plurality of flip-flop D-type positive and negative inverters outputs the signal of the input end when the phase indication signal is in the complete comparison phase state, the comparison time is determined by a number of the plurality of flip-flop D-type positive and negative inverters outputting the enable signal in the enabled state, and the number is related to a total delay time length of the plurality of delay units passing the enable signal in the enabled state.

5. The comparison circuit of claim 4, wherein the decision circuit is electrically coupled to a delay output end of each of the plurality of delay units to obtain the accumulated time, and the decision circuit is electrically coupled to the output end of each of the plurality of flip-flop D-type positive and negative inverters to obtain the comparison time.

6. The comparison circuit of claim 1, wherein the comparison circuit is disposed in an analog-to-digital conversion circuit, the comparator is configured to compare the first voltage and the second voltage to generate the comparison result in each of a plurality of comparison phases enabled by the enable signal in the enabled state, and the comparison circuit further comprises: ​ ​ a digital-to-analog conversion circuit configured to sample a positive input voltage and a negative input voltage to output a first voltage and a second voltage; and a control circuit configured to switch a set of states of the digital-to-analog conversion circuit according to a set of digital codes based on the comparison result in each of a plurality of comparison stages, and output a corresponding one of the set of digital codes as a digital output signal when a difference between the first voltage and the second voltage is less than a predetermined level.

7. A comparison circuit operation method with adaptive comparison mechanism, comprising: enabling a comparator to compare a first voltage and a second voltage to generate a comparison result in a comparison stage after an enabling signal is enabled in an enabled state; causing a comparison determining circuit to set a stage indication signal in a comparison stage incomplete state before the comparison result is generated in the comparison stage, and set the stage indication signal in a comparison stage complete state after the comparison result is generated; causing a time accumulation circuit to start accumulating an accumulated time when the enabling signal is in the enabled state, and stop accumulating to generate a comparison time when the stage indication signal is in the comparison stage complete state; and causing a decision circuit to generate a predetermined threshold time by counting the comparison time in the comparison stage, and directly set a predetermined comparison result as the comparison result when the accumulated time exceeds the predetermined threshold time and the comparison result has not been generated in the comparison stage.

8. The comparison circuit operation method of claim 7, further comprising: causing the decision circuit to generate corresponding predetermined threshold times for different environmental conditions, and determine according to corresponding predetermined threshold times when different environmental conditions are detected.

9. The comparison circuit operation method of claim 7, wherein the time accumulation circuit comprises a delay circuit and a flip-flop circuit, and the flip-flop circuit comprises a plurality of flip-flop D-type positive and negative inverters connected in series, each comprising an input terminal, an output terminal, and a clock input terminal configured to receive the stage indication signal, the comparison circuit operation method further comprising: causing the delay circuit to comprise a plurality of delay units connected in series to pass the enabling signal; causing a first one of the plurality of flip-flop D-type positive and negative inverters to directly receive the enabling signal, and other ones of the plurality of flip-flop D-type positive and negative inverters to be electrically coupled to one of the plurality of delay units to receive the enabling signal passed by the one of the plurality of delay units; and causing the output terminal of each of the plurality of flip-flop D-type positive and negative inverters to output a signal of the input terminal when the stage indication signal is in the comparison stage complete state, wherein the comparison time is determined by a number of the plurality of flip-flop D-type positive and negative inverters outputting the enabling signal in the enabled state, and the number is related to a total delay time length of the plurality of delay units passing the enabling signal in the enabled state. ​ ​ 10. The comparison circuit operation method of claim 9, wherein the decision circuit is electrically coupled to a delay output terminal of each of the plurality of delay units and obtains the accumulated time therefrom, and the decision circuit is electrically coupled to the output terminal of each of the plurality of flip-flops and obtains the comparison time therefrom.

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