Multi-path parallel circuit based on QC-LDPC hard decision decoding algorithm and implementation method thereof

Abstract

The application provides a multi-path parallel circuit based on QC-LDPC hard decision decoding algorithm and an implementation method thereof, and is used for solving the technical problems that the existing circuit based on hard decision GDBF algorithm consumes too much hardware resource and the processing speed cannot meet the current high-speed data transmission. The multi-path parallel circuit comprises parallel P-path hard decision circuits, a first conversion circuit and a second conversion circuit. The hard decision circuit comprises an offset module, a first storage RAM, a second storage RAM, a second selector, L shift check modules, a calculation module, L+1 energy value storage RAMs, a flip module and a second XOR module. The offset module is used for storing column offset and row offset of a selected check matrix. The shift check module is used for shifting a code word and obtaining a check subsum. The calculation module is used for calculating the energy value of the code word, encoding the energy value, and obtaining a maximum energy value. The flip module is used for determining whether to flip according to the energy value of each bit of the code word and the maximum energy value.

Description

TECHNICAL FIELD

[0001] The present application relates to decoding technology, in particular to a multi-path parallel circuit based on QC-LDPC hard decision decoding algorithm and an implementation method thereof. BACKGROUND

[0002] Low density parity check code (LPDC) is a special linear block code, which is an excellent channel coding scheme because of its flexible code rate and performance approaching the Shannon limit. Let the code word length of QC-LPDC be n, and the signal code length be k, then the code group can be represented as LPDC(n, k), and the check bit length is n-k. Hard decision decoding is to judge the received information as 0 and 1 and then decode, and the hard decision GDBF algorithm proposes the concept of target equation, and applies a simple gradient descent algorithm to the GDBF decoding algorithm, and uses the flipping equation to determine the position of the bit to be flipped in each iteration.

[0003] With the rapid development of modern communication technology and application specific integrated circuit design, how to reduce the bit error rate in the case of high-speed data transmission has become an important research direction. A large number of experimental results show that the hard decision GDBF algorithm has excellent ability to reduce the bit error rate, and can greatly improve the reliability of the system, but the existing parallel circuit based on hard decision GDBF algorithm in the case of slow transmission speed, the hardware resource consumption of the circuit can be accepted, but with the increase of transmission rate, the hardware resource consumption will be significantly improved, and the processing speed of the circuit cannot meet the current high-speed data transmission. SUMMARY

[0004] The technical problem to be solved by the present application is that the existing circuit based on hard decision GDBF algorithm has too large hardware resource consumption, and the processing speed cannot meet the current high-speed data transmission, and a multi-path parallel circuit based on QC-LDPC hard decision decoding algorithm and an implementation method thereof are provided.

[0005] In order to achieve the above-mentioned purpose, the technical solution of the present application is as follows:

[0006] A multi-path parallel circuit based on QC-LDPC hard decision decoding algorithm, wherein the QC-LDPC hard decision decoding algorithm is provided with a check matrix of binary LDPC code, and the special feature is that it comprises a parallel P-path hard decision circuit, a first conversion circuit connected to the input end of the P-path hard decision circuit, and a second conversion circuit connected to the output end of the P-path hard decision circuit.

[0007] The hard decision circuit comprises an offset module, a first storage RAM, a second storage RAM, a second selector, L shift check modules, a calculation module, L+1 energy value storage RAMs, a flipping module and a second XOR module, wherein the number of L is the number of layers of the check matrix.

[0008] The offset module is used to store and select column offset and row offset of the check matrix; the shift check module is used to shift the code word and obtain the sum of the check subcode corresponding to the position where the value of each column in the check matrix is 1; the calculation module is used to calculate the energy value of each bit of the code word and encode all the energy values to obtain the maximum energy value; the number of the encoded bits is L+1 bits, if there is one 1, the L+1th bit is 1, and the remaining bits are all 0, if there are two 1s, the Lth bit and the L+1th bit are 1, and the remaining bits are all 0, and so on, if there are L+1 1s, all the bits are 1; the flip module is used to determine whether to flip according to the comparison result of the energy value of each bit of the code word and the maximum energy value;

[0009] The first conversion circuit input end is used to receive the input initial code word information and perform serial-parallel conversion, the output end thereof is connected to the input end of the first storage RAM in the P-path hard decision circuit, the two output ends of the first storage RAM are connected to one input end of the second selector and one input end of the second XOR module respectively, and are used to input the initial code word information to the second selector and the second XOR module respectively; the output ends of the second selector and the offset module are connected to the input ends of the L shift check modules respectively, the output ends of the L shift check modules and the output end of the second XOR module are connected to the L+1 input ends of the calculation module respectively, one output end of the calculation module is connected to the input end of the L+1 energy value storage RAM, the other output end of the calculation module and the output end of the energy value storage RAM are both connected to the input end of the flip module, the flip module is interconnected with the second storage RAM, the first output end and the second output end of the second storage RAM are connected to the other input end of the second selector and the other input end of the second XOR module respectively, and are used to select or XOR the flipped code word information and the initial code word information; the third output end of the second storage RAM of the P-path hard decision circuit is connected to the input end of the second conversion circuit in parallel, and is used to output the code word information decoded successfully through the second conversion circuit after serial-parallel conversion.

[0010] Further, the calculation module includes an addition module, L+1 energy value registers, L+1 OR modules, L+1 AND gates and an energy maximum value register;

[0011] The addition module is used to add the input L-path check subcode sum and the flipped code word information to obtain the energy value, and encode the energy value;

[0012] The L+1 energy registers are respectively used to store the encoded energy value in high-low bit order;

[0013] The L+1 input ends of the adding module are connected with the output ends of the L shift check modules and the output end of the second exclusive OR module respectively, the output end of the adding module is connected with the input ends of the L+1 energy value registers respectively, one output end of the L+1 energy value registers is connected with the input ends of the L+1 energy value storage RAMs respectively, the other output end of the L+1 energy value registers is connected with the input ends of the L+1 OR modules respectively, which are used for performing OR operation on the L+1 groups of encoded energy values to obtain the maximum energy value of the current block of the check matrix, the output ends of the L+1 OR modules are connected with one input end of the L+1 OR gates respectively, the output end of the L+1 OR gates is connected with the input end of the maximum energy value register, which is used for inputting the latest maximum energy value into the maximum energy value register; the output end of the maximum energy value register is connected with the other input end of the L+1 OR gates, which is used for comparing the maximum energy value of the current block of the check matrix with the maximum energy value of the previous block of the check matrix to obtain the latest maximum energy value; meanwhile, the output end of the maximum energy value register is also connected with the input end of the flip module.

[0014] Further, the shift check module comprises a third selector, a barrel shift circuit, a first exclusive OR module and a register.

[0015] One input end of the third selector is connected with the output end of the second selector, the output end of the third selector is connected with one input end of the barrel shift circuit, the other input end of the barrel shift circuit is connected with the output end of the offset module, which is used for shifting the code word information according to the selected offset; the output end of the barrel shift circuit is connected with one input end of the first exclusive OR module, the output end of the first exclusive OR module is connected with the input end of the register, which is used for storing the generated check sub after shifting; the output end of the register is also connected with the other input end of the third selector, which is used for shifting the check sub according to the selected offset; the other output end of the register is connected with the other input end of the first exclusive OR module, which is used for performing exclusive OR operation on the shifted data and the check sub of the previous beat to generate a new check sub, until the check sub sum of all blocks of the corresponding layer of the check matrix is obtained after shifting; the other output end of the barrel shift circuit is also connected with the input end of the adding module.

[0016] Further, the offset module comprises a first selector, L first storage ROMs and L second storage ROMs.

[0017] The first storage ROMs are used for storing the column offset of the check matrix, and the second storage ROMs are used for storing the row offset of the check matrix.

[0018] The first selector is used for selecting the column offset or the row offset of the check matrix.

[0019] The output ends of the L first storage ROMs and the output ends of the L second storage ROMs are respectively connected to the input ends of a first selector, and the L output ends of the first selector are respectively connected to the other input ends of L barrel shift circuits of a shift check module.

[0020] Further, the number of the first storage ROMs and the second storage ROMs is equal to the number of layers of the check matrix.

[0021] The depth of the first storage ROMs and the second storage ROMs is equal to the number of blocks of each layer of the check matrix.

[0022] Further, the P is an integer, which is determined by the following formula:

[0023] P >= (T*a+B / b) / (B / b);

[0024] Wherein, T is the clock cycle required by the hard decision GDBF decoding algorithm for one iteration; a is the iteration number; B is the bit value of a frame of code word; and b is the bit value sent per clock cycle.

[0025] The application further provides an implementation method of a multi-path parallel circuit based on a QC-LDPC hard decision decoding algorithm, which is characterized by comprising the following steps:

[0026] 1. Decoding start

[0027] The code word information inputted from outside is received by the first conversion circuit, and is sent into the first storage RAM after being converted from serial to parallel, and is stored in the first storage RAM; when a frame of code word is stored, the first storage RAM generates a decoding start signal, and the subsequent circuit starts decoding after receiving the decoding start signal;

[0028] 2. Calculate the sum of the check subscripts corresponding to the positions where the value of each column of the check matrix is 1

[0029] 2.1. The first storage RAM 5 takes out a block of initial code word information, and sends the code word information into the L shift check modules through the second selector; and the offset module sends the column offset of the check matrix into the L shift check modules;

[0030] 2.2. The L shift check modules shift the code words of all the blocks in the L layers of the check matrix through the column offset of the check matrix, and obtain the corresponding check subscripts and the sum of the check subscripts;

[0031] 2.3. The offset module sends the row offset of the check matrix into the L shift check modules, the shift check modules shift the sum of the check subscripts obtained in step 2.2 according to the row offset, obtain the sum of the check subscripts corresponding to the positions where the value of each column of the check matrix is 1, and send the sum of the check subscripts corresponding to the positions where the value of each column of the check matrix is 1 into the calculation module;

[0032] 3】Calculate the energy value of each bit of the code word and the maximum energy value

[0033] 3.1】The second XOR module sends the XOR of the initial code word information input from the first storage RAM 5 and the flipped code word information input from the second storage RAM to the calculation module; the first flipped code word information is sent to the flipping module to generate through the initial code word information pre-stored in the second storage RAM;

[0034] 3.2】The calculation module calculates the sum of the syndrome corresponding to the position where each column value in the input check matrix is 1 and the XOR value of the initial code word information and the flipped code word information, and obtains the energy value of each bit of the code word;

[0035] 3.3】Encode the obtained energy value of each bit of the code word through the calculation module, and the number of encoded bits is L+1 bits; if there is one 1, the L+1th bit is 1 and the remaining bits are 0; if there are two 1s, the Lth and L+1th bits are 1 and the remaining bits are 0; if there are L+1 1s, all bits are 1; send the encoded N+1 groups of energy values to N+1 energy value storage RAMs (14);

[0036] 3.4】Calculate the N+1 groups of maximum energy values through the calculation module, and send the obtained N+1 groups of maximum energy values and the N+1 groups of energy values in the N+1 energy value storage RAMs (14) to the flipping module;

[0037] 4】Flip correction and successful decoding

[0038] The flipping module compares the energy value of each bit sent by the N+1 energy value storage RAMs with the N+1 groups of maximum energy values:

[0039] If the values of the corresponding bits of the code word are not equal, the flipping module does not flip, and step 5】 is executed;

[0040] If the values of the corresponding bits of the code word are equal, flip the value of the bit, complete the correction, and send the corresponding code word to the second XOR module and the second selector through the updated second storage RAM, and iterate through the second selector to complete the next check until the syndrome sum is 0 or the maximum iteration number is reached, then the decoding is successful, the flipping module does not flip, and step 5】 is executed;

[0041] 5】Send the corresponding code word to the second conversion circuit through the updated second storage RAM for serial-parallel conversion and output.

[0042] The beneficial effects of the present application compared with the prior art are:

[0043] The application provides a multi-path parallel circuit based on QC-LDPC hard decision decoding algorithm, which is decoded by setting P-path parallel hard decision circuits, and the energy maximum value is obtained by specially coding the energy value of each bit of the code word, so that the code word is corrected, and the circuit structure is simple, the hardware resource consumption is small, the throughput is high, and the high-speed processing of parallel data can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 The circuit structure diagram of the embodiment of the application is shown in the figure, and the other 9 parallel hard decision circuits are not shown.

[0045] Figure 2 The circuit structure diagram of the calculation module in the embodiment of the application is shown in the figure.

[0046] Specific reference signs are as follows:

[0047] 1-first storage ROM; 2-second storage ROM; 3-first conversion circuit; 4-second conversion circuit; 5-first storage RAM; 6-second storage RAM; 7-first selector; 8-second selector; 9-third selector; 10-barrel shift circuit; 11-first XOR module; 12-register; 13-calculation module, 131-addition module, 132-energy value register, 133-OR module, 134-OR gate, 135-energy maximum value register; 14-energy value storage RAM; 15-flip module; 16-second XOR module. DETAILED DESCRIPTION

[0048] In order to make the advantages and characteristics of the application clearer, the application is further described in detail below in combination with the drawings and specific embodiments.

[0049] In the hard decision GDBF algorithm used by the application, the check matrix H of the regular binary LDPC code is an M*N sparse matrix, C=[c0, c1, …, c n-1 ] is the coded code word, X=[x0, x1, …, x n-1 ] is the binary phase shift keying modulated code word, Y=[y0, y1, …, y n-1 ] is the received signal after the additive white Gaussian noise channel transmission, S=[s0, s1, …, s m-1 ] is the check sub, wherein Y=X+V, V is a Gaussian random variable, the mean is 0, and the variance is δ 2 =N0 / 2; Z=[z0, z1, …, z n-1 ] is obtained after hard decision of Y.

[0050] The conventional hard decision GDBF algorithm mainly includes the following three steps:

[0051] First step: calculate the syndrome s in each iteration of the hard decision algorithm n The process needs a product of a 1*N matrix and an N*M matrix, and the syndrome s in each iteration n is calculated by the following formula:

[0052]

[0053] If the syndrome s in each iteration n is 0, it proves that the code word transmission is error-free, and if the syndrome s in each iteration n is not 0, it proves that the code word transmission is erroneous.

[0054] Second step: calculate the energy value Δ of each bit of the code word n (z), also known as the maximum value of the energy function;

[0055] The energy value Δ of each bit of the code word n (z) is calculated by the following formula:

[0056]

[0057] Wherein, z n represents the flipped code word information, y n represents the initial code word information, and s i represents the syndrome corresponding to the position where each column of the check matrix H is 1; that is, the energy value Δ of each bit of the code word n (z) is obtained by the sum of the exclusive-OR value of the initial code word information and the flipped code word information and the syndrome corresponding to the position where each column of the check matrix H is 1.

[0058] Then, the corresponding maximum energy value is calculated based on the energy value Δ of each bit of the code word n (z), and the code bit position corresponding to the maximum energy value is the error position, which needs to be flipped to realize the error correction function.

[0059] Third step: the flipped code word information continues to the next iteration, and returns to step 1 to check. If the sum of the syndromes is zero or the maximum number of iterations is reached, it proves that the decoding is successful, otherwise the iteration continues.

[0060] The code word length n of the QC-LDPC (9216, 7680) in the embodiment is 9216 bits, the information code length k is 7680 bits, the check bit n-k is 1536 bits, the check matrix H is an M*N matrix, the size of which is 1536*9216, the row weight is 24, that is, the number of values 1 in M rows is 24, and the column weight is 4, that is, the number of values 1 in N columns is 4. The size of the cyclic sub-matrix in the check matrix H is 384*384, the cyclic sub-matrix has the cyclic right shift property, and the whole check matrix H is divided into 4 layers, and each layer has 24 blocks.

[0061] In order to meet the speed limit requirement, the code word needs to be sent continuously in each frame in the decoding and error correction process, but because the first frame code word is in the decoding process in the traditional circuit, the second frame code word is in the waiting stage of writing into the RAM, and the second frame code word can enter the circuit only after the decoding of the first frame code word is completed. In order to solve this problem, the P-way parallel hard decision circuit is adopted in the application, so that the first frame code word passes through the first circuit for iteration, and at the same time, the code word memory of the second circuit starts to receive the second frame code word. The number P of parallel hard decision circuits needs to be determined through the following method steps:

[0062] 1. According to the bit value B of a frame code word and the bit value b sent in each clock cycle, the number of clock cycles required to receive a frame code word and the number of clock cycles required to output a frame code word are both B / b.

[0063] 2. According to the period T required for one iteration of the hard decision GDBF decoding algorithm and the iteration number n, the number of clock cycles for successful decoding of a frame code word is T*n. Combined with the number of clock cycles required to output a frame code word B / b obtained in step 1, the number of clock cycles from decoding success to output of a frame code word is T*n+B / b.

[0064] 3. According to the number of clock cycles T*n+B / b from decoding success to output of a frame code word and the number of clock cycles B / b required to receive a frame code word, the number P of required decoding iteration circuits is ≥(T*n+B / b) / (B / b), and P is an integer. Preferably, the minimum value of the calculation result is selected as the number of hard decision circuits.

[0065] In this embodiment, a frame of code word is 9216 bits, 80 bits are sent in each period, and the code word memory receives a frame of code word in 115.2 clock periods. According to the hard decision GDBF decoding algorithm, one iteration needs 64 clock periods, and 15 iterations are needed to decode successfully, that is, 960 clock periods are needed for a frame of code word to decode successfully, and the output also needs 115.2 clock periods. Therefore, the number of clock periods from decoding success to output of a frame of code word is 960+115.2=1075.2. Through calculation, 1076 / 115.2=9.34, that is, 10 parallel hard decision circuits are needed to enable each subsequent frame of code word data to be received by other parallel hard decision circuits during the decoding process, ensuring uninterrupted output at a certain rate.

[0066] The application provides a multi-path parallel circuit based on a QC-LDPC hard decision decoding algorithm, which is used for realizing the transmission of QC-LDPC (9216, 7680) and specifically comprises 10 parallel hard decision circuits, a first conversion circuit 3 connected with the input ends of the 10 parallel hard decision circuits, and a second conversion circuit 4 connected with the output ends of the 10 parallel hard decision circuits. The first conversion circuit 3 is an 80-to-384 serial-parallel conversion circuit, which is used for receiving input data of the entire circuit and converting the input code word from 80 bits to 384 bits. The second conversion circuit 4 is a 384-to-80 serial-parallel conversion circuit, which is used for converting the decoded code word from 384 bits to 80 bits and serving as the output of the entire 10 parallel circuits. The hard decision circuit comprises four first storage ROMs 1, four second storage ROMs 2, a first storage RAM 5, a second storage RAM 6, a first selector 7, a second selector 8, four third selectors 9, four barrel shift circuits 10, four first XOR modules 11, four registers 12, a calculation module 13, five energy value storage RAMs 14, a flip module 15, and a second XOR module 16. The first storage ROM 1 is used for storing the column offset of the check matrix H, that is, the column position of the cyclic submatrix value 1. The second storage ROM 2 is used for storing the row offset of the check matrix H, that is, the row position of the cyclic submatrix value 1. The number of the first storage ROM 1 and the second storage ROM 2 is the number of layers of the check matrix, and the depth is the number of blocks of each layer of the check matrix. Therefore, in this embodiment, the number of the first storage ROM 1 and the second storage ROM 2 is four, and the depth is 24 bits. The width of the first storage ROM 1 and the second storage ROM 2 is calculated according to the column offset and the row offset, respectively. For example, the width of the first storage ROM 1 is used to represent the maximum column offset, and the width of the second storage ROM 2 is used to represent the maximum row offset. The width of the first storage ROM 1 is 384 bits, and the width of the second storage ROM 2 is 256 bits. 8 9 ​=512, 256<384<512, therefore, the width of the first storage ROM 1 and the second storage ROM 2 is set to 9 bits in this embodiment. The first storage RAM 5 is used to store initial codeword information and to generate a decoding start signal; the second storage RAM 6 is used to store initial codeword information and flipped codeword information, wherein the initial codeword information is used to provide a primary comparison value to the flipping module 15 to generate first flipped codeword information. The first selector 7 is an 8-to-4 selector used to select 4 sets of row offsets or 4 sets of column offsets of the check matrix H. The second selector 8 is a 2-to-l selector used to select initial codeword information and flipped codeword information. The four third selectors 9 are all the same in structure and are 2-to-l selectors used to select codeword information input by the second selector 8 and syndrome S input by the register 12. The four barrel shift circuits 10 are all the same in structure and are used to shift 4 layers of 24 blocks of the check matrix H or the syndrome S. The first exclusive OR module 11 is used to exclusive OR the value of the shifted codeword information with the syndrome S stored in the register 12 at the previous moment. The register 12 is used to store the sum of the syndrome S and the shifted and exclusive ORed check matrix H. The calculation module 13 includes an addition module 131, 5 energy value registers 132, 5 OR modules 133, 5 OR gates 134, and an energy maximum value register 135. The addition module 131 is used to add the input 4-way syndrome sum with the flipped codeword information to obtain the energy value of each bit of the corresponding codeword and to encode the energy value. Each bit of the 384 bits of the codeword corresponds to an energy value. Specifically, the number of encoded bits is 5 bits in this embodiment. If there is one 1 in the energy value, the 5th bit is 1 and the remaining bits are all 0, i.e., the encoding is 00001. If there are two 1s in the energy value, the 4th bit and the 5th bit are 1 and the remaining bits are all 0, i.e., the encoding is 00011. If there are five 1s in the energy value, all the bits are 1, i.e., the encoding is 11111. The 5 energy registers 132 are used to store the encoded energy values in order of high and low bits respectively. The OR modules 133 are used to OR the 384-bit encoded energy values in the 5 energy registers 132 to obtain the 5-bit maximum energy value of the block in the check matrix. The OR gates 134 are used to compare the 5-bit maximum energy value of the block in the check matrix with the maximum energy value of the previous block and to input the latest maximum energy value into the energy maximum value register 135 for storage, so that the latest maximum energy value is always stored in the energy maximum value register 135. The flipping module 15 is used to determine whether to flip according to the comparison result of the energy value of each bit of the codeword and the maximum energy value, and to determine whether to proceed to the next iteration or whether the decoding is successful. The second exclusive OR module 16 is used to exclusive OR the input initial codeword information with the flipped codeword information.

[0067] The specific connection relationship of the ten parallel circuits based on the hard decision GDBF algorithm in the embodiment is as follows: the input end of the first conversion circuit 3 is used for receiving the input initial code word information, the output ends of the first conversion circuit 3 are respectively connected to the input ends of the first storage RAM 5 in the 10-way hard decision circuit, the two output ends of the first storage RAM 5 are respectively connected to one input end of the second selector 8 and one input end of the second exclusive OR module 16, and are all used for inputting the initial code word information; the output end of the second selector 8 is connected to one input end of four third selectors 9, and the output ends of the third selectors 9 are respectively connected to one input end of the corresponding barrel shift circuit 10. The output ends of the four first storage ROMs 1 and the output ends of the four second storage ROMs 2 are all connected to the input end of the first selector 7, and the four output ends of the first selector 7 are respectively connected to the other input end of the four barrel shift circuits 10. One output end of the barrel shift circuit 10 is connected to one input end of the first exclusive OR module 11, and the output end of the first exclusive OR module 11 is connected to the input end of the register 12; one output end of the register 12 is connected to the other input end of the corresponding third selector 9, and the other output end of the register 12 is connected to the other input end of the corresponding first exclusive OR module 11. The other output of the four barrel shift circuits 10 is connected to the four input ends of the addition module 131, and the output end of the second exclusive OR module 16 is connected to the fifth input end of the addition module 131; the output ends of the addition module 131 are respectively connected to the input ends of the five energy value registers 132, one output end of the five energy value registers 132 is respectively connected to the input end of the five energy value storage RAMs 14, the other output end of the five energy value registers 132 is respectively connected to the input end of the five OR modules 133, the output ends of the five OR modules 133 are connected to one input end of the five OR gates 134, and the output ends of the five OR gates are connected to the input end of the maximum energy value register 135; one output end of the maximum energy value register 135 is respectively connected to the other input end of the five OR gates, and the other output end of the maximum energy value register 135 is connected to one input end of the flip module 15; the output ends of the five energy value storage RAMs 14 are connected to the other output end of the flip module 15. The flip module 15 and the second storage RAM 6 are interconnected, and the first output end and the second output end of the second storage RAM 6 are respectively connected to the other input end of the second selector 8 and the other input end of the second exclusive OR module 16. The third output end of the second storage RAM 6 in the 10-way hard decision circuit is connected to the input end of the second conversion circuit 4 in parallel, and the output end of the second conversion circuit 4 is used for outputting data after serial-parallel conversion.

[0068] Based on the ten parallel circuits based on the QC-LDPC hard decision decoding algorithm in the above embodiment, the application further provides a ten parallel circuit implementation method based on the QC-LDPC hard decision decoding algorithm, which specifically comprises the following steps:

[0069] 1】Decoding starts

[0070] The 80bit data inputted from outside, i.e. initial codeword information, is converted into 384bit by the first conversion circuit 3 and then stored in the first storage RAM 5. When the 24 384bit of the first layer of the check matrix H are stored, the first storage RAM 5 generates a decoding start signal, and the subsequent circuit starts decoding after receiving the decoding start signal.

[0071] 2】Calculate the sum of the check sub-matrix corresponding to the position where the value of each column of the check matrix H is 1

[0072] 2.1】The first storage RAM 5 takes out one 384bit and sends it to the fourth selector 9 through the second selector 8, and then sends it to the corresponding four barrel shift circuits 10 through the third selector 9. The first selector 7 selects the four 9bit column offsets stored in the four first storage ROMs 1 for the first time, i.e. the column positions with value 1 in the cyclic sub-matrix, and sends them to the four barrel shift circuits 10.

[0073] 2.2】The four barrel shift circuits 10 shift the 384bit data inputted by the third selector 9 through the four 9bit column offsets. The shifted value first enters the corresponding first XOR module 11 and is XORed with the check sub-matrix of the previous beat in the register 12 to obtain a new check sub-matrix. Then the new check sub-matrix is stored in the corresponding register 12. After the 24 384bit data are shifted and XORed, the sum of the check sub-matrix is obtained. Finally, the sum of the four layers of check sub-matrix is stored in the corresponding four registers 12.

[0074] 2.3】The third selector 9 selects the sum of the check sub-matrix stored in the register 12 and sends it to the four barrel shift circuits 10. The first selector 7 selects the four 9bit row offsets stored in the four second storage ROMs 2 and sends them to the four barrel shift circuits 10. The four barrel shift circuits 10 shift the 384bit of the check sub-matrix according to the four 9bit row offsets to obtain the sum of the check sub-matrix corresponding to the position where the value of each column of the check matrix H is 1. The barrel shift circuit 10 sends the obtained sum of the check sub-matrix corresponding to the position where the value of each column of the check matrix H is 1 to the addition module 131 of the calculation module 13. The four barrel shift circuits 10 output the sum of the check sub-matrix of the four layers of shift.

[0075] 3】Calculate the energy value and the maximum energy value of each bit of the codeword

[0076] 3.1】The second XOR module 16 XORs the initial codeword information inputted by the first storage RAM 5 and the flipped codeword information inputted by the second storage RAM 6 and sends it to the addition module 131 of the calculation module 13. The first flipped codeword information is generated by sending the initial codeword information pre-stored in the second storage RAM 6 to the flipping module 15.

[0077] 3.2】Addition module 131 calculates the sum of the corresponding syndrome of the position where the value of each column of the input check matrix H is 1 and the exclusive-OR value of the initial codeword information and the flipped codeword information, and obtains the energy value of each bit of the codeword;

[0078] 3.3】The obtained energy value of each bit of the codeword is encoded by the addition module 131, and the number of encoded bits is 5 bits. If there is one 1 in the energy value, the 5th bit is 1 and the remaining bits are 0, that is, the encoding is 00001. If there are two 1s in the energy value, the 4th and 5th bits are 1 and the remaining bits are 0, that is, the encoding is 00011. In this way, if there are five 1s in the energy value, all the bits are 1, that is, the encoding is 11111. The encoded 5 groups of 384-bit energy values are stored in 5 energy value registers 132 according to high and low bits. The 5 groups of 384-bit energy values in the 5 energy value registers 132 are sent to 5 energy value storage RAMs 14 respectively in one way and to 5 OR modules 133 in the other way.

[0079] 3.4】The 384-bit energy values in each group of encoded energy values are ORed by the 5 OR modules 133 respectively, and the 5-bit maximum energy value, that is, the 5-bit maximum energy value of the current block in the check matrix, is obtained. After comparison with the 5-bit maximum energy value of the previous block in the check matrix stored in the energy maximum value register 135 through the corresponding 5 OR gates 13, the latest energy maximum value is input into the energy maximum value register 135 for storage, so that the energy maximum value register 135 always stores the latest energy maximum value. Then, the latest 5-bit maximum energy value in the energy maximum value register 135 and the 5 groups of 384-bit energy values in the 5 energy value storage RAMs 14 are sent to the flipping module 15.

[0080] 4】Flip correction and successful decoding

[0081] The flipping module 15 compares each bit of the energy value sent by the 5 energy value storage RAMs 14 with the 5-bit maximum energy value:

[0082] If the values of the corresponding bit positions of the codeword are not equal, the flipping module 15 does not flip and step 5】 is executed.

[0083] If the values of the corresponding bit positions of the codeword are equal, the value of the bit position is flipped to complete the error correction. The flipped codeword is sent to the second exclusive-OR module 16 and the second selector 8 through the updated second storage RAM 6. The second selector 8 is selected to complete the next iteration until the syndrome sum is 0 or the maximum iteration number is reached, then the decoding is successful, the flipping module 15 does not flip, and step 5】 is executed.

[0084] 5】The corresponding codeword is sent into the second conversion circuit 4 through the updated second storage RAM 6 to convert 384 bits into 80 bits output.

[0085] The above is only one embodiment of the present application, in other embodiments of the present application, the number, depth and width of the first storage ROM 1 and the second storage ROM 2 are adjusted according to the codeword length, the size of the check matrix H, the number of layers, and the size of the cyclic sub-matrix; the depth of the first codeword storage RAM 5 and the second codeword storage RAM 6 is adjusted according to the codeword length; the output width of the first codeword storage RAM 5, the second codeword storage RAM 6, the first selector 7, the second selector 8, the third selector 9, the barrel shift circuit 10, the first XOR module 11, the register 12, the calculation module 13, the energy value storage RAM 14, the flip module 15 and the second XOR module 16 is adjusted according to the size of the cyclic sub-matrix; the input width of the energy maximum value register 14 and the number of the energy value storage RAM 15 are adjusted according to the number of layers of the check matrix H.

[0086] The above is only to illustrate the technical solutions of the present application, and is not a limitation. For ordinary skilled persons in the art, the specific technical solutions described in the above embodiments can be modified, or some technical features can be replaced with equivalent ones, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions protected by the present application.

Claims

1. A multi-channel parallel circuit based on a QC-LDPC hard-decision decoding algorithm, wherein the hard-decision decoding algorithm includes a check matrix for binary LDPC codes, characterized in that: It includes a parallel P-path hard decision circuit, a first conversion circuit (3) connected to the input of the P-path hard decision circuit, and a second conversion circuit (4) connected to the output of the P-path hard decision circuit. The hard decision circuit includes an offset module, a first storage RAM (5), a second storage RAM (6), a second selector (8), L shift check modules, a calculation module (13), L+1 energy value storage RAMs (14), a flip module (15), and a second XOR module (16); the number L is the number of layers in the check matrix; The offset module is used to store and select the column offset and row offset of the check matrix; The shift verification module is used to shift the codeword and obtain the sum of the check elements corresponding to the positions with a value of 1 in each column of the verification matrix; The calculation module (13) is used to calculate the energy value of each bit of the codeword and encode all the energy values ​​to obtain the maximum energy value; the number of bits of the encoding is L+1 bits. If there is one 1, the L+1th bit is 1 and the rest bits are 0. If there are two 1s, the Lth bit and the L+1th bit are 1 and the rest bits are 0. And so on. If there are L+1 1s, all bits are 1. The flipping module (15) is used to determine whether to flip the codeword based on the comparison result between the energy value of each bit of the codeword and the maximum energy value. The input terminal of the first conversion circuit (3) is used to receive the initial codeword information and perform serial-to-parallel conversion. Its output terminal is connected to the input terminal of the first storage RAM (5) in the P-way hard decision circuit. The two output terminals of the first storage RAM (5) are connected to one input terminal of the second selector (8) and one input terminal of the second XOR module (16). The output terminal of the second selector (8) and the output terminal of the offset module are connected to the input terminals of L shift check modules. The output terminals of the L shift check modules and the output terminal of the second XOR module (16) are connected to the L+1 input terminals of the calculation module (13). One output terminal of the calculation module (13) is connected to the L+1 energy value storage RAMs. 14) The other output terminal and the output terminal of the energy value storage RAM (14) are both connected to the input terminal of the flip module (15). The flip module (15) is interconnected with the second storage RAM (6). The first output terminal and the second output terminal of the second storage RAM (6) are respectively connected to the other input terminal of the second selector (8) and the other input terminal of the second XOR module (16), which are used to select or XOR the flipped code word information and the initial code word information. The third output terminal of the second storage RAM (6) of the P-path hard decision circuit is connected in parallel to the input terminal of the second conversion circuit (4), which is used to output the successfully decoded code word information after serial-to-parallel conversion through the second conversion circuit (4).

2. The multi-channel parallel circuit based on the QC-LDPC hard-decision decoding algorithm according to claim 1, characterized in that: The calculation module (13) includes an addition module (131), L+1 energy value registers (132), L+1 OR modules (133), L+1 OR gates (134), and an energy maximum value register (135); The addition module (131) is used to add the sum of the input L-way parities to the flipped codeword information to obtain the energy value, and to encode the energy value; The L+1 energy registers (132) are used to store the encoded energy values ​​in high-low order, respectively; The L+1 input terminals of the addition module (131) are respectively connected to the output terminals of the L shift check modules and the output terminal of the second XOR module (16). The output terminal of the addition module (131) is respectively connected to the input terminals of the L+1 energy value registers (132). One output terminal of the L+1 energy value registers (132) is respectively connected to the input terminals of the L+1 energy value storage RAM (14). The other output terminal of the L+1 energy value registers (132) is respectively connected to the input terminals of the L+1 OR modules (133), which are used to OR the L+1 groups of encoded energy values ​​to obtain the maximum energy value of this block of the check matrix. The output of the OR module (133) is connected to one input of L+1 OR gates (134), and the output of L+1 OR gates is connected to the input of the maximum energy register (135) to input the latest maximum energy value into the maximum energy register (135); the output of the maximum energy register (135) is connected to the other input of L+1 OR gates (134) to compare the maximum energy value of this block of the parity matrix with the maximum energy value of the previous block of the parity matrix to obtain the latest maximum energy value; at the same time, the output of the maximum energy register (135) is also connected to the input of the flip module (15).

3. A multi-channel parallel circuit based on the QC-LDPC hard-decision decoding algorithm according to claim 2, characterized in that: The shift verification module includes a third selector (9), a barrel shift circuit (10), a first XOR module (11), and a register (12); One input of the third selector (9) is connected to the output of the second selector (8), and the output of the third selector (9) is connected to one input of the barrel shift circuit (10). The other input of the barrel shift circuit (10) is connected to the output of the offset module, which is used to shift the codeword information according to the selected offset. The output of the barrel shift circuit (10) is connected to one input of the first XOR module (11), and the output of the first XOR module (11) is connected to the input of the register (12), which is used to store the parity generated after shifting. The output of the register (12) is connected to the other input of the third selector (9), which is used to shift the parity according to the selected offset. The output of the register (12) is also connected to the other input of the first XOR module (11), which is used to XOR the shifted data with the parity of the previous step to generate a new parity, until all blocks of the corresponding parity matrix layer are shifted to obtain the sum of the parities. The output of the barrel shift circuit (10) is also connected to the input of the addition module (131).

4. A multi-channel parallel circuit based on the QC-LDPC hard-decision decoding algorithm according to claim 3, characterized in that: The offset module includes a first selector (7), L first storage ROMs (1), and L second storage ROMs (2); The first storage ROM (1) is used to store the column offset of the parity matrix, and the second storage ROM and (2) are used to store the row offset of the parity matrix; The first selector (7) is used to select the offset of the column or the row offset of the check matrix; The output terminals of the L first storage ROMs (1) and the L second storage ROMs (2) are respectively connected to the input terminals of the first selector (7), and the L output terminals of the first selector (7) are respectively connected to the other input terminals of the L barrel shift circuits (10) of the shift verification module.

5. A multi-channel parallel circuit based on the QC-LDPC hard-decision decoding algorithm according to claim 4, characterized in that: The number of the first storage ROM (1) and the second storage ROM (2) are both the number of layers of the parity check matrix; The depth of the first storage ROM (1) and the second storage ROM (2) is the number of blocks in each layer of the parity check matrix.

6. A multi-channel parallel circuit based on the QC-LDPC hard-decision decoding algorithm according to any one of claims 1-5, characterized in that: P is an integer, which is determined by the following formula: P≥(T*a+B / b) / (B / b); Where T is the clock cycle required for one iteration of the hard-decision GDBF decoding algorithm; a is the number of iterations; B is the bit value of one frame of codewords; and b is the bit value sent per clock cycle.

7. A method for implementing a multi-channel parallel circuit based on the QC-LDPC hard-decision decoding algorithm as described in any one of claims 1-6, characterized in that, Includes the following steps: 1】Decoding begins The first conversion circuit (3) receives externally input codeword information, converts it from serial to parallel, and sends it to the first storage RAM (5) for storage. When a frame of codewords is stored, the first storage RAM (5) generates a decoding start signal. The subsequent circuit starts decoding after receiving the decoding start signal.

2. Calculate the sum of the checksums corresponding to the positions with a value of 1 in each column of the check matrix. 2.1】The first storage RAM 5 (5) retrieves a block of initial codeword information and sends it to L shift verification modules through the second selector (8); the offset module sends the column offset of the verification matrix to L shift verification modules; 2.2】L shift check modules shift the codewords of all blocks in the L layers of the check matrix by the column offset of the check matrix, and obtain the corresponding check and the sum of the check; 2.3】The offset module sends the row offset of the check matrix to L shift check modules. The shift check modules shift the sum of check items obtained in step 2.2 according to the row offset to obtain the sum of check items corresponding to the position of each column with a value of 1 in the check matrix, and send the sum of check items corresponding to the position of each column with a value of 1 in the check matrix to the calculation module (13).

3. Calculate the energy value and maximum energy value of each bit in the codeword. 3.1】The second XOR module (16) XORs the initial codeword information input from the first storage RAM 5 (5) and the flipped codeword information input from the second storage RAM (6) and sends it to the calculation module (13); the first flipped codeword information is generated by sending the initial codeword information pre-stored in the second storage RAM (6) to the flipping module (15); 3.2】The calculation module (13) calculates the sum of the parsing elements corresponding to the positions with a value of 1 in each column of the input parity matrix and the XOR value of the initial codeword information and the flipped codeword information to obtain the energy value of each bit of the codeword; 3.3】The energy value of each bit of the obtained codeword is encoded by the calculation module (13). The number of bits encoded is L+1. If there is one 1, the L+1th bit is 1 and the rest bits are 0. If there are two 1s, the Lth bit and the L+1th bit are 1 and the rest bits are 0. And so on. If there are L+1 1s, all bits are 1. The encoded N+1 groups of energy values ​​are sent to the N+1 energy value storage RAM (14). 3.4】The calculation module (13) performs calculations on the encoded N+1 groups of energy values ​​to obtain the maximum value of N+1 groups of energy; the obtained maximum value of N+1 groups of energy and the N+1 groups of energy values ​​stored in RAM (14) are sent to the flipping module (15); 4) Flip error correction and successful decoding The flip module (15) compares the energy value of each bit sent from the N+1 energy value storage RAM (14) with the N+1 sets of maximum energy values: If the values ​​of the corresponding bits of the codeword are not equal, the flip module (15) will not flip and will execute step 5. If the values ​​of the corresponding bits of the codeword are equal, the value of the bitword is flipped to complete the error correction. The flipped codeword is sent to the second XOR module (16) and the second selector (8) respectively by updating the second storage RAM (6). The second selector (8) is used to select to complete the next iteration until the sum of the checksums is 0 or the maximum number of iterations is reached. Then the decoding is successful, the flip module (15) does not flip, and step 5 is executed. 5】The corresponding codeword is sent to the second conversion circuit (4) through the second storage RAM (6) for serial-to-parallel conversion and then output.

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