Operating methods of controllers and semiconductor memory devices and memory systems

Abstract

This disclosure provides a controller, a method for operating a semiconductor memory device, and a memory system. The document provides a semiconductor memory device, a controller, and a memory system having the semiconductor memory device and the controller. A method for operating the controller of the memory system controls a semiconductor memory device included in the memory system and comprising a plurality of memory blocks. The method for operating the controller may include: sensing the energized state of the memory system; and, based on the sensing that the memory system is energized, performing an erase block scan operation on the plurality of memory blocks using a scan read voltage. Each memory cell in the plurality of memory blocks can store at least two bits of data, and the scan read voltage enables the erasure state and programming state of the memory cell to be distinguished from each other.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to an electronic device, and more specifically to a semiconductor memory device, a controller, and a memory system having the semiconductor memory device and the controller. Background Technology

[0002] Semiconductor memory devices can have a two-dimensional (2D) structure, in which strings are arranged horizontally on a semiconductor substrate. In response to the physical scaling limit (i.e., the limit of integration) of two-dimensional semiconductor memory devices, three-dimensional (3D) semiconductor memory devices are manufactured, comprising multiple memory cells vertically stacked on a semiconductor substrate.

[0003] A controller can control the operation of a semiconductor memory device. Summary of the Invention

[0004] Various embodiments of this disclosure relate to semiconductor memory devices with improved operating speeds, and to controllers and memory systems having the semiconductor memory devices and controllers.

[0005] One embodiment of this disclosure provides a method for operating a controller of a memory system, the controller controlling a semiconductor memory device comprising a plurality of memory blocks. The method includes the steps of: sensing an energized state of the memory system; and, based on the sensing that the memory system is in the energized state, performing an erase block scan operation on the plurality of memory blocks using a scan read voltage. Each memory cell in the plurality of memory blocks can store at least two bits of data. The scan read voltage enables the erasure state and programming state of the memory cells to be distinguished from each other.

[0006] In one embodiment, the step of performing an erase block scan operation on the plurality of memory blocks using a scan read voltage may include the following steps: selecting from the plurality of memory blocks a memory block that has not yet undergone the erase block scan operation; controlling the semiconductor memory device to perform a single-level cell (SLC) read operation on the selected memory block using the scan read voltage; and updating the block state of the selected memory block based on the result of the (SLC) read operation.

[0007] In one embodiment, controlling the semiconductor memory device to perform the SLC read operation on a selected memory block using the scan read voltage may include the following steps: controlling the semiconductor memory device to sequentially read data stored in a plurality of pages in the selected memory block using the scan read voltage; and analyzing the read data.

[0008] In one implementation, the method may further include the step of: determining the selected storage block as a programming block in response to an analysis result indicating that all pages in the selected storage block are programming pages.

[0009] In one embodiment, the method may further include the following steps: in response to an analysis result indicating that all pages in the selected storage block are erased pages, determining the selected storage block as an erase block.

[0010] In one embodiment, the method may further include the step of: determining the selected block as an open block in response to the analysis result that the selected memory block includes both programming pages and erase pages.

[0011] One embodiment of this disclosure provides a method for operating a semiconductor memory device comprising multiple memory blocks, each of which includes multiple memory cells, each memory cell storing at least two bits of data. The method for operating the semiconductor memory device may include the steps of: receiving a read command from a controller; checking the type of the received read command; and selectively using a scan read voltage or a normal read voltage set based on the type of the read command to perform a data read operation on the page corresponding to the read command.

[0012] In one embodiment, the method may further include the step of transmitting the read data to the controller.

[0013] In one implementation, the step of selectively using a scan read voltage or a normal read voltage set to read data from a page corresponding to a read command based on the type of the read command includes the following steps: in response to a determination that the type of the read command is a single-level cell (SLC) read command, reading data from the page corresponding to the read command using the scan read voltage.

[0014] In one embodiment, the scan read voltage enables the erase state and at least one programming state of the memory cell to be distinguished from each other.

[0015] In one implementation, the step of selectively using a scan read voltage or a normal read voltage set to read data from the page corresponding to the read command based on the type of the read command may include the following steps: in response to a determination that the type of the read command is a normal read command, reading data from the page corresponding to the read command using the normal read voltage set.

[0016] In one embodiment, each of the plurality of memory cells can store two bits of data, and the normal read voltage set can be at least one of a first read voltage set for reading the least significant bit (LSB) page data stored in the selected page and a second read voltage set for reading the most significant bit (MSB) page data stored in the selected page.

[0017] In one embodiment, each of the plurality of memory cells can store three bits of data, and the normal read voltage set is at least one of a first read voltage set for reading least significant bit (LSB) page data stored in the selected page, a second read voltage set for reading center significant bit (CSB) page data stored in the selected page, and a third read voltage set for reading most significant bit (MSB) page data stored in the selected page.

[0018] Embodiments of this disclosure can provide a storage system. The storage system may include a semiconductor memory device and a controller. The semiconductor memory device may include a plurality of memory blocks, each memory block including a plurality of memory cells, each memory cell storing at least two bits of data. The controller may be configured to control the operation of the semiconductor memory device. The controller may be configured to control the semiconductor memory device to perform an erase block scan operation on the plurality of memory blocks using a scan read voltage in response to sensing the power-on state of the storage system, the scan read voltage enabling the erasure state and programming state of each of the memory cells to be distinguished from each other.

[0019] In one embodiment, the controller can control the semiconductor memory device to perform the erase block scan operation by transmitting a single-layer cell (SLC) read command to the semiconductor memory device that is different from a normal read command.

[0020] In one embodiment, the controller can select from the plurality of memory blocks a memory block that has not yet undergone the erase block scan operation, sequentially generate a plurality of SLC read commands corresponding to a plurality of pages in the selected memory block, and transmit the SLC read commands to the semiconductor memory device.

[0021] In one implementation, the controller may update the block status of the selected memory block based on read data received in response to the plurality of SLC read commands for the selected memory block.

[0022] In one implementation, in response to the SLC read command, the semiconductor memory device can use the scan read voltage to read data from the page corresponding to the SLC read command.

[0023] One embodiment of this disclosure provides a storage system including a storage device and a controller. The storage device may include a plurality of storage blocks. The controller may be configured to: sense the power-on state of the storage system; in response to the sensed power-on state of the storage system, select a storage block from the plurality of storage blocks; and control the storage device to perform a scan read operation on the selected storage block using a scan read voltage to distinguish between erase and program states; and determine, based on the scan read operation, whether the selected storage block is an open storage block, an erase storage block, or a programmable storage block. Attached Figure Description

[0024] Figure 1 This is a block diagram showing a storage system with a controller and semiconductor storage devices.

[0025] Figure 2 It is shown Figure 1 A block diagram of one embodiment of a semiconductor memory device.

[0026] Figure 3 It is shown Figure 2 A block diagram of one implementation of a storage cell array.

[0027] Figure 4 It is shown Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0028] Figure 5 It is shown Figure 3 A circuit diagram of an implementation of any one of the storage blocks BLK1 to BLKz, BLKb.

[0029] Figure 6 It is shown Figure 2 A circuit diagram of an implementation of any one of the storage blocks BLK1 to BLKz in the storage cell array, BLKc.

[0030] Figure 7 This is a graph showing the threshold voltage distribution of a three-layer cell (TLC).

[0031] Figure 8 This is a block diagram illustrating a storage system according to one embodiment of the present disclosure.

[0032] Figure 9A and Figure 9B A cell string including memory cells in a programmed state and a cell string including memory cells in an erased state are shown.

[0033] Figure 10It is a diagram used to explain the cell current flowing through a cell string that includes memory cells in the programming state and a cell string that includes memory cells in the erasure state.

[0034] Figure 11 This is a timing diagram illustrating the erase block scan operation using LSB read operations.

[0035] Figure 12 This is a diagram used to explain the SLC read operation used in an erase block scan operation according to one embodiment of the present disclosure.

[0036] Figure 13 This is a diagram used to explain the cell current flowing through the cell string during an SLC read operation according to one embodiment of this disclosure.

[0037] Figure 14 This is a timing diagram illustrating an erase block scan operation using an SLC read operation according to one embodiment of the present disclosure.

[0038] Figure 15 This is a flowchart illustrating an operation method of a controller according to one embodiment of the present disclosure.

[0039] Figure 16 It is shown Figure 15 A flowchart of one implementation of operation S200.

[0040] Figure 17 It is shown Figure 16 A flowchart of one implementation of operation S230.

[0041] Figures 18A to 18C This is a diagram showing memory blocks in erase, programmed, and open states.

[0042] Figure 19 This is a block diagram illustrating a storage system according to one embodiment of the present disclosure.

[0043] Figure 20 This is a flowchart illustrating an operation method of a semiconductor memory device according to one embodiment of the present disclosure.

[0044] Figure 21 It is shown that has Figure 2 A block diagram of a semiconductor memory device's memory system.

[0045] Figure 22 It is shown Figure 21 A block diagram of an exemplary application of a storage system.

[0046] Figure 23 It shows including Figure 22 A block diagram of a storage system and a computing system. Detailed Implementation

[0047] Specific structural and functional descriptions are provided herein to illustrate embodiments of this disclosure. However, the invention can be embodied in various forms and manners and should not be construed as limited to the disclosed embodiments.

[0048] Figure 1 This is a block diagram showing a storage system 1000 having a controller and a semiconductor storage device.

[0049] refer to Figure 1 The storage system 1000 may include a semiconductor storage device 100 and a controller 200. Furthermore, the storage system 1000 communicates with a host 300. The controller 200 controls the overall operation of the semiconductor storage device 100 by transmitting commands (CMDs) in response to requests received from the host 300. The controller 200 also transmits data (DATA) corresponding to the corresponding command (CMD) to or receives data (DATA) from the semiconductor storage device 100. When a programming request and programming data are received from the host 300, the controller 200 transmits a programming command corresponding to the programming request and programming data to the semiconductor storage device 100. When a read request is received from the host 300, the controller 200 transmits a read command corresponding to the read request to the semiconductor storage device 100. Subsequently, the semiconductor storage device 100 transmits read data corresponding to the read command to the controller 200.

[0050] When the storage system 1000 switches from a closed state to an open state, the operation of starting the storage system 1000 can be performed. The startup operation of the storage system 1000 may include scanning multiple storage blocks in the semiconductor storage device 100 to determine the current scan state of the corresponding storage blocks and storing the scan state in the memory of the controller 200. For example, the multiple storage blocks in the semiconductor storage device 100 may be in any of the following states: erased state, programmed state, and open state. A storage block is in an erased state when no data is stored in any physical page of it and all cells in the corresponding storage block are in an erased state. A storage block is in a programmed state when all physical pages in a storage block contain data. A storage block is in an open state when some, but not all, physical pages in a storage block contain data. The state of a corresponding storage block can be determined by sequentially reading the data stored in the pages of the storage block. To this end, the controller 200 can generate multiple read commands to read data from the pages in the storage block and transmit the read commands to the semiconductor storage device 100. The semiconductor storage device 100 can perform a read operation corresponding to each received read command and transmit the read data as the result of the read operation to the controller 200.

[0051] Figure 2 It is shown Figure 1 A block diagram of one embodiment of the semiconductor memory device 100.

[0052] refer to Figure 2 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150.

[0053] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Memory blocks BLK1 to BLKz may be connected to the address decoder 120 via word lines WL. Memory blocks BLK1 to BLKz may be connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells and may be implemented as non-volatile memory cells with a vertical channel structure. In one embodiment, the memory cell array 110 may be implemented as a memory cell array with a two-dimensional (2D) structure. In another embodiment, the memory cell array 110 may be implemented as a memory cell array with a three-dimensional (3D) structure. Each memory cell in the memory cell array may store at least one bit of data. In one embodiment, each memory cell in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In one embodiment, each memory cell in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In one embodiment, each storage cell in the storage cell array 110 may be a three-level cell (TLC) that stores three bits of data. In another embodiment, each storage cell in the storage cell array 110 may be a four-level cell (QLC) that stores four bits of data. In various embodiments, the storage cell array 110 may include a plurality of storage cells, each of which stores five or more bits of data.

[0054] The address decoder 120, read / write circuitry 130, and voltage generator 150 operate together as peripheral circuitry to drive the memory cell array 110. Here, the peripheral circuitry operates under the control of control logic 140. The address decoder 120 is connected to the memory cell array 110 via word line WL. The address decoder 120 can operate under the control of control logic 140. The address decoder 120 can receive addresses via an input / output buffer (not shown) disposed in the semiconductor memory device 100.

[0055] Address decoder 120 can decode the block address in the received address. Address decoder 120 selects at least one memory block based on the decoded block address. When a read voltage application operation is performed during a read operation, address decoder 120 can apply the read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines. During a program verification operation, address decoder 120 can apply the verification voltage generated by voltage generator 150 to the selected word line of the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines.

[0056] Address decoder 120 can decode the column address in the received address. Address decoder 120 can transmit the decoded column address to read / write circuit 130.

[0057] Both read and program operations of the semiconductor memory device 100 are performed on a page basis. Addresses received in response to read and program operation requests may include block addresses, row addresses, and column addresses. Address decoder 120 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 120 and then provided to read / write circuitry 130. Multiple memory cells connected to a word line can form a physical page. When each of the multiple memory cells in the semiconductor memory device 100 stores a single-level cell (SLC) of one bit, one logical page of data can be stored in a physical page. When each of the multiple memory cells in the semiconductor memory device 100 stores a multi-level cell (MLC) of two bits, two logical page of data can be stored in a physical page, for example, most significant bit (MSB) page data and least significant bit (LSB) page data. When each of the plurality of memory cells in the semiconductor memory device 100 stores a three-bit three-level cell (TLC), a physical page can store three logical page data entries, such as MSB page data, CSB page data, and LSB page data. When each of the plurality of memory cells in the semiconductor memory device 100 stores a four-bit four-level cell (QLC), a physical page can store four logical page data entries, such as MSB page data, HCSB page data, LCSB page data, and LSB page data.

[0058] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0059] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110 and as a "write circuit" during a write operation. The multiple page buffers PB1 to PBm can be connected to the memory cell array 110 via bit lines BL1 to BLm. During a read or program verification operation, in order to sense the threshold voltage of the memory cell, the page buffers PB1 to PBm can continuously supply a sensing current to the bit lines connected to the memory cell, while each page buffer PB1 to PBm senses the change in the amount of current flowing according to the programming state of the corresponding memory cell via a sensing node and latches it as sense data. The read / write circuit 130 operates in response to a page buffer control signal output from control logic 140.

[0060] During a read operation, the read / write circuit 130 can sense the data stored in the memory cell and temporarily store the read data, and then output the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, the read / write circuit 130 may include a column select circuit or similar circuitry and a page buffer (or page register).

[0061] Control logic 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 can control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 can output control signals to control the precharge potential levels of sensing nodes of multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110. Control logic 140 can control voltage generator 150 to generate various voltages for programming operations on memory cell array 110. Furthermore, control logic 140 can control address decoder 120 to transmit the voltage generated by voltage generator 150 to the local line of the memory block targeted for operation via a global line. Control logic 140 can control read / write circuit 130 so that during a read operation, read / write circuit 130 reads data from the selected page of the memory block via bit lines BL1 to BLm and stores the read data in page buffers PB1 to PBm. Furthermore, control logic 140 can control read / write circuit 130 so that during a programming operation, read / write circuit 130 programs the data stored in page buffers PB1 to PBm into the selected page.

[0062] Voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass for read operations in response to a control signal output from control logic 140. Voltage generator 150 may include multiple pumping capacitors for receiving internal power supply voltages to generate multiple voltages with various voltage levels, and can generate multiple voltages by selectively activating multiple pumping capacitors under the control of control logic 140.

[0063] The address decoder 120, read / write circuit 130, and voltage generator 150 (collectively referred to as peripheral circuitry) can perform read, write, and erase operations on the memory cell array 110. Under the control of control logic 140, the peripheral circuitry can also perform read, write, and erase operations on the memory cell array 110.

[0064] Figure 3 It is shown Figure 2 A block diagram of one embodiment of the storage cell array 110.

[0065] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLK2. Each memory block may have a three-dimensional (3D) structure. Each memory block includes multiple memory cells stacked on a substrate. These memory cells are arranged along the positive X (+X) direction, the positive Y (+Y) direction, and the positive Z (+Z) direction. See below for reference. Figure 4 and Figure 5 Describe the structure of each storage block in detail.

[0066] Figure 4 It is shown Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0067] refer to Figure 4 The storage block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the storage block BLKa, m cell strings are arranged along the row direction (i.e., the positive (+)X direction). Figure 4 In the diagram, two unit strings are shown arranged in the column direction (i.e., the positive (+)Y direction). However, this illustration is for clarity; three or more unit strings can be arranged in the column direction.

[0068] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a tube transistor PT, and at least one drain selection transistor DST.

[0069] The select transistors SST and DST, and the memory cells MC1 to MCn, can each have similar structures. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, pillars for providing the channel layer may also be provided to each cell string. In one embodiment, pillars for providing at least one of the channel layer, tunnel insulating layer, charge storage layer, and blocking insulating layer may be provided to each cell string.

[0070] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0071] In one implementation, source-select transistors in cell strings arranged in the same row are connected to source-select lines extending along the row direction, and source-select transistors in cell strings arranged in different rows are connected to different source-select lines. Figure 4 In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. In the second row, the source selection transistors of cell strings CS21 to CS2m are connected to the second source selection line SSL2.

[0072] In one implementation, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0073] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0074] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially along the negative (-)Z direction and connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially along the +Z direction and connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are interconnected via the transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0075] The gate of the tubular transistor PT in each unit string is connected to the pipeline PL.

[0076] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings in the row direction are connected to drain select lines extending along the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0077] The cells arranged along the column direction are connected in series to the bit lines extending along the column direction. Figure 4 In the first column, the cell strings CS11 and CS21 are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0078] Memory cells connected to the same word line in a cell string arranged along a row direction constitute a single page. For example, memory cells connected to the first word line WL1 of cell strings CS11 to CS1m in the first row constitute a single page. Memory cells connected to the first word line WL1 of cell strings CS21 to CS2m in the second row constitute a single supplementary page. A cell string arranged along a single row direction can be selected by selecting either the drain selection line DSL1 or DSL2. A single page can be selected from the selected cell string by selecting any of the word lines WL1 to WLn.

[0079] In one implementation, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Furthermore, the even-numbered cell strings in the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and the odd-numbered cell strings in the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0080] In one implementation, one or more of the first memory cells MC1 to the nth memory cell MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and memory cells MC1 to MCp. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and memory cells MCp+1 to MCn. Providing more dummy memory cells improves the operational reliability of the memory block BLKa, but increases the size of the memory block BLKa. Providing fewer memory cells reduces the size of the memory block BLKa, but may worsen its operational reliability.

[0081] To effectively control the one or more virtual memory cells, each virtual memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the virtual memory cells before or after the erase operation of the memory block BLKa. When an erase operation is performed after programming, the threshold voltage control of the virtual memory cells applies to the virtual word lines connected to each virtual memory cell, thus allowing the virtual memory cells to have the desired threshold voltage.

[0082] Figure 5 It is shown Figure 3 A circuit diagram of an implementation of any one of the storage blocks BLK1 to BLKz, BLKb.

[0083] refer to Figure 5 The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the positive Z (+Z) direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST, which are stacked on a substrate (not shown) beneath the memory block BLKb.

[0084] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In one embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be commonly connected to a single source select line.

[0085] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0086] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of the cell strings arranged along the row direction are connected to the drain select lines extending along the row direction.

[0087] The drain select transistors in the first row, cell string CS11' to CS1m', are connected to the first drain select line DSL1.

[0088] The drain select transistors in the second row, cell strings CS21' to CS2m', are connected to the second drain select line DSL2.

[0089] therefore, Figure 5 BLKb storage blocks have similar characteristics to Figure 4 The equivalent circuit of the storage block BLKa, except that each cell string does not include the tube transistor PT.

[0090] In one implementation, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Furthermore, the even-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction can be connected to the odd-numbered bit lines respectively.

[0091] In one implementation, one or more of the first memory cells MC1 to the nth memory cell MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. Providing more dummy memory cells improves the operational reliability of the memory block BLKb, but increases its size. Providing fewer memory cells reduces the size of the memory block BLKb, but may decrease its operational reliability.

[0092] To effectively control the one or more virtual memory cells, each virtual memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the virtual memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after programming, the threshold voltage control of the virtual memory cell applies to the virtual word line connected to the corresponding virtual memory cell, thus allowing the virtual memory cell to have the desired threshold voltage.

[0093] Figure 6 It is shown Figure 2 A circuit diagram of an implementation of any one of the storage blocks BLK1 to BLKz, BLKc, in the storage cell array 110.

[0094] refer to Figure 6The memory block BLKc includes multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm can be connected to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0095] The select transistors SST and DST can have similar structures to the memory cells MC1 to MCn. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In one embodiment, pillars for providing at least one of the channel layer, tunnel insulating layer, charge storage layer, and blocking insulating layer may be provided in each cell string.

[0096] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0097] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0098] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0099] Memory cells connected to the same word line can form a single page. Cell strings CS1 to CSm can be selected by choosing the drain selection line DSL. A page can be selected from the selected cell string by choosing any one of the word lines WL1 to WLn.

[0100] In other embodiments, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. In the unit strings CS1 to CSm, the even-numbered unit strings can be connected to the even-numbered bit lines respectively, and the odd-numbered unit strings can be connected to the odd-numbered bit lines respectively.

[0101] like Figures 3 to 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array with a 3D structure. Furthermore, as... Figure 6 As shown, the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array with a 2D structure.

[0102] Figure 7 This is a graph showing the threshold voltage distribution of a three-layer cell (TLC). (Reference) Figure 7The threshold voltage distribution of the TLC and the read levels R1 to R7 used to read the threshold voltage distribution are shown. Figure 7 The diagram depicts multiple bit data corresponding to the erase state E and the first programming states P1 through P7, respectively. The specific logic code shown is exemplary; the specific bit set specifying each state may differ from... Figure 7 The difference is shown.

[0103] refer to Figure 7 The memory cell storing bit "1 1 1" in the MSB-CSB-LSB sequence is maintained in the erase state E. The memory cell storing bit "1 1 0" is programmed to the first programming state P1. Thus, the memory cells storing bits "0 1 0", "0 0 0", "1 00", "1 0 1", "0 0 1", and "0 1 1" are programmed to any of the second programming states P2 to the seventh programming states P7. To distinguish the threshold voltage state of the corresponding memory cell, the first read level R1 to the seventh read level R7 can be used.

[0104] refer to Figure 7 To read data from an MSB page, the threshold voltage of the memory cell should be sensed at the second read level 2, the fourth read level 4, and the sixth read level 6. To read data from a CSB page, the threshold voltage of the memory cell should be sensed at the third read level 3 and the seventh read level 7. To read data from an LSB page, the threshold voltage of the memory cell should be sensed at the first read level R1 and the fifth read level R5.

[0105] To determine whether all memory cells in the selected physical page are in the erase state E, an LSB read operation can be performed as an implementation. For example, when all bits in the LSB page data are "1" as a result of an LSB read operation using the first read level R1 and the fifth read level R5, the corresponding physical page can be determined to be an erase page (i.e., a page in the erase state). When both "0" and "1" bits coexist in the LSB page data as a result of an LSB read operation using the first read level R1 and the fifth read level R5, the corresponding physical page can be determined to be a programming page (i.e., a page in the programming state).

[0106] Figure 8 This is a block diagram illustrating a storage system 1001 according to one embodiment of the present disclosure. (See reference...) Figure 8 The storage system 1001 may include a first semiconductor storage device 101 to a fourth semiconductor storage device 104 and a controller 201. Each of the first semiconductor storage devices 101 to the fourth semiconductor storage device 104 can be configured in a manner similar to... Figure 2The semiconductor memory device 100 is constructed in such a manner. The first semiconductor memory device 101 to the fourth semiconductor memory device 104 can be connected to the controller 201 via one or more channels. Although in Figure 8 The first semiconductor memory device 101 to the fourth semiconductor memory device 104 are shown connected to the controller 201 via a single channel, but the first semiconductor memory device 101 to the fourth semiconductor memory device 104 may alternatively be connected to the controller 201 via two to four channels. In some embodiments, the controller 201 may include a block status table 211. The block status table 211 may indicate the status of multiple memory blocks in each of the first semiconductor memory devices 101 to the fourth semiconductor memory devices 104. The block status table 211 may be stored in volatile memory (e.g., static random access memory (SRAM) or dynamic random access memory (DRAM)) in the controller 201. When the memory system 1001 is started, the controller 201 may scan the current of multiple memory blocks in the first semiconductor memory devices 101 to the fourth semiconductor memory devices 104 to determine the status of the corresponding memory blocks, construct the block status table 211 based on the scanned status, and then store the block status table 211 in memory (e.g., SRAM or DRAM) in the controller 201.

[0107] Figure 9A and Figure 9B A cell string including memory cells in a programmed state and a cell string including memory cells in an erased state are shown. Figure 10 This is a diagram used to explain the cell current flowing through a cell string that includes memory cells in the programming state and a cell string that includes memory cells in the erasure state. (Reference) Figure 9A This illustrates a string of cells within a programmable memory block. A string of cells in a programmable memory block comprises multiple programmable memory cells. When a read voltage is applied to the selected word line and a read pass voltage is applied to the unselected word line, the cell current ICELL flowing through the programmable memory cell can have a relatively low value. (Reference) Figure 9B The diagram illustrates a string of cells in an erased memory block. The string of cells in the erased memory block is in a state where all memory cells have been erased. When a read voltage is applied to the selected word line and a read pass voltage is applied to the unselected word line, the cell current ICELL flowing through the string of cells including those in the erased state can have a relatively high value because the threshold voltage of the erased memory cells has a relatively low value, and the read pass voltage or read voltage has a relatively high value.

[0108] Therefore, as Figure 10As shown, the cell current ICELL caused by a read operation on a cell string where all cells have been erased is greater than the current caused by a read operation on a cell string where all cells have been programmed. In other words, during the startup of the memory system 1001, the current consumption when a read operation is performed on a memory block in the erased state is greater than the current consumption when a read operation is performed on a memory block in the programmed state. Figure 8 As shown, when the storage system 1001 includes a plurality of storage devices 101 to 104 and simultaneously performs erase block scan operations on a plurality of storage blocks in the plurality of storage devices 101 to 104, high peak currents may occur.

[0109] Figure 11 This is a timing diagram illustrating an erase block scan operation using LSB read operations. Figure 11 In the process, the first chip CHIP1 to the fourth chip CHIP4 can respectively correspond to Figure 8 The first semiconductor memory device 101 to the fourth semiconductor memory device 104.

[0110] refer to Figure 11 During the erase block scan operation, LSB read operations (i.e., read operations on the least significant bit (LSB) page) can be performed. See the reference above. Figure 7 The LSB read operation can use a first read level 1 and a fifth read level 5. When performing an erase block scan operation using the LSB read operation, the maximum current consumed by each chip can be, for example, 200mA. When the maximum current allowed in the design of the storage system 1001 is 400mA, it is not possible to perform erase block scan operations on the first chip CHIP1 to the fourth chip CHIP4 simultaneously. In one embodiment, as... Figure 11 As shown, erase block scan operations can be performed on the first chip CHIP1 and the second chip CHIP2 during the time period t0 to t1, and erase block scan operations can be performed on the third chip CHIP3 and the fourth chip CHIP4 during the time period t2 to t3. Through this operation, the internal current consumption ICC of the storage system 1001 can be limited to a maximum of 400mA.

[0111] like Figure 11 As shown, when an LSB read operation is used in an erase block scan operation, the maximum current used for the erase block scan operation for each chip is relatively high. Therefore, in order to meet the permissible maximum current limit of the memory system 1001, erase block scan operations can be performed on multiple chips within two time intervals or time periods. In this case, the time required to perform the erase block scan operation increases, which becomes a factor leading to the deterioration of the operating performance of the memory system 1001.

[0112] According to one embodiment of this disclosure, the read operation in an erase block scan operation can be configured differently from a normal read operation. More specifically, an SLC read operation is used during the erase block scan operation. The SLC read operation used for the erase block scan operation uses a read level. The read level used in the SLC read operation used for the erase block scan operation is lower than the read level used in the SLC read operation used for a normal read operation. Therefore, the current used in the read operation performed on the erase block can be reduced, thereby reducing the maximum current consumed by each semiconductor memory device in the erase block scan operation. Therefore, the number of semiconductor memory devices capable of performing erase block scan operations simultaneously can be increased, and in this case, the time required to perform the erase block scan operation can be reduced. Therefore, the operating performance of the memory system 1001 can be improved.

[0113] Figure 12 This is a diagram used to explain the SLC read operation used in an erase block scan operation according to one embodiment of the present disclosure. Figure 13 This is a diagram used to explain the cell current flowing through the cell string during an SLC read operation according to one embodiment of this disclosure. (Reference) Figure 12 Similar to Figure 7 The graph shows the threshold voltage distribution of a three-layer cell (TLC). According to one embodiment of this disclosure, even an SLC read operation can be used in the erase block scan operation of a semiconductor memory device including a three-layer cell. For this operation, the SLC read level R is used. SLC A read operation is performed on the selected memory block to distinguish between memory cells in the erase state E and memory cells in the first programming state P1 to the seventh programming state P7. For example... Figure 12 As shown, the SLC read level R SLC It is a relatively small value, so the cell current ICELL flowing through the cell string, including memory cells in the erase state, can be relatively low. Therefore, as Figure 13 As shown, the difference between the cell current ICELL caused by a read operation on a cell string where all cells are programmed and the cell current ICELL caused by a read operation on a cell string where all cells are erased is not significant. In other words, the current consumed when performing a read operation on a memory block in an erased state during the startup of the memory system 1001 can be reduced relative to the cell current when performing a read operation on a programmed cell.

[0114] Although it has been referenced Figure 12SLC read operations on memory blocks comprising three-level cells (TLC) are described, but this disclosure is not limited thereto. For example, based on SLC read operations, erase block scan operations can even be performed on memory blocks comprising multi-level cells (MLC), four-level cells (QLC), or memory cells used to store 5 or more bits of data.

[0115] Figure 14 This is a timing diagram illustrating an erase block scan operation using an SLC read operation according to one embodiment of the present disclosure. Figure 14 In the process, the first chip CHIP1 to the fourth chip CHIP4 can respectively correspond to Figure 8 The first semiconductor memory device 101 to the fourth semiconductor memory device 104.

[0116] refer to Figure 14 According to one embodiment of this disclosure, the SLC read operation can be used in an erase block scan operation. (See above reference...) Figure 12 The SLC read operation can use the SLC read level R. SLC When using SLC read operations for erase block scan operations, the current consumed by erasing blocks can be reduced. Therefore, the maximum current consumed by each chip during an SLC read operation can be, for example, 100mA. When the maximum current allowed in the design of the storage system 1001 is 400mA, erase block scan operations can be performed simultaneously on the first chip CHIP1 through the fourth chip CHIP4. In one embodiment, as... Figure 14 As shown, during the time period from t4 to t5, erase block scan operations can be performed on the first chip CHIP1 to the fourth chip CHIP4. This operation minimizes the time period from t4 to t5 for performing erase block scan operations during startup, while limiting the internal current consumption (ICC) of the storage system 1001 to a maximum of 400mA or less. Therefore, the time required for erase block scan operations can be reduced, thereby improving the operational performance of the storage system 1001.

[0117] Figure 15 This is a flowchart illustrating an operation method of a controller according to one embodiment of the present disclosure. (Reference) Figure 15 The controller can perform operation S100 to sense the power-on state of the storage system 1001. Furthermore, the controller can perform operation S200 to perform an erase block scan operation on multiple storage blocks in the semiconductor storage device using a scan read voltage. When the storage system switches from an off state to an on state, the controller can sense that the storage system is powered on. In response to this sensing, the controller can begin the operation of starting the storage system.

[0118] During the startup of the storage system, the controller can use a scan read voltage at operation S200 to perform an erase block scan operation on multiple storage blocks in the semiconductor storage device. The scan read voltage can be combined with... Figure 12 The SLC read level R shown in the figure SLC They are essentially the same. In one implementation, the scan read voltage can be a read level used to distinguish between the erase state E of the memory cell and the remaining states (i.e., programming states P1 to P7). See below for reference. Figure 16 A detailed implementation of operation S200 is described.

[0119] Figure 16 It is shown Figure 15 A flowchart of one implementation of operation S200.

[0120] refer to Figure 16 , Figure 15 Operation S200 may include operations S210 to S270. Operation S210 may include selecting a memory block from a plurality of memory blocks that have not yet undergone a scan operation to perform a read operation based on the SLC read scheme. Operation S230 may include controlling the semiconductor memory device to perform an SLC read operation on the selected memory block using a scan read voltage. Operation S250 may include updating the block state of the selected memory block based on the result of the SLC read operation. Operation S270 may include determining whether erase block scans on all blocks have been completed.

[0121] In operation S210, a memory block that has not yet undergone an erase block scan operation is selected from a plurality of memory blocks in the semiconductor memory device. In operation S230, using Figure 12 The SLC read level R shown in the figure SLC An SLC read operation is performed on the selected memory block. Furthermore, at step S230, the block state of the selected memory block can be determined. At operation S250, the block state of the selected memory block is updated based on the result of the SLC read operation. Specifically, at operation S250, the block state can be updated... Figure 8 Block status table 211. When it is determined at operation S270 that the erase block scan operation on all memory blocks has been completed (S270, Yes), operation S200 is terminated. When it is determined at operation S270 that the erase block scan operation on all memory blocks has not been completed (S270, No), the process returns to operation S210, which selects memory blocks from the plurality of memory blocks in the semiconductor memory device that have not yet undergone the erase block scan operation, and then repeats operations S230 to S250.

[0122] Figure 17 It is shown Figure 16 A flowchart of one implementation of operation S230. Figures 18A to 18CThis is a diagram showing memory blocks in erase, programmed, and open states. See below for reference. Figure 17 as well as Figures 18A to 18C describe Figure 16 One implementation of operation S230.

[0123] refer to Figure 17 In operation S231, data stored in the pages of the selected storage block is read sequentially. Since a storage block consists of multiple physical pages, the current state of the storage block can be determined by verifying whether the data is stored in multiple physical pages.

[0124] refer to Figures 18A to 18C The embodiment illustrates a storage block comprising 16 physical pages, Page1 to Page16. Figures 18A to 18C In the diagram, pages in the erased state without stored data are represented by white areas, while pages in the programmed state with stored data are represented by shaded areas.

[0125] refer to Figure 18A In this context, all physical pages within a storage block are erased pages, meaning they contain no stored data. This indicates that all storage units within the storage block are in an erased state E, such as... Figure 12 The state within. Therefore, Figure 18A The storage block shown is in an erased state.

[0126] refer to Figure 18B In a storage block, all physical pages are programmable pages, which store data. This means that all storage units in the storage block are evenly distributed. Figure 12 The erase state E and the first programming state P1 to the seventh programming state P7. Therefore, Figure 18B The storage block shown is in a programmed state.

[0127] refer to Figure 18C As can be seen, among all the physical pages of the storage block, pages 1 through 9 are programming pages containing data, while pages 10 through 16 are erased pages without data. This means that the corresponding storage block is an open block, indicating that at least one page is an erased page that can store data.

[0128] Back Figure 17At operation S231, a scan read voltage is used to read physical pages in the memory block. When data is stored in a physical page, as a result of the read operation using the scan read voltage, bits 0 and 1 can coexist in the read data. In this case, the corresponding physical page is identified as a programming page. When no data is stored in a physical page, as a result of the read operation using the scan read voltage, only bits "1" can be included in the read data. In this case, the corresponding physical page is identified as an erase page.

[0129] At operation S233, the read data is analyzed, and corresponding operations are performed based on the analysis results. When it is determined that all pages in the corresponding storage block are erase pages, at operation S237, the selected storage block is determined to be an erase block. When it is determined that all pages in the corresponding storage block are programmable pages, at operation S239, the selected storage block is determined to be a programmable block. When it is determined that the corresponding storage block contains both erase pages and programmable pages, at operation S235, the selected storage block is determined to be an open block.

[0130] Figure 19 This is a block diagram illustrating a storage system 1003 according to one embodiment of the present disclosure. The storage system 1003 may include a controller 203 and first semiconductor storage devices 101 to fourth semiconductor storage devices 104. The controller 203 may store a block status table 213. During a block erase scan operation of the storage system 1003, the controller 203 may generate an SLC read command RCMD. SLC The generated command is then transmitted to the first semiconductor memory device 101 through the fourth semiconductor memory device 104. During normal read operations of the memory system 1003, the controller 203 can generate a normal read command RCMD. NRM The generated command is then transmitted to a semiconductor memory device selected from the first semiconductor memory device 101 to the fourth semiconductor memory device 104. Each of the first semiconductor memory device 101 to the fourth semiconductor memory device 104 can perform a read operation according to the type of the received read command. For example, when any of the first semiconductor memory device 101 to the fourth semiconductor memory device 104 receives the SLC read command RCMD... SLC At that time, the SLC read command RCMD had been received. SLC The semiconductor memory device can use a scan read voltage to read selected physical pages. In one embodiment, when any of the first semiconductor memory device 101 to the fourth semiconductor memory device 104 receives a normal read command RCMD... NRM When (e.g., an LSB read command) is received, the semiconductor memory device that receives the LSB read command can use... Figure 7The first read level R1 and the fifth read level R5 shown in the figure are used to read the selected physical page. See below for reference. Figure 20 A method of operating a semiconductor memory device according to one embodiment of the present disclosure is described.

[0131] Figure 20 This is a flowchart illustrating an operation method of a semiconductor memory device according to one embodiment of the present disclosure.

[0132] refer to Figure 20 In operation S310, the semiconductor memory device receives a read command from the controller 203. In operation S330, the semiconductor memory device checks the type of the received read command. Here, the semiconductor memory device can be... Figure 19 Any of the first semiconductor memory device 101 to the fourth semiconductor memory device 104 shown. When the received read command is an SLC read command RCMD SLC At operation S350, the semiconductor memory device uses a scan read voltage to read data from the physical page corresponding to the read command. Subsequently, at operation S390, the read data is transferred to the controller. In this case, the read data can be used to identify whether the corresponding page is an erase page or a programming page, rather than user data that has already been actually received from the host and stored in the semiconductor memory device.

[0133] When the received read command is a normal read command RCMD NRM At operation S370, the semiconductor memory device uses a normal read voltage set to read data from the physical page corresponding to the read command. The normal read voltage set may include at least one read level for reading data from the corresponding page in response to the read command. When the memory cell in the semiconductor memory device is a TLC, the normal read command may be at least one of an LSB read command, a CSB read command, and an MSB read command.

[0134] For example, when the semiconductor memory device receives an LSB read command from the controller, it performs a read operation at operation S370 using a first read level R1 and a fifth read level R5 corresponding to the normal read voltage set for reading LSB page data. When the semiconductor memory device receives a CSB read command from the controller, it performs a read operation at operation S370 using a third read level R3 and a seventh read level R7 corresponding to the normal read voltage set for reading CSB page data. When the semiconductor memory device receives an MSB read command from the controller, it performs a read operation at operation S370 using a second read level R2, a fourth read level R4, and a sixth read level R6 corresponding to the normal read voltage set for reading MSB page data. In this case, the read data can be user data actually received from the host and stored in the semiconductor memory device.

[0135] Subsequently, the semiconductor memory device transmits the read data to the controller at operation S390.

[0136] Figure 21 It shows including Figure 2 Block diagram of a storage system 1000 for a semiconductor storage device 100.

[0137] refer to Figure 21 The storage system 1000 may include a semiconductor storage device 100 and a controller 1100. The semiconductor storage device 100 may be a reference... Figure 2 The aforementioned semiconductor memory device.

[0138] Controller 1100 is connected to both the host and the semiconductor storage device 100. Controller 1100 can access the semiconductor storage device 100 in response to requests from the host. For example, controller 1100 can control read, write, erase, and background operations of the semiconductor storage device 100. Controller 1100 provides an interface between the semiconductor storage device 100 and the host. Controller 1100 can run firmware for controlling the semiconductor storage device 100.

[0139] The controller 1100 includes random access memory (RAM) 1110, a processor 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: working memory of the processor 1120, cache memory between the semiconductor storage device 100 and the host, and buffer memory between the semiconductor storage device 100 and the host. The processor 1120 can control the overall operation of the controller 1100. Furthermore, the controller 1100 can temporarily store programming data provided from the host during write operations.

[0140] The host interface 1130 includes protocols for exchanging data between the host and the controller 1100. In one embodiment, the controller 1100 may communicate with the host using at least one of various interface protocols, such as the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-express (PCI-e or PCIe) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Electronic Integrated Drive (IDE) protocol, and / or proprietary protocols.

[0141] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface may include a NAND interface or a NOR interface.

[0142] Error correction block 1150 can use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. In one embodiment, the error correction block can be provided as an element of controller 1100.

[0143] The controller 1100 and the semiconductor storage device 100 can be integrated into a single semiconductor device. In one embodiment, the controller 1100 and the semiconductor storage device 100 can be integrated into a single semiconductor device to form a memory card, such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash Card (CF), a Smart Media Card (e.g., SM or SMC), a Memory Stick, a Multimedia Card (e.g., MMC, RS-MMC, or MMCmicro), a Secure Digital (SD) Card (e.g., SD, miniSD, microSD, or SDHC), or Universal Flash Memory (UFS).

[0144] In another embodiment, the controller 1100 and the semiconductor storage device 100 can be integrated into a single semiconductor device to form a solid-state drive (SSD). The SSD includes a storage device configured to store data in semiconductor memory. When the storage system 1000 is used as an SSD, the operating speed of the host connected to the storage system 1000 can be significantly improved.

[0145] In one embodiment, the storage system 1000 may provide one of various elements of an electronic device, such as a computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, network tablet, wireless telephone, mobile phone, smartphone, e-book, portable multimedia player (PMP), game console, navigation device, black box, digital camera, three-dimensional (3D) television, digital audio recorder, digital audio player, digital image recorder, digital image player, digital video recorder, digital video player, device capable of transmitting / receiving information in a wireless environment, one of various electronic devices forming a home network, one of various electronic devices forming a computer network, one of various electronic devices forming a telematics network, radio frequency identification (RFID) device, or one of various elements forming a computing system.

[0146] In one embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in types such as stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle wafer, wafer-scale wafer, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit package (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stacked package (WSP).

[0147] Figure 22 It is shown Figure 21 A block diagram illustrating the application implementation of the storage system.

[0148] refer to Figure 22 The storage system 2000 may include a semiconductor storage device 2100 and a controller 2200. The semiconductor storage device 2100 may include a plurality of semiconductor storage chips. The semiconductor storage chips are divided into multiple (e.g., k) groups.

[0149] exist Figure 22 The diagram illustrates k groups communicating with controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip can communicate with a reference... Figure 2 The semiconductor memory device 100 is constructed and operated in the same manner.

[0150] Each group can communicate with controller 2200 via a common channel. Controller 2200 may have a reference... Figure 21 The controller 1100 described has the same construction and can control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0151] Figure 23 It shows that it includes references Figure 22 Block diagram of the computing system 3000, which describes the storage system.

[0152] refer to Figure 23 The computing system 3000 includes a central processing unit (CPU) 3100, random access memory (RAM) 3200, user interface 3300, power supply 3400, system bus 3500 and storage system 2000.

[0153] The storage system 2000 is electrically connected to the CPU 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided by the user interface 3300 or processed by the CPU 3100 can be stored in the storage system 2000.

[0154] exist Figure 23 In the diagram, semiconductor memory device 2100 is shown connected to system bus 3500 via controller 2200. However, semiconductor memory device 2100 can be directly connected to system bus 3500. Here, the functions of controller 2200 can be executed by CPU 3100 and RAM 3200.

[0155] exist Figure 23 The provided reference is shown in the image. Figure 22 The storage system 2000 is described. However, the storage system 2000 can be referenced. Figure 21 The described storage system 1000 is replaced. In one embodiment, the computing system 3000 may include a reference... Figure 21 and Figure 22 The storage systems described are 1000 and 2000.

[0156] This disclosure provides a semiconductor memory device with improved operating speed, and provides a controller and a method for operating the semiconductor memory device and the controller.

[0157] While the invention has been shown and described in conjunction with various embodiments, those skilled in the art will recognize that various modifications can be made to any of the disclosed embodiments within the spirit and scope of this disclosure. The invention includes all such modifications falling within the scope of the claims.

[0158] Cross-references to related applications

[0159] This application claims priority to Korean Patent Application 10-2020-0119015, filed on September 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of operating a controller for a storage system, the controller controlling a semiconductor storage device comprising a plurality of storage blocks, the method comprising the following steps: Sensing the power-on state of the storage system; and Based on the sensing that the storage system is in the powered-on state, an erase block scan operation is performed on the plurality of storage blocks using a scan read voltage. Specifically, the erase block scanning operation determines whether each of the plurality of storage blocks is an erase block. Each storage unit in the plurality of storage blocks stores at least two bits of data, and The scan read voltage enables the erase state and programming state of the memory cell to be distinguished from each other.

2. The method according to claim 1, wherein, The steps of performing an erase block scan operation on the plurality of memory blocks using a scan read voltage include the following steps: Select from the plurality of storage blocks the storage blocks that have not yet undergone the erase block scan operation; Control the semiconductor memory device to perform a single-level cell (SLC) read operation on the selected memory block using the scan read voltage; and Based on the result of the SLC read operation, the block status of the selected storage block is updated.

3. The method according to claim 2, wherein, The steps of controlling the semiconductor memory device to perform the SLC read operation on the selected memory block using the scan read voltage include the following steps: Control the semiconductor memory device to sequentially read data stored in multiple pages of a selected memory block using the scan read voltage; and Analyze the data read.

4. The method according to claim 3, further comprising the following step: In response to the analysis result indicating that all pages in the selected memory block are programming pages, the selected memory block is determined as a programming block.

5. The method according to claim 3, further comprising the following step: In response to the analysis result indicating that all pages in the selected storage block are erased pages, the selected storage block is determined as an erase block.

6. The method according to claim 3, further comprising the following step: In response to the analysis results that the selected memory block includes both programming pages and erase pages, the selected block is determined to be an open block.

7. A method of operating a semiconductor memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of memory cells, each memory cell storing at least two bits of data, the method comprising the steps of: Receive read commands from the controller; Check the type of the received read command; as well as The data reading operation is performed on the page corresponding to the read command by selectively using either a scan read voltage or a normal read voltage set based on the type of the read command. Specifically, by using the scan read voltage to perform the data read operation on the page, it is determined whether each of the plurality of storage blocks is an erase block.

8. The method according to claim 7, further comprising: The read data is transmitted to the controller.

9. The method according to claim 7, wherein, The step of selectively using either a scan read voltage or a normal read voltage set to read data from the page corresponding to the read command based on the type of the read command includes the following steps: In response to the determination that the type of the read command is a single-level cell (SLC) read command, data is read from the page corresponding to the read command using the scan read voltage.

10. The method according to claim 9, wherein, The scan read voltage enables the erase state and at least one programming state of the memory cell to be distinguished from each other.

11. The method according to claim 7, wherein, The step of selectively using either a scan read voltage or a normal read voltage set to read data from the page corresponding to the read command based on the type of the read command includes the following steps: In response to the determination that the type of the read command is a normal read command, data is read from the page corresponding to the read command using the normal read voltage set.

12. The method according to claim 11, wherein, Each of the plurality of storage units stores two bits of data, and The normal read voltage set is at least one of a first read voltage set for reading the least significant bit (LSB) page data stored in the selected page and a second read voltage set for reading the most significant bit (MSB) page data stored in the selected page.

13. The method according to claim 11, wherein, Each of the plurality of storage units stores three bits of data, and The normal read voltage set is at least one of a first read voltage set for reading the least significant bit (LSB) page data stored in the selected page, a second read voltage set for reading the middle significant bit (CSB) page data stored in the selected page, and a third read voltage set for reading the most significant bit (MSB) page data stored in the selected page.

14. A storage system, the storage system comprising: A semiconductor memory device, the semiconductor memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of memory cells, each memory cell storing at least two bits of data; as well as A controller that controls the operation of the semiconductor memory device. The controller controls the semiconductor memory device to perform an erase block scan operation on the plurality of memory blocks in response to sensing the power-on state of the memory system. This scan read voltage allows for the differentiation between the erase and programming states of each memory cell. Specifically, the erase block scanning operation determines whether each of the plurality of storage blocks is an erase block.

15. The storage system according to claim 14, wherein, The controller controls the semiconductor memory device to perform the erase block scan operation by transmitting a single-layer cell (SLC) read command, which is different from a normal read command, to the semiconductor memory device.

16. The storage system according to claim 14, wherein, The controller selects a memory block from the plurality of memory blocks that has not yet undergone the erase block scan operation, sequentially generates a plurality of SLC read commands corresponding to a plurality of pages in the selected memory block, and transmits the SLC read commands to the semiconductor memory device.

17. The storage system according to claim 16, wherein, The controller updates the block status of the selected storage block based on read data received in response to the plurality of SLC read commands for the selected storage block.

18. The storage system according to claim 15, wherein, In response to the SLC read command, the semiconductor memory device reads data from the page corresponding to the SLC read command using the scan read voltage.

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