Semiconductor device and semiconductor memory device
By setting a barrier layer and a contact layer between the oxide semiconductor layer and the electrode, the problem of threshold voltage variation in oxide semiconductor transistors during heat treatment is solved, achieving high heat resistance and low contact resistance, making it suitable for switching transistors in dynamic random access memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2021-02-26
- Publication Date
- 2026-07-10
AI Technical Summary
Oxide semiconductor transistors are prone to threshold voltage fluctuations during heat treatment, resulting in insufficient heat resistance and affecting their application in dynamic random access memory.
A barrier layer and a contact layer are disposed between the oxide semiconductor layer and the electrode. The barrier layer contains specific metal elements and nitrogen and oxygen, and the contact layer contains specific metal oxides to suppress oxygen diffusion and reduce contact resistance.
It effectively suppressed the change in threshold voltage after heat treatment, improved the heat resistance of oxide semiconductor transistors, reduced contact resistance, and ensured the stability and performance of the device.
Smart Images
Figure CN114267728B_ABST
Abstract
Description
[0001] [Related Applications]
[0002] This application enjoys priority to Japanese Patent Application No. 2020-155888 (filed on September 16, 2020). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field
[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device. Background Technology
[0004] Oxide semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during disconnection. Therefore, for example, switching transistors using OSTs in memory cells of dynamic random access memory (DRAM) have been investigated.
[0005] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, they undergo heat treatment that accompanies the formation of the memory cells or wiring. Therefore, it is desirable to realize an oxide semiconductor transistor that exhibits less characteristic variation and high heat resistance even after heat treatment. Summary of the Invention
[0006] The present invention provides a semiconductor device and a semiconductor memory device with high heat resistance.
[0007] The semiconductor device of the embodiment includes: an oxide semiconductor layer; a gate electrode; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first electrode electrically connected to a first position in the oxide semiconductor layer; a second electrode electrically connected to a second position in the oxide semiconductor layer relative to the first position in a first direction; a first conductive layer disposed at at least one position between the oxide semiconductor layer and the first electrode, and between the oxide semiconductor layer and the second electrode, and containing at least one element selected from oxygen (O) and nitrogen (N), a first metal element, and a first element different from the first metal element; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, and containing a second element different from the first metal element and the first element, and oxygen (O); and the first direction position of the portion of the gate electrode facing the oxide semiconductor layer across the gate insulating layer is located between the first position and the second position. Attached Figure Description
[0008] Figure 1This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.
[0009] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.
[0010] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.
[0011] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.
[0012] Figure 5 This is a block diagram of the semiconductor memory device according to the fourth embodiment.
[0013] Figure 6 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fourth embodiment.
[0014] Figure 7 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fourth embodiment.
[0015] Figure 8 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the fourth embodiment.
[0016] Figure 9 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the fourth embodiment.
[0017] Figure 10 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Detailed Implementation
[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be referred to by the same reference numerals, and descriptions of components that have already been described once will be appropriately omitted.
[0019] In addition, for convenience, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" refers only to the relative positional relationship within the accompanying drawings and does not specify the positional relationship relative to gravity.
[0020] Qualitative and quantitative analyses of the chemical composition of the components of the semiconductor devices and semiconductor memory devices described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness of the components, the distance between components, and the crystal grain size of the semiconductor devices can be performed, for example, using a transmission electron microscope (TEM).
[0021] (First Embodiment)
[0022] The semiconductor device of the first embodiment includes: an oxide semiconductor layer; a gate electrode; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first electrode electrically connected to a first position in the oxide semiconductor layer; a second electrode electrically connected to a second position in the oxide semiconductor layer relative to the first position in a first direction; a first conductive layer disposed at at least one position between the oxide semiconductor layer and the first electrode, and between the oxide semiconductor layer and the second electrode, and containing a first metal element, a first element different from the first metal element, and at least one element selected from oxygen (O) and nitrogen (N); and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, and containing a second element different from the first metal element and the first element, and oxygen (O); the first position of the portion of the gate electrode facing the oxide semiconductor layer across the gate insulating layer is located between the first position and the second position.
[0023] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.
[0024] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 100 is a so-called bottom-gate transistor, with a gate electrode disposed on the lower side of the oxide semiconductor layer in which the channel is formed, and a source electrode and a drain electrode disposed on the upper side.
[0025] The transistor 100 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, a first insulating layer 24, and a second insulating layer 26.
[0026] Source electrode 16 is an example of the first electrode. Drain electrode 18 is an example of the second electrode. Barrier layer 20 is an example of the first conductive layer. Contact layer 22 is an example of the second conductive layer.
[0027] The oxide semiconductor layer 10 has a first region 10a, a second region 10b and a third region 10c.
[0028] In the oxide semiconductor layer 10, a channel is formed that serves as a current path when the transistor 100 is turned on. The direction in which electrons flow in the channel is called the channel length direction. Figure 1 The two arrows in the middle indicate the direction of the channel length.
[0029] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.
[0030] The oxide semiconductor layer 10 contains, for example, indium (In), gallium (Ga), and zinc (Zn). The total atomic ratio of indium, gallium, and zinc in the oxide semiconductor layer 10 is, for example, 90% or more. Furthermore, the total atomic ratio of indium, gallium, and zinc in the oxide semiconductor layer 10, excluding oxygen, is, for example, 90% or more. For example, the oxide semiconductor layer 10 does not contain any element other than oxygen that has a larger atomic ratio than any of indium, gallium, and zinc.
[0031] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. At least a portion of the third region 10c is disposed between the first region 10a and the second region 10b.
[0032] Region 10a functions as the source region of transistor 100, and region 10b functions as the drain region of transistor 100. Additionally, a channel is formed in region 10c when transistor 100 is turned on.
[0033] Region 10a and Region 10b are, for example, n-type semiconductors. The oxygen defect concentration in Region 10a and Region 10b is, for example, higher than the oxygen defect concentration in Region 10c. Oxygen defects in the oxide semiconductor layer 10 function as donors.
[0034] The n-type carrier concentration in region 10a and region 10b is, for example, higher than the n-type carrier concentration in region 10c. The resistance of region 10a and region 10b is, for example, lower than the resistance of region 10c.
[0035] The thickness of the oxide semiconductor layer 10 is, for example, 10 nm or more and 100 nm or less.
[0036] The oxide semiconductor layer 10 is formed, for example, by atomic layer deposition (ALD).
[0037] Gate electrode 12 is disposed on the underside of oxide semiconductor layer 10. Gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. Gate electrode 12 is, for example, tungsten (W). The gate length of gate electrode 12 is, for example, 20 nm or more and 100 nm or less.
[0038] A gate insulating layer 14 is disposed between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 is disposed between the third region 10c and the gate electrode 12.
[0039] The gate insulating layer 14 is, for example, an oxide or an oxide nitride. The gate insulating layer 14 is, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more but less than 10 nm.
[0040] Alternatively, an oxide layer (not shown) with a different material from the gate insulating layer 14 can be provided between the oxide semiconductor layer 10 and the gate insulating layer 14.
[0041] The source electrode 16 is electrically connected to the oxide semiconductor layer 10 at a first position. The first position is, for example, the position where the contact layer 22 between the source electrode 16 and the oxide semiconductor layer 10 is in contact with the oxide semiconductor layer 10.
[0042] The source electrode 16 is disposed on the upper side of the oxide semiconductor layer 10. The oxide semiconductor layer 10 is sandwiched between the gate electrode 12 and the source electrode 16.
[0043] The source electrode 16 is disposed on the upper side of the first region 10a. The source electrode 16 is electrically connected to the first region 10a, for example.
[0044] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, a metal having a different chemical composition from the barrier layer 20. The source electrode 16 contains, for example, tungsten (W) or molybdenum (Mo).
[0045] The concentration of the first metal element contained in the source electrode 16 is, for example, less than 1 atom%. The first metal element is a metal element contained in the barrier layer 20.
[0046] The drain electrode 18 is electrically connected to the oxide semiconductor layer 10 at the second position. The second position is, for example, the position where the contact layer 22 between the drain electrode 18 and the oxide semiconductor layer 10 is connected to the oxide semiconductor layer 10.
[0047] The second position is located relative to the first position along the length of the channel. The length of the channel is an example of the first direction.
[0048] The position of the portion of the gate electrode 12 facing the oxide semiconductor layer 10 across the gate insulating layer 14 in the channel length direction is located between the first position and the second position. In other words, taking into account the coordinate axis extending along the channel length direction, the coordinate value of the position of the portion of the gate electrode 12 facing the oxide semiconductor layer 10 across the gate insulating layer 14 in the channel length direction is a value between the coordinate value of the first position and the coordinate value of the second position.
[0049] The drain electrode 18 is disposed on the upper side of the oxide semiconductor layer 10. The oxide semiconductor layer 10 is sandwiched between the gate electrode 12 and the drain electrode 18.
[0050] The drain electrode 18 is disposed on the upper side of the second region 10b. The drain electrode 18 is electrically connected to the second region 10b.
[0051] The drain electrode 18 is, for example, a metal or a metal compound. The drain electrode 18 is, for example, a metal having a different chemical composition from the barrier layer 20. The drain electrode 18 contains, for example, tungsten (W) or molybdenum (Mo).
[0052] The concentration of the first metal element contained in the drain electrode 18 is, for example, less than 1 atomic percent. The first metal element is the metal element contained in the barrier layer 20.
[0053] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 20 is disposed between the first region 10a and the source electrode 16. The barrier layer 20 is, for example, in contact with the source electrode 16. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 towards the source electrode 16.
[0054] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 20 is disposed between the second region 10b and the drain electrode 18. The barrier layer 20 is, for example, in contact with the drain electrode 18. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 towards the drain electrode 18.
[0055] The barrier layer 20 contains a first metallic element, a first element different from the first metallic element, and at least one element selected from oxygen (O) and nitrogen (N). The first element may contain two or more elements.
[0056] The first metallic element is, for example, at least one element selected from the group consisting of titanium (Ti), silver (Ag), nickel (Ni), copper (Cu), and tantalum (Ta). Alternatively, the first element is, for example, at least one element selected from the group consisting of zinc (Zn), silicon (Si), aluminum (Al), tin (Sn), gallium (Ga), hafnium (Hf), lanthanum (La), and cerium (Ce).
[0057] The barrier layer 20 is, for example, an oxide, a nitride, or a nitrogen oxide.
[0058] The barrier layer 20 is, for example, an oxide containing titanium (Ti) as the first metal element and zinc (Zn) and silicon (Si) as the first elements.
[0059] The concentration of the first metallic element contained in the barrier layer 20 is, for example, more than 3 atomic percent and less than 30 atomic percent.
[0060] The thickness of the barrier layer 20 is, for example, greater than the thickness of the contact layer 22. The thicknesses of both the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.
[0061] The thickness of the barrier layer 20 is, for example, more than 1.5 times the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, more than 5 nm and less than 30 nm.
[0062] The barrier layer 20 is, for example, crystalline. The grain size of the barrier layer 20 is, for example, smaller than the grain size of the contact layer 22. The grain size of the barrier layer 20 and the contact layer 22 is, for example, represented by the median of the long axis of the grains.
[0063] The barrier layer 20 is, for example, amorphous.
[0064] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is disposed between the first region 10a and the source electrode 16. Additionally, the contact layer 22 is disposed between the second region 10b and the drain electrode 18.
[0065] Contact layer 22 is, for example, connected to barrier layer 20. Contact layer 22 is, for example, connected to oxide semiconductor layer 10. Contact layer 22 is, for example, connected to first region 10a. Contact layer 22 is, for example, connected to second region 10b.
[0066] Contact layer 22 has the function of reducing the resistance between the first region 10a and the source electrode 16. Contact layer 22 has the function of reducing the resistance between the second region 10b and the drain electrode 18.
[0067] Contact layer 22 contains a second element that is different from the first metal element and the first element. The second element may contain more than two elements.
[0068] The second element is, for example, at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd).
[0069] Contact layer 22 is, for example, a metal oxide.
[0070] Contact layer 22 may contain indium (In) and tin (Sn) as second elements. Contact layer 22 may be an oxide containing indium (In) and tin (Sn).
[0071] The thickness of the contact layer 22 is, for example, more than 1 nm and less than 10 nm.
[0072] Contact layer 22 is, for example, a crystalline material.
[0073] The first insulating layer 24 is disposed on the underside of the oxide semiconductor layer 10. The first insulating layer 24 is, for example, an oxide, a nitride, or an oxide oxynitride. The first insulating layer 24 is, for example, silicon oxide, silicon nitride, or silicon oxynitride.
[0074] The second insulating layer 26 is disposed on the upper side of the oxide semiconductor layer 10. The second insulating layer 26 is disposed between the source electrode 16 and the drain electrode 18.
[0075] The second insulating layer 26 electrically separates the source electrode 16 from the drain electrode 18. The second insulating layer 26 is, for example, an oxide, a nitride, or an oxynitride. The second insulating layer 26 is, for example, silicon oxide, silicon nitride, or silicon oxynitride.
[0076] The function and effects of the semiconductor device according to the first embodiment will be explained below.
[0077] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, the oxide semiconductor transistors undergo heat treatment that accompanies the formation of the memory cells or wiring. Due to this heat treatment, the threshold voltage of the oxide semiconductor transistor can sometimes vary.
[0078] The threshold voltage variation of an oxide semiconductor transistor (OST) is caused by oxygen escaping from the OST layer containing the channels to the source or drain electrode. This oxygen escape creates oxygen defects within the OST layer. These oxygen defects function as donors within the OST layer. Therefore, for example, in the case of an n-channel OST transistor, the threshold voltage of the OST transistor decreases.
[0079] The transistor 100 of the first embodiment has a barrier layer 20 for suppressing oxygen diffusion between the oxide semiconductor layer 10 and the source electrode 16, and between the oxide semiconductor layer 10 and the drain electrode 18. By providing the barrier layer 20, the escape of oxygen from the oxide semiconductor layer 10 to the source electrode 16 or the drain electrode 18 can be suppressed. Therefore, the fluctuation of the threshold voltage of the transistor 100 can be suppressed.
[0080] By including the first metal element, the resistivity of the barrier layer 20 is reduced, for example, compared to the case without the first metal element. Therefore, it is possible to suppress the increase in contact resistance caused by the barrier layer 20 being provided between the oxide semiconductor layer 10 and the source electrode 16 and between the oxide semiconductor layer 10 and the drain electrode 18.
[0081] The transistor 100 of the first embodiment has a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. By having the contact layer 22, for example, compared to the case where the barrier layer 20 is directly connected to the oxide semiconductor layer 10 without the contact layer 22, the contact resistance is reduced.
[0082] From the viewpoint of suppressing oxygen diffusion, the grain size of the barrier layer 20 is preferably small. From the viewpoint of suppressing oxygen diffusion, the grain size of the barrier layer 20 is preferably smaller than the grain size of the contact layer 22. Furthermore, from the viewpoint of suppressing oxygen diffusion, the barrier layer 20 is preferably amorphous.
[0083] From the perspective of inhibiting oxygen diffusion, the barrier layer 20 is preferably an oxide.
[0084] From the viewpoint of suppressing oxygen diffusion, the barrier layer 20 is preferably an oxide containing silicon (Si). That is, the first element is preferably silicon (Si).
[0085] Furthermore, from the viewpoint of suppressing oxygen diffusion, the barrier layer 20 is preferably an oxide containing silicon (Si) and zinc (Zn). That is, the first element is preferably silicon (Si) and zinc (Zn).
[0086] Furthermore, from the viewpoint of reducing the resistivity of the barrier layer 20, the barrier layer 20 preferably contains titanium (Ti). That is, the first metallic element is preferably titanium (Ti).
[0087] The thickness of the barrier layer 20 is preferably 5 nm to 30 nm, more preferably 8 nm to 20 nm. Exceeding the lower limit improves the oxygen diffusion suppression effect. Below the upper limit, the contact resistance decreases.
[0088] The thickness of the barrier layer 20 is preferably greater than the thickness of the contact layer 22. The thickness of the barrier layer 20 is preferably more than 1.5 times the thickness of the contact layer 22.
[0089] From the viewpoint of reducing the contact resistance between the oxide semiconductor layer 10 and the contact layer 22, the contact layer 22 is preferably a metal oxide. By making the contact layer 22 a metal oxide, it is possible to suppress the formation of high-resistivity reaction products between the oxide semiconductor layer 10 and the contact layer 22 due to heat treatment.
[0090] From the viewpoint of suppressing the formation of reaction products with high resistance, the second element is preferably at least one element contained in the oxide semiconductor layer 10.
[0091] From the viewpoint of reducing the contact resistance between the oxide semiconductor layer 10 and the contact layer 22, the contact layer 22 is preferably an oxide containing indium (In) and tin (Sn).
[0092] The thickness of the contact layer 22 is preferably 1 nm to 10 nm, more preferably 3 nm to 5 nm. By exceeding the lower limit, the contact resistance between the oxide semiconductor layer 10 and the contact layer 22 can be reduced. Therefore, the contact resistance is reduced.
[0093] Furthermore, by lowering the value below the upper limit, the resistance of the contact layer 22 itself can be reduced. Therefore, the contact resistance is reduced.
[0094] From the viewpoint of heat resistance and reduced resistance, the source electrode 16 and the drain electrode 18 are preferably metals containing tungsten (W) or molybdenum (Mo).
[0095] According to the first embodiment, the change in threshold voltage after heat treatment can be suppressed, thereby realizing an oxide semiconductor transistor with high heat resistance.
[0096] (Second Implementation)
[0097] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that it further includes a third conductive layer. This third conductive layer is disposed between the first electrode or the second electrode and the first conductive layer, and contains a first metal element, the concentration of which is higher than the concentration of the first metal element in the first conductive layer. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.
[0098] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.
[0099] The semiconductor device in the second embodiment is a transistor 200.
[0100] The transistor 200 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, a metal layer 23, a first insulating layer 24, and a second insulating layer 26.
[0101] Source electrode 16 is an example of the first electrode. Drain electrode 18 is an example of the second electrode. Barrier layer 20 is an example of the first conductive layer. Contact layer 22 is an example of the second conductive layer. Metal layer is an example of the third conductive layer.
[0102] The oxide semiconductor layer 10 has a first region 10a, a second region 10b and a third region 10c.
[0103] Metal layer 23 is disposed between source electrode 16 and barrier layer 20, and between drain electrode 18 and barrier layer 20. Metal layer 23 is, for example, connected to source electrode 16 and barrier layer 20. Metal layer 23 is, for example, connected to drain electrode 18 and barrier layer 20. Metal layer 23, for example, functions as a supply source for the first metal element contained in barrier layer 20 during the manufacture of transistor 200.
[0104] Metal layer 23 is metal. Metal layer 23 contains the first metallic element contained in barrier layer 20. The concentration of the first metallic element contained in metal layer 23 is higher than the concentration of the first metallic element contained in barrier layer 20. For example, the concentration of the first metallic element contained in metal layer 23 is 70 atomic percent to 100 atomic percent.
[0105] The first metallic element is, for example, at least one element selected from the group consisting of titanium (Ti), silver (Ag), nickel (Ni), copper (Cu) and tantalum (Ta).
[0106] Metal layer 23 is metal. Metal layer 23 may contain, for example, titanium (Ti). Metal layer 23 may be a titanium layer.
[0107] The thickness of the metal layer 23 is, for example, thinner than the thickness of the barrier layer 20. The thickness of the metal layer 23 is, for example, more than 1 nm and less than 10 nm.
[0108] The chemical composition of the barrier layer 20 differs from that of the source electrode 16 and the drain electrode 18. The concentration of the first metal element contained in the source electrode 16 and the drain electrode 18 is, for example, less than 1 atomic percent.
[0109] The transistor 200 of the second embodiment can easily introduce the first metal element into the barrier layer 20 by providing the metal layer 23.
[0110] According to the second embodiment, similar to the first embodiment, the change in threshold voltage after heat treatment can be suppressed, thereby realizing an oxide semiconductor transistor with high heat resistance.
[0111] (Third Implementation)
[0112] The semiconductor device of the third embodiment differs from that of the semiconductor device of the first embodiment in that the gate electrode surrounds the oxide semiconductor layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0113] Figure 3 , Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 4yes Figure 3 AA' sectional view. Figure 3 In this context, the horizontal direction is referred to as the first direction, the depth direction as the second direction, and the vertical direction as the third direction.
[0114] The semiconductor device in the third embodiment is a transistor 300. The transistor 300 is an oxide semiconductor transistor in which channels are formed in an oxide semiconductor. The transistor 300 is a so-called surrounding gate transistor (SGT) in which a gate electrode surrounds the oxide semiconductor layer in which the channels are formed. The transistor 300 is a so-called vertical transistor.
[0115] Transistor 300 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, and an interlayer insulating layer 32. The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer.
[0116] The oxide semiconductor layer 10 has a first region 10a, a second region 10b and a third region 10c.
[0117] An oxide semiconductor layer 10 is disposed between the source electrode 16 and the drain electrode 18. A channel is formed in the oxide semiconductor layer 10 that serves as a current path when the transistor 300 is turned on. The oxide semiconductor layer 10 extends in a third direction. The oxide semiconductor layer 10 is columnar and extends in the third direction. For example, the oxide semiconductor layer 10 is cylindrical.
[0118] The direction in which electrons flow in the channel is called the channel length direction. The third direction is the channel length direction of transistor 300.
[0119] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.
[0120] The oxide semiconductor layer 10 contains, for example, indium (In), gallium (Ga), and zinc (Zn). The total atomic ratio of indium, gallium, and zinc in the oxide semiconductor layer 10 is, for example, 90% or more. Furthermore, the total atomic ratio of indium, gallium, and zinc in the oxide semiconductor layer 10, excluding oxygen, is, for example, 90% or more. For example, the oxide semiconductor layer 10 does not contain any element other than oxygen that has a larger atomic ratio than any of indium, gallium, and zinc.
[0121] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. At least a portion of the third region 10c is disposed between the first region 10a and the second region 10b.
[0122] Region 10a functions as the source region of transistor 300, and region 10b functions as the drain region of transistor 300. Additionally, a channel is formed in region 10c when transistor 300 is turned on.
[0123] Region 10a and Region 10b are, for example, n-type semiconductors. The oxygen defect concentrations in Region 10a and Region 10b are, for example, higher than the oxygen defect concentration in Region 10c. Oxygen defects in the oxide semiconductor layer 10 function as donors.
[0124] The n-type carrier concentration in region 10a and region 10b is, for example, higher than the n-type carrier concentration in region 10c. The resistance of region 10a and region 10b is, for example, lower than the resistance of region 10c.
[0125] The width of the oxide semiconductor layer 10 in the first direction is, for example, 20 nm or more and 100 nm or less. The length of the oxide semiconductor layer 10 in the third direction is, for example, 80 nm or more and 200 nm or less.
[0126] The oxide semiconductor layer 10 is formed, for example, by the ALD method.
[0127] The gate electrode 12 is disposed surrounding the oxide semiconductor layer 10.
[0128] The gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 12 is, for example, tungsten (W). The gate length of the gate electrode 12 is, for example, 20 nm to 100 nm. The gate length of the gate electrode 12 is the length of the gate electrode 12 in the third direction.
[0129] A gate insulating layer 14 is disposed between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 surrounds the oxide semiconductor layer 10. The gate insulating layer 14 is disposed at least between the third region 10c and the gate electrode 12.
[0130] The gate insulating layer 14 is, for example, an oxide or an oxide nitride. The gate insulating layer 14 is, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more but less than 10 nm.
[0131] Alternatively, an oxide layer (not shown) with a different material from the gate insulating layer 14 can be provided between the oxide semiconductor layer 10 and the gate insulating layer 14.
[0132] The source electrode 16 is electrically connected to the oxide semiconductor layer 10 at a first position. The first position is, for example, the position where the contact layer 22 between the source electrode 16 and the oxide semiconductor layer 10 is connected to the oxide semiconductor layer 10.
[0133] The source electrode 16 is disposed on the underside of the oxide semiconductor layer 10. The source electrode 16 is disposed on the underside of the first region 10a. The source electrode 16 is electrically connected to the first region 10a.
[0134] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, tungsten (W) or molybdenum (Mo).
[0135] The drain electrode 18 is electrically connected to the oxide semiconductor layer 10 at the second position. The second position is, for example, the position where the contact layer 22 between the drain electrode 18 and the oxide semiconductor layer 10 is connected to the oxide semiconductor layer 10.
[0136] The second position is located along the length of the channel relative to the first position.
[0137] The position of the portion of the gate electrode 12 facing the oxide semiconductor layer 10 across the gate insulating layer 14 in the channel length direction is located between the first position and the second position. In other words, taking into account the coordinate axis extending along the channel length direction, the coordinate value of the position of the portion of the gate electrode 12 facing the oxide semiconductor layer 10 across the gate insulating layer 14 in the channel length direction is a value between the coordinate value of the first position and the coordinate value of the second position.
[0138] Drain electrode 18 is disposed on the upper side of oxide semiconductor layer 10. Drain electrode 18 is disposed on the upper side of second region 10b. Drain electrode 18 is electrically connected to second region 10b.
[0139] The drain electrode 18 is, for example, a metal or a metal compound. The source electrode 16 is, for example, tungsten (W) or molybdenum (Mo).
[0140] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 20 is disposed between the first region 10a and the source electrode 16. The barrier layer 20 is, for example, in contact with the source electrode 16. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 towards the source electrode 16.
[0141] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 20 is disposed between the second region 10b and the drain electrode 18. The barrier layer 20 is, for example, in contact with the drain electrode 18. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 towards the drain electrode 18.
[0142] The barrier layer 20 contains a first metallic element, a first element different from the first metallic element, and at least one element selected from oxygen (O) and nitrogen (N). The first element may contain two or more elements.
[0143] The first metallic element is, for example, at least one element selected from the group consisting of titanium (Ti), silver (Ag), nickel (Ni), copper (Cu), and tantalum (Ta). Alternatively, the first element is, for example, at least one element selected from the group consisting of zinc (Zn), silicon (Si), aluminum (Al), tin (Sn), gallium (Ga), hafnium (Hf), lanthanum (La), and cerium (Ce).
[0144] The barrier layer 20 is, for example, an oxide, a nitride, or a nitrogen oxide.
[0145] The barrier layer 20 is, for example, an oxide containing titanium (Ti) as the first metal element and zinc (Zn) and silicon (Si) as the first elements.
[0146] The concentration of the first metallic element contained in the barrier layer 20 is, for example, more than 3 atomic percent and less than 30 atomic percent.
[0147] The thickness of the barrier layer 20 is, for example, greater than the thickness of the contact layer 22. The thicknesses of both the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.
[0148] The thickness of the barrier layer 20 is, for example, more than 1.5 times the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, more than 5 nm and less than 30 nm.
[0149] The barrier layer 20 is, for example, crystalline. The grain size of the barrier layer 20 is, for example, smaller than the grain size of the contact layer 22. The grain size of the barrier layer 20 and the contact layer 22 is, for example, represented by the median of the long axis of the grains.
[0150] The barrier layer 20 is, for example, amorphous.
[0151] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is disposed between the first region 10a and the source electrode 16. Additionally, the contact layer 22 is disposed between the second region 10b and the drain electrode 18.
[0152] Contact layer 22 is, for example, connected to barrier layer 20. Contact layer 22 is, for example, connected to oxide semiconductor layer 10. Contact layer 22 is, for example, connected to first region 10a. Contact layer 22 is, for example, connected to second region 10b.
[0153] Contact layer 22 has the function of reducing the resistance between the first region 10a and the source electrode 16. Contact layer 22 has the function of reducing the resistance between the second region 10b and the drain electrode 18.
[0154] Contact layer 22 contains a second element that is different from the first metal element and the first element. The second element may contain more than two elements.
[0155] The second element is, for example, at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd).
[0156] Contact layer 22 is, for example, a metal oxide.
[0157] Contact layer 22 may contain indium (In) and tin (Sn) as second elements. Contact layer 22 may be an oxide containing indium (In) and tin (Sn).
[0158] The thickness of the contact layer 22 is, for example, more than 1 nm and less than 10 nm. The contact layer 22 is, for example, crystalline.
[0159] An interlayer insulating layer 32 is disposed around the gate electrode 12, the source electrode 16, and the drain electrode 18. The interlayer insulating layer 32 is, for example, an oxide, a nitride, or an oxide oxynitride. Alternatively, the interlayer insulating layer 32 may be silicon oxide, silicon nitride, or silicon oxynitride.
[0160] In addition, the same metal layer as that described in the second embodiment can be provided between the source electrode 16 and the barrier layer 20 and between the drain electrode 18 and the barrier layer 20.
[0161] As described above, according to the third embodiment, similar to the first embodiment, fluctuations in the threshold voltage after heat treatment can be suppressed, thereby realizing an oxide semiconductor transistor with high heat resistance. Furthermore, according to the third embodiment, since it is an SGT (Semiconductor Ground Tunnel), transistors can be configured at a higher density per unit area.
[0162] (Fourth implementation)
[0163] The semiconductor memory device of the fourth embodiment includes: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; and a memory cell; the memory cell includes: an oxide semiconductor layer electrically connected to the first wiring and surrounded by a portion of the second wiring; a gate insulating layer disposed between the oxide semiconductor layer and a portion of the second wiring; a capacitor electrically connected to the oxide semiconductor layer; a first conductive layer disposed at at least at any position between the oxide semiconductor layer and the first wiring, and between the oxide semiconductor layer and the capacitor, and containing a first metal element, a first element different from the first metal element, and at least one element selected from oxygen (O) and nitrogen (N); and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, and containing a second element different from the first metal element and the first element, and oxygen (O). Hereinafter, descriptions that are repeated in the first to third embodiments will sometimes be omitted.
[0164] The semiconductor memory device of the fourth embodiment is a semiconductor memory 400. The semiconductor memory device of the fourth embodiment is a dynamic random access memory (DRAM). The semiconductor memory 400 uses the transistor 300 of the third embodiment as a switching transistor for the memory cell of the DRAM.
[0165] Figure 5 This is a block diagram of the semiconductor memory device according to the fourth embodiment.
[0166] like Figure 5 As shown, the semiconductor memory 400 includes a memory cell array 210, a word line driving circuit 212, a row decoder circuit 214, a sense amplifier circuit 215, a column decoder circuit 217, and a control circuit 221.
[0167] Figure 6 , Figure 7 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fourth embodiment. Figure 6 It is a cross-sectional view of the plane including the first direction, which is the third direction. Figure 7 This is a cross-sectional view of a plane including the second and third directions. The first and second directions intersect. The first and second directions are, for example, perpendicular. The third direction is perpendicular to both the first and second directions. The third direction is, for example, perpendicular to the substrate.
[0168] The storage cell array 210 of the fourth embodiment has a three-dimensional structure in which storage cells are arranged in a three-dimensional manner. Figure 6 , Figure 7 The areas enclosed by dashed lines represent one storage unit each.
[0169] The memory cell array 210 has a silicon substrate 250.
[0170] The memory cell array 210 has, for example, multiple bit lines BL and multiple word lines WL on the silicon substrate 250. The bit lines BL extend in a first direction. The word lines WL extend in a second direction.
[0171] Bit line BL and word line WL intersect perpendicularly, for example. Memory cells are arranged in the area where bit line BL and word line WL intersect. Each memory cell contains a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 and the second memory cell MC2 are examples of memory cells.
[0172] The bit line BL connected to the first memory cell MC1 and the second memory cell MC2 is called bit line BLx. Bit line BLx is an example of the first wiring. The word line WL connected to the first memory cell MC1 is called word line WLx. Word line WLx is an example of the second wiring.
[0173] The word line WL connected to the second memory cell MC2 is designated as word line WLy. Word line WLx is configured on one side of bit line BLx. Word line WLy is configured on the other side of bit line BLx.
[0174] The memory cell array 210 has multiple plate-shaped electrode lines PL. The plate-shaped electrode lines PL are connected to the plate-shaped electrodes 72 of each memory cell.
[0175] The storage cell array 210 has an interlayer insulation layer 260 to electrically separate each wiring from each electrode.
[0176] Multiple word lines (WL) are electrically connected to the line decoder circuit 214. Multiple bit lines (BL) are electrically connected to the sense amplifier circuit 215.
[0177] The line decoder circuit 214 has the function of selecting word lines WL according to the input line address signal. The word line drive circuit 212 has the function of applying a specific voltage to the word lines WL selected by the line decoder circuit 214.
[0178] The column decoder circuit 217 has the function of selecting bit line BL according to the input column address signal. The sense amplifier circuit 215 has the function of applying a specific voltage to the bit line BL selected by the column decoder circuit 217. In addition, it has the function of detecting and amplifying the potential of the bit line BL.
[0179] The control circuit 221 has the functions of controlling word line drive circuit 212, row decoder circuit 214, sense amplifier circuit 215, column decoder circuit 217 and other circuits not shown.
[0180] The word line driver circuit 212, row decoder circuit 214, sense amplifier circuit 215, column decoder circuit 217, and control circuit 221, etc., may include transistors or wiring layers (not shown). The transistors are formed, for example, using a silicon substrate 250.
[0181] Bit lines BL and word lines WL are, for example, metallic. Bit lines BL and word lines WL are, for example, titanium nitride, tungsten, or a composite structure of titanium nitride and tungsten.
[0182] Figure 8 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the fourth embodiment. Figure 9 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the fourth embodiment.
[0183] The first memory cell MC1 is disposed between the silicon substrate 250 and the bit line BLx. The bit line BLx is disposed between the silicon substrate 250 and the second memory cell MC2.
[0184] The first memory cell MC1 is located below the bit line BLx. The second memory cell MC2 is located above the bit line BLx.
[0185] The first memory cell MC1 is located on one side of bit line BLx. The second memory cell MC2 is located on the other side of bit line BLx.
[0186] The second storage cell MC2 has a structure that inverts the first storage cell MC1. The first storage cell MC1 and the second storage cell MC2 each have a transistor 300 and a capacitor 201.
[0187] Transistor 300 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, and a contact layer 22. The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer. Transistor 300 has the same configuration as the transistor 300 of the third embodiment.
[0188] The oxide semiconductor layer 10 is electrically connected to the bit line BLx. The oxide semiconductor layer 10 is surrounded by a portion of the word line WL. The portion of the word line WL surrounding the oxide semiconductor layer 10 is the gate electrode 12.
[0189] The oxide semiconductor layer 10 has a first region 10a, a second region 10b and a third region 10c.
[0190] The capacitor 201 includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 and the plate electrode 72 are, for example, titanium nitride. In addition, the capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.
[0191] Capacitor 201 is electrically connected to one end of the oxide semiconductor layer 10 of the first memory cell MC1 and the second memory cell MC2. The cell electrode 71 of capacitor 201 is connected to the drain electrode 18. The plate electrode 72 is connected to the plate electrode line PL.
[0192] Source electrode 16 is connected to bit line BL. Gate electrode 12 is connected to word line WL. Gate electrode 12 is a part of word line WL.
[0193] also, Figure 6 , Figure 7 , Figure 8 , Figure 9 In the diagram, the bit line BL and the source electrode 16, and the word line WL and the gate electrode 12 are illustrated as being formed simultaneously from the same material. Alternatively, the bit line BL and the source electrode 16, and the word line WL and the gate electrode 12, can also be formed separately from different materials.
[0194] Bit line BLx is electrically connected to the end of the oxide semiconductor layer 10 of the first memory cell MC1 that is opposite to the end connected to the capacitor 201. Bit line BLx is also electrically connected to the end of the oxide semiconductor layer 10 of the second memory cell MC2 that is opposite to the end connected to the capacitor 201.
[0195] The gate electrode 12 of the first memory cell MC1 is electrically connected to the word line WLx. Additionally, the gate electrode 12 of the second memory cell MC2 is electrically connected to the word line WLy.
[0196] The transistor 300 has a barrier layer 20 between the oxide semiconductor layer 10 and the source electrode 16 and the drain electrode 18. In addition, a contact layer 22 is provided between the oxide semiconductor layer 10 and the barrier layer 20.
[0197] When using oxide semiconductor transistors (OSTs) as switching transistors in DRAM memory cells, a high-temperature and prolonged heat treatment is applied after the transistor is formed. This heat treatment is, for example, the heat treatment used to form a capacitor. Due to the high temperature and prolonged heat treatment, the threshold voltage of the OST is prone to variation.
[0198] The transistor 300 has a barrier layer 20 between the oxide semiconductor layer 10 and the source electrode 16 and drain electrode 18. Therefore, even if a high-temperature and long-term heat treatment is applied after the transistor is formed, the threshold voltage variation can be suppressed.
[0199] Furthermore, the transistor 300 has a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. Therefore, the contact resistance is reduced. Consequently, the conduction current of the transistor 300 increases.
[0200] According to the fourth embodiment, by using the transistor 300 of the third embodiment as the switching transistor of the DRAM, the fluctuation of the threshold voltage after heat treatment can be suppressed, thereby realizing a semiconductor memory with high heat resistance.
[0201] (Fifth Embodiment)
[0202] The semiconductor device of the fifth embodiment includes: an oxide semiconductor layer; an electrode; a first conductive layer disposed between the oxide semiconductor layer and the electrode, and containing a first metal element, a first element different from the first metal element, and at least one element selected from oxygen (O) and nitrogen (N); and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, and containing a second element different from the first metal element and the first element, and oxygen (O). Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.
[0203] Figure 10 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.
[0204] The semiconductor device of the fifth embodiment includes a contact structure 500. The contact structure 500 includes an oxide semiconductor layer 10, a barrier layer 20, a contact layer 22, a wiring layer 40, a contact plug 42, and an interlayer insulating layer 44. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer. The contact plug 42 is an example of an electrode.
[0205] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.
[0206] The oxide semiconductor layer 10 contains, for example, indium (In), gallium (Ga), and zinc (Zn). The atomic ratio of indium, gallium, and zinc in the first metal element contained in the oxide semiconductor layer 10 is, for example, 90% or more. Furthermore, the atomic ratio of indium, gallium, and zinc in the elements other than oxygen contained in the oxide semiconductor layer 10 is, for example, 90% or more. For example, in the oxide semiconductor layer 10, there are no elements other than oxygen that have an atomic ratio greater than any of indium, gallium, and zinc.
[0207] Wiring layer 40 is, for example, metal or metal compound.
[0208] Contact plug 42 is disposed between oxide semiconductor layer 10 and wiring layer 40. Contact plug 42 contains metal. Contact plug 42 is, for example, a metal or metal compound. Contact plug 42 is, for example, tungsten (W) or molybdenum (Mo).
[0209] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the contact plug 42. The barrier layer 20 is, for example, in contact with the contact plug 42. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 to the contact plug 42 side.
[0210] The barrier layer 20 contains a first metallic element, a first element different from the first metallic element, and at least one element selected from oxygen (O) and nitrogen (N). The first element may contain two or more elements.
[0211] The first metallic element is, for example, at least one element selected from the group consisting of titanium (Ti), silver (Ag), nickel (Ni), copper (Cu), and tantalum (Ta). Alternatively, the first element is, for example, at least one element selected from the group consisting of zinc (Zn), silicon (Si), aluminum (Al), tin (Sn), gallium (Ga), hafnium (Hf), lanthanum (La), and cerium (Ce).
[0212] The barrier layer 20 is, for example, an oxide, a nitride, or a nitrogen oxide.
[0213] The barrier layer 20 is, for example, an oxide containing titanium (Ti) as the first metal element and zinc (Zn) and silicon (Si) as the first elements.
[0214] The concentration of the first metallic element contained in the barrier layer 20 is, for example, more than 3 atomic percent and less than 30 atomic percent.
[0215] The thickness of the barrier layer 20 is, for example, greater than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the contact plug 42.
[0216] The thickness of the barrier layer 20 is, for example, more than 1.5 times the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, more than 5 nm and less than 30 nm.
[0217] The barrier layer 20 is, for example, crystalline. The grain size of the barrier layer 20 is, for example, smaller than the grain size of the contact layer 22. The grain size of the barrier layer 20 and the contact layer 22 is, for example, represented by the median of the long axis of the grains.
[0218] The barrier layer 20 is, for example, amorphous.
[0219] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is, for example, in contact with the barrier layer 20. The contact layer 22 is, for example, in contact with the oxide semiconductor layer 10.
[0220] The contact layer 22 has the function of reducing the resistance between the oxide semiconductor layer 10 and the contact plug 42.
[0221] Contact layer 22 contains a second element that is different from the first metal element and the first element. The second element may contain more than two elements.
[0222] The second element is, for example, at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd).
[0223] Contact layer 22 is, for example, a metal oxide.
[0224] Contact layer 22 may contain indium (In) and tin (Sn) as second elements. Contact layer 22 may be an oxide containing indium (In) and tin (Sn).
[0225] The thickness of the contact layer 22 is, for example, more than 1 nm and less than 10 nm. The contact layer 22 is, for example, crystalline.
[0226] An interlayer insulating layer 44 is disposed between the oxide semiconductor layer 10 and the wiring layer 40. The interlayer insulating layer 44 is, for example, silicon oxide, silicon nitride, or silicon oxynitride.
[0227] In the absence of a barrier layer 20 in the contact structure 500, the contact plug 42 is oxidized due to the heat treatment applied after the formation of the contact structure 500. That is, oxygen contained in the oxide semiconductor layer 10 diffuses to the contact plug 42, causing the metal constituting the contact plug 42 to oxidize and form a metal oxide layer.
[0228] By forming a metal oxide layer between the oxide semiconductor layer 10 and the contact plug 42, the contact resistance between the oxide semiconductor layer 10 and the contact plug 42 is increased.
[0229] The contact structure 500 has a barrier layer 20 between the oxide semiconductor layer 10 and the contact plug 42. By having the barrier layer 20, oxidation of the contact plug 42 can be suppressed. Therefore, the increase in contact resistance between the oxide semiconductor layer 10 and the contact plug 42 can be suppressed.
[0230] Furthermore, the contact structure 500 has a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. Therefore, the contact resistance between the oxide semiconductor layer 10 and the contact plug 42 is reduced.
[0231] In addition, a metal layer identical to the metal layer described in the second embodiment can be provided between the contact plug 42 and the barrier layer 20.
[0232] According to the fifth embodiment, the increase in contact resistance after heat treatment can be suppressed, thereby realizing a semiconductor device with high heat resistance.
[0233] In the first to fourth embodiments, a transistor with a barrier layer 20 and a contact layer 22 disposed at two locations: between the first region 10a and the source electrode 16, and between the second region 10b and the drain electrode 18, was described as an example. However, the barrier layer 20 and the contact layer 22 may also be disposed at any location between the first region 10a and the source electrode 16, and between the second region 10b and the drain electrode 18.
[0234] In embodiments 1 to 5, the case where the oxide semiconductor layer 10 is a metal oxide containing indium (In), gallium (Ga) and zinc (Zn) was described as an example, but other metal oxides can also be used in the oxide semiconductor layer 10.
[0235] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified to be constituent elements of other embodiments. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the claims and their equivalents.
[0236] [Explanation of Symbols]
[0237] 10: Oxide semiconductor layer
[0238] 10a: Region 1
[0239] 10b: Area 2
[0240] 10c: Region 3
[0241] 12: Gate electrode
[0242] 14: Gate insulating layer
[0243] 16: Source electrode (Electrode 1)
[0244] 18: Drain electrode (second electrode)
[0245] 20: Barrier layer (first conductive layer)
[0246] 22: Contact layer (second conductive layer)
[0247] 23: Metal layer (third conductive layer)
[0248] 42: Contact plug (conductive layer)
[0249] 100: Transistor (semiconductor device)
[0250] 200: Transistor (semiconductor device)
[0251] 201: Capacitor
[0252] 300: Transistor (semiconductor device)
[0253] 400: Semiconductor memory (semiconductor storage device)
[0254] BLx: Bit line (first wiring)
[0255] MC1: First storage unit (storage unit)
[0256] WLx: Word line (second wiring).
Claims
1. A semiconductor device, characterized in that... include: Oxide semiconductor layer; Gate electrode; A gate insulating layer is disposed between the oxide semiconductor layer and the gate electrode; The first electrode is electrically connected to the first position of the oxide semiconductor layer; The second electrode is electrically connected to the oxide semiconductor layer at a second position relative to the first position in the first direction; The first conductive layer is disposed at at least at any position between the oxide semiconductor layer and the first electrode, and between the oxide semiconductor layer and the second electrode, and contains at least any element selected from oxygen and nitrogen, a first metal element, and a first element different from the first metal element; as well as A second conductive layer is disposed between the oxide semiconductor layer and the first conductive layer, and contains a second element different from the first metal element and the first element, as well as oxygen; and The position of the portion of the gate electrode that faces the oxide semiconductor layer across the gate insulating layer in the first direction is located between the first position and the second position; The first metallic element is selected from at least one element chosen from the group consisting of titanium, silver, nickel, copper and tantalum; The first element is selected from at least one element in the group consisting of zinc, silicon, aluminum, tin, gallium, hafnium, lanthanum and cerium; The thickness of the first conductive layer is greater than the thickness of the second conductive layer.
2. The semiconductor device according to claim 1, characterized in that: The second element is selected from at least one element chosen from the group consisting of indium, zinc, tin and cadmium.
3. The semiconductor device according to claim 1, characterized in that: The first electrode and the second electrode are metals having a different chemical composition than the first conductive layer.
4. The semiconductor device according to claim 1, characterized in that: The first electrode and the second electrode contain tungsten or molybdenum.
5. The semiconductor device according to claim 1, characterized in that: The oxide semiconductor layer contains indium, gallium, and zinc.
6. The semiconductor device according to claim 1, characterized in that... Also includes: The third conductive layer is disposed between the first electrode or the second electrode and the first conductive layer, and contains the first metal element, wherein the concentration of the first metal element is higher than the concentration of the first metal element in the first conductive layer.
7. The semiconductor device according to claim 1, characterized in that: The grain size of the first conductive layer is smaller than that of the second conductive layer.
8. The semiconductor device according to claim 1, characterized in that: The first conductive layer is amorphous.
9. The semiconductor device according to claim 1, characterized in that: The gate electrode surrounds the oxide semiconductor layer.
10. A semiconductor memory device, characterized in that... include: The first wiring extends in the first direction; The second wiring extends in a second direction that intersects the first direction; as well as Storage unit; The storage unit includes: An oxide semiconductor layer, electrically connected to the first wiring, is surrounded by a portion of the second wiring; A gate insulating layer is disposed between the oxide semiconductor layer and a portion of the second wiring; A capacitor is electrically connected to the oxide semiconductor layer; A first conductive layer, disposed at at least at any location between the oxide semiconductor layer and the first wiring, and between the oxide semiconductor layer and the capacitor, contains at least one element selected from oxygen and nitrogen, a first metal element, and a first element different from the first metal element; and The second conductive layer is disposed between the oxide semiconductor layer and the first conductive layer, and contains a second element different from the first metal element and the first element, as well as oxygen; The first metallic element is selected from at least one element chosen from the group consisting of titanium, silver, nickel, copper and tantalum; The first element is selected from at least one element in the group consisting of zinc, silicon, aluminum, tin, gallium, hafnium, lanthanum and cerium; The thickness of the first conductive layer is greater than the thickness of the second conductive layer.
11. The semiconductor memory device according to claim 10, characterized in that: The second element is selected from at least one element chosen from the group consisting of indium, zinc, tin and cadmium.
12. A semiconductor device, characterized in that... include: Oxide semiconductor layer; electrode; A first conductive layer is disposed between the oxide semiconductor layer and the electrode, and contains at least one element selected from oxygen and nitrogen, a first metal element, and a first element different from the first metal element; as well as The second conductive layer is disposed between the oxide semiconductor layer and the first conductive layer, and contains a second element different from the first metal element and the first element, as well as oxygen; The first metallic element is selected from at least one element chosen from the group consisting of titanium, silver, nickel, copper and tantalum; The first element is selected from at least one element in the group consisting of zinc, silicon, aluminum, tin, gallium, hafnium, lanthanum and cerium; The thickness of the first conductive layer is greater than the thickness of the second conductive layer.
13. The semiconductor device according to claim 12, characterized in that: The second element is selected from at least one element chosen from the group consisting of indium, zinc, tin and cadmium.