Embedded substrate for electronic components

Abstract

This disclosure provides an embedded substrate for electronic components, the embedded substrate for electronic components comprising: a wiring structure including a plurality of insulating layers and a plurality of wiring layers and having a cavity penetrating at least one of the plurality of insulating layers; a first electronic component disposed in the cavity; a dam structure disposed on the wiring structure and having a through portion; a first insulating material disposed in at least a portion of each of the cavity and the through portion and covering at least a portion of each of the wiring structure and the first electronic component; and a first circuit layer disposed on the first insulating material.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0118805, filed on September 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to an embedded substrate for electronic components. Background Technology

[0003] As electronic devices used in the information technology (IT) field (including mobile phones) have become lighter and thinner, there is a need for technologies to insert electronic components (such as integrated circuits (ICs)) into printed circuit boards (PCBs) in response to technological demands. Technologies using various methods to embed electronic components into PCBs are being developed. Consequently, various cavity structures are formed within the PCB. Summary of the Invention

[0004] An exemplary embodiment provides an electronic component embedded substrate with reduced thickness, wherein the electronic component can be embedded in a cavity with its face facing upward.

[0005] An exemplary embodiment provides an embedded substrate for an electronic component, wherein microcircuit regions can be locally applied to the electronic component.

[0006] For example, an embedded substrate for electronic components is provided by positioning a dam structure with a through portion on a wiring structure with a cavity, positioning the electronic component in the cavity, filling the cavity and through portion with an insulating material having excellent flow properties, and forming a circuit layer on the insulating material.

[0007] For example, an embedded substrate for an electronic component includes: a wiring structure including a plurality of insulating layers and a plurality of wiring layers and having a cavity penetrating at least one of the plurality of insulating layers; a first electronic component disposed in the cavity; a dam structure disposed above the wiring structure and having a through portion; a first insulating material disposed in at least a portion of each of the cavity and the through portion, and covering at least a portion of each of the wiring structure and the first electronic component; and a first circuit layer disposed on the first insulating material.

[0008] According to an exemplary embodiment, an embedded substrate for an electronic component includes: a wiring structure including an insulating layer and a wiring layer disposed on and / or in the insulating layer and having a cavity, the cavity having a bottom surface; an electronic component having one surface and another surface opposite to the one surface, and disposed such that the other surface faces the bottom surface of the cavity, the one surface having a connection pad disposed thereon; a dam structure disposed above the wiring structure and having a through portion, the area of ​​the through portion being larger than the area of ​​the cavity in a plane; and a circuit structure disposed in the through portion and including an insulating material and a circuit layer, the electronic component being embedded in the insulating material, the circuit layer being disposed on the insulating material. At least a portion of the wiring layer and at least a portion of the connection pad are connected to each other through at least a portion of the circuit layer.

[0009] According to an exemplary embodiment, an embedded substrate for an electronic component includes: a wiring structure including a plurality of insulating layers and a plurality of wiring layers; a first electronic component attached to the wiring structure; a dam structure disposed above the wiring structure and having a through portion; an insulating material disposed in the through portion and covering at least a portion of each of the wiring structure and the first electronic component; and a circuit layer disposed on the insulating material.

[0010] According to an exemplary embodiment, an embedded substrate for an electronic component includes: a wiring structure including a plurality of insulating layers and a plurality of wiring layers and having a cavity penetrating at least a portion of the plurality of insulating layers; a first electronic component disposed in the cavity; a dam structure disposed above the wiring structure and having a through portion; a first insulating material disposed in at least a portion of each of the cavity and the through portion, and covering at least a portion of each of the wiring structure and the first electronic component; and a first circuit layer disposed within the dam structure on the first insulating material and electrically connecting the first electronic component to the uppermost wiring layer of the plurality of wiring layers. Attached Figure Description

[0011] The above and other aspects, features and advantages of the present invention will be more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0012] Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system;

[0013] Figure 2 It is a perspective view schematically illustrating an example of an electronic device;

[0014] Figure 3 This is a schematic cross-sectional view showing an example of an embedded substrate for electronic components;

[0015] Figure 4 It is along Figure 3 A schematic plan view of the cross-section of the embedded substrate of the electronic component, taken by line I-I'.

[0016] Figure 5 It is shown schematically. Figure 3 A plan view of a partial area of ​​the first circuit layer of the circuit structure of an embedded substrate for electronic components;

[0017] Figure 6 It is shown schematically. Figure 3 A partial plan view of the second wiring layer of the wiring structure of the embedded substrate of electronic components;

[0018] Figure 7 and Figure 8 It is a schematic representation of manufacturing. Figure 3 A process diagram of an example of an embedded substrate for electronic components;

[0019] Figure 9 This is a schematic cross-sectional view showing another example of an embedded substrate for electronic components;

[0020] Figure 10 It is along Figure 9 A schematic plan view of the cross-section of the embedded substrate of the electronic component, taken by line II-II' in the figure;

[0021] Figure 11 This is a schematic cross-sectional view showing another example of an embedded substrate for electronic components;

[0022] Figure 12 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components;

[0023] Figure 13 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components;

[0024] Figure 14 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components;

[0025] Figure 15 This is a schematic cross-sectional view showing another example of an embedded substrate for electronic components; and

[0026] Figure 16 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components. Detailed Implementation

[0027] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various variations, modifications, and equivalents of the methods, apparatus, and / or systems described herein will be readily apparent to those skilled in the art. The order of operations described herein is merely illustrative and is not limited to the order presented, but rather, changes that will be readily apparent to those skilled in the art may be made, except for operations that necessarily occur in a particular order. Furthermore, for clarity and brevity, descriptions of functions and constructions that are well-known to those skilled in the art may be omitted.

[0028] The features described herein may be implemented in various forms and are not to be construed as being limited to the examples described herein. Rather, the examples provided herein make this disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0029] Here, it should be noted that the use of the term "may" in relation to embodiments or examples (e.g., what an example or embodiment may include or implement) means that there exists at least one embodiment or example that includes or implements such a feature, and is not limited to all examples and embodiments including or implementing such a feature.

[0030] Throughout the specification, when an element (such as a layer, region, or substrate) is described as being "on" another element, "connected" to another element, or "bonded" to another element, the element may be directly "on" said other element, directly "connected" to said other element, or directly "bonded" to said other element, or there may be one or more other elements in between. In contrast, when an element is described as being "directly on" another element, "directly connected" to another element, or "directly bonded" to another element, there are no other elements in between.

[0031] As used herein, the term “and / or” includes any one or any combination of two or more of the relevant listed items.

[0032] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Thus, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0033] For ease of description, spatial relative terms such as “above,” “above,” “below,” and “under” are used herein to describe the relationship between one element and another as shown in the accompanying drawings. Such spatial relative terms are intended to encompass not only the orientation depicted in the drawings but also different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as being “above” or “above” relative to another element will then be “below” or “under” relative to said other element. Thus, the term “above” encompasses both above and below orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing various examples only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms “comprising,” “including,” and “having” enumerate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0035] Due to manufacturing techniques and / or tolerances, variations in the shapes shown in the accompanying drawings may occur. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

[0036] The features of the examples described herein can be combined in various ways that will be apparent upon understanding the disclosure of this application. Furthermore, while the examples described herein have various constructions, other constructions that will be apparent upon understanding the disclosure of this application are possible.

[0037] In the following description, embodiments will be illustrated with reference to the accompanying drawings. In the drawings, the shape and size of the elements may be exaggerated or reduced for clarity.

[0038] Figure 1 This is a schematic block diagram illustrating an example of an electronic device system.

[0039] Reference Figure 1 The electronic device 1000 can house the motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 can be physically or electrically connected to the motherboard 1010. These components can be connected to other components described below via various signal lines 1090.

[0040] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.); application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these, and may include other types of chip-related components in addition to these. Furthermore, chip-related components 1020 can be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips.

[0041] Network-related components 1030 may include components that are compatible with or operate using protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the protocols listed above. However, the network-related component 1030 is not limited to this, but may also include components that are compatible with or operate using various other wireless or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the aforementioned chip-related component 1020 and disposed in a package.

[0042] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these, and may also include passive devices in the form of chip assemblies for various other purposes. Furthermore, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030, and may be provided in package form.

[0043] Depending on the type of electronic device 1000, it may include other electronic components that are physically or electrically connected to the motherboard 1010 or not physically or electrically connected to the motherboard 1010. For example, these other electronic components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), optical disc (CD) drives, digital versatile optical disc (DVD) drives, etc. Furthermore, electronic device 1000 may also include other electronic components for various purposes, depending on the type of electronic device 1000.

[0044] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0045] Figure 2 This is a schematic perspective view showing an example of an electronic device.

[0046] Reference Figure 2 The electronic device can be, for example, a smartphone 1100. For instance, a motherboard 1110 can be housed in the smartphone 1100, and various components 1120 can be physically and / or electrically connected to the motherboard 1110. Additionally, a camera module 1130 and / or a speaker 1140, etc., can be housed in the smartphone 1100. Some of the components 1120 can be chip-related components, such as, but not limited to, a semiconductor package 1121. The semiconductor package 1121 can be a package in which semiconductor chips are disposed on a multilayer printed circuit board in a surface-mount manner, but is not limited to this. The electronic device is not limited to the smartphone 1100, but can be other electronic devices as described above.

[0047] Figure 3 This is a schematic cross-sectional view showing an example of an embedded substrate for electronic components.

[0048] Figure 4 It shows along Figure 3 A schematic plan view of the cross-section of the embedded substrate of the electronic component, taken by line I-I'.

[0049] Figure 5 It is shown schematically. Figure 3 A plan view of a partial area of ​​the first circuit layer of the circuit structure of an embedded substrate for electronic components.

[0050] Figure 6 It is shown schematically. Figure 3 A plan view of a partial area of ​​the second wiring layer of the wiring structure of an embedded substrate for electronic components.

[0051] Reference Figures 3 to 6 The example electronic component embedded substrate 100A may include: a wiring structure 110 having a cavity 110H; an electronic component 120 (also referred to as a first electronic component 120) disposed in the cavity 110H; a dam structure 130 disposed on the wiring structure 110 and having a through portion 130H; and a circuit structure 140 disposed on the electronic component 120 in the wiring structure 110 and the through portion 130H. The circuit structure 140 may include: a first insulating material 141a filling at least a portion of each of the cavity 110H and the through portion 130H and covering at least a portion of each of the wiring structure 110 and the electronic component 120; and a first circuit layer 142a disposed on the first insulating material 141a.

[0052] On the other hand, as mentioned above, technologies for embedding electronic components into printed circuit boards (PCBs) in various ways have recently been developed, resulting in various cavity structures within the PCBs. For example, a structure is provided as an example where a cavity is formed in the PCB, bump pads are formed in the internal region of the cavity, and the die is mounted face down. In this case, a barrier is needed to prevent damage to the bump pads during cavity formation. Furthermore, the increased number of wiring beneath the die increases the number of substrate layers, making it difficult to reduce thickness. Additionally, when multiple dies are mounted, the paths for interconnecting between dies are lengthened, and circuit density can become complex. Moreover, there are some difficulties in handling microcircuits. Additionally, since the back surface of the die is only covered by molding material, heat dissipation efficiency is relatively low.

[0053] Furthermore, in the case of the example electronic component embedded substrate 100A, after the electronic component 120 is disposed in the cavity 110H of the wiring structure 110, the cavity 110H and the through-hole 130H are filled with a first insulating material 141a having excellent flowability using a dam structure 130 having a through-hole 130H, and a first circuit layer 142a is formed on the first insulating material 141a. Therefore, no bump pads are needed in the internal region of the cavity 110H, and when the electronic component 120 is a bare die, the electronic component can be mounted face up. In addition, since the overall number of wiring layers can be reduced, it is also advantageous for thinning. Furthermore, when multiple bare dies are mounted, since they can be interconnected through the circuit structure 140, the interconnection paths can be reduced and the circuit density can be simplified. Furthermore, the circuit structure 140 can be manufactured by performing a plating process on an insulating material with excellent flow properties. This insulating material (e.g., photosensitive dielectric (PID) or Ajinomoto build-up film (ABF), etc., including inorganic fillers and insulating resin but excluding glass fibers) can be used in processes that facilitate the formation of microcircuits (e.g., photolithography or semi-additive process (SAP)). Therefore, the circuit structure 140 is easily implemented as a microcircuit. As a result, microcircuits can be easily and locally implemented on the electronic component 120.

[0054] On the other hand, the dam structure 130 can be configured to surround the cavity 110H in a plane. The through portion 130H can expose the cavity 110H. For example, the through portion 130H can have a larger area in the plane than the area of ​​the cavity 110H. The dam structure 130 can be continuously configured to stably form the circuit structure 140. The dam structure 130 can have a quadrilateral ring shape in the plane, but its shape is not limited to this and can have other ring shapes. In one example, the plane can refer to a plane parallel to the upper surface of the wiring structure 110. The dam structure 130 can include a solder resist (SR) as a photosensitive dielectric material, and in this case, the through portion 130H can be formed more easily by a photolithography process.

[0055] On the other hand, the wiring structure 110 may include multiple insulating layers 111a and 111b and multiple wiring layers 112a, 112b and 112c. The cavity 110H can penetrate at least one of the multiple insulating layers 111a and 111b. A barrier layer (e.g., a metal layer M) may be disposed on the bottom surface of the cavity 110H, thus the cavity 110H can be easily fabricated, and the electronic component 120 can be easily disposed on the metal layer M in an upward-facing manner using an adhesive member A or the like. Furthermore, heat can be easily radiated to the underside of the electronic component 120 through the metal layer M. The metal layer M and any one of the multiple wiring layers 112a, 112b and 112c may be formed together by a plating process and may be located at the same height. For example, the metal layer M may be formed together with the second wiring layer 112b by a plating process to be located at the same height. For example, the barrier layer may be formed without using additional processes.

[0056] At least a portion of at least one of the plurality of wiring layers 112a, 112b, and 112c of the wiring structure 110 (e.g., at least a portion of the third wiring layer 112c) can be electrically connected via at least a portion of the first circuit layer 142a to at least one of the plurality of connection pads 120P (also referred to as first connection pads 120P) disposed on the top surface of the electronic assembly 120. For example, at least one connection pad of the plurality of connection pads 120P of the electronic assembly 120 and at least a portion of the third wiring layer 112c are electrically connected to at least a portion of the first circuit layer 142a via a first connection via V1 and a second connection via V2 penetrating at least a portion of the first insulating material 141a, respectively. Therefore, the electronic assembly 120 and the third wiring layer 112c can be electrically connected to each other via the first circuit layer 142a.

[0057] On the other hand, the wiring structure 110 may further include: a first passivation layer 115a disposed above the uppermost second insulating layer 111b among the plurality of insulating layers 111a and 111b; and a second passivation layer 115b disposed below the lowermost first insulating layer 111a among the plurality of insulating layers 111a and 111b. The first passivation layer 115a may have an opening 115ah1, which exposes at least a portion of the uppermost third wiring layer 112c among the plurality of wiring layers 112a, 112b and 112c. The opening 115ah1 may be located in a through-hole 130H in a plane. Therefore, the first insulating material 141a may fill at least a portion of the opening 115ah1. The second connection via V2 may penetrate the first insulating material 141a in the opening 115ah1 to electrically connect to at least a portion of the third wiring layer 112c.

[0058] On the other hand, the first circuit layer 142a of the circuit structure 140 can be thinner than at least one of the plurality of wiring layers 112a, 112b, and 112c of the wiring structure 110, and the pitch between the patterns of the first circuit layer 142a can be relatively smaller than the pitch between the patterns of the at least one wiring layer. For example, when the thickness of the first circuit layer 142a is t1 and the thickness of the second wiring layer 112b is t2, t1 < t2 can be satisfied. In addition, when the pitch between the patterns of the first circuit layer 142a is P1 and the pitch between the patterns of the second wiring layer 112b is P2, P1 < P2 can be satisfied. For example, a high-density microcircuit with a relatively finer pitch can be provided.

[0059] On the other hand, the circuit structure 140 can be configured as a multi-layer. For example, the circuit structure 140 can further include: a second insulating material 141b disposed on the first insulating material 141a and covering at least a part of the first circuit layer 142a within the through-hole portion 130H; and a second circuit layer 142b disposed on the second insulating material 141b. Similar to the first insulating material 141a, the second insulating material 141b can include an insulating material with good fluidity, such as PID or ABF. Similar to the first circuit layer 142a, the second circuit layer 142b can be thinner than at least one of the plurality of wiring layers 112a, 112b, and 112c of the wiring structure 110, and can have a relatively finer pitch between the patterns of the second circuit layer 142b. For example, a high-density microcircuit with a relatively finer pitch can be provided.

[0060] If necessary, the exemplary electronic component-embedded substrate 100A can further include a cover layer 150 disposed on the circuit structure 140 to cover at least a part of each of the wiring structure 110, the dam structure 130, and the circuit structure 140. Additionally, the electronic component-embedded substrate 100A can further include an electrically connecting metal member 160 disposed under the wiring structure 110 and electrically connected to the lowermost first wiring layer 112a among the plurality of wiring layers 112a, 112b, and 112c.

[0061] Hereinafter, each configuration included in the exemplary electronic component-embedded substrate 100A will be described in more detail with reference to the drawings.

[0062] The wiring structure 110 may include multiple insulating layers 111a and 111b and multiple wiring layers 112a, 112b and 112c, and has a cavity 110H penetrating at least one of the multiple insulating layers 111a and 111b. The wiring structure 110 may also include multiple wiring via layers 113a and 113b and / or multiple passivation layers 115a and 115b. For example, the wiring structure 110 may include: a first insulating layer 111a; a first wiring layer 112a embedded in the underside of the first insulating layer 111a and having a lower surface exposed from the lower surface of the first insulating layer 111a; a second wiring layer 112b disposed on the upper surface of the first insulating layer 111a; a first wiring via layer 113a penetrating at least a portion of the first insulating layer 111a and connecting the first wiring layer 112a and the second wiring layer 112b; and a second insulating layer 111b disposed on the upper surface of the first insulating layer 111a and covering the second wiring layer 112b. At least a portion of the second insulating layer 111b includes: a third wiring layer 112c disposed on the upper surface of the second insulating layer 111b; a second wiring via layer 113b penetrating at least a portion of the second insulating layer 111b and connecting the second wiring layer 112b and the third wiring layer 112c; a first passivation layer 115a disposed above the second insulating layer 111b; and a second passivation layer 115b disposed below the first insulating layer 111a. The wiring structure 110 may have a cavity 110H that penetrates at least a portion of each of the second insulating layer 111b and the first passivation layer 115a.

[0063] The insulating material can be used as the material for the multiple insulating layers 111a and 111b, and thermosetting resins (such as epoxy resins) or thermoplastic resins (such as polyimide), as well as materials in which these resins are mixed with inorganic fillers (such as silica) and / or reinforcing materials (such as glass fiber), can be used as the insulating material. For example, prepreg (PPG) can be used as the material for each of the multiple insulating layers 111a and 111b. The multiple insulating layers 111a and 111b can be stacked in a coreless manner. For example, the multiple insulating layers 111a and 111b can have approximately the same thickness, but their structure is not limited to this.

[0064] Metallic materials can be used as the materials for the multiple wiring layers 112a, 112b, and 112c, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as metallic materials. Each of the multiple wiring layers 112a, 112b, and 112c can perform various functions according to the design. For example, the multiple wiring layers 112a, 112b, and 112c may include ground patterns, power patterns, signal patterns, etc. In this case, signal patterns include various signal patterns other than ground patterns and power patterns, such as data signal patterns. Each of these patterns may have a line shape, a surface shape, or a pad shape. The multiple wiring layers 112a, 112b, and 112c can be formed by plating processes (such as modified SAP (MSAP), via sealing (TT) processes, etc.), so the multiple wiring layers 112a, 112b, and 112c may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer. A particular layer may also include copper foil.

[0065] On the other hand, the lower surface of the first wiring layer 112a and the lower surface of the first insulating layer 111a may have a step difference. For example, the lower surface of the first wiring layer 112a may be located at a height higher than the lower surface of the first insulating layer 111a. Additionally, the upper surface of the metal layer M may have a step. For example, the thickness of the metal layer M in the region exposed to the cavity 110H may be thinner than its thickness in the region covering the second insulating layer 111b. These step characteristics can be provided by the characteristics of the process forming the wiring structure 110 and the cavity 110H.

[0066] Metallic materials can be used as the materials for the multiple wiring via layers 113a and 113b, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as metallic materials. Depending on the design, each of the multiple wiring via layers 113a and 113b may include signal connection vias, ground connection vias, power connection vias, etc. Each of the wiring vias in the multiple wiring via layers 113a and 113b may be a filled via where the via is filled with metallic material, or it may be a conformal via where metallic material is formed along the wall surface of the via. Additionally, the wiring vias may have a tapered shape in the same direction. The multiple wiring via layers 113a and 113b can be formed by a plating process (e.g., MSAP or TT process), therefore, the multiple wiring via layers 113a and 113b may include a seed layer as an electroless plating layer and an electrolytic plating layer formed based on the seed layer.

[0067] Multiple passivation layers 115a and 115b protect the internal structure of the wiring structure 110 from external physical and chemical damage. The multiple passivation layers 115a and 115b may respectively cover at least a portion of the third wiring layer 112c and at least a portion of the first wiring layer 112a, and may respectively have openings exposing at least a portion of the third wiring layer 112c and at least a portion of the first wiring layer 112a. An insulating material may also be used as the material for the multiple passivation layers 115a and 115b. In this case, the insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material in which such resins are mixed with inorganic fillers (e.g., ABF), but this disclosure is not limited thereto. For example, SR as a photosensitive dielectric material may be used.

[0068] Electronic component 120 can be disposed in cavity 110H. Electronic component 120 can be an IC in which hundreds to millions of devices are integrated into a single chip. For example, electronic component 120 can be a processor chip such as a central processing unit (e.g., central processing unit (CPU)), a graphics processing unit (e.g., graphics processing unit (GPU)), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. Specifically, electronic component 120 can be an application processor (AP), but is not limited thereto. In addition, electronic component 120 can be a memory such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.), or it can be a logic chip (e.g., an analog-to-digital converter (ADC), an application-specific integrated circuit (ASIC)), etc. Electronic component 120 can be a chip passive component, such as a chip inductor or a chip capacitor. Optionally, electronic component 120 can be a combination of IC and chip passive components, and in this case, cavity 110H can be configured as multiple cavities.

[0069] Electronic component 120 can be arranged with its face upward, such that the surface on which the connection pad 120P is disposed is positioned facing the circuit structure 140. Electronic component 120 can be attached to the bottom surface of cavity 110H via an adhesive member A (such as die attachment film (DAF)). Connection pad 120P can comprise a metallic material (such as copper (Cu) or aluminum (Al)). Connection pad 120P can be configured to protrude from the insulating body of electronic component 120, or alternatively, connection pad 120P can be configured to be embedded in the insulating body of electronic component 120. Metal bumps (such as copper bumps) can also be disposed on connection pad 120P.

[0070] The dam structure 130 can be configured to surround the cavity 110H in a plane. The through portion 130H can expose the cavity 110H. For example, the through portion 130H can have an area larger than the area of ​​the cavity 110H in a plane. The dam structure 130 can be continuously arranged, thus allowing the circuit structure 140 to be stably formed. The dam structure 130 can have a quadrilateral annular shape in a plane, but its shape is not limited to this, and it can have other annular shapes. The dam structure 130 can include SR as a photosensitive dielectric material, but its material is not limited to this.

[0071] The circuit structure 140 may include one or more insulating materials 141a and 141b and one or more circuit layers 142a and 142b, and may also include one or more connection via layers 143a and 143b. For example, the circuit structure 140 may include: a first insulating material 141a; a first circuit layer 142a disposed on the first insulating material 141a; a first connection via layer 143a penetrating at least a portion of the first insulating material 141a and connecting the first circuit layer 142a to the connection pad 120P and the third wiring layer 112c; a second insulating material 141b disposed on the first insulating material 141a and covering at least a portion of the first circuit layer 142a; a second circuit layer 142b disposed on the second insulating material 141b; and a second connection via layer 143b penetrating at least a portion of the second insulating material 141b and connecting the first circuit layer 142a and the second circuit layer 142b.

[0072] The insulating material can be used as the material of insulating materials 141a and 141b that are configured as one or more layers, and materials with good flowability can be used as insulating materials, such as PID as a photosensitive dielectric material, or materials including inorganic fillers and insulating resins but not glass fibers (such as ABF), etc.

[0073] Metallic materials can be used as the materials for one or more circuit layers 142a and 142b, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as metallic materials. Each of the one or more circuit layers 142a and 142b can perform various functions according to the design. For example, circuit layers 142a and 142b may include ground patterns, power patterns, signal patterns, etc. In this case, signal patterns include various signal patterns (such as data signal patterns) other than ground patterns and power patterns. Each of these patterns may have a line shape, a surface shape, or a pad shape. One or more circuit layers 142a and 142b may be formed by plating processes (such as AP or SAP), so each circuit layer may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer.

[0074] Metallic materials can be used as the materials for one or more connection via layers 143a and 143b, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as metallic materials. Depending on the design, each of the one or more connection via layers 143a and 143b may include signal connection vias, ground connection vias, power connection vias, etc. Each of the wiring vias in the one or more connection via layers 143a and 143b may be a filled via in which the via is filled with metallic material, or a conformal via in which metallic material is formed along the wall surface of the via. Additionally, the wiring vias in the one or more connection via layers 143a and 143b may have a tapered shape that tapers in the same direction. One or more interconnect via layers 143a and 143b can be formed by plating processes (e.g., AP, SAP, etc.), and thus one or more interconnect via layers 143a and 143b may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer.

[0075] The cover layer 150 can protect the circuit structure 140 and the like from external physical and chemical damage. The material of the cover layer 150 can be an insulating material. In this case, thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials in which these resins are mixed with inorganic fillers (such as ABF) can be used as insulating materials, but are not limited thereto. For example, other known epoxy molding compounds (EMCs) can be used.

[0076] Electrical connection metal parts 160 can physically connect and / or electrically connect the electronic component embedded substrate 100A to external components. Therefore, for example, the electronic component embedded substrate 100A can be mounted on the motherboard or other BGA (Ball Grid Array) substrate of an electronic device. Electrical connection metal parts 160 can be formed using tin (Sn) or tin-containing alloys (such as solder), this is merely an example, and the material is not particularly limited thereto. Electrical connection metal parts 160 can be pads, solder balls, or leads, respectively.

[0077] Figure 7 and Figure 8 It is a schematic representation of manufacturing. Figure 3 A process diagram of an example of an embedded substrate for electronic components.

[0078] Reference Figure 7First, a wiring structure 110 is fabricated using a coreless process with a separate carrier. Then, a dam structure 130 with a through-hole 130H is formed on the first passivation layer 115a of the wiring structure 110 using solder resist and photolithography. Next, a cavity 110H is formed in the wiring structure 110 by sandblasting or laser processing. Then, an electronic component 120 is attached to the bottom surface of the cavity 110H with its face facing upwards using an adhesive component A or the like.

[0079] Reference Figure 8 Next, an insulating material with excellent flowability is introduced into the dam structure 130 to form a first insulating material 141a. For example, a photosensitive dielectric material (such as PID) or an insulating material (such as fiber-free ABF) can be applied. Then, vias are formed in the first insulating material 141a by photolithography or laser processing, and a first circuit layer 142a and a first connection via layer 143a are formed by a plating process. Next, an insulating material with excellent flowability is introduced again into the dam structure 130 to form a second insulating material 141b. Similarly, vias are formed in the second insulating material 141b, and a second circuit layer 142b and a second connection via layer 143b are formed by a plating process. Through this series of processes, the circuit structure 140 can be formed. Thereafter, when a cover layer 150 or an electrical connection metal element 160 is formed as needed, an electronic component embedded substrate 100A according to the above example can be provided.

[0080] Other details are essentially the same as described above, so their detailed description can be omitted.

[0081] Figure 9 This is a schematic cross-sectional view showing another example of an embedded substrate for electronic components.

[0082] Figure 10 It is along Figure 9 A schematic plan view of the cross-section of the embedded substrate of the electronic component, taken by line II-II'.

[0083] Reference Figure 9 and Figure 10In the case of an embedded electronic component substrate 100B according to another example, the dam structure 130 includes a plurality of dam portions 131 and 132, each having a through portion 131H and a through portion 132H. For example, the dam structure 130 may include a first dam portion 131 and a second dam portion 132, the first dam portion 131 having a first through portion 131H, and the second dam portion 132 disposed on the first dam portion 131 and having a second through portion 132H communicating with the first through portion 131H. The inner wall of the first through portion 131H and the inner wall of the second through portion 132H may have a step difference, in which case the circuit structure 140 can be formed to have a relatively larger area. If desired, the circuit structure 140 may be constructed with more layers accordingly.

[0084] Other details are essentially the same as described above, so their detailed description can be omitted.

[0085] Figure 11 This is a schematic cross-sectional view showing another example of an embedded substrate for electronic components.

[0086] Figure 12 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components.

[0087] Reference Figure 11 and Figure 12 According to other examples, the embedded electronic component substrates 100C and 100D also include a second electronic component 180, which is disposed on the first passivation layer 115a, and... Figure 11In the cross-section shown in Figure 12, the second electronic component 180 is at least partially stacked with the first electronic component 120. In this case, the circuit structure 140 is disposed between the first electronic component 120 and the second electronic component 180 and can be used as an interconnect between them. For example, the second electronic component 180 may be disposed face down such that a plurality of second connection pads 1801P1 and 180P2 face the circuit structure 140, and at least one of the plurality of second connection pads 180P1 and 180P2 is electrically connected to at least one of the plurality of first connection pads 120P of the first electronic component 120 via the first connection member 191 and the circuit structure 140. In addition, the first passivation layer 115a may include not only a first opening 115ah1 that exposes at least a portion of the uppermost third wiring layer 112c of the circuit structure 140, but also a second opening 115ah2 that exposes at least another portion of the uppermost third wiring layer 112c. In this configuration, at least one of the plurality of second connection pads 180P1 and 180P2 of the second electronic component 180 is electrically connected to at least another portion of the third wiring layer 112c exposed through the second opening 115ah2 of the first passivation layer 115a. The second opening 115ah2 may be located outside the through portion 130H of the dam structure 130. Furthermore, in both the internal space surrounded by the dam structure 130 and the external space outside the dam structure 130, insulating materials (e.g., first insulating material 141a and second insulating material 141b) may be disposed only in the internal space, and circuit layers (e.g., first circuit layer 142a and second circuit layer 142b) may also be disposed only in the internal space.

[0088] The second electronic component 180 may be an IC in which hundreds to millions of devices are integrated into a single chip. For example, the second electronic component 180 may be a processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processing unit (e.g., a graphics processing unit (GPU)), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. Specifically, the second electronic component 180 may be an application processor (AP), but is not limited thereto. Additionally, the second electronic component 180 may be a memory such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.), or a logic chip (e.g., an analog-to-digital converter (ADC), an application-specific integrated circuit (ASIC)). The second electronic component 180 may be a surface-mount passive component, such as a surface-mount inductor or a surface-mount capacitor. Optionally, the second electronic component 180 may be a combination of an IC and a surface-mount passive component.

[0089] The second electronic component 180 can be disposed face down, such that the surface on which the second connecting pads 180P1 and 180P2 are disposed faces the circuit structure 140. The second electronic component 180 can be mounted on the circuit structure 140 and the wiring structure 110 via the surfaces of the first connecting member 191 and the second connecting member 192. The second connecting pads 180P1 and 180P2 may comprise metallic materials (such as copper (Cu), aluminum (Al), etc.). The second connecting pads 180P1 and 180P2 can be configured to protrude from the insulating body of the second electronic component 180, or alternatively, the second connecting pads 180P1 and 180P2 can be configured to be embedded in the insulating body of the second electronic component 180. The second connecting pads 180P1 and 180P2 are also provided with metallic bumps (such as copper bumps) for connection to the first connecting member 191 and the second connecting member 192, respectively. The first connecting member 191 and the second connecting member 192 may be formed using tin (Sn) or tin-containing alloys (e.g., solder, etc.), this is merely an example, and the material is not particularly limited thereto. Each of the first connecting member 191 and the second connecting member 192 may be a solder ball, etc.

[0090] Other details are essentially the same as described above, so their detailed description can be omitted.

[0091] Figure 13 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components.

[0092] Reference Figure 13In the case of an embedded substrate 100E for an electronic component according to another example, the wiring structure 110 has a core substrate shape. For example, the wiring structure 110 may include: a first insulating layer 111a; a first wiring layer 112a disposed on the lower surface of the first insulating layer 111a; a second wiring layer 112b disposed on the upper surface of the first insulating layer 111a; a first wiring via layer 113a penetrating the first insulating layer 111a and connecting the first wiring layer 112a and the second wiring layer 112b; a second insulating layer 111b disposed on the lower surface of the first insulating layer 111a to cover at least a portion of the first wiring layer 112a; a third wiring layer 112c disposed on the lower surface of the second insulating layer 111b; and a second wiring via layer 113b penetrating at least a portion of the second insulating layer 111b and connecting the first wiring layer 112a and the second wiring layer 112b. A third wiring layer 112c; a third insulating layer 111c disposed on the upper surface of the first insulating layer 111a and covering at least a portion of the second wiring layer 112b; a fourth wiring layer 112d disposed on the upper surface of the third insulating layer 111c; a third wiring via layer 113c penetrating at least a portion of the third insulating layer 111c and connecting the second wiring layer 112b and the fourth wiring layer 112d; a first passivation layer 115a disposed on the upper surface of the third insulating layer 111c; and a second passivation layer 115b disposed on the lower surface of the second insulating layer 111b, and the wiring structure 110 may have a cavity 110H penetrating the first insulating layer 111a, the third insulating layer 111c, and the first passivation layer 115a. A metal layer M serving as a barrier layer may be located at the same height as the first wiring layer 112a. Among the multiple insulating layers 111a, 111b, and 111c, the uppermost insulating layer can be the third insulating layer 111c, and the lowermost insulating layer can be the second insulating layer 111b. Among the multiple wiring layers 112a, 112b, 112c, and 112d, the uppermost wiring layer can be the fourth wiring layer 112d, and the lowermost wiring layer can be the third wiring layer 112c.

[0093] The insulating material can be used as the material for the multiple insulating layers 111a, 111b, and 111c, and can be a thermosetting resin (such as epoxy resin) or a thermoplastic resin (such as polyimide), or a mixture thereof with inorganic fillers (such as silica) and / or reinforcing materials (such as glass fiber). For example, the insulating material of copper-clad laminate (CCL) can be used as the material for the first insulating layer 111a, and polypropylene glycol (PPG) can be used as the material for the second insulating layer 111b and the third insulating layer 111c, respectively. The multiple insulating layers 111a, 111b, and 111c can be stacked in a core shape. For example, the thickness of the first insulating layer 111a can be greater than the thickness of each of the second insulating layer 111b and the third insulating layer 111c, but is not limited thereto.

[0094] Metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as the materials for the multiple wiring layers 112a, 112b, 112c, and 112d. Each of the multiple wiring layers 112a, 112b, 112c, and 112d can perform various functions depending on the design. For example, the multiple wiring layers 112a, 112b, 112c, and 112d may include ground patterns, power patterns, signal patterns, etc. In this case, signal patterns include various signal patterns (such as data signal patterns) other than ground and power patterns. Each of these patterns may have a line shape, a surface shape, or a pad shape. The multiple wiring layers 112a, 112b, 112c, and 112d can be formed by plating processes (such as MSAP or TT processes), so each wiring layer may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer. Certain layers may also include copper foil.

[0095] Metallic materials can be used as the materials for the multiple wiring via layers 113a, 113b, and 113c, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as the metallic materials. Depending on the design, each of the multiple wiring via layers 113a, 113b, and 113c may include signal connection vias, ground connection vias, power connection vias, etc. Each of the wiring vias in the multiple wiring via layers 113a, 113b, and 113c may be a filled via where the via is filled with metallic material, or it may be a conformal via where metallic material is formed along the wall surface of the via. The wiring vias in the first wiring via layer 113a may have an hourglass shape or a cylindrical shape, and the wiring vias in the second wiring via layer 113b and the third wiring via layer 113c may have a tapering shape in opposite directions. Multiple wiring via layers 113a, 113b and 113c can be formed by plating processes (e.g., MSAP, TT process, etc.). Therefore, multiple wiring via layers 113a, 113b and 113c can include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer.

[0096] Other details are essentially the same as described above, so their corresponding descriptions can be omitted.

[0097] Figure 14 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components.

[0098] Reference Figure 14In an electronic component embedded substrate 100F according to another example, the dam structure 130 includes a plurality of dam portions 131 and 132, each having a through portion 131H and a through portion 132H. For example, the dam structure 130 may include a first dam portion 131 and a second dam portion 132, the first dam portion 131 having a first through portion 131H, and the second dam portion 132 disposed on the first dam portion 131 and having a second through portion 132H communicating with the first through portion 131H. The inner wall of the first through portion 131H and the inner wall of the second through portion 132H may have a step difference, in which case the circuit structure 140 can be formed to have a relatively larger area. If desired, the circuit structure 140 may be constructed with more layers accordingly.

[0099] Other details are essentially the same as described above, so their corresponding descriptions can be omitted.

[0100] Figure 15 This is a schematic cross-sectional view showing another example of an embedded substrate for electronic components.

[0101] Figure 16 This is a schematic cross-sectional view of another example of an embedded substrate for electronic components.

[0102] Reference Figure 15 and Figure 16 The electronic component embedded substrates 100G and 100H, according to other examples, also include a second electronic component 180, which is disposed on the first passivation layer 115a and, as shown in the figure... Figure 15In the cross-section shown in Figure 16, the second electronic component 180 is at least partially stacked with the first electronic component 120. In this case, the circuit structure 140 is disposed between the first electronic component 120 and the second electronic component 180 and can be used as an interconnect between them. For example, the second electronic component 180 may be disposed face down such that a plurality of second connection pads 1801P1 and 180P2 face the circuit structure 140, and at least one of the plurality of second connection pads 180P1 and 180P2 is electrically connected to at least one of the plurality of first connection pads 120P of the first electronic component 120 via the first connection member 191 and the circuit structure 140. In addition, the first passivation layer 115a may include not only a first opening 115ah1 that exposes at least a portion of the uppermost fourth wiring layer 112d of the circuit structure 140, but also a second opening 115ah2 that exposes at least another portion of the uppermost fourth wiring layer 112d. In this configuration, at least one of the plurality of second connection pads 180P1 and 180P2 of the second electronic component 180 can be electrically connected via the second connection member 192 to at least another portion of the fourth wiring layer 112d exposed through the second opening 115ah2 of the first passivation layer 115a. The second opening 115ah2 can be located outside the through-hole 130H of the dam structure 130.

[0103] The second electronic component 180 may be an IC in which hundreds to millions of devices are integrated on a single chip. For example, the second electronic component 180 may be a processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processing unit (e.g., a graphics processing unit (GPU)), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. Specifically, the second electronic component 180 may be an AP, but is not limited thereto. Additionally, the second electronic component 180 may be a memory such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.), or a logic chip (e.g., an analog-to-digital converter (ADC), an application-specific integrated circuit (ASIC)). The second electronic component 180 may be a surface-mount passive component, such as a surface-mount inductor or a surface-mount capacitor. Optionally, the second electronic component 180 may be a combination of an IC and surface-mount passive components.

[0104] The second electronic component 180 may be disposed face down, such that the surface on which the second connecting pads 180P1 and 180P2 are disposed faces the circuit structure 140. The second electronic component 180 may be mounted on the circuit structure 140 and the wiring structure 110 via the surfaces of the first connecting member 191 and the second connecting member 192. The second connecting pads 180P1 and 180P2 may comprise a metallic material (such as copper (Cu) or aluminum (Al)). The second connecting pads 180P1 and 180P2 may be configured to protrude from the insulating body of the second electronic component 180, or alternatively, the second connecting pads 180P1 and 180P2 may be configured to be embedded in the insulating body of the second electronic component 180. The second connecting pads 180P1 and 180P2 may also be provided with metallic bumps (such as copper bumps) for connection to the first connecting member 191 and the second connecting member 192, respectively. The first connecting member 191 and the second connecting member 192 may be formed using tin (Sn) or tin-containing alloys (e.g., solder, etc.), which is merely an example, and the materials of the first connecting member 191 and the second connecting member 192 are not particularly limited thereto. Each of the first connecting member 191 and the second connecting member 192 may be a solder ball, etc.

[0105] Other details are essentially the same as described above, so their corresponding descriptions can be omitted.

[0106] As described above, according to the embodiments, an electronic component embedded substrate can be provided, wherein the size and thickness of the substrate can be reduced and the electronic component can be embedded in the cavity in an upward-facing manner.

[0107] In addition, an embedded substrate for electronic components can be provided, wherein microcircuit regions can be locally applied to the electronic components.

[0108] Although this disclosure includes specific examples, it will be apparent to those skilled in the art that various changes in form and detail may be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered merely for descriptive purposes and not for limiting purposes. The description of features or aspects in each example is to be considered applicable to similar features or aspects in other examples. Suitable results may be obtained if the described techniques are performed in a different order, and / or if the components in the described system, architecture, apparatus, or circuit are combined in a different manner and / or if the components in the described system, architecture, apparatus, or circuit are replaced or supplemented with other components or their equivalents. Therefore, the scope of this disclosure is not limited by the specific embodiments but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents shall be construed as included in this disclosure.

Claims

1. An embedded substrate for electronic components, comprising: A wiring structure includes multiple insulating layers and multiple wiring layers and has a cavity penetrating at least one of the multiple insulating layers; A first electronic component is disposed in the cavity; A dam structure is disposed above the wiring structure and has a through section; A first insulating material is disposed in at least a portion of each of the cavity and the through portion, and covers at least a portion of each of the wiring structure and the first electronic component; as well as The first circuit layer is disposed on the first insulating material. The first circuit layer is disposed in the through portion. Wherein, the thickness of the first circuit layer is less than the thickness of at least one of the plurality of wiring layers.

2. The electronic component embedded substrate according to claim 1, wherein, The dam structure protrudes from the wiring structure, and the first insulating material is disposed only in the internal space surrounded by the dam structure and in the external space outside the dam structure.

3. The embedded substrate for electronic components according to claim 1 or 2, wherein, The dam structure includes a first dam section and a second dam section. The first dam section has a first through section, and the second dam section is disposed on the first dam section and has a second through section connecting to the first through section. The inner wall of the first through section and the inner wall of the second through section have a step difference.

4. The embedded substrate for electronic components according to claim 1, wherein the embedded substrate for electronic components further comprises: A second insulating material is disposed on the first insulating material within the through portion and covers at least a portion of the first circuit layer; as well as The second circuit layer is disposed on the second insulating material.

5. The embedded substrate for electronic components according to claim 1, wherein, The dam structure includes a welding resist.

6. The embedded substrate for electronic components according to claim 1, wherein, The first insulating material includes a photosensitive dielectric material.

7. The embedded substrate for electronic components according to claim 1, wherein, The first insulating material includes insulating resin and inorganic filler but does not include glass fiber.

8. The embedded substrate for electronic components according to any one of claims 1-2 and 4-7, wherein, The spacing between the patterns of the first circuit layer is smaller than the spacing between the patterns of at least one of the plurality of wiring layers.

9. The embedded substrate for electronic components according to claim 1, wherein, The cavity is provided with a barrier layer, which is disposed on the bottom surface of the cavity. The first electronic component is attached to the barrier layer via an adhesive member.

10. The embedded substrate for electronic components according to claim 9, wherein, The first electronic component is provided with a plurality of first connection pads, which are disposed on the upper surface of the first electronic component. At least a portion of the first circuit layer is connected to at least one of the plurality of first connection pads through a first connection via that penetrates at least a portion of the first insulating material.

11. The embedded substrate for electronic components according to claim 1, wherein, The wiring structure further includes: a first passivation layer disposed on the uppermost insulating layer among the plurality of insulating layers; and a second passivation layer disposed on the lowermost insulating layer among the plurality of insulating layers.

12. The embedded substrate for electronic components according to claim 11, wherein, The first passivation layer has a first opening that exposes at least a portion of the uppermost wiring layer among the plurality of wiring layers. The first opening is located in the through portion on the plane. The first insulating material is disposed in at least a portion of the first opening, and At least a portion of the first circuit layer is connected to at least a portion of the uppermost wiring layer through a second connection via that penetrates at least a portion of the first insulating material in the first opening.

13. The embedded electronic component substrate of claim 11, further comprising a second electronic component, the second electronic component being disposed on the first passivation layer and configured to at least partially overlap with the first electronic component in a plane. in, The first circuit layer is disposed between the first electronic component and the second electronic component.

14. The embedded substrate for electronic components according to claim 13, wherein, The upper surface of the first electronic component is provided with a plurality of first connection pads. The lower surface of the second electronic component is provided with a plurality of second connection pads. The first passivation layer has a second opening that exposes at least another portion of the uppermost wiring layer of the plurality of wiring layers. The second opening is located on the outside of the through portion in the plane. At least one of the plurality of second connection pads is connected to at least one of the plurality of first connection pads via a first connection member and the first circuit layer. At least one of the plurality of second connecting pads is connected via a second connecting member to at least another portion of the uppermost wiring layer exposed through the second opening.

15. The embedded substrate for electronic components according to claim 1, wherein, The dam structure surrounds the cavity in a plane, and the through portion exposes the cavity.

16. An embedded substrate for electronic components, comprising: A wiring structure includes multiple insulating layers and multiple wiring layers and has a cavity penetrating at least one of the multiple insulating layers; A first electronic component is disposed in the cavity; A dam structure is disposed above the wiring structure and has a through section; A first insulating material is disposed in at least a portion of each of the cavity and the through portion, and covers at least a portion of each of the wiring structure and the first electronic component; as well as The first circuit layer is disposed on the first insulating material. The first circuit layer is disposed in the through portion. The wiring structure further includes: a first passivation layer disposed on the uppermost insulating layer among the plurality of insulating layers; and a second passivation layer disposed on the lowermost insulating layer among the plurality of insulating layers.

17. An embedded substrate for electronic components, comprising: A wiring structure includes an insulating layer and a wiring layer disposed on and / or in the insulating layer, and has a cavity having a bottom surface; An electronic component has one surface and another surface opposite to the one surface, and is arranged such that the other surface faces the bottom surface of the cavity, and a connection pad is provided on the one surface; A dam structure is disposed above the wiring structure and has a through portion, wherein the area of ​​the through portion is larger than the area of ​​the cavity in a plane; as well as A circuit structure is disposed within the through portion and includes an insulating material and a circuit layer, wherein the electronic component is embedded in the insulating material and the circuit layer is disposed on the insulating material. Wherein, at least a portion of the wiring layer and at least a portion of the connection pad are connected to each other through at least a portion of the circuit layer. The circuit layer is disposed in the through portion. The thickness of the circuit layer is less than the thickness of the wiring layer.

18. The embedded substrate for electronic components according to claim 17, wherein, The spacing between the patterns in the circuit layer is smaller than the spacing between the patterns in the wiring layer.

19. The embedded substrate for electronic components according to claim 17, wherein, The circuit structure is also located above the cavity.

20. The embedded substrate for electronic components according to claim 17, wherein, The at least portion of the wiring layer and the at least portion of the connection pad are respectively connected to the at least portion of the circuit layer through connection vias that penetrate at least a portion of the insulating material.

21. An embedded substrate for electronic components, comprising: The wiring structure includes multiple insulation layers and multiple wiring layers; A first electronic component is attached to the wiring structure; A dam structure is disposed above the wiring structure and has a through section; An insulating material is disposed in the through portion and covers at least a portion of the wiring structure and each of the first electronic components; as well as The circuit layer is disposed on the insulating material. The circuit layer is disposed in the through portion. The embedded electronic component substrate further includes a second electronic component disposed on the circuit layer. The upper surface of the first electronic component is provided with a plurality of first connection pads. The lower surface of the second electronic component is provided with a plurality of second connection pads, and At least one of the plurality of first connection pads is connected to at least one of the plurality of second connection pads via at least a portion of the circuit layer disposed between the first electronic component and the second electronic component.

22. The embedded substrate for electronic components according to claim 21, wherein, The dam structure protrudes from the wiring structure, and The insulating material is disposed only in the internal space surrounded by the dam structure and in the external space outside the dam structure.

23. The embedded substrate for electronic components according to claim 21, wherein, The dam structure protrudes from the wiring structure, and The circuit layer is disposed only in the internal space surrounded by the dam structure and in the external space outside the dam structure.

24. The electronic component embedded substrate according to any one of claims 21 to 23, wherein, The dam structure includes a welding resist.

25. The electronic component embedded substrate according to any one of claims 21 to 23, wherein, The thickness of the circuit layer is less than the thickness of at least one of the plurality of wiring layers, and the spacing between the patterns of the circuit layer is less than the spacing between the patterns of at least one of the plurality of wiring layers.

26. The embedded substrate for electronic components according to claim 21, wherein, The first electronic component is provided with a plurality of first connection pads, which are disposed on the upper surface of the first electronic component. A portion of the circuit layer is connected to at least one of the plurality of first connection pads via a first connection via that penetrates at least a portion of the insulating material, and Another portion of the circuit layer is connected to at least a portion of the uppermost wiring layer of the plurality of wiring layers through a second connection via that penetrates at least another portion of the insulating material.

27. The embedded substrate for electronic components according to claim 21, wherein, The dam structure includes a first dam section and a second dam section. The first dam section has a first through section, and the second dam section is disposed on the first dam section and has a second through section that connects to the first through section.

28. An embedded substrate for electronic components, comprising: A wiring structure includes multiple insulating layers and multiple wiring layers, and has a cavity that penetrates at least a portion of the multiple insulating layers; A first electronic component is disposed in the cavity; A dam structure is disposed above the wiring structure and has a through section; A first insulating material is disposed in at least a portion of each of the cavity and the through portion, and covers at least a portion of each of the wiring structure and the first electronic component; as well as A first circuit layer, disposed within the dam structure on the first insulating material, and electrically connecting the first electronic component to the uppermost wiring layer of the plurality of wiring layers. The first circuit layer is disposed in the through portion. The embedded substrate of the electronic component further includes a second electronic component, which is connected to the uppermost wiring layer through a first connecting member located on the outside of the dam structure.

29. The embedded substrate for electronic components according to claim 28, wherein, The first circuit layer has a pattern, and the spacing between the patterns of the first circuit layer is smaller than the spacing between the patterns of at least one of the plurality of wiring layers.

30. The embedded substrate for electronic components according to claim 28, wherein, The embedded substrate for the electronic components also includes: A second insulating material is disposed within the through portion on the first insulating material and covers at least a portion of the first circuit layer; and The second circuit layer is disposed on the second insulating material.

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