Randomized computing methods, circuits, chips, and devices

Abstract

A random computing method, circuit, chip and device belong to the technical field of circuit. The random computing circuit comprises: a control circuit configured to input a control parameter to a pulse input circuit, the control parameter comprising: a control word having an integer part and a decimal part; a pulse output circuit configured to input a to-be-computed pulse to a computing circuit according to the control parameter and a plurality of uniformly-spaced reference pulses; wherein the to-be-computed pulse comprises at least one of a first sub-pulse and a second sub-pulse, the period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and the probability of the first sub-pulse and the second sub-pulse appearing in the to-be-computed pulse is controlled by the decimal part; and the computing circuit is configured to perform a logic calculation according to the duty cycle of the to-be-computed pulse and output a calculation result of the logic calculation. The application can improve the accuracy of the calculation result, and the application is used for a computing circuit.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a random calculation method, circuit, chip, and device. Background Technology

[0002] Computational circuits are an important component of processing chips such as the central processing unit (CPU) and graphics processing unit (GPU). They are used to perform logical calculations.

[0003] In related technologies, computing circuits are based on binary calculation. The computing circuit converts the numbers to be calculated from decimal to binary, and then performs calculations on the binary numbers.

[0004] However, when a bit in a binary number is incorrect, the binary number will change significantly, resulting in a large difference between the calculation result output by the computing circuit and the correct calculation result, and thus the accuracy of the calculation result output by the computing circuit is low. Summary of the Invention

[0005] This application provides a random calculation method, circuit, chip, and device, which can solve the problem of low accuracy of calculation results. The technical solution is as follows:

[0006] In a first aspect, a random calculation circuit is provided, the random calculation circuit comprising: a control circuit, a pulse output circuit, and a calculation circuit; the control circuit and the calculation circuit are both connected to the pulse output circuit.

[0007] The control circuit is used to input control parameters to the pulse output circuit, the control parameters including: a control word having an integer part and a fractional part;

[0008] The pulse output circuit is used to input a pulse to be calculated into the calculation circuit according to the control parameters and a multi-channel reference pulse with uniform phase interval; wherein, the pulse to be calculated includes at least one sub-pulse among a first sub-pulse and a second sub-pulse arranged in the time domain, the period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and the probability of the first sub-pulse and the second sub-pulse appearing in the pulse to be calculated is controlled by the fractional part.

[0009] The calculation circuit is used to perform logical calculations based on the duty cycle of the pulse to be calculated, and output the calculation results of the logical calculations.

[0010] Optionally, the control parameters further include: a high-level parameter ζ; T HI_A =T HI_B=ζ·Δ;

[0011] T HI_A T represents the duration of the high level of the first sub-pulse; HI_B The duration of the high level of the second sub-pulse is indicated; ζ is an integer, and 1≤ζ≤I-1, where I represents the integer part; Δ represents the phase difference between any two adjacent reference pulses in the multi-path reference pulses.

[0012] Optionally, the random calculation circuit includes a plurality of the pulse output circuits;

[0013] The control circuit is used to input the control parameters corresponding to each pulse output circuit to each pulse output circuit.

[0014] Optionally, the plurality of pulse output circuits include: a first pulse output circuit for inputting a first pulse to be calculated to the computing circuit, and a second pulse output circuit for inputting a second pulse to be calculated to the computing circuit;

[0015] The first pulse to be calculated is unrelated to the second pulse to be calculated.

[0016] Optionally, the first pulse to be calculated is independent of the second pulse to be calculated.

[0017] Optionally, the target parameters of the first pulse to be calculated and the target parameters of the second pulse to be calculated are coprime numbers;

[0018] For any of the pulses to be calculated, the target parameter of the pulse is q·I+p, where p / q is equal to the fractional part and I represents the integer part.

[0019] Optionally, the random calculation circuit further includes a sampling circuit and a clock circuit, wherein the calculation circuit and the clock circuit are both connected to the sampling circuit, and the sampling circuit is also connected to the control circuit;

[0020] The control circuit is also used to input the target sequence length into the sampling circuit;

[0021] The clock circuit is used to provide a clock signal to the sampling circuit;

[0022] The sampling circuit is used to sample the calculation result output by the calculation circuit according to the clock signal and the target sequence length to obtain a result sequence of the target sequence length;

[0023] The sampling circuit is also used to output an indication signal of the duty cycle of the result sequence.

[0024] Optionally, the duration T of the pulse to be calculated FD=(qp)·T A +p·T B ;

[0025] p / q equals the fractional part; T A =I·Δ,T A The period of the first sub-pulse is represented by I, the integer part of the pulse, and Δ, which represents the phase difference between any two adjacent reference pulses in the multi-path reference pulses. B = (I+1)·Δ, T B This indicates the period of the second sub-pulse.

[0026] Optionally, p / q is the simplest form of the fractional part.

[0027] Optionally, the integer part is greater than 16.

[0028] Optionally, the pulse output circuit includes: a first processing circuit, a second processing circuit, and an output circuit, wherein the first processing circuit and the output circuit are both connected to the second processing circuit;

[0029] The first processing circuit is used to output a first control signal and a second control signal according to the control parameters respectively;

[0030] The second processing circuit is used to select the I-th reference pulse from the multiple reference pulses according to the first control signal, and to select the J-th reference pulse from the multiple reference pulses according to the second control signal, and to select one reference pulse from the I-th reference pulse and the J-th reference pulse as the output pulse, where 1≤I, 1≤J;

[0031] The output circuit is used to output the pulse to be calculated based on the output pulse of the second processing circuit.

[0032] Optionally, the logical calculation includes at least one of addition, subtraction, multiplication, division, square root, and squaring.

[0033] In a second aspect, a random computation method is provided, the method being used in any of the random computation circuits provided in the first aspect, the method comprising:

[0034] The control circuit inputs control parameters to the pulse output circuit, the control parameters including a control word having an integer part and a fractional part;

[0035] The pulse output circuit inputs a pulse to be calculated into the calculation circuit based on the control parameters and multiple reference pulses with uniform phase intervals; wherein the pulse to be calculated includes at least one sub-pulse among a first sub-pulse and a second sub-pulse arranged in the time domain, the period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and the probability of the first sub-pulse and the second sub-pulse appearing in the pulse to be calculated is controlled by the fractional part.

[0036] The calculation circuit performs logical calculations based on the duty cycle of the pulse to be calculated and outputs the calculation results.

[0037] Thirdly, a chip is provided, the chip comprising any of the random computing circuits provided in the first aspect.

[0038] Fourthly, an electronic device is provided, the electronic device comprising the chip provided in the third aspect.

[0039] In summary, in the random calculation circuit provided in this application embodiment, the pulse output circuit can output a pulse to be calculated, and the calculation circuit can perform logical calculations based on the duty cycle of the pulse to be calculated. When a bit in the pulse to be calculated is faulty, the duty cycle of the pulse to be calculated will not change significantly, and consequently, the result of the logical calculation will not change significantly. Therefore, the accuracy of the calculation result output by the calculation circuit is high. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a random calculation circuit provided in an embodiment of this application;

[0041] Figure 2 Waveform diagram of multiple reference pulses provided by the signal source in the embodiments of this application;

[0042] Figure 3 A schematic diagram of a pulse to be calculated provided for an embodiment of this application;

[0043] Figure 4 D provided for the embodiments of this application FD A schematic diagram showing the value range of I under different conditions;

[0044] Figure 5 This is a schematic diagram of the structure of a pulse output circuit 02 provided in an embodiment of this application;

[0045] Figure 6 This is a schematic diagram of another random calculation circuit provided in an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of another random calculation circuit provided in an embodiment of this application;

[0047] Figure 8 This is a schematic diagram of another random calculation circuit provided in an embodiment of this application;

[0048] Figure 9 The result diagram of Example 1 in Table 1 provided for the embodiments of this application;

[0049] Figure 10 The result diagrams in Example 2 of Table 1 provided for embodiments of this application;

[0050] Figure 11 A flowchart of a random calculation method provided in an embodiment of this application. Detailed Implementation

[0051] To make the principles, technical solutions and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0052] With the rapid development of chip technology and the gradual implementation of Internet of Things applications, the calculations in the computing circuits of chips are becoming increasingly complex, and the computing paradigm (also known as the computing method) adopted by the computing circuits has reached a point where breakthroughs are needed.

[0053] In related technologies, the computing circuit adopts the classic von Neumann architecture and is based on binary computation. The computing circuit converts the numbers to be calculated from decimal to binary before performing the calculations on the binary numbers. For example, if the product of 3 and 8 needs to be calculated, the computing circuit will convert 3 to binary 0011 and 8 to binary 0100. Then, it will multiply 0011 and 0100 to obtain the result 24.

[0054] However, when a bit in a binary number is incorrect, the binary number changes significantly, leading to a large discrepancy between the calculated result and the correct result, resulting in lower accuracy. For example, continuing with the previous example, when the second bit in the binary representation of 3 (0011) is incorrect, it becomes 0111. 0111 represents 12, which is significantly different from 3. Multiplying the binary representation of 12 (0111) with the binary representation of 8 (0100) yields a result of 96, which is significantly different from 24.

[0055] Furthermore, the computational precision of this method is absolutely related to the number of bits in the binary representation. As the computational task increases, the number of bits in the binary representation reaches 64, 128, 256, and 1024 bits, resulting in different computational precisions for circuits using different bit widths. If the computational circuit needs to be compatible with multiple computational precisions, it will increase the design cost. If the computational circuit is not compatible with multiple computational precisions, it will only have a fixed precision, resulting in poor scalability.

[0056] Furthermore, before the computing circuit can perform calculations, the processor where the computing circuit resides needs to read the data to be calculated from the memory. It can be seen that the computing efficiency of the computing circuit is related to the bandwidth of both the processor and the memory, and the slower bandwidth of the processor and the memory will affect the computing efficiency of the computing circuit.

[0057] This application provides a random calculation circuit that outputs calculation results with high accuracy and can have unlimited calculation precision. The memory bandwidth does not affect the calculation efficiency of the random calculation circuit.

[0058] For example, Figure 1 This is a schematic diagram of a random calculation circuit provided in an embodiment of this application, such as... Figure 1 As shown, the random calculation circuit includes: a control circuit 01, a pulse output circuit 02, and a calculation circuit 03; both the control circuit 01 and the calculation circuit 03 are connected to the pulse output circuit 02.

[0059] Control circuit 01 is used to input control parameters to pulse output circuit 02. The control parameters include a control word having an integer part and a fractional part. The control word is a number and has both an integer and a fractional part. For example, a control word of 2.5 has an integer part of 2 and a fractional part of 0.5. It should be noted that when the control word is an integer, the fractional part is 0.

[0060] The pulse output circuit 02 is used to input the pulse to be calculated into the calculation circuit 03 according to the control parameters and the multi-channel reference pulse with uniform phase interval; wherein, the pulse to be calculated includes at least one sub-pulse among the first sub-pulse and the second sub-pulse arranged in the time domain, the period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and the probability of the first sub-pulse and the second sub-pulse appearing in the pulse to be calculated is controlled by the fractional part.

[0061] Please continue to refer to this. Figure 1 The multiple reference pulses with uniform phase spacing can be pulses provided by a signal source. The signal source can be located outside the pulse output circuit 02. Of course, the signal source can also be located within the pulse output circuit 02. In this embodiment, the example is that the signal source is located outside the pulse output circuit 02.

[0062] Figure 2 Waveform diagram of multiple reference pulses provided for the signal source. Figure 2 Taking a multi-channel reference pulse system including K reference pulses as an example, where K > 1. See [link / reference]. Figure 2 The waveforms of the multiple reference pulses are identical (i.e., the period and amplitude are the same). The waveforms of the multiple reference pulses are uniformly arranged, and these reference pulses are spaced equally in the time domain. The phase difference Δ between any two adjacent reference pulses in the multiple reference pulses is the same, and the frequency of the multiple reference pulses is fi.

[0063] The control parameters are used to control the pulse to be calculated output by the pulse output circuit 02.

[0064] For example, the duty cycle of the pulse to be calculated is used to represent the decimal to be calculated. The decimal to be calculated is the decimal that will be used in the calculation. The random calculation circuit provided in this application embodiment is used to perform logical calculations on the decimal. For example, if the decimal to be calculated is 0.5, then the duty cycle of the pulse to be calculated output by the pulse output circuit 02 is 1 / 2, that is, the proportion of the high level duration in the pulse to be calculated is 1 / 2. The pulse to be calculated can be 11110000.

[0065] For example, the periods of the first and second sub-pulses in the pulse to be calculated are controlled by the integer part, while the probabilities of the first and second sub-pulses appearing in the pulse to be calculated are controlled by the fractional part. For instance, suppose the period of the first sub-pulse is represented as T. A The period of the second sub-pulse is denoted as T. B If the integer part of the control word is represented as I, then T A =I*Δ,T B = (I+1)*Δ. Of course, T A and T B There are other ways to represent it, such as T. B = (I+2)*Δ etc., in the embodiments of this application, T is used. A =I*Δ,T B For example, if the control word is represented by the fractional part as r, then the ratio of the probability of the first sub-pulse and the second sub-pulse appearing in the pulse to be calculated is (qp) / p, where p / q = r. In this case, the duration T of the pulse to be calculated... FD =(qp)·T A +p·T B p / q can be the simplest form of the decimal part r. For example, if the decimal part is 0.5, then p / q is 1 / 2, p = 1, q = 2. p / q can also not be the simplest form of the decimal part r. For example, when the decimal part is 0.5, p = 2, q = 4.

[0066] like Figure 3 As shown, T B Compared to T A The cycle is longer, in Figure 3 The middle is manifested as T B The length of T A Length. When the decimal part of the control word is 0.5, the first and second sub-pulses have equal probabilities of appearing in the pulse to be calculated, T. A and T B The probability of occurrence is equal, see Figure 3 The pulse to be calculated is shown, where T A and T B Alternating occurrences. When the decimal part is less than 0.5, the probability of the first sub-pulse appearing in the pulse to be calculated is greater than the probability of the second sub-pulse appearing, T. A The probability of occurrence is greater than T B The probability of occurrence. When the decimal part is greater than 0.5, the probability of the first sub-pulse appearing in the pulse to be calculated is less than the probability of the second sub-pulse appearing, T. B The probability of occurrence is greater than T A It should be noted that when the control word is an integer, the decimal part of the control word is 0. In this case, the pulse signal only contains the first sub-pulse and does not contain the second sub-pulse.

[0067] The calculation circuit 03 performs logical calculations based on the duty cycle of the pulse to be calculated and outputs the result. The pulse output circuit 02 inputs the pulse to be calculated to the calculation circuit 03. The calculation circuit 03 can perform logical calculations based on the duty cycle of the pulse (representing the decimal to be calculated), which is equivalent to performing logical calculations based on the decimal. For example, if the duty cycle of the pulse to be calculated is 1 / 2, then the calculation circuit 03 can perform logical calculations based on 1 / 2. The logical calculation here can be any logical calculation, such as at least one of addition, subtraction, multiplication, division, square root, and squaring. When the logical calculation includes addition, the calculation circuit 03 includes an OR gate or a multiplexer (MUX).

[0068] In summary, in the random calculation circuit provided in this application embodiment, the pulse output circuit can output a pulse to be calculated, and the calculation circuit can perform logical calculations based on the duty cycle of the pulse to be calculated. When a bit in the pulse to be calculated is faulty, the duty cycle of the pulse to be calculated will not change significantly, and consequently, the result of the logical calculation will not change significantly. Therefore, the accuracy of the calculation result output by the calculation circuit is high.

[0069] Furthermore, the control circuit can control the duty cycle, period, and probability of occurrence of the sub-pulse output by the pulse output circuit through control words. Therefore, precise control of the pulse to be calculated can be achieved.

[0070] The duration T of the pulse to be calculated FD =(qp)·T A +p·T B Assume the period of the pulse to be calculated is T. TAF ,So:

[0071] T FD =q·T TAF =(qp)·T A +p·T B = (q·I+p)·Δ;

[0072]

[0073] Where F represents the control word, F = I + r. It can be seen that f s The frequency of the pulse to be calculated changes linearly with the change of F. Correspondingly, the period of the pulse to be calculated also changes with the change of F. Therefore, in the embodiments of this application, the period and frequency of the pulse to be calculated can be controlled by the control word F.

[0074] In the above embodiment, taking the control parameters input by the control circuit 01 to the pulse output circuit 02, including the control word, as an example, optionally, the control parameters further include a high-level parameter ζ. The high-level parameter ζ is used to control the high-level duration of the first sub-pulse and the second sub-pulse in the pulse to be calculated. HI_A =T HI_B =ζ·Δ; where, T HI_A T represents the duration of the high level of the first sub-pulse; HI_B This indicates the duration of the high level of the second sub-pulse. ζ is an integer, and 1 ≤ ζ ≤ I-1, where I represents the integer part; Δ represents the phase difference between any two adjacent reference pulses in the multi-channel reference pulse. For example... Figure 3 As shown, the duration T of the high level of the first sub-pulse HI_A Equal to the high-level duration T of the second sub-pulse HI_B .

[0075] In T HI_A =T HI_B When =ζ·Δ, the total high-level time T in the pulse to be calculated HI_FD It can be represented as:

[0076] T HI_FD =(qp)·ζ·Δ+p·ζ·Δ=q·ζ·Δ;

[0077] The proportion D of the high level in the pulse to be calculated FD It can be represented as:

[0078]

[0079] According to 1≤ζ≤I-1, we can derive D FD The range of values ​​for is:

[0080]

[0081] The above D FD By deriving the range of values ​​for , we can conclude that:

[0082]

[0083] According to D FD This range of values ​​shows that D FD The range of values ​​for can almost cover the entire interval from 0 to 1. For example, when I = 128, D FD The range of values ​​for is as follows:

[0084]

[0085] For example, D FD The range of values ​​for different I is as follows Figure 4 As shown, it can be seen that when I > 16, D FD The value range of can almost cover the entire interval from 0 to 1. In the embodiments of this application, 1 > 16 is taken as an example.

[0086] In D FD When the value range of is almost covering the entire interval from 0 to 1, the decimal represented by the pulse to be calculated can almost cover the entire interval from 0 to 1, and the application range of random calculation circuits is large.

[0087] Furthermore, the pulse output circuit 02 provided in the embodiments of this application has various structures, which will be described below. Figure 5 The structure shown will be used as an example for explanation. Please refer to the following. Figure 5 The pulse output circuit 02 includes a first processing circuit 21, a second processing circuit 22, and an output circuit 23, wherein the first processing circuit 21 and the output circuit 23 are both connected to the second processing circuit 22.

[0088] The first processing circuit 21 is used to output a first control signal and a second control signal according to the control parameters respectively; the second processing circuit 22 is used to select the I-th reference pulse from multiple reference pulses (such as K reference pulses, K>1) according to the first control signal, and to select the J-th reference pulse from multiple reference pulses according to the second control signal, and to select one reference pulse from the I-th reference pulse and the J-th reference pulse as the output pulse, 1≤I, 1≤J; the output circuit 23 is used to output the pulse to be calculated according to the output pulse of the second processing circuit 22.

[0089] The following is combined with Figure 5 The operation of the first processing circuit 21, the second processing circuit 22, and the output circuit 23 will be explained as follows:

[0090] The first processing circuit 21 includes a first logic controller 211 and a second logic controller 212.

[0091] refer to Figure 5 The first logic controller 211 includes a first adder 2111, a first register 2112, and a second register 2113. The first register 2112 is connected to both the first adder 2111 and the second register 2113. The function of the first logic controller 211 is to generate a first control signal.

[0092] The first adder 2111, under the action of an enable signal, adds the control word F and the most significant bits (e.g., 5 bits) stored in the first register 2112, and then saves the sum to the first register 2112 at the rising edge of the second clock frequency CLK2; alternatively, the first adder 2111 can add the control word F and all bits stored in the first register 2112 under the action of an enable signal, and then save the sum to the first register 2112 at the rising edge of the second clock frequency CLK2. At the next rising edge of the second clock frequency CLK2, the most significant bit stored in the first register 2112 will be stored in the second register 2113 as the selection signal for the first K→1 multiplexer 221, i.e., the aforementioned first control signal, used to select the I-th reference pulse output from K-channel reference pulses with uniformly spaced phases.

[0093] When adding the control word F and the most significant bit stored in the first register 2112, assuming the value in the first register 2112 is less than 1, if there is a carry-over in the fractional part of the addition result, the most significant bit stored in the second register 2113 is I+1. If no carry-over occurs in the control word during addition, the most significant bit stored in the second register 2113 is I. When the value in the second register 2113 is I+1, the pulse output circuit outputs T. B = (I+1)·Δ, when the value in the second register 2113 is I, the corresponding output of the pulse output circuit is T. A =I·Δ, which shows that the output T A Or T B The value is related to the size of the fractional part of the control word. The smaller the fractional part of the control word, the less likely a carry will occur, and the output will be T. A The higher the probability, the better; otherwise, output T. B The probability is high.

[0094] Here, the first register 2112 may include a first part for storing integers and a second part for storing decimals. During addition, the integer part of the control word F is added to the contents of the first part, and the decimal part of the control word F is added to the contents of the second part. The addition is a binary addition, implemented by an adder.

[0095] The second logic controller 212 includes a second adder 2121, a third register 2122, and a fourth register 2123. The third register 2122 is connected to both the second adder 2121 and the fourth register 2123. The function of the second logic controller 212 is to generate a second control signal.

[0096] The second adder 2121, under the action of the enable signal, adds the high-level parameter ζ and the most significant bit stored in the first register 2112, and then saves the sum to the third register 2122 at the rising edge of the second clock frequency CLK2. After saving the sum to the third register 2122, at the rising edge of the first clock frequency CLK1, the information stored in the third register 2122 is stored in the fourth register 2123 and used as the selection signal for the second K→1 multiplexer 222, i.e., the aforementioned second control signal, to select the J-th reference pulse output from the K reference pulses. The second clock frequency CLK2 is the signal obtained by passing the first clock frequency CLK1 through an NOT gate.

[0097] It should be noted that, in this embodiment of the application, the high-level parameter ζ is taken as an example where the input of the second adder 2121 includes a high-level parameter ζ. Optionally, the high-level parameter ζ in the input of the second adder 2121 can also be other parameters used to control T. HI_A and T HI_B The parameters are not limited in this embodiment.

[0098] refer to Figure 5The second processing circuit 22 includes a first K→1 multiplexer 221, a second K→1 multiplexer 222, and a 2→1 multiplexer 223. The first K→1 multiplexer 221 and the second K→1 multiplexer 222 each include multiple input terminals, control input terminals, and output terminals. The 2→1 multiplexer 223 includes a control input terminal, an output terminal, a first input terminal, and a second input terminal. The output of the first K→1 multiplexer 221 is connected to the first input of the 2→1 multiplexer 223, and the output of the second K→1 multiplexer 222 is connected to the second input of the 2→1 multiplexer 223. Multiple inputs of the first K→1 multiplexer 221 and multiple inputs of the second K→1 multiplexer 222 are connected to a signal generator. The control input of the first K→1 multiplexer 221 is connected to the second register 2113, and the control input of the second K→1 multiplexer 222 is connected to the fourth register 2123.

[0099] The control input terminal of the first K→1 multiplexer 221, under the control of the first control signal generated by the first logic controller 211, selects the I-th reference pulse from the K-channel reference pulses with uniformly spaced phases and outputs it; the control input terminal of the second K→1 multiplexer 222, under the control of the second control signal generated by the second logic controller 212, selects the J-th reference pulse from the K-channel reference pulses with uniformly spaced phases and outputs it.

[0100] Taking the first K→1 multiplexer as an example, when selecting the reference pulse, it can be selected according to the value stored in the second register 2113, that is, the value of the first control signal. For example, if the first control signal is 3, then the third reference pulse in the K uniformly spaced reference pulses is selected for output.

[0101] The 2→1 multiplexer 223 can select one of the I-th reference pulse from the output of the first K→1 multiplexer 221 and the J-th reference pulse from the output of the second K→1 multiplexer 222 as the output of the 2→1 multiplexer 223 at the rising edge of the first clock frequency CLK1. For example, it can start selecting the I-th reference pulse at the first rising edge until the second rising edge, start selecting the J-th reference pulse at the second rising edge until the third rising edge, and so on.

[0102] Since the 2→1 multiplexer selects from the outputs of two K→1 multiplexers, and the outputs of the two K→1 multiplexers are combined to form a new cycle, the first and second pulse signals from the outputs of the two K→1 multiplexers differ by an integer number of Δ, and there are two cases where the difference is I Δ and I+1 Δ, resulting in a T in the final pulse output by the pulse output circuit. A and T BTwo different cycles.

[0103] refer to Figure 5 The output circuit 23 includes a trigger circuit. The trigger circuit generates a pulse train. The trigger circuit includes a D flip-flop 231, a first inverter 232, and a second inverter 233. The D flip-flop 231 includes a data input terminal, a clock input terminal, and an output terminal. The first inverter 232 includes an input terminal and an output terminal. The second inverter 233 includes an input terminal and an output terminal. The clock input terminal of the D flip-flop 231 is connected to a 2→1 multiplexer 223, the data input terminal of the D flip-flop 231 is connected to the output terminal of the first inverter 232, and the output terminal of the D flip-flop 231 is connected to the input terminals of both the first inverter 232 and the second inverter 233. The output terminal of the D flip-flop 231 or the output terminal of the second inverter 233 can serve as the output terminal of the pulse output circuit, i.e., the terminal that generates the pulse to be calculated. Therefore, the pulse to be calculated output by the pulse output circuit is... Figure 5 The first clock frequency CLK1 or the second clock frequency CLK2.

[0104] In this embodiment of the disclosure, the first clock signal and the second clock signal are the first clock frequency CLK1 output by the pulse output circuit when different control words are input. Alternatively, the first clock signal and the second clock signal are the second clock frequency CLK2 output by the pulse output circuit when different control words are input.

[0105] The clock input of the D flip-flop 231 receives the output from the output of the 2→1 multiplexer 223 and outputs the first clock frequency CLK1 through the output terminal; the input of the first inverter 232 receives the first clock frequency CLK1 and outputs the output signal to the data input of the D flip-flop 231; the input of the second inverter 233 receives the first clock frequency CLK1 and outputs the second clock frequency CLK2 through the output terminal.

[0106] The pulse output circuit provided in this application embodiment can be called a fixed probability random number generator, such as a fixed probability random number generator based on a Time-Average-Frequency Direct Period Synthesis (TAF-DPS) circuit.

[0107] The phase difference Δ between any two adjacent reference pulses in the multi-path reference pulse system can be adjusted. When Δ is large, the power consumption of the random calculation circuit is low. When Δ is small, the calculation efficiency and performance of the random calculation circuit are high.

[0108] Furthermore, in the above embodiments, the random calculation circuit includes one pulse output circuit 02 as an example. Optionally, the random calculation circuit provided in this application embodiment may also include multiple pulse output circuits 02. In this case, the control circuit 01 is used to input the control parameters corresponding to each pulse output circuit 02 to each pulse output circuit 02. The control parameters corresponding to different pulse output circuits 02 may be the same or different, and this application embodiment does not limit this.

[0109] For example, consider a multi-pulse output circuit including: a first pulse output circuit 02A and a second pulse output circuit 02B. Figure 6 As shown, both the first pulse output circuit 02A and the second pulse output circuit 02B are connected to the control circuit 01 and the calculation circuit 03, respectively. The control circuit 01 inputs the corresponding control parameters to these two pulse output circuits. The first pulse output circuit 02A inputs a first pulse to be calculated to the calculation circuit 03, and the second pulse output circuit 02B inputs a second pulse to be calculated to the calculation circuit 03. The duty cycle of the first pulse to be calculated represents the first decimal number to be calculated, and the duty cycle of the second pulse to be calculated represents the second decimal number to be calculated. The calculation circuit 03 can perform logical calculations on the first and second decimal numbers to be calculated, for example... Figure 6 Taking the logic calculation including multiplication as an example, in this case, the calculation circuit 03 is an AND logic gate. When the AND logic gate performs logic calculations on the first decimal to be calculated and the second decimal to be calculated, it can multiply the first decimal to be calculated and the second decimal to be calculated.

[0110] Optionally, when multiple pulse output circuits include a first pulse output circuit and a second pulse output circuit, the first pulse to be calculated output by the first pulse output circuit is unrelated to the second pulse to be calculated output by the second pulse output circuit. For example, the first pulse to be calculated and the second pulse to be calculated are independent; when these two pulses are independent, they are unrelated.

[0111] It should be noted that in random computation, when multiple pulses to be computed are uncorrelated, the computation circuit performs logic computation based on the duty cycle of these multiple pulses, and the output logic computation result is relatively accurate. In this embodiment, the multiple pulses to be computed output by the multiple pulse output circuit include a first pulse and a second pulse. When the multiple pulses to be computed also include other pulses, these multiple pulses are also uncorrelated.

[0112] Optionally, when the first pulse to be calculated and the second pulse to be calculated are independent, the target parameters of the first pulse to be calculated and the target parameters of the second pulse to be calculated are coprime numbers; wherein, for any pulse to be calculated, the target parameter of the pulse to be calculated is q·I+p, where p / q equals the fractional part and I represents the integer part.

[0113] Assuming the first pulse to be calculated is X, and the second pulse to be calculated is Y, then the period T of X is... X =(q X ·I X +p X )Δ, the period T of Y Y =(q Y ·I Y +p Y )Δ; Assume (q X ·I X +p X )Δ=Iqp X ·Δ,(q Y ·I Y +p Y )Δ=Iqp Y ·Δ,Iqp X Iqp represents the target parameters of X. Y This represents the target parameters of Y.

[0114] When Δ is used as the time resolution, the set of values ​​for the elements in the time series represented by X is:

[0115] X i ={0,1}, X i Let X represent the i-th element in the time series, where 0 ≤ i ≤ Iqp. x -1.

[0116] When X is sampled using Y, the resulting time series space is as follows:

[0117] Ω X|Y ={Iqp Y .imodIqp X :i∈N}; where mod represents the modulo operation and N represents a natural number.

[0118] From the above set, it can be seen that when Iqp x and IQP y When they are coprime, Ω X and Ω X|Y Equal, that is

[0119] At this point, P(X=a)·P(Y)=P(ω) X ∈Ω X )·P(Y);

[0120] P(ω X ∈Ω X )·P(Y)=P(ω X ∈Ω X |ωY ∈Ω Y )·P(Y)=P(X|Y)·P(Y);

[0121]

[0122] Since P(X)·P(Y)=P(X∩Y), X and Y are independent. It can be seen that X and Y are independent when Iqpx and Iqpy are coprime. Therefore, in the embodiments of this application, the control word can be designed to make Iqpx and Iqpy coprime, thereby making X and Y independent and improving the accuracy of the logic calculation results output by the computing circuit.

[0123] Furthermore, such as Figure 7 As shown, the random calculation circuit provided in this embodiment further includes a sampling circuit 04 and a clock circuit 05. Both the calculation circuit 03 and the clock circuit 05 are connected to the sampling circuit 04. For example, the calculation circuit 03 is connected to the D terminal of the sampling circuit. The sampling circuit 04 is also connected to the control circuit 01. Figure 7 (The connection relationship is not shown in the diagram). Control circuit 01 is also used to input the target sequence length to sampling circuit 04, and clock circuit 05 is used to provide a clock signal to sampling circuit 04. Sampling circuit 04 is used to sample the calculation result output by calculation circuit 03 according to the clock signal and the target sequence length, to obtain a result sequence of the target sequence length, and outputs an indication signal of the duty cycle of the result sequence (e.g., outputting the indication signal from the Q terminal). For example, the indication signal can be all 1s (high level) and / or all 0s (low level) in the result sequence.

[0124] Figure 7 Using random computing circuits in Figure 1 In addition to the sampling circuit 04 and clock circuit 05, for example, when the random calculation circuit is in Figure 6 When the random calculation circuit includes sampling circuit 04 and clock circuit 05 in addition to the above, it can be used as follows: Figure 8 As shown.

[0125] It should be noted that the longer the sequence length, the higher the precision of the decimal representation. Therefore, the precision of the calculation result output by the calculation circuit 03 is positively correlated with the length of the result sequence (target sequence length) sampled by the calculation circuit 03. In this embodiment, the control circuit 01 can control the calculation circuit 03 to sample the result sequence of the target sequence length by inputting the target sequence length to the calculation circuit 03, thereby controlling the precision of the calculation result output by the calculation circuit 03. It is evident that the calculation precision (precision of the calculation result) of the random calculation circuit provided in this embodiment can be arbitrarily adjusted and is compatible with various calculation precisions. Furthermore, this random calculation circuit can achieve arbitrary calculation precision within a limited circuit area; therefore, the random calculation circuit has high area utilization and low cost.

[0126] The calculation accuracy of a random computing circuit refers to the ratio of the calculated difference to the theoretical calculation result. This calculated difference is the absolute value of the difference between the actual calculation result output by the random computing circuit and the theoretical calculation result.

[0127] Randomized computation, a computational paradigm proposed by John von Neumann, is characterized by numbers being represented by a bitstream that can be processed by very simple circuits. The numbers themselves are interpreted as probabilities—the probability that each bit in the bitstream is 1. According to Bernoulli's law of large numbers, probability can be estimated using frequency; that is, the probability of each bit being 1 can be represented by the proportion of 1s in the bitstream. For example, 1000 can represent 1 / 4, and 1100 can represent 1 / 2. In this embodiment, the pulse output circuit outputs a pulse (a bitstream) representing the decimal to be calculated. The computation circuit then performs random calculations based on this pulse. This randomized computation circuit possesses both analog (duty cycle) and digital (logic value) characteristics. Furthermore, as a digital circuit, it is easy to integrate and port, reducing development costs.

[0128] In addition, the random computing circuit can be part of the processor. In this case, the random computing circuit does not need to access memory during the calculation process. Therefore, the memory bandwidth will not affect the calculation efficiency of the random computing circuit.

[0129] In summary, in the random calculation circuit provided in this application embodiment, the pulse output circuit can output a pulse to be calculated, and the calculation circuit can perform logical calculations based on the duty cycle of the pulse to be calculated. When a bit in the pulse to be calculated is faulty, the duty cycle of the pulse to be calculated will not change significantly, and consequently, the result of the logical calculation will not change significantly. Therefore, the accuracy of the calculation result output by the calculation circuit is high.

[0130] Table 1 below shows... Figure 8 Two application examples of the random computation circuit shown, where FX F represents the control word of the control circuit input first pulse output circuit. Y This represents the control word for the second pulse output circuit of the control circuit. ζ X ζ represents the high-level parameter of the control circuit's input first pulse output circuit. Y This represents the high-level parameters of the control circuit's input second pulse output circuit. {I=2, p=17, q=64} X Let {I, p, q}, {I = 2, p = 57, q = 128} be the values ​​in the first pulse output circuit. Y Let {I, p, q} represent the second pulse output circuit. TAFX T represents the period of the first pulse to be calculated output by the first pulse output circuit. TAFY This indicates the period of the second pulse to be calculated output by the second pulse output circuit. (D) FD-X D represents the duty cycle (representing the decimal part to be calculated) of the first pulse output by the first pulse output circuit. FD-Y The duty cycle (representing the decimal part to be calculated) of the second pulse output circuit is indicated. The closer the correlation coefficient between the first and second pulses to be calculated is to 0, the less correlated the two pulses are. Table 1 shows that the correlation coefficients of these two pulses both approach 0. The result graph for Example 1 is shown below. Figure 9 As shown in the figure, the result of Example 2 is as follows. Figure 10 As shown in the figures, the horizontal axis in these two graphs represents the number of Δ values ​​corresponding to the target sequence length. It should be noted that the target sequence length has a corresponding duration; the sampling circuit obtains the result sequence of the target sequence length after sampling this duration, which is equal to the product of the number of Δ values ​​corresponding to the target sequence length and Δ.

[0131] Table 1

[0132]

[0133] This application provides a random calculation method, which can be used in any of the random calculation circuits provided in this application. For example... Figure 11 As shown, the method includes:

[0134] Step 1001: Input control parameters into the pulse output circuit using the control circuit. The control parameters include a control word with an integer part and a fractional part.

[0135] Step 1002: Using the pulse output circuit, the pulse to be calculated is input to the calculation circuit according to the control parameters and the multiple reference pulses with uniform phase intervals; wherein, the pulse to be calculated includes a first sub-pulse and a second sub-pulse arranged in the time domain, the period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and the probability of the first sub-pulse and the second sub-pulse appearing in the pulse to be calculated is controlled by the fractional part.

[0136] Step 1003: Use the calculation circuit to perform logic calculations based on the duty cycle of the pulse to be calculated, and output the calculation results of the logic calculations.

[0137] Optionally, the control parameters further include: a high-level parameter ζ; T HI_A =T HI_B =ζ·Δ;

[0138] T HI_A T represents the duration of the high level of the first sub-pulse; HI_B The duration of the high level of the second sub-pulse is indicated; ζ is an integer, and 1≤ζ≤I-1, where I represents the integer part; Δ represents the phase difference between any two adjacent reference pulses in the multi-path reference pulses.

[0139] Optionally, the random calculation circuit includes multiple pulse output circuits. Step 1001 includes: using the control circuit to input control parameters corresponding to each pulse output circuit. Step 1002 includes: using each pulse output circuit to input the pulse to be calculated to the calculation circuit according to the input control parameters and multiple reference pulses with uniform phase intervals.

[0140] Optionally, the plurality of pulse output circuits include: a first pulse output circuit for inputting a first pulse to be calculated to the computing circuit, and a second pulse output circuit for inputting a second pulse to be calculated to the computing circuit; the first pulse to be calculated and the second pulse to be calculated are unrelated.

[0141] Optionally, the first pulse to be calculated is independent of the second pulse to be calculated.

[0142] Optionally, the target parameters of the first pulse to be calculated and the target parameters of the second pulse to be calculated are coprime numbers;

[0143] For any of the pulses to be calculated, the target parameter of the pulse is q·I+p, where p / q is equal to the fractional part and I represents the integer part.

[0144] Optionally, the random calculation circuit further includes a sampling circuit and a clock circuit, wherein the calculation circuit and the clock circuit are both connected to the sampling circuit, and the sampling circuit is also connected to the control circuit;

[0145] The method further includes:

[0146] The target sequence length is input to the sampling circuit using the control circuit.

[0147] The clock circuit provides a clock signal to the sampling circuit.

[0148] The sampling circuit samples the calculation result output by the calculation circuit according to the clock signal and the target sequence length to obtain a result sequence of the target sequence length;

[0149] The sampling circuit outputs an indication signal of the duty cycle of the result sequence.

[0150] Optionally, the duration T of the pulse to be calculated FD =(qp)·T A +p·T B ;

[0151] p / q equals the fractional part; T A =I·Δ,T A The period of the first sub-pulse is represented by I, the integer part of the pulse, and Δ, which represents the phase difference between any two adjacent reference pulses in the multi-path reference pulses. B = (I+1)·Δ, T B This indicates the period of the second sub-pulse.

[0152] Optionally, p / q is the simplest form of the fractional part.

[0153] Optionally, the integer part is greater than 16.

[0154] Optionally, the pulse output circuit includes: a first processing circuit, a second processing circuit, and an output circuit, wherein the first processing circuit and the output circuit are both connected to the second processing circuit; step 1002 includes:

[0155] The first processing circuit outputs a first control signal and a second control signal according to the control parameters.

[0156] The second processing circuit selects the I-th reference pulse from the multiple reference pulses according to the first control signal, and selects the J-th reference pulse from the multiple reference pulses according to the second control signal, and selects one reference pulse from the I-th reference pulse and the J-th reference pulse as the output pulse, where 1≤I, 1≤J;

[0157] The output circuit outputs the pulse to be calculated based on the output pulse of the second processing circuit.

[0158] Optionally, the logical calculation includes at least one of addition, subtraction, multiplication, division, square root, and squaring.

[0159] The explanation of each of the above steps can be found in the corresponding descriptions in the above embodiments for random computing circuits, and will not be repeated in the method embodiments.

[0160] This application also provides a chip that includes any of the random computing circuits provided in this application. The chip can be a CPU, GPU, or other similar chip.

[0161] This application also provides an electronic device, which includes any of the chips provided in this application. The electronic device may be a computer.

[0162] In this disclosure, the terms “first,” “second,” etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term “multiple” refers to two or more unless otherwise expressly defined.

[0163] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0164] It should be noted that the different embodiments provided in this application can be referenced each other, and this application does not limit them. The order of the steps in the method embodiments provided in this application can be appropriately adjusted, and the steps can also be added or removed according to the situation. Any variations that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application, and therefore will not be described in detail.

[0165] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A stochastic computing circuit, comprising: The random computing circuit comprises a control circuit, a pulse output circuit and a computing circuit; the control circuit and the computing circuit are connected with the pulse output circuit; The control circuit is configured to input a control parameter to the pulse output circuit, and the control parameter comprises a control word having an integer part and a decimal part; The pulse output circuit is configured to input a to-be-computed pulse to the computing circuit according to the control parameter and a plurality of reference pulses with uniformly-spaced phases; the to-be-computed pulse comprises at least one of a first sub-pulse and a second sub-pulse arranged in a time domain, a period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and a probability of occurrence of the first sub-pulse and the second sub-pulse in the to-be-computed pulse is controlled by the decimal part; The computing circuit is configured to perform a logic computation according to a duty cycle of the to-be-computed pulse, and output a computation result of the logic computation.

2. The stochastic computing circuit of claim 1, wherein, The control parameter further comprises: a high level parameter ζ; T HI_A = T HI_B = ζ · Δ; T HI_A represents the duration of the high level of the first sub-pulse; T HI_B represents the duration of the high level of the second sub-pulse; ζ is an integer, and 1≤ζ≤I-1, I represents the integer part; Δ represents the phase difference between any two adjacent reference pulses in the multipath reference pulses.

3. The stochastic computing circuit of claim 1 or 2, wherein, The random computing circuit comprises a plurality of pulse output circuits; The control circuit is configured to input a control parameter corresponding to each pulse output circuit to each pulse output circuit.

4. The stochastic computing circuit of claim 3, wherein, The plurality of pulse output circuits comprise a first pulse output circuit configured to input a first to-be-computed pulse to the computing circuit, and a second pulse output circuit configured to input a second to-be-computed pulse to the computing circuit; The first to-be-computed pulse is irrelevant to the second to-be-computed pulse.

5. The stochastic computing circuit of claim 4, wherein, The first to-be-computed pulse is independent of the second to-be-computed pulse.

6. The stochastic computing circuit of claim 5, wherein, A target parameter of the first to-be-computed pulse and a target parameter of the second to-be-computed pulse are prime numbers to each other; For any to-be-computed pulse, the target parameter of the to-be-computed pulse is q·I+p, p / q is equal to the decimal part, and I represents the integer part.

7. The stochastic computing circuit of claim 1 or 2, wherein, The random computing circuit further comprises a sampling circuit and a clock circuit, the computing circuit and the clock circuit are connected to the sampling circuit, and the sampling circuit is further connected to the control circuit; The control circuit is further configured to input a target sequence length to the sampling circuit; The clock circuit is configured to provide a clock signal to the sampling circuit; The sampling circuit is configured to sample the computation result output by the computing circuit according to the clock signal and the target sequence length, to obtain a result sequence of the target sequence length; The sampling circuit is further configured to output an indication signal of a duty cycle of the result sequence.

8. The stochastic computing circuit of claim 1 or 2, wherein, the duration T of the pulse to be calculated FD = (q - p) - T A + p - T B ; p / q is equal to the decimal part; T A = I • Δ, T A denotes the period of the first sub-pulse, I denotes the integer part, and Δ denotes the phase difference of the reference pulses of any two adjacent ones of the plurality of reference pulses. T B = (I + 1) • Δ, T B denotes the period of the second sub-pulse.

9. The stochastic computing circuit of claim 8, wherein, p / q is the simplest approximation of the decimal part.

10. The stochastic computing circuit of claim 1 or 2, wherein, The integer part is greater than 16.

11. The stochastic computing circuit of claim 1 or 2, wherein, The pulse output circuit comprises a first processing circuit, a second processing circuit and an output circuit, the first processing circuit and the output circuit are connected with the second processing circuit; The first processing circuit is configured to output a first control signal and a second control signal according to the control parameter, respectively; The second processing circuit is configured to select an Ith reference pulse from the multiple reference pulses according to the first control signal, select a Jth reference pulse from the multiple reference pulses according to the second control signal, and select one reference pulse from the Ith reference pulse and the Jth reference pulse as an output pulse, 1≤I, 1≤J; The output circuit is configured to output the pulse to be calculated according to the output pulse of the second processing circuit.

12. The stochastic computing circuit of claim 1 or 2, wherein, The logic calculation includes at least one of addition, subtraction, multiplication, division, square root extraction, and squaring.

13. A method of random computation, characterized by, The method is used for the random calculation circuit of any one of claims 1 to 12, and the method comprises: The control circuit is configured to input a control parameter to the pulse output circuit, the control parameter comprising a control word having an integer part and a decimal part; The pulse output circuit is configured to input a pulse to be calculated to the calculation circuit according to the control parameter and multiple reference pulses that are uniformly spaced in phase, wherein the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse arranged in a time domain, a period of the first sub-pulse and the second sub-pulse is controlled by the integer part, and a probability of the first sub-pulse and the second sub-pulse appearing in the pulse to be calculated is controlled by the decimal part; The calculation circuit is configured to perform a logic calculation according to a duty cycle of the pulse to be calculated and output a calculation result of the logic calculation.

14. A chip, characterized by The chip comprises the random calculation circuit of any one of claims 1 to 12.

15. An electronic device, comprising: The electronic device comprises the chip of claim 14.

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