Instruction Processing Method, Instruction Execution Method, and Processor

Abstract

The present disclosure provides an instruction processing method, an instruction execution method, and a processor. The instruction processing method includes: obtaining an access address of an object instruction to an application stack in a decoding stage of the object instruction; and accessing the application stack by using the access address in an execution stage of the object instruction. The instruction processing method, the instruction execution method, and the processor can improve the performance of the processor and reduce the system power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction processing method, an instruction execution method, and a processor. Background Art

[0002] During the process of an application running in a computer system, code, stack, heap, and data segments are usually required. The code segment mainly stores the code in the executable file; the data segment stores data such as global variables and static variables in the program; the heap is the dynamic memory area of the program. For example, the memory obtained when the program uses malloc or new comes from the heap; the stack maintains the context of function calls, and it is impossible to implement function calls without the stack. Summary of the Invention

[0003] According to at least one embodiment of the present disclosure, an instruction processing method is provided, including: in the decoding stage of an object instruction, obtaining an access address of the object instruction to an application stack; in the execution stage of the object instruction, accessing the application stack using the access address.

[0004] For example, in the instruction processing method according to at least one embodiment of the present disclosure, the obtaining an access address of the object instruction to the application stack includes: determining whether a first stack top value is a valid value in the decoding stage of the object instruction; in response to the first stack top value being a valid value, using the first stack top value to obtain the access address, where the first stack top value is a value maintained by a decoding unit in a pipeline of a processor core for recording a stack pointer of the application stack.

[0005] For example, in the instruction processing method according to at least one embodiment of the present disclosure, the in response to the first stack top value being a valid value, using the first stack top value to obtain the access address includes: in response to the object instruction being a call instruction or a push instruction, using the first stack top value minus a system architecture parameter value to obtain the access address; or, in response to the object instruction being a ret or pop instruction, using the first stack top value as the access address; or, in response to the object instruction being an instruction that accesses the application stack and using an address encoding method that is the sum of the stack pointer and an immediate number, using the first stack top value plus the immediate number to obtain the access address.

[0006] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: in the decoding stage of the object instruction, obtaining a decoded instruction corresponding to the object instruction in combination with the access address; where the in the execution stage of the object instruction, accessing the application stack using the access address includes: using the access address to execute the decoded instruction to access the application stack.

[0007] According to at least one embodiment of the present disclosure, a processor is further provided, including:

[0008] A decoding unit configured to obtain, during the decoding stage of an object instruction, an access address of the object instruction to an application stack;

[0009] An execution unit configured to access the application stack using the access address during the execution stage of the object instruction.

[0010] For example, in a processor according to at least one embodiment of the present disclosure, the decoding unit is further configured to obtain, during the decoding stage of the object instruction, a decoded instruction corresponding to the object instruction; and the execution unit is further configured to execute the decoded instruction to access the application stack using the access address.

[0011] According to at least one embodiment of the present disclosure, an instruction processing method is further provided, including: maintaining, by a decoding unit of a pipeline of a processor core, a first stack top value for recording a stack pointer of an application stack, and providing the first stack top value for obtaining an access address to the application stack during the decoding unit of the pipeline of the processor core.

[0012] For example, in the instruction processing method according to at least one embodiment of the present disclosure, the maintaining, by a decoding unit of a pipeline of a processor core, a first stack top value for recording the stack pointer of the application stack includes: during the decoding stage of an object instruction, setting a first stack top value for recording the stack pointer of the application stack according to the content of the object instruction.

[0013] For example, in the instruction processing method according to at least one embodiment of the present disclosure, the setting a first stack top value for recording the stack pointer of the application stack according to the content of the object instruction includes: in response to the object instruction being an instruction for changing the stack pointer of the application stack, determining whether the object instruction belongs to a first type of instruction or a second type of instruction, where the first type of instruction is an instruction that directly uses the stack pointer for arithmetic operations to update the stack top value, and the second type of instruction is an instruction that does not directly use the stack pointer for arithmetic operations to update the stack top value; in response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction; in response to the object instruction belonging to the second type of instruction, setting the first stack top value to the initial value (0) of the stack pointer of the application stack, setting the validity of the first stack top value to invalid, and recording the instruction sequence number of the object instruction as the relevant instruction sequence number of the first stack top value.

[0014] For example, in the instruction processing method according to at least one embodiment of the present disclosure, in response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction includes: in response to the object instruction being a call instruction or a push instruction, using the first stack top value minus the system architecture parameter value to obtain the updated first stack top value; or, in response to the object instruction being a ret or pop instruction, using the first stack top value plus the system architecture parameter value to obtain the updated first stack top value; or, in response to the object instruction being an instruction that changes the stack pointer of the application stack and using an immediate number as the source operand, performing an operation on the first stack top value and the immediate number to obtain the updated first stack top value.

[0015] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: in response to the object instruction belonging to the second type of instruction, marking the object instruction as requiring feedback of a second stack top value corresponding to the stack pointer of the application stack obtained by executing the object instruction after the execution stage of the object instruction.

[0016] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: in response to the object instruction belonging to the second type of instruction, receiving the second stack top value, and in response to the instruction sequence number of the object instruction being the same as the relevant instruction sequence number of the current first stack top value, using the second stack top value to update the first stack top value.

[0017] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: during the execution stage of the object instruction, in response to the object instruction being marked as requiring feedback of the second stack top value, feeding back the second stack top value and the instruction sequence number of the object instruction to the decoding unit of the pipeline of the processor core after the object instruction is executed.

[0018] For example, in the instruction processing method according to at least one embodiment of the present disclosure, the decoding unit of the pipeline of the processor core maintains a first stack top value for recording the stack pointer of the application program stack, and further includes: in the decoding stage of the object instruction, receiving a second stack top value corresponding to the stack top value of the application program stack provided by the instruction execution unit of the pipeline of the processor core, and in response to a pipeline flush of the processor core, setting the first stack top value to the second stack top value; in response to no pipeline flush of the processor core, further receiving the instruction sequence number of the executed instruction that generates the second stack top value provided by the instruction execution unit, and in response to the instruction sequence number of the executed instruction being the same as the relevant instruction sequence number of the first stack top value, setting the first stack top value with the second stack top value and setting the validity of the first stack top value to valid, where the relevant instruction sequence number of the first stack top value refers to the instruction sequence number of the latest prior instruction that modifies the stack pointer of the application program stack recorded before the decoding stage of the object instruction.

[0019] According to at least one embodiment of the present disclosure, there is also provided a processor including a decoding unit, where the decoding unit is configured to: maintain a first stack top value for recording the stack pointer of the application program stack, and provide the first stack top value for obtaining an access address to the application program stack in the decoding unit.

[0020] According to at least one embodiment of the present disclosure, there is also provided an instruction execution method, including: in response to a pipeline flush of the processor core, providing the stack top value of the stack pointer of the application program stack obtained after the pipeline flush of the processor core to the decoding unit of the pipeline of the processor core; in response to no pipeline flush of the processor core, executing the decoded instruction of the object instruction and providing the stack top value of the stack pointer of the application program stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core, where the object instruction is marked as needing to feedback the stack top value of the stack pointer of the application program stack after being executed.

[0021] For example, the instruction execution method according to at least one embodiment of the present disclosure further includes: in response to no pipeline flush of the processor core, providing the instruction sequence number of the object instruction to the decoding unit of the pipeline of the processor core.

[0022] For example, in the instruction execution method according to at least one embodiment of the present disclosure, in response to a pipeline flush of a non-occurring processor core, executing the decoded instruction of the object instruction and providing the top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core includes: in response to the object instruction being the latest currently distributed instruction marked as needing to feedback the top value of the stack pointer of the application stack after execution, executing the decoded instruction of the object instruction and providing the top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core.

[0023] For example, the instruction execution method according to at least one embodiment of the present disclosure further includes: in the instruction distribution stage, recording the latest currently distributed instruction marked as needing to feedback the top value of the stack pointer of the application stack after execution.

[0024] According to at least one embodiment of the present disclosure, there is also provided a processor, including an execution unit and a decoding unit, wherein the execution unit is configured to: in response to a pipeline flush of a processor core occurring, provide the top value of the stack pointer of the application stack obtained after the pipeline flush of the processor core to the decoding unit; in response to a non-occurring pipeline flush of the processor core, execute the decoded instruction of the object instruction and provide the top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit, wherein the object instruction is marked as needing to feedback the top value of the stack pointer of the application stack corresponding to the execution of the object instruction after the execution stage of the object instruction.

[0025] For example, in the processor according to at least one embodiment of the present disclosure, the execution unit is further configured to: in response to a non-occurring pipeline flush of the processor core, provide the instruction sequence number of the object instruction to the decoding unit.

[0026] For example, in the processor according to at least one embodiment of the present disclosure, the execution unit is further configured to: in response to the object instruction being the latest currently distributed instruction marked as needing to feedback the top value of the stack pointer of the application stack after execution, execute the decoded instruction of the object instruction and provide the top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core.

[0027] For example, the processor according to at least one embodiment of the present disclosure further includes an instruction distribution unit, wherein the instruction distribution unit is configured to record the latest currently distributed instruction marked as needing to feedback the top value of the stack pointer of the application stack after execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0029] Figure 1 Shows a schematic diagram of application program virtual memory allocation;

[0030] Figure 2 Shows a schematic diagram of a pipeline of a processor core;

[0031] Figure 3 Shows a pipeline of a processor core provided according to at least one embodiment of the present disclosure;

[0032] Figure 4 Shows a schematic diagram of an example of a cache DESP according to at least one embodiment of the present disclosure;

[0033] Figure 5 Shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure;

[0034] Figure 6 Shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure;

[0035] Figure 7 Shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure;

[0036] Figure 8 Shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure;

[0037] Figure 9A Shows an example of an arithmetic unit for obtaining the access address of an application program stack according to an embodiment of the present disclosure; and

[0038] Figure 9B Shows an example of an arithmetic unit for maintaining the current stack top value in the decoding stage according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] The data address space of each application program running in a computer system includes a stack and a heap, which are defined by the Application Binary Interface (ABI). Figure 1 A schematic diagram of virtual memory allocation for an application program is shown.

[0042] As Figure 1 As shown, the application program stack is automatically allocated and released by the operating system and is used to store function parameter values, register values, local variable values, etc. The operation mode of the stack is similar to that of a stack in a normal data structure, adopting the Last In First Out (LIFO) method. Data can only be read from and written to the top of the stack. Therefore, the stack can be identified by only one stack pointer (SP) to indicate the current top position of the stack (the top value of the stack), and this top value is stored in the top-of-stack register. For the stack, there are the following two basic operations:

[0043] ● Push: Adjust the value of the top-of-stack register (i.e., the top value of the stack) and write data at the new top of the stack;

[0044] ● Pop: Take out data from the top of the stack and adjust the value of the top-of-stack register.

[0045] When a program calls a function, the return address is pushed onto the stack; after the function execution is completed, the return address is taken out (ret) from the stack, and then the program jumps to this address to continue execution.

[0046] Another function of the application program stack is to cache the values of registers, which enables these registers to be used in different functions.

[0047] In some hardware architectures, the application stack grows from the high address to the low address, such as the X86-64 (64-bit X86) hardware architecture. At the same time, each push / pop operation in X86-64 is 64 bits (i.e., 8 bytes), so a push operation subtracts 8 from the top value of the stack, and a pop operation adds 8 to the top value of the stack.

[0048] Figure 2 FIG. shows a schematic diagram of a pipeline of a processor core. The dashed lines with arrows in the figure represent the redirected instruction flow. As shown, the processor core of a single-core processor or a multi-core processor (e.g., a CPU core) improves the instruction-level parallelism through pipeline technology. Inside the processor core, there are multiple pipeline stages. For example, after the program counter from various sources is fed into the pipeline and the next program counter (PC) is selected through a multiplexer (Mux), the instruction corresponding to the program counter has to go through branch prediction, instruction fetch, instruction decode, instruction dispatch and rename, instruction execution, instruction retirement, etc. Waiting queues are set up between the respective pipeline stages as needed, and these queues are usually first-in-first-out (FIFO) queues. For example, after the branch prediction unit, there is a branch prediction (BP) FIFO queue to store the branch prediction results; after the instruction fetch unit, there is an instruction cache (Instruction Cache, IC) FIFO to cache the fetched instructions; after the instruction decode unit, there is a decode (DE) FIFO to cache the decoded instructions; after the instruction dispatch and rename unit, there is a retirement (RT) FIFO to cache the instructions waiting for confirmation of retirement after execution. At the same time, the pipeline of the processor core also includes an instruction queue to cache the instructions waiting for the instruction execution unit to execute after instruction dispatch and rename. To support a high operating frequency, each pipeline stage may in turn contain multiple pipeline levels (clock cycles). Although each pipeline level performs limited operations, in this way each clock can be made the shortest, and the performance of the CPU core is improved by increasing the operating frequency of the CPU. Each pipeline level can also further improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology).

[0049] The processor core within the microarchitecture translates each architectural instruction into one or more micro-operations (uOps), with each micro-operation performing only limited operations, ensuring that each pipeline stage is very short, thus increasing the operating frequency of the processor core. For example, a memory load instruction can be translated into an address generation micro-operation and a memory read micro-operation. The second micro-operation depends on the result of the first one. Therefore, the second micro-operation will not start until the first one has been completed. Micro-operations contain multiple microarchitecture-related fields for passing relevant information between pipeline stages.

[0050] Speculative Execution is another technique for improving processor performance. This technique executes the instructions following an instruction before it has completed execution. The branch prediction unit (branch predictor) at the front end of the processor core predicts the jump direction of branch instructions, prefetches and executes the instructions in that direction. Another speculative execution technique is to execute a memory read instruction before the addresses of all previous memory write instructions have been obtained. Speculative Execution further increases the instruction-level parallelism, thus significantly improving the performance of the processor core. When a speculative execution error occurs, such as a branch prediction error being detected, or a write instruction before the memory read instruction overwriting the same address, all the instructions in the pipeline after the faulty instruction need to be flushed (or "cleared"), and then the program jumps back to the error point to be re-executed to ensure the correct execution of the program. To support speculative execution, the microarchitecture of the processor core also needs to support an architectural register recovery mechanism to ensure that the architectural registers always have the correct values during speculative execution.

[0051] The memory access addresses of many memory access instructions are dynamically generated using one or more registers. The processor core may contain separate execution stage hardware (called AGEN) for performing these address calculations. A memory access instruction can only start its memory access operation after obtaining its address through AGEN, which increases the latency of these instructions. Some instruction sets support multiple complex address generation methods, such as X86-64, whose AGEN is also more complex, consuming more power and taking multiple clock cycles to obtain the result. Additionally, many instructions include an immediate value (imm) in the instruction data as an offset for address generation.

[0052] The Application Binary Interface (ABI) defines the software call interface, which includes specifications for the use of the application stack. Generally, data on the application stack is only added or removed at the top of the stack, and only one stack top register (such as the RSP register in X86-64) is needed to identify the top position of the application stack.

[0053] For example, there are often dedicated instructions for accessing the application stack, such as the call, ret, push, and pop instructions in X86-64. As described above, the call and push instructions first increment the stack top position and then push new data onto the stack; the ret / pop instructions read data from the stack top and then retreat the stack top position. In addition, the call and ret instructions can also include instruction flow jump operations. In addition, normal memory read and write instructions can also be used to access data at any position in the application stack, and these application stack read and write operations often use the stack top register as one of the sole or multiple address calculation registers.

[0054] In a high-performance, multi-pipeline-stage processor core, memory read and write instructions often require multiple pipeline stages to obtain their data, and their address generation is part of the reason for long latency. For the access to the above-mentioned application stack, whether it is operated through dedicated instructions or ordinary memory access instructions, its address generation is also dynamically generated during the instruction execution stage and requires the use of AGEN and at least one clock cycle to complete.

[0055] The inventors of the present disclosure have noticed that due to the characteristics of the application stack, its access rules are relatively simple. Utilizing these rules to obtain the access addresses for the application stack in advance can reduce the latency of these instructions, thereby further improving the performance of the processor; moreover, this can also reduce the power consumption caused by accessing the register file and using AGEN.

[0056] Specifically, the inventors of the present disclosure have observed the following phenomena and accordingly proposed the technical solutions of at least one embodiment of the present disclosure. Due to the characteristics of the application stack, most of the read / write operations on the application stack and the changes to the value of the stack top register (stack top value) occur near the current stack top position, which means:

[0057] (1) For most instructions that change the stack top value of the application stack, their offset values can be obtained during the decoding stage, so that the current stack top value can be updated during the decoding stage.

[0058] (2) Many access addresses for reading and writing the application stack use fixed offsets (for example, the call / push offset value in X86-64 is 8, and the ret / pop offset value is 0), or use offsets saved in the instruction immediate value.

[0059] Based on the above observations, in at least one embodiment of the present disclosure, the current stack top value at this stage (abbreviated as SP@DE) of the instruction decoding stage is maintained, and this current stack top value is used to obtain the access addresses of application stack specific instructions (such as call / ret / push / pop in X86-64) and some ordinary memory read / write instructions that access the application stack during the instruction decoding stage. Therefore, these instructions can avoid address generation, register file and AGEN access during the instruction execution stage and the corresponding latency, thereby improving the processor performance and reducing the system power consumption.

[0060] According to at least one embodiment of the present disclosure, there is provided an instruction processing method, including: during the decoding stage of an object instruction, obtaining the access address of the object instruction to the application stack; during the execution stage of the object instruction, accessing the application stack using the access address.

[0061] According to at least one embodiment of the present disclosure, there is also provided a processor, including:

[0062] A decoding unit configured to obtain the access address of an object instruction to the application stack during the decoding stage of the object instruction;

[0063] An execution unit configured to access the application stack using the access address during the execution stage of the object instruction.

[0064] According to at least one embodiment of the present disclosure, there is also provided an instruction processing method, including: maintaining, by a decoding unit in a pipeline of a processor core, a first stack top value for recording a stack pointer of an application stack, and providing the first stack top value for obtaining an access address to the application stack in the decoding unit of the pipeline of the processor core.

[0065] According to at least one embodiment of the present disclosure, there is also provided a processor including a decoding unit, wherein the decoding unit is configured to: maintain a first stack top value for recording a stack pointer of an application stack, and provide the first stack top value for obtaining an access address to the application stack in the decoding unit.

[0066] According to at least one embodiment of the present disclosure, there is also provided an instruction execution method, including: in response to a pipeline flush of a processor core, providing the stack top value of the stack pointer of the application stack obtained after the pipeline flush of the processor core to the decoding unit of the pipeline of the processor core; in response to no pipeline flush of the processor core, executing the decoded instruction of the object instruction and providing the stack top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core, wherein the object instruction is marked as needing to feedback the stack top value of the stack pointer of the application stack after being executed.

[0067] According to at least one embodiment of the present disclosure, a processor is further provided, including an execution unit and a decoding unit. Wherein, the execution unit is configured to: in response to a pipeline flush of the processor core occurring, provide the top value of the stack pointer of the application program stack obtained after the pipeline flush of the processor core to the decoding unit; in response to no pipeline flush of the processor core occurring, execute the decoded instruction of the target instruction and provide the top value of the stack pointer of the application program stack obtained by the execution of the target instruction to the decoding unit, wherein the target instruction is marked as needing to feedback the top value of the stack pointer of the application program stack corresponding to the execution of the target instruction after the execution stage of the target instruction.

[0068] The instruction processing method or processor provided by at least one embodiment of the present disclosure considers at least one of the following aspects to achieve the optimization of the processor core:

[0069] (1) In a multi-stage pipelined processor core, the top value (abbreviation: SP@EX) of the stack pointer updated (or generated) in the instruction execution stage is often different from the current top value (SP@DE) maintained in the instruction decoding stage, because there may be multiple instructions that change the SP in the pipeline stages between these two stages;

[0070] (2) Obtain the addresses of the application program stack access instructions in the instruction decoding stage, and in the corresponding cases where no address generation is required, decode them into access instructions for the application program stack, and execute these access instructions in the execution stage.

[0071] The instruction processing method of at least one embodiment of the present disclosure classifies the target instructions into the following two types in the decoding stage:

[0072] (1) Instructions that change the top value (SP value)

[0073] (a) Simple instructions that change the SP value (Simple SP Instruction). These instructions include call / ret / push / pop instructions, which increase or decrease the SP value by a fixed value defined by the processor core architecture (hereinafter referred to as "architecture parameter value"), such as 8 or 4 bytes. This type of instruction also includes increasing / decreasing the SP value by an immediate number (such as addSP, 0x30 increases the SP value by 48), and this immediate number (imm) is included in the corresponding instruction, so it can be obtained in the decoding stage. For these instructions, the SP value can be updated using arithmetic operations in the instruction decoding stage. For example, an adder can be used to update the SP value.

[0074] (b) Complex instructions that change the SP value. These instructions include all other instructions that change the SP value in addition to the simple instructions that change the SP value described above. These complex instructions use other registers or require more complex operations and cannot update the SP value using only one adder. The SP value modified by these complex instructions must be obtained through AGEN during the execution stage and then passed back to the instruction decoding stage. When these instructions are decoded into micro-instructions during the decoding stage, these micro-instructions are marked (passed through the parameter NeedSP value as described below) so that the updated SP value can be passed back to the instruction decoding stage after these micro-instructions are executed.

[0075] (2) Instructions for accessing the application stack

[0076] (a) Simple instructions for accessing the application stack (Simple SP Load / Store). These instructions include call / ret / push / pop instructions and other read / write instructions using the "SP + immediate value" address encoding. For example, at least some embodiments of the present disclosure optimize the execution process of these instructions.

[0077] (b) Complex instructions for accessing the application stack. These instructions are other instructions for accessing the application stack in addition to the simple instructions for accessing the application stack described above. They may not use the SP register or may use multiple register values to calculate the memory access address.

[0078] In at least some embodiments of the present disclosure, an object instruction can be both a simple instruction that changes the SP value and a simple instruction that accesses the application stack, such as call / ret / push / pop instructions. For call / push instructions, the access address to the application stack is equal to the new SP@DE value, which is equal to the current SP@DE value minus the architecture parameter value (e.g., 8 bytes) respectively. For ret / pop instructions, the access address to the application stack is equal to the current SP@DE value, while the new SP@DE value is incremented by the architecture parameter value (e.g., 8 bytes).

[0079] Figure 3 Fig. shows a pipeline of a processor core provided according to at least one embodiment of the present disclosure. The dashed line with an arrow in the figure represents the redirected instruction flow. The processor core can be a single-core processor or a processor core of a multi-core processor (e.g., a CPU core). For example, the processor core improves the instruction-level parallelism through pipeline technology, but the embodiments of the present disclosure are not limited thereto.

[0080] For example, the processor core internally includes multiple pipeline stages. For instance, after the next program counter (PC) is fed into and selected in the pipeline, the instruction corresponding to the program counter needs to go through branch prediction, instruction fetch, decode, dispatch and rename, execute, retire, etc. Waiting queues are set between the respective pipeline stages as needed, and these queues are typically first-in-first-out (FIFO) queues.

[0081] Compared with Figure 2 the pipeline of the processor core provided by at least one embodiment of the present disclosure further includes a cache DESP for recording the current stack top value SP@DE in the decode stage. The cache DESP can be implemented by means of registers, etc. For example, the cache can be set in the instruction decode unit or can be set separately, and the embodiments of the present disclosure do not limit this.

[0082] In the embodiments of the present disclosure, in addition to recording SP@DE, other attributes of this value, such as validity, etc., can be further recorded. For example, Figure 4 shows an example of the cache DESP. As Figure 4 shown, the cache DESP includes the following 3 fields:

[0083] ● The SP@DE field, for example, with a length of N bits (N-bits). SP@DE stores the current stack top position (i.e., the stack top value) in the instruction decode stage. For example, N is the number of virtual address bits supported by the current architecture (a positive integer). For example, the X86-64 processor core can support 48-bit virtual addresses, and at this time N = 48.

[0084] ● The Valid field, for example, with a length of 1 bit (1-bit). When Valid is 1, it indicates that the validity of SP@DE is valid, that is, the value in SP@DE is a valid stack top value; when Valid is 0, it indicates that the validity of SP@DE is invalid. For example, the value in SP@DE is -1 or the difference between SP@DE and SP@EX.

[0085] ● The SN field, for example, with a length of M bits (M-bits). SN is used to record the instruction sequence number of the most recent architecture instruction / micro-instruction (hereinafter collectively referred to as "instruction") marked with the NeedSP flag. An instruction marked with the NeedSP flag means that after an instruction is executed, the generated stack top value needs to be passed back to the decode stage of the pipeline.

[0086] For example, a processor core may identify each instruction in a pipeline to implement functions such as debugging, and this identification is generated in the decoding stage. Therefore, embodiments of the present disclosure may use this identification of the instruction to record the NeedSP identification. The size of this identification only needs to be sufficient to record all instructions in the pipeline. For example, an 8-bit SN can represent 256 instructions, and at this time M is equal to 8. The SN field in the cache DESP only records the instruction sequence number of the most recently marked instruction with the NeedSP identification. Therefore, the previously recorded old instruction sequence numbers are always replaced by the newly recorded ones.

[0087] Embodiments of the present disclosure are not limited to reusing the above-mentioned identification for debugging in instructions. Instead, a field of, for example, 1 bit (1-bit) may be additionally added to each architecture instruction / micro-instruction to mark the NeedSP identification. The NeedSP identification can be set by an instruction decoding unit to notify the SP value updated in the execution stage (SP@EX) to be passed back to the instruction decoding unit. The SP value updated in the execution stage (SP@EX) can be passed through an existing or separately set data transmission path.

[0088] For example, compared with Figure 2 as Figure 3 shown, the pipeline of the processor core provided by at least one embodiment of the present disclosure further includes a data path for passing the executed message from the instruction execution unit to the decoding unit (as shown by the arrow implementation in the figure) to pass the SP value updated in the execution stage (SP@EX) and the instruction sequence number (INST_SN) of the instruction that generates the SP value updated in the execution stage (SP@EX).

[0089] In embodiments of the present disclosure, for the SP@DE value, in addition to setting the above-mentioned Valid and / or SN attributes, other attributes may also be provided, and embodiments of the present disclosure do not limit this.

[0090] Meanwhile, Figure 4 it is also shown that in at least one embodiment of the present disclosure, the initial values of the above-mentioned Valid, SP@DE, and SN are 0, -1, and 0 respectively, and embodiments of the present disclosure do not limit this. The scenarios where these initial values need to be set will be specifically described below.

[0091] At least one embodiment of the present disclosure provides an instruction processing method, including: in the decoding stage of an object instruction, obtaining the access address of the object instruction to the application stack; in the execution stage of the object instruction, accessing the application stack using the access address. Here, the "object instruction" refers to the instruction currently being processed in this method.

[0092] In at least one example, obtaining an access address for an object instruction to an application stack includes: determining whether a first stack top value is a valid value during the decoding stage of the object instruction; and in response to the first stack top value being a valid value, obtaining the access address using the first stack top value. Here, the "first stack top value" is a value maintained by the decoding unit of the pipeline of the processor core for recording the stack pointer of the application stack, that is, the current stack top value (SP@DE) during the decoding stage.

[0093] In at least one example, in response to the first stack top value being a valid value, obtaining the access address using the first stack top value includes:

[0094] ● In response to the object instruction being a call instruction or a push instruction, obtaining the access address by subtracting the system architecture parameter value from the first stack top value; or

[0095] ● In response to the object instruction being a ret or pop instruction, using the first stack top value as the access address; or

[0096] ● In response to the object instruction being an instruction that accesses the application stack and uses the sum of the stack pointer and an immediate number for address encoding, obtaining the access address by adding the immediate number to the first stack top value.

[0097] In at least one example, the instruction processing method of the above embodiments of the present disclosure further includes: during the decoding stage of the object instruction, obtaining a decoded instruction corresponding to the object instruction in combination with the access address. And during the execution stage of the object instruction, accessing the application stack using the access address includes: using the access address to execute the decoded instruction to access the application stack.

[0098] In the above embodiments of the present disclosure, by using the current stack top value (i.e., the first stack top value, SP@DE) during the instruction decoding stage, obtaining the access address for the object instruction to access the application stack during the instruction decoding stage, and then using this access address to access the application stack during the instruction execution stage, it is possible to eliminate address generation, register file and AGEN access during the instruction execution stage and the corresponding time delays, thereby improving the processor performance and reducing the system power consumption.

[0099] Figure 5 FIG. shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure, which is used to obtain an access address for accessing an application stack during the decoding stage. As Figure 5 shown, the instruction processing method includes the following steps 500 to 508:

[0100] Step 500: Enter the instruction decoding stage of the object instruction.

[0101] Step 501: Determine whether the object instruction is a simple instruction for accessing the application stack. If not, end the process of this method; otherwise, proceed to Step 502.

[0102] Step 502: Determine whether the validity of the current top-of-stack value (SP@DE) in the decoding stage is valid (for example, whether the value of Valid is 1). If it is invalid, end the process of this method; otherwise, proceed to Step 503.

[0103] Step 503: Determine whether the object instruction is a call or push instruction. If so, proceed to Step 504; otherwise, proceed to Step 505.

[0104] Step 504: Obtain the access address Addr by subtracting the system architecture parameter value (S) from the current top-of-stack value (SP@DE), i.e., Addr = SP@DE - S.

[0105] Step 505: Determine whether the object instruction is a ret or pop instruction. If so, proceed to Step 506; otherwise, proceed to Step 507.

[0106] Step 506: Obtain the access address Addr by adding the system architecture parameter value (S) to the current top-of-stack value (SP@DE), i.e., Addr = SP@DE + S.

[0107] Step 507: Obtain the access address by adding the immediate value (inst_imm) included in the object instruction as the source operand to the current top-of-stack value (SP@DE), i.e., Addr = SP@DE + inst_imm.

[0108] Step 508: Obtain the decoded instruction of the object instruction in combination with the access address (Addr).

[0109] In Step 508, the decoded instruction itself will include the access address, and this decoded instruction will be executed in the execution stage of the object instruction. Thus, using this access address to access the application stack can improve the processor performance and reduce the system power consumption.

[0110] Corresponding to the above instruction execution method, at least one embodiment of the present disclosure further provides a processor, including a decoding unit and an execution unit. The decoding unit is configured to obtain the access address of the object instruction for the application stack in the decoding stage of the object instruction; the execution unit is configured to access the application stack using the access address in the execution stage of the object instruction.

[0111] In at least one example, in this processor, the decoding unit is further configured to obtain the decoded instruction corresponding to the object instruction in the decoding stage of the object instruction; the execution unit is further configured to execute the decoded instruction to access the application stack using the access address.

[0112] According to requirements, refer to Figure 3 , the processor of the above embodiment may further include, but is not limited to, structures such as branch prediction, instruction fetch, dispatch and rename, and retire. The embodiments of the present disclosure do not limit this.

[0113] At least one embodiment of the present disclosure also provides an instruction processing method, including: maintaining, by a decoding unit of a pipeline of a processor core, a first stack top value for recording a stack pointer of an application stack, and providing the first stack top value for obtaining an access address to the application stack through the decoding unit of the pipeline of the processor core.

[0114] In the instruction processing method of this embodiment, by maintaining, through the decoding unit of the pipeline of the processor core, a first stack top value for recording the stack pointer of the application stack, that is, maintaining the current stack top value (SP@DE) in the decoding stage, so that the current stack top value in the decoding stage can be correctly used to obtain the access address to the application stack, enabling the object instruction to be correctly executed in the execution stage.

[0115] Here, similarly, the "first stack top value" refers to the current stack top value in the decoding stage, and the "object instruction" refers to the instruction currently being processed in this method.

[0116] In at least one example, maintaining, by a decoding unit of a pipeline of a processor core, a first stack top value for recording a stack pointer of the application stack includes: in the decoding stage of the object instruction, setting the first stack top value for recording the stack pointer of the application stack according to the content of the object instruction.

[0117] In at least one example, setting the first stack top value for recording the stack pointer of the application stack according to the content of the object instruction includes: in response to the object instruction being an instruction for changing the stack pointer of the application stack, determining whether the object instruction belongs to a first type of instruction or a second type of instruction, where the first type of instruction is an instruction that directly uses the stack pointer for arithmetic operations to update the stack top value (for example, corresponding to the simple instruction for changing the SP value mentioned above), and the second type of instruction is an instruction that does not directly use the stack pointer for arithmetic operations to update the stack top value (for example, corresponding to the complex instruction for changing the SP value mentioned above). In response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction; in response to the object instruction belonging to the second type of instruction, setting the first stack top value to the initial value of the stack pointer of the application stack (for example, 0), setting the validity of the first stack top value to invalid, and recording the instruction sequence number of the object instruction as the relevant instruction sequence number of the first stack top value.

[0118] In at least one example, in response to an object instruction belonging to a first type of instruction, updating a first stack top value according to the content of the object instruction includes:

[0119] ● In response to the object instruction being a call instruction or a push instruction, obtaining an updated first stack top value by subtracting a system architecture parameter value from the first stack top value; or

[0120] ● In response to the object instruction being a ret or pop instruction, obtaining an updated first stack top value by adding a system architecture parameter value to the first stack top value; or

[0121] ● In response to the object instruction being an instruction that changes the stack pointer of the application stack and using an immediate number as a source operand, obtaining an updated first stack top value by performing an operation on the first stack top value and the immediate number.

[0122] In at least one example, the instruction processing method of this embodiment further includes: in response to the object instruction belonging to a second type of instruction, marking the object instruction as requiring feedback of a second stack top value corresponding to the stack pointer of the application stack obtained after the execution of the object instruction after the execution stage of the object instruction. Here, the "second stack top value" is used to refer to the stack top value of the application stack updated in the execution stage (i.e., SP@EX).

[0123] In at least one example, the instruction processing method of this embodiment further includes: in response to the object instruction belonging to a second type of instruction, receiving the second stack top value, and in response to the instruction sequence number of the object instruction being the same as the relevant instruction sequence number of the first stack top value currently, updating the first stack top value with the second stack top value.

[0124] In at least one example, the instruction processing method of this embodiment further includes: in the execution stage of the object instruction, in response to the object instruction being marked as requiring feedback of the second stack top value, feeding back the second stack top value and the instruction sequence number of the object instruction to the decoding unit of the pipeline of the processor core after the object instruction is executed.

[0125] In at least one example, maintaining a first stack top value for recording the stack pointer of the application stack by the decoding unit of the pipeline of the processor core further includes: in the decoding stage of the object instruction, receiving a second stack top value corresponding to the stack pointer of the application stack provided by the instruction execution unit of the pipeline of the processor core, and

[0126] ● In response to a pipeline flush of the processor core occurring, setting the first stack top value to the second stack top value,

[0127] ● In response to a pipeline flush of a non-occurring processor core, also receive the instruction sequence number of the executed instruction that generates the second stack top value provided by the instruction execution unit, and in response to the instruction sequence number of the executed instruction being the same as the relevant instruction sequence number of the first stack top value, set the first stack top value using the second stack top value, and set the validity of the first stack top value to valid, where the relevant instruction sequence number of the first stack top value refers to the instruction sequence number of the latest prior instruction that modifies the stack pointer of the application stack recorded before the decoding stage of the object instruction.

[0128] Figure 6 FIG. shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure. The instruction processing method is used to maintain the current stack top value (SP@DE) in the decoding stage during the decoding stage. As Figure 6 shown, the instruction processing method includes the following steps 600 to 610:

[0129] Step 600: Enter the instruction decoding stage of the object instruction.

[0130] Step 601: Determine whether the current stack top value (SP@DE) in the decoding stage is the initial value (e.g., -1). If not, proceed to step 602; otherwise, proceed to step 609.

[0131] The current stack top value (SP@DE) in the decoding stage being the initial value corresponds to a situation such as when an application starts execution or when a process switch occurs.

[0132] Step 602: Determine whether the object instruction is an instruction that changes the SP. If so, proceed to step 603; otherwise, end the process flow of the method.

[0133] Step 603: Determine whether the object instruction is a simple instruction that changes the SP. If so, proceed to step 604; otherwise, proceed to step 609.

[0134] Step 604: Determine whether the object instruction is a call or push instruction. If so, proceed to step 605; otherwise, proceed to step 606.

[0135] Step 605: Use the current stack top value (SP@DE) minus the system architecture parameter value (S) to obtain the updated current stack top value, i.e., SP@DE = SP@DE - S.

[0136] Step 606: Determine whether the object instruction is a ret or pop instruction. If so, proceed to step 607; otherwise, proceed to step 608.

[0137] Step 607: Use the current stack top value (SP@DE) plus the system architecture parameter value (S) to obtain the updated current stack top value, i.e., SP@DE = SP@DE + S.

[0138] Step 608: Obtain the updated current stack top value by adding the current stack top value (SP@DE) to the immediate value (inst_imm) included in the object instruction as the source operand, i.e., SP@DE = SP@DE + inst_imm.

[0139] Step 609: Set the current stack top value (SP@DE) to the initial value (e.g., 0), set the validity of the current stack top value to valid (Valid = 1), and set the SN field of the current stack top value to the instruction sequence number of the object instruction.

[0140] Step 610: Label the object instruction to require feedback of the latest stack top value (i.e., SP@EX) corresponding to the stack pointer of the application stack obtained after the execution stage of the object instruction.

[0141] In the above embodiments of the present disclosure, in the following several cases, the instruction execution stage will send the latest obtained SP@EX value to the instruction decoding stage:

[0142] (a) When the pipeline is flushed, it is necessary to restore the SP value of the application stack;

[0143] (b) When an application starts to execute, it is necessary to obtain the initial SP value;

[0144] (c) After process switching between multiple processes in the system, it is necessary to restore the SP value;

[0145] (d) Complex instructions that change the SP value need to update the SP value in the instruction execution stage and pass it to the decoder.

[0146] In the first case above, as described below, the execution unit in the instruction execution stage will pass the SP value to the decoding unit. In the other three cases, only when the NeedSP flag of an instruction (architecture instruction or micro-instruction) is 1 (i.e., it is marked to require passing SP@EX), the instruction execution stage will pass the SP@EX value to the decoding unit; in this way, the SP@EX value is only passed when necessary, which can reduce the power consumption caused by the work of passing the SP@EX value.

[0147] In the above embodiments of the present disclosure as Figure 6 shown, the decoding unit updates the SP@DE value or sets the micro-instruction NeedSP flag in different cases:

[0148] ● Set the NeedSP flag in one of the following two cases;

[0149] ■ The SP@DE value is -1 (corresponding to the above cases (b) and (c). At this time, the cache storing SP@DE is in the initial state, and Valid is 0);

[0150] ■ Complex instructions that change the SP value (the above case (d));

[0151] ● Otherwise, update the SP@DE value;

[0152] ■ Call or Push instructions: SP@DE minus S;

[0153] ■ Ret or Pop instructions: SP@DE plus S;

[0154] ■ Other simple instructions that change the SP value: SP@DE plus an immediate number.

[0155] Figure 7 A schematic flowchart of an instruction processing method according to an embodiment of the present disclosure is shown. The instruction processing method is used to maintain the current stack top value (SP@DE) in the decoding stage during the decoding stage. As Figure 7 shown, the instruction processing method includes the following steps 700 to 705:

[0156] Step 700: Receive the latest stack top value (SP@EX) in the instruction execution stage.

[0157] Step 701: Determine whether to perform a pipeline flush currently. If not, proceed to step 702; otherwise, proceed to step 705.

[0158] Step 702: Determine whether the instruction sequence number (INST_SN) of the instruction that obtains the above latest stack top value in the instruction execution stage is the same as the instruction sequence number (SN) associated with the current stack top value (SP@DE) in the decoding stage. If so, proceed to step 703; otherwise, end the process of this method.

[0159] Step 703: Update the current stack top value (SP@DE) in the decoding stage using the latest stack top value (SP@EX) in the instruction execution stage, and SP@DE = SP@EX + SP@DE.

[0160] Step 704: Set the validity of the current stack top value in the decoding stage to valid (Valid = 1).

[0161] Step 705: Update the current stack top value (SP@DE) in the decoding stage using the latest stack top value (SP@EX) in the instruction execution stage, that is, SP@DE = SP@EX.

[0162] When a pipeline flush of the processor core occurs, there will be no instructions in the decoding stage and the execution stage of the pipeline. Therefore, the current stack top value (SP@DE) in the decoding stage can be set to the stack top value (SP@EX) updated in the execution stage.

[0163] On the other hand, when a pipeline flush of the processor core does not occur, it is necessary to determine whether the currently cached SN is equal to the INST_SN transmitted from the execution stage. This is because the decoding unit may issue multiple instructions with the NeedSP flag within a period of time before receiving a reply for the NeedSP from the execution stage. However, only the reply for the last one of the aforementioned multiple NeedSP flags is valid, and the replies for other older NeedSP flags will be ignored. Also, when a pipeline flush of the processor core does not occur, the difference between the SP from the decoding stage to the execution stage is saved in SP@DE. Therefore, it is necessary to add SP@EX and SP@DE to obtain the current stack top value in the decoding stage.

[0164] The instruction processing method of the above embodiment helps to maintain the current stack top value (SP@DE) in the decoding stage, so that the current stack top value (SP@DE) in the decoding stage can be used to obtain an accurate access address to the application program stack, thereby improving the processor performance and reducing the system power consumption.

[0165] Corresponding to the instruction processing method of the above embodiment, at least one embodiment of the present disclosure further provides a processor, including a decoding unit. The decoding unit is configured to maintain a first stack top value for recording the stack pointer of the application program stack and provide the first stack top value for obtaining an access address to the application program stack in the decoding unit.

[0166] In the processor of this embodiment, the decoding unit of the pipeline of the processor core maintains a first stack top value for recording the stack pointer of the application program stack, that is, maintains the current stack top value (SP@DE) in the decoding stage, so that the current stack top value in the decoding stage can be correctly used to obtain an access address to the application program stack, enabling the object instruction to be correctly executed in the execution stage.

[0167] In at least one example, the decoding unit is further configured to maintain a first stack top value for recording the stack pointer of the application program stack, including: in the decoding stage of the object instruction, setting the first stack top value for recording the stack pointer of the application program stack according to the content of the object instruction.

[0168] In at least one example, setting a first stack top value for recording a stack pointer of an application stack according to the content of an object instruction includes: in response to the object instruction being an instruction for changing the stack pointer of the application stack, determining whether the object instruction belongs to a first type of instruction or a second type of instruction, where the first type of instruction is an instruction that directly uses the stack pointer for arithmetic operations to update the stack top value (for example, corresponding to the simple instruction for changing the SP value mentioned above), and the second type of instruction is an instruction that does not directly use the stack pointer for arithmetic operations to update the stack top value (for example, corresponding to the complex instruction for changing the SP value mentioned above). In response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction; in response to the object instruction belonging to the second type of instruction, setting the first stack top value to the initial value (for example, 0) of the stack pointer of the application stack, setting the validity of the first stack top value to invalid, and recording the instruction sequence number of the object instruction as the relevant instruction sequence number of the first stack top value.

[0169] In at least one example, in response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction includes:

[0170] ● In response to the object instruction being a call instruction or a push instruction, using the first stack top value minus the system architecture parameter value to obtain the updated first stack top value; or

[0171] ● In response to the object instruction being a ret or pop instruction, using the first stack top value plus the system architecture parameter value to obtain the updated first stack top value; or

[0172] ● In response to the object instruction being an instruction for changing the stack pointer of the application stack and using an immediate number as the source operand, performing an operation on the first stack top value and the immediate number to obtain the updated first stack top value.

[0173] In at least one example, the decoding unit is further configured to, in response to the object instruction belonging to the second type of instruction, label the object instruction as requiring feedback of a second stack top value corresponding to the stack pointer of the application stack obtained after the execution of the object instruction after the execution stage of the object instruction. Here, the "second stack top value" is used to refer to the new stack top value of the application stack updated in the execution stage (i.e., SP@EX).

[0174] In at least one example, the decoding unit is further configured to, in response to the object instruction belonging to the second type of instruction, receive the second stack top value, and in response to the instruction sequence number of the object instruction being the same as the current relevant instruction sequence number of the first stack top value, update the first stack top value using the second stack top value.

[0175] In at least one example, the decoding unit is further configured to, during the execution stage of the object instruction, in response to the object instruction being marked as requiring feedback of the second top-of-stack value, feedback the second top-of-stack value and the instruction sequence number of the object instruction to the decoding unit of the pipeline of the processor core after the object instruction is executed.

[0176] In at least one example, the decoding unit is further configured to, during the decoding stage of the object instruction, receive the second top-of-stack value corresponding to the top-of-stack value of the application program stack provided by the instruction execution unit of the pipeline of the processor core, and

[0177] in response to a pipeline flush of the processor core occurring, set the first top-of-stack value to the second top-of-stack value,

[0178] in response to a pipeline flush of the processor core not occurring, further receive the instruction sequence number of the executed instruction that generates the second top-of-stack value provided by the instruction execution unit, and in response to the instruction sequence number of the executed instruction being the same as the relevant instruction sequence number of the first top-of-stack value, set the first top-of-stack value using the second top-of-stack value and set the validity of the first top-of-stack value to valid, where the relevant instruction sequence number of the first top-of-stack value refers to the instruction sequence number of the latest preceding instruction that modifies the stack pointer of the application program stack recorded before the decoding stage of the object instruction.

[0179] As needed, with reference to Figure 3 , the above-mentioned processor may further include, but is not limited to, structures such as branch prediction, instruction fetch, instruction dispatch and rename, instruction execution, and instruction retire. Embodiments of the present disclosure do not limit this.

[0180] At least one embodiment of the present disclosure further provides an instruction execution method, which includes: in response to a pipeline flush of the processor core occurring, providing the top-of-stack value of the stack pointer of the application program stack obtained after the pipeline flush of the processor core to the decoding unit of the pipeline of the processor core; in response to a pipeline flush of the processor core not occurring, executing the decoded instruction of the object instruction and providing the top-of-stack value of the stack pointer of the application program stack obtained after the object instruction is executed to the decoding unit of the pipeline of the processor core, where the object instruction is marked as requiring feedback of the top-of-stack value of the stack pointer of the application program stack after being executed.

[0181] During the execution of the object instruction in the instruction execution method of this embodiment, in the case where the object instruction is marked as requiring feedback of the top-of-stack value of the stack pointer of the application program stack after being executed, the latest top-of-stack value (SP@EX) at the execution stage obtained by executing the object instruction is fed back to the decoding stage, for more accurately maintaining the current top-of-stack value (SP@DE) at the decoding stage at the decoding stage.

[0182] In at least one example of this embodiment, the instruction execution method further includes: in response to a non-occurrence of a pipeline flush of a processor core, providing the instruction sequence number of an object instruction to a decoding unit of the pipeline of the processor core.

[0183] In at least one example of this embodiment, in response to a non-occurrence of a pipeline flush of a processor core, executing the decoded instruction of the object instruction and providing the top value of the stack pointer of the application program stack obtained by executing the object instruction to a decoding unit of the pipeline of the processor core, including: in response to the object instruction being the latest instruction that has been distributed and is marked as needing to feedback the top value of the stack pointer of the application program stack after being executed, executing the decoded instruction of the object instruction and providing the top value of the stack pointer of the application program stack obtained by executing the object instruction to a decoding unit of the pipeline of the processor core.

[0184] In at least one example of this embodiment, the instruction execution method further includes: in the instruction distribution stage, recording the latest instruction that has been distributed and is marked as needing to feedback the top value of the stack pointer of the application program stack after being executed.

[0185] Figure 8 Fig. shows a schematic flowchart of an instruction processing method according to an embodiment of the present disclosure. The instruction processing method is used to transfer the latest top value of the stack (SP@EX) in the execution stage to the decoding stage. As Figure 8 shown, the instruction processing method includes the following steps 800 to 803:

[0186] Step 800: Enter the execution stage of the object instruction.

[0187] Step 801: Determine whether a pipeline flush is to be performed currently. If not, proceed to step 802; otherwise, proceed to step 803.

[0188] Step 802: Determine whether the object instruction is an instruction marked as needing to feedback the top value of the stack pointer of the application program stack after being executed, that is, whether the object instruction has a representation of NeedSP. If so, proceed to step 803; otherwise, end the process of this method.

[0189] Step 803: Send the latest top value of the stack (SP@EX) in the execution stage obtained by executing the object instruction and the instruction sequence number of the object instruction.

[0190] In the process of executing an object instruction by the instruction execution method of the foregoing embodiment, in the case where the object instruction is marked as needing to feedback the top value of the stack pointer of the application stack after being executed, the latest top value of the stack (SP@EX) obtained in the execution stage by executing the object instruction is fed back to the decoding stage, so as to more accurately maintain the current top value of the stack (SP@DE) in the decoding stage.

[0191] Corresponding to the foregoing instruction execution method, at least one embodiment of the present disclosure provides a processor, which includes an execution unit and a decoding unit. The execution unit is configured to: in response to a pipeline flush of the processor core occurring, provide the top value of the stack pointer of the application stack obtained after the pipeline flush of the processor core to the decoding unit; in response to no pipeline flush of the processor core occurring, execute the decoded instruction of the object instruction and provide the top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit, where the object instruction is marked as needing to feedback the top value of the stack pointer of the application stack obtained by executing the object instruction after the execution stage of the object instruction.

[0192] In at least one example of this embodiment, the execution unit is further configured to: in response to no pipeline flush of the processor core occurring, provide the instruction sequence number of the object instruction to the decoding unit.

[0193] In at least one example of this embodiment, the execution unit is further configured to: in response to the object instruction being the latest distributed instruction that is marked as needing to feedback the top value of the stack pointer of the application stack after being executed, execute the decoded instruction of the object instruction and provide the top value of the stack pointer of the application stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core.

[0194] In at least one example of this embodiment, the processor further includes an instruction distribution unit, where the instruction distribution unit is configured to record the latest distributed instruction that is marked as needing to feedback the top value of the stack pointer of the application stack after being executed.

[0195] In the process of executing an object instruction by the instruction execution method of the foregoing embodiment, in the case where the object instruction is marked as needing to feedback the top value of the stack pointer of the application stack after being executed, the latest top value of the stack (SP@EX) obtained in the execution stage by executing the object instruction is fed back to the decoding stage, so as to more accurately maintain the current top value of the stack (SP@DE) in the decoding stage.

[0196] For example Figure 5 In the embodiment shown, in order to execute arithmetic operations for generating access addresses for instructions such as call / ret / push / pop, at least one embodiment of the present disclosure provides an arithmetic unit to execute the arithmetic operation.Figure 9A An example of the arithmetic unit is shown. As Figure 9A shown, the arithmetic unit includes a multiplexer 901 and an adder 902. The multiplexer 901 has multiple three inputs, which are 0, -S (negative architecture parameter value), and inst_imm (immediate value in the object instruction) respectively. The adder 902 has two inputs, which are the output of the multiplexer 901 and the current stack top value (SP@DE) in the decoding stage respectively, and is used to add the two to obtain the access address (Inst_addr) of the object instruction to the application stack. The selection signal of the multiplexer 901 is inst_type, which can respectively have three values corresponding to ret / pop instructions, call / push instructions, and other simple instructions for accessing the application stack, and is used to respectively select one of the above three inputs. The selected input is sent to the adder to be added to the current stack top value (SP@DE) in the decoding stage to obtain the access address (Inst_addr) of the object instruction to the application stack.

[0197] For example Figure 6 in the embodiment shown, in order to perform arithmetic operations for updating the current stack top value (SP@DE) in the decoding stage for instructions such as call / ret / push / pop, in at least one embodiment of the present disclosure, an arithmetic unit is provided to perform the arithmetic operation. Figure 9B An example of the arithmetic unit is shown. As Figure 9B shown, the arithmetic unit includes a multiplexer 911 and an adder 912. The multiplexer 911 has multiple three inputs, which are S (architecture parameter value), -S (negative architecture parameter value), and inst_imm (immediate value in the object instruction) respectively. The adder 912 has two inputs, which are the output of the multiplexer 901 and the current stack top value (SP@DE) in the decoding stage respectively, and is used to add the two to obtain a sum for updating the current stack top value (SP@DE) in the decoding stage. The selection signal of the multiplexer 911 is inst_type, which can respectively have three values corresponding to ret / pop instructions, call / push instructions, and other simple instructions for accessing and modifying the stack top value of the application stack, and is used to respectively select one of the above three inputs. The selected input is sent to the adder to be added to the current stack top value (SP@DE) in the decoding stage, and the obtained sum is used to update the current stack top value (SP@DE) in the decoding stage.

[0198] In at least some embodiments of the present disclosure, for Figure 5 , Figure 6 , Figure 7 the methods shown can all be performed in the instruction decoding stage. And, the method of maintaining SP@DE ( Figure 6 and Figure 7The method shown) and the method of generating an access address for accessing the application stack ( Figure 5 The method shown) can be parallel, for example, it can be completed in the same clock cycle.

[0199] In at least some embodiments of the present disclosure, maintaining the two operations of SP@DE (i.e., Figure 6 and Figure 8 The method shown) can occur within the same clock cycle. At this time, they will be completed in sequence, but their order does not affect the correctness of maintaining SP@DE.

[0200] In the description of the above embodiments of the present disclosure, the X86-64 processor core is partially used as an example for description. However, each embodiment of the present disclosure is applicable to all types of processor cores that use an application stack.

[0201] For the present disclosure, the following points need to be noted:

[0202] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures can refer to the general design.

[0203] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0204] The above is only an exemplary implementation manner of the present disclosure, rather than being used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. An instruction processing method, comprising: In the decoding stage of an object instruction, obtaining an access address of the object instruction to an application stack; In the execution stage of the object instruction, accessing the application stack by using the access address; Wherein, the obtaining the access address of the object instruction to the application stack includes: Determining whether a first stack top value is a valid value in the decoding stage of the object instruction; In response to the first stack top value being a valid value, obtaining the access address by using the first stack top value, Wherein, the first stack top value is a value maintained by a decoding unit of a pipeline of a processor core for recording a stack pointer of the application stack.

2. The instruction processing method according to claim 1, wherein The obtaining the access address by using the first stack top value in response to the first stack top value being a valid value includes: In response to the object instruction being a call instruction or a push instruction, obtaining the access address by subtracting a system architecture parameter value from the first stack top value; or In response to the object instruction being a ret or pop instruction, using the first stack top value as the access address; or In response to the object instruction being an instruction for accessing the application stack and being an address encoding method using a sum of the stack pointer and an immediate number, obtaining the access address by adding the immediate number to the first stack top value.

3. The instruction processing method according to claim 2, further comprising: In the decoding stage of the object instruction, obtaining a decoded instruction corresponding to the object instruction in combination with the access address; Wherein, the accessing the application stack by using the access address in the execution stage of the object instruction includes: Using the access address to execute the decoded instruction to access the application stack.

4. A processor, comprising: A decoding unit configured to obtain an access address of an object instruction to an application stack in the decoding stage of the object instruction; An execution unit configured to access the application stack by using the access address in the execution stage of the object instruction; Wherein, the decoding unit is further configured to: determine whether a first stack top value is a valid value in the decoding stage of the object instruction; in response to the first stack top value being a valid value, obtain the access address by using the first stack top value, wherein the first stack top value is a value maintained by a decoding unit of a pipeline of a processor core for recording a stack pointer of the application stack.

5. The processor according to claim 4, wherein, The decoding unit is further configured to obtain a decoded instruction corresponding to the object instruction in the decoding stage of the object instruction; The execution unit is further configured to execute the decoded instruction to access the application stack by using the access address.

6. An instruction processing method, comprising: Maintaining, by a decoding unit of a pipeline of a processor core, a first stack top value for recording a stack pointer of an application stack, Providing the first stack top value for obtaining an access address to the application stack in the decoding unit of the pipeline of the processor core; Wherein, the maintaining, by a decoding unit of a pipeline of a processor core, a first stack top value for recording the stack pointer of the application stack includes: In the decoding stage of the object instruction, a first stack top value for recording the stack pointer of the application stack is set according to the content of the object instruction.

7. The instruction processing method according to claim 6, wherein, The setting of the first stack top value for recording the stack pointer of the application stack according to the content of the object instruction includes: In response to the object instruction being an instruction to change the stack pointer of the application stack, determining whether the object instruction belongs to a first type of instruction or a second type of instruction, where the first type of instruction is an instruction that directly uses the stack pointer for arithmetic operations to update the stack top value, and the second type of instruction is an instruction that does not directly use the stack pointer for arithmetic operations to update the stack top value; In response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction; In response to the object instruction belonging to the second type of instruction, setting the first stack top value to the initial value of the stack pointer of the application stack, setting the validity of the first stack top value to invalid, and recording the instruction sequence number of the object instruction as the relevant instruction sequence number of the first stack top value.

8. The instruction processing method according to claim 7, wherein, In response to the object instruction belonging to the first type of instruction, updating the first stack top value according to the content of the object instruction includes: In response to the object instruction being a call instruction or a push instruction, using the first stack top value minus the system architecture parameter value to obtain the updated first stack top value; or In response to the object instruction being a ret or pop instruction, using the first stack top value plus the system architecture parameter value to obtain the updated first stack top value; or In response to the object instruction being an instruction to change the stack pointer of the application stack and using an immediate number as the source operand, performing an operation on the first stack top value and the immediate number to obtain the updated first stack top value.

9. The instruction processing method according to claim 7, further comprising: In response to the object instruction belonging to the second type of instruction, marking the object instruction as requiring feedback of a second stack top value corresponding to the stack pointer of the application stack obtained after the execution of the object instruction after the execution stage of the object instruction.

10. The instruction processing method according to claim 9, further comprising: In response to the object instruction belonging to the second type of instruction, receiving the second stack top value, In response to the instruction sequence number of the object instruction being the same as the current relevant instruction sequence number of the first stack top value, using the second stack top value to update the first stack top value.

11. The instruction processing method according to claim 9, further comprising: In the execution stage of the object instruction, in response to the object instruction being marked as requiring feedback of the second stack top value, feeding back the second stack top value and the instruction sequence number of the object instruction to the decoding unit of the pipeline of the processor core after the object instruction is executed.

12. The instruction processing method according to claim 6, wherein, The maintaining of the first stack top value for recording the stack pointer of the application stack by the decoding unit of the pipeline of the processor core further includes: In the decoding stage of the object instruction, receive a second stack top value corresponding to the stack top value of the application program stack provided by the instruction execution unit of the pipeline of the processor core, and in response to a pipeline flush of the processor core occurring, set the first stack top value to the second stack top value, in response to a pipeline flush of the processor core not occurring, further receive the instruction sequence number of the executed instruction that generates the second stack top value provided by the instruction execution unit, and in response to the instruction sequence number of the executed instruction being the same as the relevant instruction sequence number of the first stack top value, set the first stack top value using the second stack top value and set the validity of the first stack top value to valid, where the relevant instruction sequence number of the first stack top value refers to the instruction sequence number of the latest previous instruction that modifies the stack pointer of the application program stack recorded before the decoding stage of the object instruction.

13. A processor, including a decoding unit, wherein, The decoding unit is configured to: maintain a first stack top value for recording the stack pointer of the application program stack, provide the first stack top value for obtaining an access address to the application program stack in the decoding unit; wherein the decoding unit is further configured to, in the decoding stage of the object instruction, set the first stack top value for recording the stack pointer of the application program stack according to the content of the object instruction.

14. An instruction execution method, comprising: in response to a pipeline flush of the processor core occurring, provide the stack top value of the stack pointer of the application program stack obtained after the pipeline flush of the processor core to the decoding unit of the pipeline of the processor core; in response to a pipeline flush of the processor core not occurring, execute the decoded instruction of the object instruction and provide the stack top value of the stack pointer of the application program stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core, where the object instruction is marked as needing to feedback the stack top value of the stack pointer of the application program stack after being executed.

15. The instruction execution method according to claim 14, further comprising: in response to a pipeline flush of the processor core not occurring, provide the instruction sequence number of the object instruction to the decoding unit of the pipeline of the processor core.

16. The instruction execution method according to claim 14, wherein, The step of, in response to a pipeline flush of the processor core not occurring, executing the decoded instruction of the object instruction and providing the stack top value of the stack pointer of the application program stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core, includes: in response to the object instruction being the latest currently distributed instruction marked as needing to feedback the stack top value of the stack pointer of the application program stack after being executed, execute the decoded instruction of the object instruction and provide the stack top value of the stack pointer of the application program stack obtained by executing the object instruction to the decoding unit of the pipeline of the processor core.

17. The instruction execution method according to claim 16, further comprising: in the instruction distribution stage, record the latest currently distributed instruction marked as needing to feedback the stack top value of the stack pointer of the application program stack after being executed.

18. A processor includes an execution unit and a decoding unit, wherein, The execution unit is configured to: In response to a pipeline flush of a processor core, provide the top value of the stack pointer of the application program stack obtained after the pipeline flush of the processor core to the decoding unit; In response to no pipeline flush of the processor core, execute the decoded instruction of the target instruction and provide the top value of the stack pointer of the application program stack obtained by the execution of the target instruction to the decoding unit, where the target instruction is marked as requiring feedback of the top value of the stack pointer of the application program stack corresponding to the execution of the target instruction after the execution stage of the target instruction.

19. The processor according to claim 18, wherein, The execution unit is further configured to: in response to no pipeline flush of the processor core, provide the instruction sequence number of the target instruction to the decoding unit.

20. The processor according to claim 18, wherein, The execution unit is further configured to: In response to the target instruction being the latest currently distributed instruction marked as requiring feedback of the top value of the stack pointer of the application program stack after execution, execute the decoded instruction of the target instruction and provide the top value of the stack pointer of the application program stack obtained by the execution of the target instruction to the decoding unit of the pipeline of the processor core.

21. The processor according to claim 20 further includes an instruction distribution unit, wherein, The instruction distribution unit is configured to record the latest currently distributed instruction marked as requiring feedback of the top value of the stack pointer of the application program stack after execution.

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