Electrical failure analysis method and related device

Abstract

The present application provides an electrical failure analysis method, including: obtaining a failure log of each failed grain of a wafer; determining each high-frequency-dominated failed grain and each low-frequency-dominated failed grain according to the high-frequency test results and low-frequency test results in the failure log of the failed grain; obtaining a current high-frequency-dominated failure weight value; obtaining a failure deviation value of each structural layer according to the high-frequency failure size of each structural layer of each high-frequency-dominated failed grain, the low-frequency failure size of each structural layer of each low-frequency-dominated failed grain, the current high-frequency-dominated failure weight value and the design size of each structural layer of the wafer; adjusting the current high-frequency-dominated failure weight value according to the failure deviation value and a predetermined deviation threshold until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and obtaining the maximum failure-affected layer corresponding to the maximum failure deviation value. The electrical failure analysis method provided in the embodiment of the present application can improve the accuracy of electrical failure analysis.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuits, and in particular to an electrical failure analysis method and related devices. Background Art

[0002] Electrical failure analysis (eFA) is the most common way to capture chip defects, among which scan chain diagnosis (Scan diagnosis) is currently the most common analysis method for complex and large chips. Scan chain diagnosis (Scan diagnosis) is divided into two categories according to the difference in test frequency: low-frequency test (DC-SCAN) and high-frequency test (AC-SCAN). With the advancement of manufacturing technology to deep micron, the operating frequency of chips is gradually increasing, and high-speed functional abnormalities caused by resistive problems of high-resistance paths are becoming more and more common. Chips that have passed the original low-frequency test (DC-SCAN) will have various problems at high operating frequencies. Therefore, in the context that the original low-frequency test (DC-SCAN) can no longer capture all defects, high-frequency test (AC-SCAN) has been widely used, and the number of low-frequency test (DC-SCAN) test items has gradually decreased.

[0003] However, even so, in the test results, the number of dies dominated by low-frequency failures (DC-SCAN) is still large, resulting in the dominance of low-frequency test (DC-SCAN) failure data, which overwhelms the high-frequency test (AC-SCAN) failure data, making it impossible to accurately reflect the role of high-frequency test (AC-SCAN) failure data in electrical failure analysis, affecting the accuracy of high-frequency test (AC-SCAN) electrical failure analysis.

[0004] Therefore, how to improve the accuracy of electrical failure analysis in high-frequency testing has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] In view of this, the electrical failure analysis method provided in the embodiment of the present application can ensure that during electrical failure analysis, high-frequency test failure data will not be overwhelmed by low-frequency test failure data, thereby improving the accuracy of high-frequency test electrical failure analysis.

[0006] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides an electrical failure analysis method, comprising:

[0008] Obtain failure logs of each failed die of the wafer;

[0009] Determine each high-frequency dominant failed grain and each low-frequency dominant failed grain according to the high-frequency test results and the low-frequency test results in the failure log of each failed grain;

[0010] Get the current high-frequency dominant failure weight value;

[0011] According to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominated failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominated failure grain, the current high-frequency dominated failure weight value and the design size of each structural layer of the wafer, the failure deviation value of each structural layer is obtained, and according to the failure deviation value and a predetermined deviation threshold, the current high-frequency dominated failure weight value is adjusted until the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, and the maximum failure influence layer corresponding to the maximum failure deviation value is obtained.

[0012] In a second aspect, an embodiment of the present application provides an electrical failure analysis device, comprising:

[0013] A failure log acquisition module, adapted to acquire the failure log of each failed die of the wafer;

[0014] A failed grain determination module, adapted to determine each high-frequency dominant failed grain and each low-frequency dominant failed grain according to the high-frequency test results and the low-frequency test results in the failure log of each failed grain;

[0015] A high-frequency dominant failure weight value acquisition module is suitable for acquiring a current high-frequency dominant failure weight value;

[0016] The maximum failure influence layer acquisition module is suitable for obtaining the failure deviation value of each structural layer according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, adjusting the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold until the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, and obtaining the maximum failure influence layer corresponding to the maximum failure deviation value.

[0017] In a third aspect, an embodiment of the present application provides a storage medium storing a program suitable for electrical failure analysis to implement the electrical failure analysis method as described in the first aspect.

[0018] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising at least one memory and at least one processor; the memory stores a program, and the processor calls the program to execute the electrical failure analysis method as described in the first aspect.

[0019] The electrical failure analysis method provided in the embodiment of the present application, when performing electrical failure analysis, first obtains the failure log of each failed grain of the wafer; then determines each high-frequency dominant failed grain and each low-frequency dominant failed grain according to the high-frequency test results and low-frequency test results in the failure log of each failed grain; then obtains the current high-frequency dominant failure weight value; finally, obtains the failure deviation value of each structural layer according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failed grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failed grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, and further adjusts the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, until the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, thereby obtaining the maximum failure influence layer corresponding to the maximum failure deviation value.

[0020] In this way, the electrical failure analysis method provided in the embodiment of the present application determines each high-frequency dominant failure grain and each low-frequency dominant failure grain according to the failure log of each failed grain of the wafer, so as to distinguish each high-frequency dominant failure data from each low-frequency dominant failure data, and then obtains the failure deviation value according to the design size of each structural layer of the wafer, the failure size of each high-frequency dominant failure grain combined with the current high-frequency dominant failure weight value after weight adjustment, and the failure size of each low-frequency dominant failure grain without weight adjustment. In this way, the addition of the failure size of each low-frequency dominant failure grain can ensure the amount of data required for electrical failure analysis. At the same time, when obtaining the failure deviation value, the weight of the high-frequency failure size can be increased by the current high-frequency dominant failure weight value, and then the current high-frequency dominant failure weight value is adjusted in combination with the predetermined deviation threshold, so that the high-frequency dominant failure data is highlighted until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and then the maximum failure deviation value is obtained to obtain the maximum failure influence layer corresponding to the maximum failure deviation value, and the structural layer that accurately causes the grain failure is obtained. It can be seen that the electrical failure analysis method provided in the embodiment of the present application can utilize the dominant failure data of low-frequency tests to ensure sufficient data volume, and can also make the dominant failure data of high-frequency tests stand out without being overwhelmed by the low-frequency test failure data, thereby fully displaying the impact of high-frequency test failure data and improving the accuracy of high-frequency test electrical failure analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0022] Figure 1 A schematic diagram for explaining that high frequency test failure data is submerged in the prior art;

[0023] Figure 2 An optional flow chart of the electrical failure analysis method provided in the embodiment of the present application;

[0024] Figure 3 A schematic diagram of a failure log acquisition process of the electrical failure analysis method provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of an optional failed grain classification for the electrical failure analysis method provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of an optional process for obtaining a failure deviation value of the electrical failure analysis method provided in an embodiment of the present application;

[0027] Figure 6 A block diagram of an electrical failure analysis device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] Combined with the above discussion, it can be seen that during electrical failure analysis, the high-frequency test (AC-SCAN) failure data will be overwhelmed, making it impossible to accurately reflect the role of the high-frequency test (AC-SCAN) failure data in electrical failure analysis, affecting the accuracy of high-frequency test (AC-SCAN) electrical failure analysis.

[0030] Please refer to Figure 1 , Figure 1 The diagram is a schematic diagram illustrating the flooding of high-frequency test failure data in the prior art.

[0031] As shown in the figure, M1, M3, K2, and G1 are only examples of the structural layer. When the high-frequency test failure data is not submerged (only high-frequency failure data, that is, Figure 1 As shown in the middle table in the figure, the failure size of the structural layer G1 is the largest (100), the failure ratio of G1 is also the largest, and correspondingly, the failure deviation value of G1 is also the largest. Through data analysis, it can be seen that the probability of failure of the structural layer G1 is the highest, that is, the structural layer G1 is the main cause of grain failure.

[0032] When low-frequency failure data is added (when both high-frequency failure data and low-frequency failure data are included, that is, the table at the bottom of the figure), it can be seen from the figure that in the total failure size, the failure size of structural layer M3 becomes the largest (142), and the total failure ratio of M3 is also the largest. Correspondingly, the total failure deviation value of M3 is also the largest. Through data analysis, it is found that the probability of failure of structural layer M3 is the highest, that is, structural layer M3 is the main cause of grain failure.

[0033] It can be seen that due to the addition of low-frequency failure data, the high-frequency failure data is submerged, which reduces the role of high-frequency test failure data in electrical failure analysis and cannot be accurately reflected, affecting the accuracy of high-frequency test electrical failure analysis.

[0034] To this end, the present application embodiment provides an electrical failure analysis method, please refer to Figure 2 , Figure 2 An optional flowchart of the electrical failure analysis method provided in an embodiment of the present application.

[0035] As shown in the figure, the electrical failure analysis method provided in the embodiment of the present application includes the following steps:

[0036] Step S20: Obtaining the failure log of each failed die of the wafer.

[0037] It is easy to understand that before doing failure analysis, we must first use the test items of wafer testing to test the wafer, obtain the failed grains of the wafer based on the test results, and then obtain the failure log of each failed grain of the wafer for failure analysis.

[0038] In a specific embodiment, the wafer can be tested using an ATE test machine and failure logs can be collected. The failure logs can be analyzed using various EDA failure analysis tools. The present application does not limit the use of tools for wafer testing, failure log collection, and failure log analysis. In different embodiments, suitable tools can be used to complete the above tasks.

[0039] With the demand for upgrading the mass production wafer test mode and optimizing the test time, the low-frequency test (DC-SCAN) test items will be gradually streamlined in the existing wafer test items, and some test items will be deleted from the original low-frequency test (DC-SCAN) test items. Therefore, in a specific embodiment, the present application can obtain the failure log of each failed grain of the wafer according to the existing wafer test items.

[0040] However, since the test items of the low-frequency test (DC-SCAN) are deleted, the test data of the low-frequency test is insufficient, which may cause some low-frequency test failed grains to be misclassified as high-frequency test failed grains, thereby affecting the accuracy of the high-frequency test electrical failure analysis. Therefore, in order to ensure the accuracy of the classification of failed grains, the embodiment of the present application also provides another electrical failure analysis method, please refer to Figure 3 , Figure 3 A schematic diagram of a failure log acquisition process of the electrical failure analysis method provided in an embodiment of the present application. As can be seen from the figure, the steps of acquiring the failure log of each failed die of the wafer in the electrical failure analysis method provided in an embodiment of the present application may include:

[0041] Step S30: testing the wafer using the test items of the wafer test to obtain each failed die and the first failure log of each failed die, wherein the low-frequency test items in the test items are less than the high-frequency test items.

[0042] First, the wafer is tested using the test items of the existing wafer test to obtain each failed grain and the first failure log of each failed grain. Because some low-frequency test (DC-SCAN) test items in the test items of the existing wafer test are deleted, the low-frequency test items in the test items are less than the high-frequency test items.

[0043] Step S31: Supplement the low-frequency test items.

[0044] Because the test items of the low-frequency test (DC-SCAN) are deleted, the test data of the low-frequency test is insufficient, which may cause some grains that fail the low-frequency test to be mistakenly classified as grains that fail the high-frequency test. Therefore, in order not to affect the accuracy of the electrical failure analysis of the high-frequency test, the test items of the low-frequency test (DC-SCAN) can be supplemented.

[0045] In a specific embodiment, the step of supplementing the low-frequency test items includes: supplementing the low-frequency test items according to the high-frequency test items.

[0046] In this way, not only can the low-frequency test items be made more complete, but the supplementation of the low-frequency test items is also relatively simple, so that the test results can be easily made more accurate and the accuracy of electrical failure analysis can be ensured.

[0047] Step S32: performing a second test on each of the failed dies according to the supplemented low-frequency test items to obtain a second failure log of each of the failed dies.

[0048] After the low-frequency test items are supplemented, a second test is performed on each of the failed dies obtained above according to the supplemented low-frequency test items, so that a second failure log of each of the failed dies can be obtained.

[0049] Step S33: acquiring the failure log of each failed die according to the first failure log and the second failure log.

[0050] After obtaining the first failure log and the second failure log of each failed crystal grain, the first failure log and the second failure log are merged to obtain the required failure log of each failed crystal grain.

[0051] In this way, firstly, the first failure log of each failed grain is obtained according to the existing low-frequency test items, and then the low-frequency test items are supplemented, and the second failure log of each failed grain is obtained according to the supplemented low-frequency test items. Finally, the failure log of each failed grain is obtained. On the one hand, the low-frequency test items can be made more complete, and errors caused by the lack of low-frequency test items can be avoided, thereby further ensuring the accuracy of electrical failure analysis of high-frequency tests. On the other hand, only the testing of the supplemented low-frequency test items on the obtained failed grains can reduce the workload required for testing on the basis of meeting the test accuracy.

[0052] Of course, in another specific implementation, in order to ensure the accuracy of the classification of failed grains, low-frequency test items can be supplemented before testing, and then wafer testing can be performed, thereby ensuring the completeness of the low-frequency test items, thereby avoiding errors caused by the lack of low-frequency test items and improving the accuracy of high-frequency test electrical failure analysis.

[0053] Therefore, based on the above method, the failure log of each failed die of the wafer can be obtained, and the electrical failure analysis can be continued.

[0054] To do this, please continue to refer to Figure 2 Step S21: determining each high-frequency-dominated failed grain and each low-frequency-dominated failed grain according to the high-frequency test results and the low-frequency test results in the failure log of each failed grain.

[0055] After obtaining the failure log of each failed grain, each high-frequency-dominated failed grain and each low-frequency-dominated failed grain are determined according to the high-frequency test results and low-frequency test results in each failure log. In a specific embodiment, a well-written software script can be used to distinguish the marks of each high-frequency-dominated failed grain and each low-frequency-dominated failed grain, thereby ensuring the accuracy of the distinction and improving the efficiency of obtaining the high-frequency-dominated failed grains and the low-frequency-dominated failed grains.

[0056] In a specific embodiment, in order to facilitate the determination of high-frequency dominated failed grains and low-frequency dominated failed grains, the step of determining each high-frequency dominated failed grain and each low-frequency dominated failed grain according to the high-frequency test results and the low-frequency test results in the failure log of each failed grain may include:

[0057] When the low-frequency test result of the failed grain is failure, the failed grain is determined to be a low-frequency dominated failure grain; when the low-frequency test result of the failed grain is pass, but the high-frequency test result of the failed grain is failure, the failed grain is determined to be a high-frequency dominated failure grain.

[0058] In a specific test process, if the low-frequency test of a certain grain fails, then the high-frequency test of this grain will also fail. However, the main reason for the grain test failure at this time is the failure of the low-frequency test. Therefore, the failed grains can be classified and marked according to the high-frequency test results and low-frequency test results in each failure log of the failed grain. When the test result is that the low-frequency test fails, the failed grain can be determined and marked as a low-frequency dominated failed grain. When the test result is that the low-frequency test passes but the high-frequency test fails, the failed grain can be determined and marked as a high-frequency dominated failed grain.

[0059] Please refer to Figure 4 , Figure 4 A schematic diagram of an optional failed grain classification for the electrical failure analysis method provided in an embodiment of the present application.

[0060] In a specific embodiment, as shown in the figure, the wafer is first tested, wherein the high-frequency test items and the low-frequency test items are the same, and then the failed grains are classified according to the test results. If the low-frequency test of a grain fails, the high-frequency test of the grain will also fail. Therefore, when the test result is that the low-frequency test fails, the failed grain can be determined and marked as the low-frequency dominant failed grain C. When the test result is that the low-frequency test passes but the high-frequency test fails, the failed grain can be determined and marked as the high-frequency dominant failed grain B. It should be noted that Figure 4 This is only an example of a method for classifying failed grains. The present application does not limit the method for classifying failed grains. In different embodiments, other appropriate classification methods may be used.

[0061] By classifying the failed grains, the failure causes of the failed grains can be easily distinguished, and a basis can also be provided for completing the subsequent implementation steps of the present application.

[0062] Step S22: Obtain the current high-frequency dominant failure weight value.

[0063] After determining each high-frequency dominant failure grain and each low-frequency dominant failure grain, the current high-frequency dominant failure weight value is obtained. When subsequently calculating the failure deviation value, the weight of the high-frequency failure size of each structural layer in each failure log of each high-frequency dominant failure grain can be increased, so that the high-frequency test failure data is highlighted and not submerged by the low-frequency test failure data, thereby improving the accuracy of high-frequency test (AC-SCAN) electrical failure analysis.

[0064] The present application does not limit the method for obtaining the current high-frequency dominant failure weight value. In different embodiments, different methods for obtaining the current high-frequency dominant failure weight value may be used.

[0065] Step S23: Obtain the failure deviation value of each structural layer according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominated failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominated failure grain, the current high-frequency dominated failure weight value and the design size of each structural layer of the wafer.

[0066] After obtaining the failure logs of each failed grain of the wafer, determining each high-frequency-dominated failed grain and each low-frequency-dominated failed grain based on the high-frequency test results and low-frequency test results in the failure logs of each failed grain, and obtaining the current high-frequency-dominated failure weight value, the failure deviation value of each structural layer can be obtained based on the high-frequency failure size of each structural layer in the failure log of each high-frequency-dominated failed grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency-dominated failed grain, the current high-frequency-dominated failure weight value and the design size of each structural layer of the wafer, where the structural layer of the wafer is the same as the structural layer of the grain.

[0067] Please refer to Figure 5 , Figure 5 A schematic diagram of an optional process for obtaining a failure deviation value for an electrical failure analysis method provided in an embodiment of the present application.

[0068] As shown in the figure, the step of obtaining the failure deviation value of each structural layer includes:

[0069] Step S50: Obtain the failure size ratio of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominated failure grain, the low-frequency failure size of each structural layer of each low-frequency dominated failure grain and the current high-frequency dominated failure weight value.

[0070] In order to obtain the failure size ratio of each structural layer of the wafer, it is necessary to first obtain the structural layer failure size of each structural layer of each high-frequency dominated failure grain, the low-frequency failure size of each structural layer of each low-frequency dominated failure grain and the current high-frequency dominated failure weight value, and then obtain the failure size ratio of each structural layer of the wafer based on the failure size of each structural layer.

[0071] The step of obtaining the structural layer failure size of each structural layer of the wafer may specifically include:

[0072] Obtaining the sum of the high-frequency failure sizes of the same structural layer of each of the high-frequency dominant failure grains to obtain the high-frequency failure size of each structural layer, and obtaining the sum of the low-frequency failure sizes of the same structural layer of each of the low-frequency dominant failure grains to obtain the low-frequency failure size of each structural layer;

[0073] According to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value, obtaining the high-frequency failure weight size of each structural layer;

[0074] The structural layer failure size is acquired according to the structural layer high-frequency failure weight size and the structural layer low-frequency failure size of the same structural layer, so as to obtain the structural layer failure size of each structural layer.

[0075] In order to clearly illustrate the steps of obtaining the failure size ratio of each structural layer of the above-mentioned wafer, an example is now given: the structural layers M1-M3 are taken as an example for explanation, wherein the structural layers M1-M3 are only examples, and in different embodiments, other suitable structural layers may be used to represent them.

[0076] 1) Obtain the sum of the high-frequency failure sizes of the same structural layer of each of the high-frequency dominant failure grains to obtain the high-frequency failure size of each structural layer, that is, according to the high-frequency failure size of each failed grain in the failure log, calculate the high-frequency failure size of each structural layer according to the following formula.

[0077]

[0078] The result obtained from the formula is the high-frequency failure size of the M1 structural layer, where SCAN_AC_Main is the failure size of a high-frequency dominant failure grain. The high-frequency failure size of the M1 structural layer can be obtained by summing up the failure sizes of each high-frequency dominant failure grain in the M1 structural layer. It is easy to understand that based on the same method, the high-frequency failure sizes of the M2 and M3 structural layers can be calculated.

[0079] 2) Obtain the sum of the low-frequency failure sizes of the same structural layer of each of the low-frequency dominant failure grains to obtain the low-frequency failure size of each structural layer, that is, according to the low-frequency failure size of each failed grain in the failure log, calculate the low-frequency failure size of each structural layer according to the following formula.

[0080]

[0081] The result obtained from the formula is the low-frequency failure size of the M1 structural layer, where SCAN_DC_Main is the failure size of a low-frequency dominant failure grain. The low-frequency failure size of the M1 structural layer can be obtained by summing up the failure sizes of each low-frequency dominant failure grain in the M1 structural layer. It is easy to understand that based on the same method, the low-frequency failure sizes of the M2 and M3 structural layers can be calculated.

[0082] 3) Assuming that the current high-frequency dominant failure weight value is α, the high-frequency failure weight size of each structural layer is obtained according to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value, that is, the high-frequency failure weight size of each structural layer is calculated according to the following formula:

[0083]

[0084] The result obtained from the formula is the high-frequency failure weight size of the M1 structural layer. Based on the same method, the high-frequency failure weight sizes of the M2 and M3 structural layers can be calculated.

[0085] 4) According to the structural layer high-frequency failure weight size and the structural layer low-frequency failure size of the same structural layer, the structural layer failure size is obtained to obtain the structural layer failure size of each structural layer, that is, the structural layer failure size of each structural layer is calculated according to the following formula:

[0086]

[0087] In the formula, F1 is the structural layer failure size of the wafer M1 structural layer. Similarly, the structural layer failure sizes F2 and F3 of the wafers M2 and M3 structural layers can be calculated.

[0088]

[0089]

[0090] It can be seen that the structural layer failure size of each structural layer of the wafer obtained includes the current high-frequency dominant failure weight value, so that the high-frequency failure weight size of each structural layer with increased weight can be obtained, thereby making the high-frequency test failure data stand out and not be overwhelmed by the low-frequency test failure data.

[0091] 5) Obtain the structural layer failure size of each structural layer of the wafer, and then obtain the failure size ratio of each structural layer of the wafer according to the failure size of each structural layer, that is, calculate the failure size ratio of each structural layer of the wafer according to the following formula:

[0092] F1_P=(F1 / (F1+F2+F3))*100%

[0093] F2_P=(F2 / (F1+F2+F3))*100%

[0094] F3_P=(F3 / (F1+F2+F3))*100%

[0095] In this way, the failure size ratio of each structural layer of the wafer is obtained through the structural layer failure size of each structural layer of the wafer, which provides a basis for further calculating the failure deviation value of each structural layer.

[0096] Step S51: acquiring the design size ratio of each structural layer of the wafer according to the design size of each structural layer of the wafer.

[0097] Assuming that the design size of the wafer M1-M3 structure layer is D1-D3, the design size ratio of each structure layer is:

[0098] D1_P=(D1 / (D1+D2+D3))*100%

[0099] D2_P=(D2 / (D1+D2+D3))*100%

[0100] D3_P=(D3 / (D1+D2+D3))*100%

[0101] Step S52: According to the failure size ratio and the design size ratio of the same structural layer, the failure deviation value of the structural layer is obtained to obtain each failure deviation value, that is, the failure deviation values ​​GAP1-GAP3 of the structural layers M1-M3 are:

[0102] GAP1=F1_P-D1_P

[0103] GAP2=F2_P-D2_P

[0104] GAP3=F3_P-D3_P

[0105] It can be seen that according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominated failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominated failure grain, the current high-frequency dominated failure weight value and the design size of each structural layer of the wafer, the failure deviation value of each structural layer can be finally obtained, and then the failure conditions of each structural layer of the wafer can be further analyzed according to the failure deviation value of each structural layer, so as to obtain the required high-quality high-frequency test electrical failure analysis results.

[0106] After the failure deviation value is obtained, step S24 is further executed: determining whether the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, if not, executing step S25, and if so, executing step S26.

[0107] After the failure deviation value of each structural layer is obtained, it is determined whether the failure deviation value meets a predetermined deviation threshold.

[0108] The predetermined deviation threshold may adopt the threshold requirement predetermined in the actual failure analysis tool. For example, the YE tool in the EDA failure analysis tool combined with actual verification shows that the predetermined deviation threshold is preferably above 10%. The present application does not limit the value of the predetermined deviation threshold. In different embodiments, different failure analysis tools may be used to select a suitable predetermined deviation threshold.

[0109] When the predetermined deviation threshold is met, it indicates that the maximum failure impact layer can be determined according to the failure deviation value, otherwise, it is necessary to continue to adjust the current high-frequency dominant failure weight value, that is, execute step S25.

[0110] Step S25: adjusting the current high-frequency dominant failure weight value according to the failure deviation value and the predetermined deviation threshold, and continuing to execute step S23.

[0111] By adjusting the current high-frequency dominant failure weight value, step S23 is continued to be executed to obtain different high-frequency failure weight sizes of each structural layer, and then obtain the structural layer failure sizes of each structural layer of different wafers, and further calculate the failure size ratio of each structural layer.

[0112] Specifically, the adjustment of the current high-frequency dominant failure weight value can be adjusted according to the relationship between the failure deviation value and the predetermined deviation threshold. When the gap between each failure deviation value and the predetermined deviation threshold is large, the adjusted current high-frequency dominant failure weight value can be made larger than the preliminarily determined current high-frequency dominant failure weight value. When the gap between at least one failure deviation value and the predetermined deviation threshold is small, the adjustment amplitude can also be made smaller.

[0113] Step S26: Obtain the maximum failure affected layer corresponding to the maximum failure deviation value.

[0114] When the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, the maximum failure deviation value and the maximum failure affected layer corresponding to the maximum failure deviation value can be obtained.

[0115] It is easy to understand that the maximum failure impact layer is the structural layer corresponding to the maximum failure deviation value, that is, the structural layer that has the greatest impact on the failure, so that a more detailed analysis can be performed on the structural layer.

[0116] In this way, after obtaining the failure deviation value of each of the structural layers, the current high-frequency dominant failure weight value can be adjusted according to the failure deviation value and the predetermined deviation threshold until the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, and the maximum failure influence layer corresponding to the maximum failure deviation value is obtained.

[0117] In a specific embodiment, in order to facilitate the acquisition and adjustment of the current high-frequency dominant failure weight value, the step of acquiring the current high-frequency dominant failure weight value includes:

[0118] Randomly selecting a high-frequency dominant failure weight value within a predetermined high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value;

[0119] The step of adjusting the current high-frequency dominant failure weight value according to the failure deviation value and the predetermined deviation threshold may include:

[0120] When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased.

[0121] In a specific embodiment, the predetermined high-frequency dominant failure weight value range may be 1-10. The present application does not limit the range of the high-frequency dominant failure weight value. In different embodiments, other suitable ranges of high-frequency dominant failure weight values ​​may be used.

[0122] To clearly explain the steps of adjusting the current high-frequency dominant failure weight value, the above example is continued to be used to explain the predetermined high-frequency dominant failure weight value range of 1-10 and the predetermined deviation threshold of 10%.

[0123] First, within a predetermined high-frequency dominant failure weight value range of 1-10, a high-frequency dominant failure weight value is randomly selected as the current high-frequency dominant failure weight value, and then the current high-frequency dominant failure weight value α in F1-F3 is adjusted according to the calculation formula of the failure deviation value. When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased until the failure deviation value of at least one structural layer meets the predetermined deviation threshold. At this time, the maximum failure influence layer corresponding to the maximum failure deviation value can be obtained, and the maximum failure influence layer is the maximum failure influence layer corresponding to the high-frequency test failure.

[0124] It can be seen that through the aforementioned adjustment method of the current high-frequency dominant failure weight value, the weight of the high-frequency failure size of each structural layer can be increased relatively quickly, so that the high-frequency test failure data can be highlighted more quickly, thereby accurately obtaining the maximum failure influence layer corresponding to the high-frequency test failure, and further obtaining high-quality high-frequency test electrical failure analysis results based on the obtained maximum failure influence layer.

[0125] In another specific embodiment, in order to facilitate the acquisition and adjustment of the current high-frequency dominant failure weight value, the step of acquiring the current high-frequency dominant failure weight value includes:

[0126] Determine the minimum value within the predetermined high frequency dominant failure weight value range as the current high frequency dominant failure weight value;

[0127] The step of adjusting the current high-frequency dominant failure weight value according to the failure deviation value and the predetermined deviation threshold comprises:

[0128] When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased according to a predetermined increment.

[0129] Continuing with the above example, the following description is given by taking the predetermined high-frequency dominant failure weight value range as 1-10 and the predetermined deviation threshold as 10%.

[0130] First, within a predetermined high-frequency dominant failure weight value range of 1-10, the minimum value 1 within the predetermined high-frequency dominant failure weight value range is selected as the current high-frequency dominant failure weight value, and then the current high-frequency dominant failure weight value α in F1-F3 is adjusted according to the calculation formula of the failure deviation value. When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased according to a predetermined increment.

[0131] In different embodiments, the current high-frequency dominant failure weight value can be increased according to different predetermined increments. For example, in a specific embodiment, the current high-frequency dominant failure weight value can be gradually increased with a predetermined increment of 0.1 until the failure deviation value of a structural layer meets the predetermined deviation threshold. At this time, the maximum failure influence layer corresponding to the failure deviation value can be obtained, and the maximum failure influence layer is the maximum failure influence layer corresponding to the high-frequency test failure.

[0132] In another specific embodiment, a larger predetermined increment, for example, greater than 5, can be used to increase the current high-frequency dominant failure weight value. At this time, since a larger predetermined increment is used, it is possible that among the various failure deviation values ​​obtained, there is already a failure deviation value of at least one structural layer that meets the predetermined deviation threshold. At this time, the maximum failure influence layer corresponding to the maximum failure deviation value can be obtained.

[0133] It can be seen that adopting different adjustment methods can make the current high-frequency dominant failure weight value adjustment method more flexible and diverse, and if a larger predetermined increment is used to increase the current high-frequency dominant failure weight value, it is possible to obtain the failure deviation value of at least one structural layer at one time to meet the predetermined deviation threshold, making the acquisition of failure deviation value simpler and faster, and thus the maximum failure influence layer corresponding to the maximum failure deviation value can be obtained more quickly, so that high-quality high-frequency test electrical failure analysis results can be obtained more quickly based on the obtained maximum failure influence layer.

[0134] In summary, the electrical failure analysis method provided in the embodiment of the present application determines each high-frequency dominant failure grain and each low-frequency dominant failure grain according to the failure log of each failed grain of the wafer, so as to distinguish each high-frequency dominant failure data from each low-frequency dominant failure data, and then obtains the failure deviation value according to the design size of each structural layer of the wafer, the failure size of each high-frequency dominant failure grain combined with the current high-frequency dominant failure weight value after weight adjustment, and the failure size of each low-frequency dominant failure grain without weight adjustment. In this way, the addition of the failure size of each low-frequency dominant failure grain can ensure the amount of data required for electrical failure analysis. At the same time, when obtaining the failure deviation value, the weight of the high-frequency failure size can be increased by the current high-frequency dominant failure weight value, and then the current high-frequency dominant failure weight value is adjusted in combination with the predetermined deviation threshold, so that the high-frequency dominant failure data is highlighted until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and then the maximum failure deviation value is obtained to obtain the maximum failure influence layer corresponding to the maximum failure deviation value, and the structural layer that accurately causes the grain failure is obtained. It can be seen that the electrical failure analysis method provided in the embodiment of the present application can utilize the dominant failure data of low-frequency tests to ensure sufficient data volume, and can also make the dominant failure data of high-frequency tests stand out without being overwhelmed by the low-frequency test failure data, thereby fully displaying the impact of high-frequency test failure data and improving the accuracy of high-frequency test electrical failure analysis.

[0135] The present application also provides an electrical failure analysis device, which is described below. The electrical failure analysis device described below can be considered as a functional module architecture required for an electronic device (such as a PC) to implement the electrical failure analysis method provided in the present application. The content of the electrical failure analysis device described below can be referenced to the content of the electrical failure analysis method described above.

[0136] In a specific embodiment, please refer to Figure 6 , Figure 6 A block diagram of an electrical failure analysis device provided in an embodiment of the present application, the device may include:

[0137] A failure log acquisition module 60 is adapted to acquire a failure log of each failed die of the wafer;

[0138] A failed grain determination module 61 is adapted to determine each high-frequency dominant failed grain and each low-frequency dominant failed grain according to the high-frequency test results and the low-frequency test results in the failure log of each failed grain;

[0139] A high frequency dominant failure weight value acquisition module 62 is adapted to acquire a current high frequency dominant failure weight value;

[0140] The maximum failure influence layer acquisition module 63 is suitable for obtaining the failure deviation value of each structural layer according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, adjusting the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold until the failure deviation value of at least one of the structural layers meets the predetermined deviation threshold, and obtaining the maximum failure influence layer corresponding to the maximum failure deviation value.

[0141] In some embodiments, the failure log acquisition module 60 includes:

[0142] A first failure log acquisition unit is adapted to test the wafer using the test items of the wafer test, and acquire each failed die and a first failure log of each failed die, wherein the low-frequency test items in the test items are less than the high-frequency test items;

[0143] A supplementary unit, adapted to supplement the low-frequency test items;

[0144] A second failure log acquisition unit, adapted to perform a second test on each of the failed dies according to the supplemented low-frequency test items, and acquire a second failure log of each of the failed dies;

[0145] The failure log acquisition unit is adapted to acquire the failure log of each failed die according to the first failure log and the second failure log.

[0146] In some further embodiments, the supplementing unit, adapted to supplement the low-frequency test items, comprises:

[0147] The low-frequency test items are supplemented according to the high-frequency test items.

[0148] In some embodiments, the failed die determination module 61 is adapted to determine each high-frequency dominant failed die and each low-frequency dominant failed die according to the high-frequency test results and the low-frequency test results in the failure log of each failed die, including:

[0149] When the low-frequency test result of the failed grain is failure, determining the failed grain to be a low-frequency dominant failed grain;

[0150] When the low-frequency test result of the failed die is passed, but the high-frequency test result of the failed die is failed, it is determined that the failed die is a high-frequency dominant failed die.

[0151] In some embodiments, the maximum failure affected layer acquisition module 63 is adapted to acquire the failure deviation value of each structural layer according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, including:

[0152] Obtaining the failure size ratio of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain, and the current high-frequency dominant failure weight value;

[0153] According to the design dimensions of each of the structural layers of the wafer, obtaining the design dimension ratio of each of the structural layers of the wafer;

[0154] According to the failure size ratio and the design size ratio of the same structural layer, the failure deviation value of the structural layer is acquired to obtain each failure deviation value.

[0155] In some further embodiments, the maximum failure affected layer acquisition module 63 is adapted to acquire the failure size ratio of each structural layer of the wafer according to the high frequency failure size of each structural layer of each high frequency dominant failure grain, the low frequency failure size of each structural layer of each low frequency dominant failure grain and the current high frequency dominant failure weight value, including:

[0156] According to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value, the structural layer failure size of each structural layer of the wafer is obtained;

[0157] According to the failure size of each structural layer, the failure size ratio of each structural layer of the wafer is obtained.

[0158] In some further embodiments, the maximum failure affected layer acquisition module 63 is adapted to acquire the structural layer failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain, and the current high-frequency dominant failure weight value, including:

[0159] Obtaining the sum of the high-frequency failure sizes of the same structural layer of each of the high-frequency dominant failure grains to obtain the high-frequency failure size of each structural layer, and obtaining the sum of the low-frequency failure sizes of the same structural layer of each of the low-frequency dominant failure grains to obtain the low-frequency failure size of each structural layer;

[0160] According to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value, obtaining the high-frequency failure weight size of each structural layer;

[0161] The structural layer failure size is acquired according to the structural layer high-frequency failure weight size and the structural layer low-frequency failure size of the same structural layer, so as to obtain the structural layer failure size of each structural layer.

[0162] In some embodiments, the high frequency dominant failure weight value acquisition module 62 is adapted to acquire the current high frequency dominant failure weight value, including:

[0163] Randomly selecting a high-frequency dominant failure weight value within a predetermined high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value;

[0164] The maximum failure impact layer acquisition module 63 is adapted to adjust the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, including:

[0165] When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased.

[0166] In some embodiments, the high frequency dominant failure weight value acquisition module 62 is adapted to acquire the current high frequency dominant failure weight value, including:

[0167] Determine the minimum value within the predetermined high frequency dominant failure weight value range as the current high frequency dominant failure weight value;

[0168] The maximum failure impact layer acquisition module 63 is adapted to adjust the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, including:

[0169] When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased according to a predetermined increment.

[0170] It can be seen that the electrical failure analysis device provided in the embodiment of the present application determines each high-frequency dominant failure grain and each low-frequency dominant failure grain according to the failure log of each failed grain of the wafer, so as to distinguish each high-frequency dominant failure data from each low-frequency dominant failure data, and then obtains the failure deviation value according to the design size of each structural layer of the wafer, the failure size of each high-frequency dominant failure grain combined with the current high-frequency dominant failure weight value after weight adjustment, and the failure size of each low-frequency dominant failure grain without weight adjustment. In this way, the addition of the failure size of each low-frequency dominant failure grain can ensure the amount of data required for electrical failure analysis. At the same time, when obtaining the failure deviation value, the weight of the high-frequency failure size can be increased by the current high-frequency dominant failure weight value, and then the current high-frequency dominant failure weight value can be adjusted in combination with the predetermined deviation threshold, so that the high-frequency dominant failure data is highlighted until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and then the maximum failure deviation value is obtained to obtain the maximum failure influence layer corresponding to the maximum failure deviation value, and the structural layer that accurately causes the grain failure is obtained. The electrical failure analysis device provided in the embodiment of the present application can utilize low-frequency test dominant failure data to ensure sufficient data volume, and can also make high-frequency dominant failure data stand out without being overwhelmed by low-frequency test failure data, thereby fully displaying the impact of high-frequency test failure data and improving the accuracy of high-frequency test electrical failure analysis.

[0171] An embodiment of the present application provides a storage medium storing a program suitable for electrical failure analysis to implement the electrical failure analysis method as described above.

[0172] An embodiment of the present application provides an electronic device, comprising at least one memory and at least one processor; the memory stores a program, and the processor calls the program to execute the electrical failure analysis method as described above.

[0173] The storage medium and electronic device provided in the embodiments of the present application determine each high-frequency dominant failure grain and each low-frequency dominant failure grain according to the failure log of each failed grain of the wafer, so as to distinguish each high-frequency dominant failure data from each low-frequency dominant failure data, and then obtain the failure deviation value according to the design size of each structural layer of the wafer, the failure size of each high-frequency dominant failure grain combined with the current high-frequency dominant failure weight value after weight adjustment and the failure size of each low-frequency dominant failure grain without weight adjustment. In this way, the addition of the failure size of each low-frequency dominant failure grain can ensure the amount of data required for electrical failure analysis. At the same time, when obtaining the failure deviation value, the weight of the high-frequency failure size can be increased by the current high-frequency dominant failure weight value, and then the current high-frequency dominant failure weight value can be adjusted in combination with the predetermined deviation threshold to make the high-frequency dominant failure data stand out until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and then the maximum failure deviation value is obtained to obtain the maximum failure influence layer corresponding to the maximum failure deviation value, and the structural layer that accurately causes the grain failure is obtained. The storage medium and electronic device provided in the embodiments of the present application can utilize low-frequency test dominant failure data to ensure sufficient data volume, and can also make high-frequency dominant failure data stand out without being overwhelmed by low-frequency test failure data, fully displaying the impact of high-frequency test failure data and improving the accuracy of high-frequency test electrical failure analysis.

[0174] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. An electrical failure analysis method, characterized in that: include: Obtain failure logs of each failed die of the wafer; According to the high-frequency test results and the low-frequency test results in the failure log of each of the failed grains, each high-frequency-dominated failed grain and each low-frequency-dominated failed grain are determined, wherein the high-frequency-dominated failed grain is a failed core grain that passes the low-frequency test result and fails the high-frequency test result, and the low-frequency-dominated failed grain is a failed core grain that fails the low-frequency test result; Obtaining a current high frequency dominant failure weight value, wherein the current high frequency dominant failure weight value is randomly selected from a predetermined high frequency dominant failure weight value range; According to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, the failure deviation value of each structural layer is obtained; according to the failure deviation value and a predetermined deviation threshold, the current high-frequency dominant failure weight value is adjusted until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and the maximum failure affected layer corresponding to the maximum failure deviation value is obtained; Among them, the high-frequency failure size of each structural layer is the sum of the high-frequency failure sizes of the same structural layer of each high-frequency dominant failure grain; the low-frequency failure size of each structural layer is the sum of the low-frequency failure sizes of the same structural layer of each low-frequency dominant failure grain; the failure deviation value of the structural layer is the difference between the failure size ratio and the design size ratio of the same structural layer, and the failure size ratio is the ratio of the structural layer failure size of the current structural layer to the total failure sizes of the structural layers of the wafer; the design size ratio is the ratio of the design size of the current structural layer to the total design sizes of each structural layer of the wafer; the maximum failure influence layer is the structural layer corresponding to the maximum failure deviation value.

2. The electrical failure analysis method according to claim 1, characterized in that: The step of obtaining the failure log of each failed die of the wafer includes: Using the test items of wafer testing, the wafer is tested to obtain each failed die and a first failure log of each failed die, wherein the low-frequency test items in the test items are less than the high-frequency test items; Supplement the low-frequency test items; Perform a second test on each of the failed grains according to the supplemented low-frequency test items to obtain a second failure log of each of the failed grains; The failure logs of the respective failed dies are acquired according to the first failure log and the second failure log.

3. The electrical failure analysis method according to claim 2, characterized in that: The step of supplementing the low-frequency test items includes: supplementing the low-frequency test items according to the high-frequency test items.

4. The electrical failure analysis method according to claim 1, characterized in that: The failure size ratio of each structural layer of the wafer is obtained according to the high-frequency failure size of each structural layer of each high-frequency dominated failure grain, the low-frequency failure size of each structural layer of each low-frequency dominated failure grain and the current high-frequency dominated failure weight value.

5. The electrical failure analysis method according to claim 4, characterized in that: The step of obtaining the failure size ratio of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value comprises: According to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value, the structural layer failure size of each structural layer of the wafer is obtained; According to the failure size of each structural layer, the failure size ratio of each structural layer of the wafer is obtained.

6. The electrical failure analysis method according to claim 5, characterized in that: The step of obtaining the structural layer failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain, and the current high-frequency dominant failure weight value comprises: Obtaining the sum of the high-frequency failure sizes of the same structural layer of each of the high-frequency dominant failure grains to obtain the high-frequency failure size of each structural layer, and obtaining the sum of the low-frequency failure sizes of the same structural layer of each of the low-frequency dominant failure grains to obtain the low-frequency failure size of each structural layer; According to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value, obtaining the high-frequency failure weight size of each structural layer; The structural layer failure size is acquired according to the structural layer high-frequency failure weight size and the structural layer low-frequency failure size of the same structural layer, so as to obtain the structural layer failure size of each structural layer.

7. The electrical failure analysis method according to any one of claims 1 to 6, characterized in that: The step of obtaining the current high-frequency dominant failure weight value comprises: Randomly selecting a high-frequency dominant failure weight value within a predetermined high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value; The step of adjusting the current high-frequency dominant failure weight value according to the failure deviation value and the predetermined deviation threshold comprises: When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased.

8. The electrical failure analysis method according to any one of claims 1 to 6, characterized in that: The step of obtaining the current high-frequency dominant failure weight value comprises: Determine the minimum value within the predetermined high frequency dominant failure weight value range as the current high frequency dominant failure weight value; The step of adjusting the current high-frequency dominant failure weight value according to the failure deviation value and the predetermined deviation threshold comprises: When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased according to a predetermined increment.

9. An electrical failure analysis device, characterized in that: include: A failure log acquisition module, adapted to acquire the failure log of each failed die of the wafer; A failed grain determination module is adapted to determine each high-frequency-dominated failed grain and each low-frequency-dominated failed grain according to the high-frequency test results and the low-frequency test results in the failure log of each failed grain, wherein the high-frequency-dominated failed grain is a failed core grain that passes the low-frequency test result and fails the high-frequency test result, and the low-frequency-dominated failed grain is a failed core grain that fails the low-frequency test result; A high frequency dominant failure weight value acquisition module, adapted to acquire a current high frequency dominant failure weight value, wherein the current high frequency dominant failure weight value is randomly selected from a predetermined high frequency dominant failure weight value range; The maximum failure-affected layer acquisition module is adapted to acquire the failure deviation value of each structural layer according to the high-frequency failure size of each structural layer in the failure log of each high-frequency-dominated failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency-dominated failure grain, the current high-frequency-dominated failure weight value, and the design size of each structural layer of the wafer, and to adjust the current high-frequency-dominated failure weight value according to the failure deviation value and a predetermined deviation threshold until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and to acquire the maximum failure-affected layer corresponding to the maximum failure deviation value, wherein each The high-frequency failure size of each structural layer is the sum of the high-frequency failure sizes of the same structural layer of each high-frequency dominant failure grain; the low-frequency failure size of each structural layer is the sum of the low-frequency failure sizes of the same structural layer of each low-frequency dominant failure grain; the failure deviation value of the structural layer is the difference between the failure size ratio and the design size ratio of the same structural layer, the failure size ratio is the ratio of the structural layer failure size of the current structural layer to the total failure sizes of the structural layers of the wafer; the design size ratio is the ratio of the design size of the current structural layer to the total design sizes of each structural layer of the wafer; the maximum failure influence layer is the structural layer corresponding to the maximum failure deviation value.

10. The electrical failure analysis device according to claim 9, characterized in that: The failure log acquisition module includes: A first failure log acquisition unit is adapted to test the wafer using the test items of the wafer test, and acquire each failed die and a first failure log of each failed die, wherein the low-frequency test items in the test items are less than the high-frequency test items; A supplementary unit, adapted to supplement the low-frequency test items; A second failure log acquisition unit, adapted to perform a second test on each of the failed dies according to the supplemented low-frequency test items, and acquire a second failure log of each of the failed dies; The failure log acquisition unit is adapted to acquire the failure log of each failed die according to the first failure log and the second failure log.

11. The electrical failure analysis device according to claim 10, characterized in that: The supplementary unit is suitable for supplementing the low-frequency test items including: The low-frequency test items are supplemented according to the high-frequency test items.

12. The electrical failure analysis device according to claim 9, characterized in that: The failure deviation value acquisition module is suitable for obtaining the failure size ratio of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value.

13. The electrical failure analysis device according to claim 12, characterized in that: The failure deviation value acquisition module is adapted to acquire the failure size ratio of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain, and the current high-frequency dominant failure weight value, including: According to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value, the structural layer failure size of each structural layer of the wafer is obtained; According to the failure size of each structural layer, the failure size ratio of each structural layer of the wafer is obtained.

14. The electrical failure analysis device according to claim 13, characterized in that: The failure deviation value acquisition module is adapted to acquire the structural layer failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain, and the current high-frequency dominant failure weight value, including: Obtaining the sum of the high-frequency failure sizes of the same structural layer of each of the high-frequency dominant failure grains to obtain the high-frequency failure size of each structural layer, and obtaining the sum of the low-frequency failure sizes of the same structural layer of each of the low-frequency dominant failure grains to obtain the low-frequency failure size of each structural layer; According to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value, obtaining the high-frequency failure weight size of each structural layer; The structural layer failure size is acquired according to the structural layer high-frequency failure weight size and the structural layer low-frequency failure size of the same structural layer, so as to obtain the structural layer failure size of each structural layer.

15. The electrical failure analysis device according to claim 9, characterized in that: The high-frequency dominant failure weight value acquisition module is adapted to acquire the current high-frequency dominant failure weight value, including: Randomly selecting a high-frequency dominant failure weight value within a predetermined high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value; The failure deviation value acquisition module is adapted to adjust the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, and includes: When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased.

16. The electrical failure analysis device according to claim 9, characterized in that: The high-frequency dominant failure weight value acquisition module is adapted to acquire the current high-frequency dominant failure weight value, including: Determine the minimum value within the predetermined high frequency dominant failure weight value range as the current high frequency dominant failure weight value; The failure deviation value acquisition module is adapted to adjust the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, and includes: When the failure deviation value is less than the predetermined deviation threshold, the current high-frequency dominant failure weight value is increased according to a predetermined increment.

17. A storage medium, characterized in that: The storage medium stores a program suitable for electrical failure analysis to implement the electrical failure analysis method according to any one of claims 1 to 8.

18. An electronic device, characterized in that: The system comprises at least one memory and at least one processor; the memory stores a program, and the processor calls the program to execute the electrical failure analysis method according to any one of claims 1 to 8.

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