A program burning device and method

Abstract

The present invention relates to a program burning device and method, wherein the program burning device comprises a control module, a Flash module, and a SoC module, wherein the control module, the Flash module, and the SoC module are sequentially connected in series; a program burning method, wherein the burning method is constructed based on the burning device, and the burning method is divided into an online burning method, an offline burning method, and an online and offline mixed burning method according to different networking states, wherein each SoC station in the SoC module is started in a Flash startup mode, and the storage enable pin is controlled by the control module to realize automatic burning of the internal program of the Flash storage chip into its RAM; and after all SoC station programs in the SoC module are burned, the power supply of the Flash storage chip is cut off. The present invention has the advantages of convenient operation, cost saving, and resource saving.

Description

Technical Field

[0001] The present invention relates to a program burning technology, in particular to a program burning device and method. Background Art

[0002] At present, in the SoC (System on Chip) aging verification, some SoCs omit the cost of embedded Flash (Flash EEPROM Memory) storage modules at the beginning of the design. Therefore, in this type of SoC aging verification, it is necessary to match the corresponding Flash storage chip for aging program storage. The problems here are: first, the cost problem. The aging temperature of military chips is +125℃. Therefore, when SoC is aged, the corresponding Flash storage chip with a resistance of +125℃ is required for SoC aging and other program storage. Compared with the consumer-grade Flash storage chip for ordinary testing, the cost is doubled; second, the labor time. On the workstation of the SoC aging board, each workstation corresponds to a Flash storage chip, and each Flash storage chip needs to be burned online or offline separately, which makes such burning time-consuming and labor-intensive; third, the waste of resources. After the completion of this project, each Flash storage chip with a resistance of +125℃ is difficult to continue to use in other projects, which causes a great waste of resources. Summary of the invention

[0003] To this end, the technical problem to be solved by the present invention is to overcome the shortcomings of the prior art in verification such as aging of SoC without an embedded Flash storage module and meet the verification requirements in different situations, thereby providing a program burning device and method.

[0004] In order to solve the above technical problems, a program burning device is provided, characterized in that it comprises a control module, a Flash module, and a SoC module, wherein the control module, the Flash module, and the SoC module are sequentially connected in series;

[0005] The control module comprises a serial port bus, a JTAG signal detection circuit, a SoC workstation signal detection circuit, a SoC storage enable pin control circuit, a Flash power control circuit, a single chip microcomputer and an LED display circuit; the serial port bus, the JTAG signal detection circuit, the SoC workstation signal detection circuit, the SoC storage enable pin control circuit, the Flash power control circuit and the LED display circuit are respectively connected to the single chip microcomputer; the serial port bus, the JTAG signal detection circuit, the SoC workstation signal detection circuit and the SoC storage enable pin control circuit are respectively connected to the SoC module; the Flash power control circuit is connected to the Flash module.

[0006] In one embodiment of the present invention, the SoC module includes 2n SoC stations; the matrix layout of the SoC module is n rows*2 columns, or 2 rows*n columns, where n is a positive natural number.

[0007] In one embodiment of the present invention, each SoC station is provided with a JTAG debugging port, and the number of pins of the JTAG debugging port is 16 bits.

[0008] In one embodiment of the present invention, the 10th pin of the JTAG debugging port is a JTAG detection signal pin; and the JTAG detection signal pin is pulled up by a power supply.

[0009] In one embodiment of the present invention, any GPIO pin in the SoC station is connected to the SoC station signal detection circuit, and the pull-down resistor of the GPIO pin is grounded.

[0010] In one embodiment of the present invention, all address lines, all data lines, and all serial port buses of the SoC station are individually connected to the bus of the SOC module, and the data bit width of the address lines and data lines is not limited to 16 bits.

[0011] In one embodiment of the present invention, both the JTAG signal detection circuit and the SoC station signal detection circuit are provided with photoelectric coupling devices.

[0012] In one embodiment of the present invention, the single chip microcomputer includes a bus controller, a master-slave controller and a GPIO controller; the bus controller is connected to the serial port bus; the master-slave controller is connected to the JTAG signal detection circuit; the GPIO controller is respectively connected to the SoC station signal detection circuit, the SoC storage enable pin control circuit, the Flash power control circuit and the LED display circuit.

[0013] A program burning method, the burning method is implemented based on the burning device, and the burning method is divided into an online burning method, an offline burning method, and an online and offline mixed burning method according to different networking states. The online burning method comprises the following steps:

[0014] Step S11: The Flash storage chip is placed in the socket of the aging board, and the host computer is connected to the JTAG terminal on any SoC station on the aging board through JTAG;

[0015] Step S12: the single-chip microcomputer detects that the JTAG pin 10 of the SoC station, that is, the JTAG detection pin level is low, and the low level lasts for more than 200ms, then the single-chip microcomputer changes to slave mode, that is, device mode, and the SoC station is in master mode, that is, host mode;

[0016] Step S13: The host computer first erases the contents of the Flash storage chip, and re-burns the aging program code, and adds a GPIO feedback prompt after the burning is completed. When the burning of any station is completed, the SoC on the station will send a print message of the burning completion to the host computer, and the host computer will display a prompt that the program burning of the station is completed;

[0017] Step S14: the host computer sends a command to the MCU through the JTAG terminal, instructing the MCU to connect to the storage enable pin of the designated SoC station, and then burns the program to the designated SoC station. The SoC on the station will send a print message of the completion of burning to the host computer, and the host computer will display a prompt that the program burning of the station is completed. At the same time, the SoC station will send a burning completion message to the MCU through the serial port. After receiving the feedback information from the SoC station, the MCU disconnects the storage enable pin connection of the station;

[0018] When the aging program code of the designated SoC station is completely burned, the host computer disconnects the JTAG terminal connecting the SoC station and the aging board, and the JTAG detection signal pin of the SoC station is converted from a low level to a high level. The microcontroller detects that the high level of the JTAG detection signal pin of the SoC station lasts for more than 200ms, and determines that the JTAG terminal of the SoC station is not connected to the host computer, and cuts off the Flash power supply through the Flash power control pin.

[0019] The offline burning method comprises the following steps:

[0020] Step S21: Burn the aging program through a Flash external professional burning tool, put it into the Flash socket of the aging board, and power it on;

[0021] Step S22: The single-chip microcomputer detects the level of the SoC station detection pin on the aging board, that is, a high level indicates that a SoC chip is placed in the station and has been successfully identified;

[0022] Step S23: the single-chip microcomputer detects that there is a station where the SoC chip is correctly placed on the aging board, sequentially controls the connection of the SoC storage enable pins, and burns the program to the SoC station;

[0023] Step S24: After each station is burned, a GPIO pin of the SoC station will send feedback information of burning completion to the microcontroller through the serial port;

[0024] Step S25: After receiving the information, the single-chip microcomputer disconnects the SoC storage enable pin connection of the SoC station and connects the next SoC station whose detection pin level is high;

[0025] Step S26: When all SoC station programs whose SoC station detection pin level is high on the aging board are burned, the single-chip microcomputer cuts off the Flash power supply through the Flash power control pin, and sends several square waves to the LED display circuit through the GPIO, indicating that the entire board station program has been burned;

[0026] The online and offline hybrid burning method comprises the following steps:

[0027] Step S31: The Flash storage chip is placed in the socket of the aging board, and the host computer is connected to the JTAG terminal on any SoC station on the aging board through JTAG;

[0028] Step S32: the single-chip microcomputer detects that the JTAG pin 10 of the SoC station, that is, the JTAG detection pin level is low, then the single-chip microcomputer changes to slave mode, that is, device mode, and the SoC station is in master mode, that is, host mode;

[0029] Step S33: The host computer first erases the contents of the Flash storage chip, and re-burns the aging program code, and adds a GPIO feedback prompt after the burning is completed. When the burning of any station is completed, the SoC on the station will send a print message of the burning completion to the host computer through JTAG, and the host computer will display a prompt that the program burning of the station is completed;

[0030] Step S34: the aging board is powered off, the connection between the host computer and JTAG is disconnected, and then the aging board is powered on again;

[0031] Step S35: The single-chip microcomputer detects the level of the SoC station detection pin on the aging board, that is, a high level indicates that a SoC chip is placed in the station and is successfully identified;

[0032] Step S36: the single-chip microcomputer detects the station with the SoC chip on the aging board, sequentially controls the connection of the SoC storage enable pins, and burns the program to the SoC station;

[0033] Step S37: After each station is burned, a GPIO pin of the station will send feedback information of burning completion to the microcontroller through the serial port;

[0034] Step S38: After receiving the information, the single-chip microcomputer disconnects the SoC storage enable pin connection of the station and connects the next SoC station whose detection pin level is high;

[0035] Step S39: When all SoC station programs whose SoC station detection pin level is high on the aging board are burned, the microcontroller cuts off the Flash power supply through the Flash power control pin and sends several square waves to the LED display circuit through GPIO, indicating that the entire board station program has been burned.

[0036] The above technical solution of the present invention has the following advantages over the prior art: the program burning device and method described in the present invention provide three burning methods, namely, an online burning method, an offline burning method, and an online and offline mixed burning method, and are easy to operate, saving manpower and resource costs. The program to be burned in the JTAG format is transmitted to the chip to be burned through the communication interface, thereby eliminating the need for encoding and improving the reliability and safety of burning. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0038] Figure 1 The system framework diagram of a program burning device.

[0039] Figure 2 This is the JTAG circuit diagram of the first SoC station in the JTAG signal detection circuit of the present invention.

[0040] Figure 3 This is a block diagram of the control module described in the present invention.

[0041] Figure 4 This is a signal detection circuit diagram of the present invention.

[0042] Figure 5 This is a storage enable signal control circuit diagram of the present invention.

[0043] Figure 6 This is a Flash power supply control circuit diagram of the present invention.

[0044] Figure 7 This is a block diagram of the online program burning of the system described in the present invention.

[0045] Figure 8 This is a block diagram of the system off-line program burning described in the present invention.

[0046] Fig. 9 This is a block diagram of the online and offline mixed program burning of the system described in the present invention. DETAILED DESCRIPTION

[0047] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention. Embodiment 1

[0048] like Figure 1 As shown, this embodiment provides a program burning device, including a control module, a Flash module, and a SoC module, wherein the control module, the Flash module, and the SoC module are sequentially connected in series;

[0049] like Figure 3 As shown, the control module includes a serial port bus, a JTAG signal detection circuit, a SoC work station signal detection circuit, a SoC storage enable pin control circuit, a Flash power control circuit, a single-chip microcomputer and an LED display circuit; the serial port bus, the JTAG signal detection circuit, the SoC work station signal detection circuit, the SoC storage enable pin control circuit, the Flash power control circuit and the LED display circuit are respectively connected to the single-chip microcomputer; the serial port bus, the JTAG signal detection circuit, the SoC work station signal detection circuit and the SoC storage enable pin control circuit are respectively connected to the SoC module; the Flash power control circuit is connected to the Flash module.

[0050] Furthermore, the bus communication protocol used by the serial bus may be UART (Universal Asynchronous Receiver / Transmitter), RS232, RS485, CAN (Controller Area Network) or MIL-STD-1553B.

[0051] The Flash module includes a Flash storage chip, which is mainly used to store the aging program of the circuit board card; the serial port bus is mainly a line for the host computer to communicate with the single-chip microcomputer through the SoC station, and a feedback channel for the GPIO after the program is burned in the SoC station; the JTAG signal detection circuit is mainly used to detect the access of the single-chip microcomputer to its external JTAG debugging interface through the SoC station; the SoC station signal detection circuit is mainly used to detect whether the SoC station has a SoC chip; the SoC storage enable pin control circuit is mainly used to control the SoC station by chip selection; the Flash power supply control circuit is mainly used to connect the Flash working power supply and cut off its power supply after the program of all stations of the SoC station is burned; the LED display circuit is mainly used to indicate to the operator that it is briefly lit after the program of all stations of the circuit board card is burned; the bus controller is mainly used to send and receive information of the SoC module; the master-slave controller is mainly used to set the master-slave status of the single-chip microcomputer; the GPIO controller is mainly used to detect and control the status of the GPIO.

[0052] Specifically, after the SoC chip is packaged and tested from the wafer, its BOOT ROM is blank. It is necessary to use JTAG to connect to the host computer, burn the system initialization startup program, and set the external Flash storage chip as the system startup mapping address.

[0053] The SoC module includes 2n SoC workstations; the matrix layout of the SoC module is n rows*2 columns, or 2 rows*n columns, wherein n is a positive natural number.

[0054] Each SoC station side is provided with a JTAG debugging port, and the number of pins of the JTAG debugging port is 16 bits.

[0055] The 10th pin of the JTAG debugging port is a JTAG detection signal pin; the JTAG detection signal pin is a pull-up power supply.

[0056] Specifically, for a better understanding of the JTAG pin access detection process, here we take the first SoC station as an example, and its JTAG pin access detection process is as follows: Figure 4As shown in the figure, the 10th pin of the JTAG terminal is defined as JTAG_DEC_01. Here, JTAG_DEC_01 is the 10th pin definition of the JTAG terminal of the first SoC station and does not represent other meanings. This pin is connected to the diode D1 to prevent device damage caused by reverse connection of the signal and power supply. The purpose of the resistor and capacitor in the circuit is to filter out signal noise and ensure signal stability. The detection signal pin connected to the microcontroller end is defined as SC_DEC_01. U2 is an optocoupler device to isolate the signals on both sides to ensure signal quality.

[0057] Specifically, when the host computer debugging tool is not connected to the 10th pin JTAG_DEC_01 of the JTAG terminal, it is at a high level, the first light emitting diode of the optocoupler device of U2 is lit, the 5th and 6th pins of U2 are turned on, and the SC_DEC_01 level is at a low level.

[0058] Specifically, the JTAG debugging tool of the host computer sets the corresponding pin 10 to a low level. When the host computer debugging tool is connected to the JTAG terminal pin 10 JTAG_DEC_01, JTAG_DEC_01 is at a low level. The first light-emitting diode of the optocoupler device of U2 is not lit because the tube voltage drop does not reach the conduction voltage threshold. The 5th and 6th pins of U2 are not conducting, and the SC_DEC_01 level is at a high level.

[0059] Specifically, the JTAG debugging tool of the host computer corresponds to the 10th pin as GPIO, and the pull-down resistor is connected to the ground, which is a low level.

[0060] Any GPIO pin in the SoC station is connected to the SoC station signal detection circuit, and the pull-down resistor of the GPIO (General-purpose input / output) pin is grounded.

[0061] All address lines, all data lines, and all serial port buses of the SoC workstation are individually connected to the bus of the SOC module, and the data bit width of the address lines and data lines is not limited to 16 bits.

[0062] The JTAG signal detection circuit and the SoC workstation signal detection circuit are both provided with photoelectric coupling devices for signal isolation.

[0063] The Flash power control circuit is provided with a relay to control the Flash power switch operation; further, the device controlled by the single-chip signal can be a triode or a MOS tube, which acts as a switch device. The SoC storage enable pin control circuit uses a signal relay to control the storage enable pin switch; the storage enable pin can be WE, OE or CS.

[0064] The single chip microcomputer comprises a bus controller, a master-slave controller and a GPIO controller; the bus controller is connected to a serial port bus; the master-slave controller is connected to a JTAG signal detection circuit; the GPIO controller is respectively connected to a SoC station signal detection circuit, a SoC storage enable pin control circuit, a Flash power supply control circuit and an LED display circuit.

[0065] Specifically, the master-slave controller of the microcontroller is set. When the pin of the master-slave controller is at a high level, the microcontroller is in device mode; when the pin of the master-slave controller is at a low level, the microcontroller is in host mode.

[0066] Specifically, when the master-slave controller of the single-chip microcomputer recognizes that the level of its SC_DEC_01 pin is high, the master-slave controller level is high at this time, and automatically sets the first SoC station to host mode, and the single-chip microcomputer to device mode. The host computer sends instructions to the single-chip microcomputer through the serial port bus of the first SoC station, and commands the single-chip microcomputer 301 to make the SoC station storage enable pin connected to the first SoC station valid. For ease of understanding, it is assumed that there are only three types of SoC station storage enable pins, namely write enable WE (Write Enable), output enable OE (Output Enable) and chip select CS (Chip Select). Of course, different memory chips have corresponding enable and chip select pins of different types. Here we just take these three types of chip select signal pins as examples.

[0067] Specifically, Figure 5 As shown, the switch of the storage enable pin is controlled by the signal relay LS1. The signal on the left side of the signal relay LS1 is connected to the write enable Flash_WE, output enable Flash_OE and chip select Flash_CS pins of the Flash storage chip, and the signal on the right side is connected to the write enable SoC01_WE, output enable SoC01_OE and chip select SoC01_CS pins of the first SoC station, and the SC_ SoC01_CTL pin that controls the magnet attraction of the signal relay LS1 is connected to the microcontroller. When the SC_ SoC01_CTL pin level is high, the 3rd and 2nd pins of the transistor Q1 are turned on, the 4th and 5th pins of the signal relay LS1 are in the on state, the 1st and 6th pins of the signal relay LS1 are disconnected, the 2nd and 8th pins are disconnected, and the 3rd and 10th pins are disconnected.

[0068] Specifically, when the SC_SoC01_CTL pin level is low, the 3rd and 2nd pins of the transistor Q1 are not conducting, the 4th and 5th pins of the signal relay LS1 are in a non-conducting state, the 1st and 6th pins of the signal relay LS1 are connected, the 2nd and 8th pins are connected, and the 3rd and 10th pins are connected, that is, the write enable WE, output enable OE and chip select CS pins of the Flash storage chip are respectively connected to the write enable, output enable and chip select pins of the first SoC station.

[0069] Specifically, the host computer erases the contents of the Flash storage chip through the data line and address line of the first SoC station, and re-burns it. When the program burning of the Flash storage chip is completed, the storage enable pin of the first SoC station is disconnected, and the host computer displays a print message indicating that the program burning is completed.

[0070] Specifically, determine whether there is a SoC chip connected to other SoC stations, such as Figure 4 As shown, for ease of understanding, it is assumed that the SoC station selected is set as the fifth SoC station, and one of the GPIO detection pins is defined as SoC_DEC_05.

[0071] Specifically, when there is no corresponding SoC chip connected to this station, the SoC_DEC_05 pin is at a low level, and the voltage drop between the 3rd and 4th pins of the optocoupler device U2 does not reach the conduction threshold of the light-emitting diode, so the light-emitting diode is not turned on, and the pin connected to the microcontroller end is SC_SoC_DEC_05, which is at a high level. On the contrary, when there is a SoC chip connected to its station, the SoC_DEC_05 pin level is high, and the corresponding SC_SoC_DEC_05 pin is at a low level. In fact, after the circuit board card is powered on, the welding and installation operations of the station will no longer be performed. Here we only introduce the level change of this pin for easier understanding. Therefore, as long as the microcontroller detects that the SC_SoC_DEC_05 pin level is high, that is, when the SC_SoC_DEC_05 pin level is low, it can be determined that there is a corresponding SoC chip connected to this station.

[0072] Specifically, when the MCU detects that a SoC chip is connected to the SoC station, it sends it to the host computer through the serial port, and the host computer sends an instruction to the MCU, commanding the MCU to connect to the designated corresponding SoC station storage enable pin, and then burn the SoC station program, and burn the aging program in the Flash storage chip into the RAM (Random Access Memory) of the SoC on this station. When the program burning of this station is completed, the GPIO feedback signal of this station is sent to the MCU through the serial port bus. After receiving the feedback signal, the MCU disconnects the SoC storage enable pin of this station, and the host computer displays the print information that the burning of this station is completed.

[0073] Specifically, when all SoC stations on the circuit board are burned, the microcontroller sends information to the host computer through the serial port bus, cuts off the power supply of the Flash storage chip, and sends several square waves to the LED display circuit, indicating that the program of the entire board station has been burned.

[0074] Specifically, the relay controls the operation of the power switch of the Flash memory chip, such as Figure 6 As shown, a relay is used to control the power supply of the Flash memory chip. The power pin connected to the Flash memory chip is defined as Flash_CTL_PWR, the pin connected to the power supply is defined as Flash_PWR, and the control pin connected to the microcontroller is defined as SC_Flash _PWR_CTL. When the SC_Flash _PWR_CTL pin is at a high level, the third and second pins of the transistor Q2 are turned on, the magnet of the relay U3 is attracted, and the SC_Flash _PWR_CTL pin is disconnected from the Flash_CTL_PWR pin, that is, the power supply of the power Flash memory chip is cut off. Conversely, when the SC_Flash _PWR_CTL pin is at a low level, the SC_Flash _PWR_CTL pin is connected to the Flash_CTL_PWR pin, that is, the power supply of the power Flash memory chip is normal. Embodiment 2

[0075] This embodiment provides a program burning method, which is implemented based on the burning device. At the same time, the burning method is divided into an online burning method, an offline burning method, and an online and offline mixed burning method according to different networking states.

[0076] Specifically, Figure 7 As shown, this example shows the system online program burning process, the Flash storage chip in the Flash module is placed in its socket, the host computer program code is debugged, and a GPIO feedback prompt is added at the end of the aging program code.

[0077] The online burning method comprises the following steps:

[0078] Step S11: The Flash storage chip is placed in the socket of the aging board, and the host computer is connected to the JTAG terminal on any SoC station on the aging board through JTAG. For ease of understanding, it is assumed that the host computer is connected to the JTAG terminal on the first SoC station;

[0079] Step S12: the single-chip microcomputer detects that the JTAG pin 10 of the SoC station, that is, the JTAG detection pin level is low, then the single-chip microcomputer changes to slave mode, that is, device mode, and the SoC station is in master mode, that is, host mode;

[0080] Step S13: The host computer first erases the contents of the Flash storage chip, and re-burns the aging program code, and adds a GPIO feedback prompt after the burning is completed. When the burning of any station is completed, the SoC on the station will send a print message of the burning completion to the host computer, and the host computer will display a prompt that the program burning of the station is completed;

[0081] Step S14: the host computer sends a command to the MCU through the JTAG terminal, instructing the MCU to connect to the storage enable pin of the designated SoC station, and then burns the program to the designated SoC station. The SoC on the station will send a print message of the completion of burning to the host computer, and the host computer will display a prompt that the program burning of the station is completed. At the same time, the SoC station will send a burning completion message to the MCU through the serial port. After receiving the feedback information from the SoC station, the MCU disconnects the storage enable pin connection of the station;

[0082] When the aging program code of the designated SoC station is completely burned, the host computer disconnects the JTAG terminal connecting the SoC station and the aging board, and the JTAG detection signal pin of the SoC station is converted from a low level to a high level. The microcontroller detects that the high level of the JTAG detection signal pin of the SoC station lasts for more than 200ms, and determines that the JTAG terminal of the SoC station is not connected to the host computer, and cuts off the Flash power supply through the Flash power control pin.

[0083] Further as Figure 8 As shown, the offline burning method comprises the following steps:

[0084] Step S21: Burn the aging program through a Flash external professional burning tool, put it into the Flash socket of the aging board, and power it on;

[0085] Step S22: The single-chip microcomputer detects the level of the SoC station detection pin on the aging board, that is, a high level indicates that a SoC chip is placed in the station and has been successfully identified;

[0086] Step S23: the single-chip microcomputer detects that there is a station where the SoC chip is correctly placed on the aging board, sequentially controls the connection of the SoC storage enable pins, and burns the program to the SoC station;

[0087] Step S24: After each station is burned, a GPIO pin of the SoC station will send feedback information of burning completion to the microcontroller through the serial port;

[0088] Step S25: After receiving the information, the single-chip microcomputer disconnects the SoC storage enable pin connection of the SoC station and connects the next SoC station whose detection pin level is high;

[0089] Step S26: When all SoC station programs whose SoC station detection pin level is high on the aging board are burned, the single-chip microcomputer cuts off the Flash power supply through the Flash power control pin, and sends several square waves to the LED display circuit through the GPIO, indicating that the entire board station program has been burned;

[0090] Further as Fig. 9 As shown, the online and offline hybrid burning method comprises the following steps:

[0091] Step S31: The Flash storage chip is placed in the socket of the aging board, and the host computer is connected to the JTAG terminal on any SoC station on the aging board through JTAG;

[0092] Step S32: the single-chip microcomputer detects that the JTAG pin 10 of the SoC station, that is, the JTAG detection pin level is low, then the single-chip microcomputer changes to slave mode, that is, device mode, and the SoC station is in master mode, that is, host mode;

[0093] Step S33: The host computer first erases the contents of the Flash storage chip, and re-burns the aging program code, and adds a GPIO feedback prompt after the burning is completed. When the burning of any station is completed, the SoC on the station will send a print message of the burning completion to the host computer through JTAG, and the host computer will display a prompt that the program burning of the station is completed;

[0094] Step S34: the aging board is powered off, the connection between the host computer and JTAG is disconnected, and then the aging board is powered on again;

[0095] Step S35: The single-chip microcomputer detects the level of the SoC station detection pin on the aging board, that is, a high level indicates that a SoC chip is placed in the station and is successfully identified;

[0096] Step S36: the single-chip microcomputer detects the station with the SoC chip on the aging board, sequentially controls the connection of the SoC storage enable pins, and burns the program to the SoC station;

[0097] Step S37: After each station is burned, a GPIO pin of the station will send feedback information of burning completion to the microcontroller through the serial port;

[0098] Step S38: After receiving the information, the single-chip microcomputer disconnects the SoC storage enable pin connection of the station and connects the next SoC station whose detection pin level is high;

[0099] Step S39: When all SoC station programs whose SoC station detection pin level is high on the aging board are burned, the microcontroller cuts off the Flash power supply through the Flash power control pin and sends several square waves to the LED display circuit through GPIO, indicating that the entire board station program has been burned.

[0100] Specifically, the debugging tool of the host computer is connected to any SoC station on the circuit board. For ease of understanding, it is assumed that the debugging tool of the host computer is connected to the first SoC station, and the circuit of this station is normal. The JTAG circuit of the connected station is Figure 2 As shown in the figure, the 10th pin changes from high level to low level, but here it only demonstrates the level change of JTAG pin 10 before and after the debugging tool is connected. In fact, the circuit does not allow live operation. Therefore, as long as the MCU detects that the level of JTAG pin 10 of the station is low, it can be determined that the station has a debugging tool connected. If there are multiple JTAG terminals on the circuit board connected to the debugging tool, only the first connected SoC station JTAG is recognized as valid.

[0101] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A program burning device, characterized in that: It includes a control module, a Flash module, and a SoC module, wherein the control module, the Flash module, and the SoC module are connected in series in sequence; The control module includes a serial port bus, a JTAG signal detection circuit, a SoC workstation signal detection circuit, a SoC storage enable pin control circuit, a Flash power control circuit, a single-chip microcomputer and an LED display circuit; the serial port bus, the JTAG signal detection circuit, the SoC workstation signal detection circuit, the SoC storage enable pin control circuit, the Flash power control circuit and the LED display circuit are respectively connected to the single-chip microcomputer; the serial port bus, the JTAG signal detection circuit, the SoC workstation signal detection circuit and the SoC storage enable pin control circuit are respectively connected to the SoC module; the Flash power control circuit is connected to the Flash module; The Flash module includes a Flash storage chip for storing the aging program of the circuit board card; the serial port bus is a line for the host computer to communicate with the single-chip microcomputer through the SoC station, and a feedback channel for the GPIO of the SoC station program burning completion; the JTAG signal detection circuit is used for the single-chip microcomputer to detect the access of its external JTAG debugging interface through the SoC station; the SoC station signal detection circuit is used to detect whether the SoC station has a SoC chip; the SoC storage enable pin control circuit is used for chip selection control of the SoC station; the Flash power supply control circuit is used to connect the Flash working power supply and cut off its power supply after the program burning of all stations of the SoC station is completed; the LED display circuit is used to light up the operator briefly after the program burning of all stations of the circuit board card is completed.

2. A program burning device according to claim 1, characterized in that: The SoC module includes 2n SoC workstations; the matrix layout of the SoC module is n rows*2 columns, or 2 rows*n columns, wherein n is a positive natural number.

3. A program burning device according to claim 2, characterized in that: A JTAG debugging port is provided on each SoC workstation side, and the number of pins of the JTAG debugging port is 16 bits.

4. A program burning device according to claim 3, characterized in that: The 10th pin of the JTAG debugging port is a JTAG detection signal pin; the JTAG detection signal pin is a pull-up power supply.

5. A program burning device according to claim 2, characterized in that: Any GPIO pin in the SoC station is connected to the SoC station signal detection circuit, and the GPIO pin pull-down resistor is grounded.

6. A program burning device according to claim 1, characterized in that: The JTAG signal detection circuit and the SoC workstation signal detection circuit are both provided with photoelectric coupling devices.

7. A program burning device according to claim 1, characterized in that: The single-chip microcomputer comprises a bus controller, a master-slave controller and a GPIO controller; the bus controller is connected to a serial port bus; the master-slave controller is connected to a JTAG signal detection circuit; the GPIO controller is respectively connected to a SoC station signal detection circuit, a SoC storage enable pin control circuit, a Flash power supply control circuit and an LED display circuit; the bus controller functions to receive and send information from a SoC module; the master-slave controller is used to set the master-slave status of the single-chip microcomputer; and the GPIO controller is used to detect and control the status of the GPIO.

8. A program burning method, the burning method is implemented based on the burning device of any one of claims 1 to 7, and the burning method is divided into an online burning method, an offline burning method, and an online and offline mixed burning method according to different networking states, characterized in that: The online burning method comprises the following steps: Step S11: The Flash storage chip is placed in the socket of the aging board, and the host computer is connected to the JTAG terminal on any SoC station on the aging board through JTAG; Step S12: the single-chip microcomputer detects that the JTAG pin 10 of the SoC station, that is, the JTAG detection pin level is low, and the low level lasts for more than 200ms, then the single-chip microcomputer changes to slave mode, that is, device mode, and the SoC station is in master mode, that is, host mode; Step S13: The host computer first erases the contents of the Flash storage chip, and re-burns the aging program code, and adds a GPIO feedback prompt after the burning is completed. When the burning of any station is completed, the SoC on the station will send a print message of the burning completion to the host computer, and the host computer will display a prompt that the program burning of the station is completed; Step S14: the host computer sends a command to the MCU through the JTAG terminal, instructing the MCU to connect to the storage enable pin of the designated SoC station, and then burns the program to the designated SoC station. The SoC on the station will send a print message of the completion of burning to the host computer, and the host computer will display a prompt that the program burning of the station is completed. At the same time, the SoC station will send a burning completion message to the MCU through the serial port. After receiving the feedback information from the SoC station, the MCU disconnects the storage enable pin connection of the station; The offline burning method comprises the following steps: Step S21: Burn the aging program through a Flash external professional burning tool, put it into the Flash socket of the aging board, and power it on; Step S22: The single-chip microcomputer detects the level of the SoC station detection pin on the aging board, that is, a high level indicates that a SoC chip is placed in the station and has been successfully identified; Step S23: the single-chip microcomputer detects that there is a station where the SoC chip is correctly placed on the aging board, sequentially controls the connection of the SoC storage enable pins, and burns the program to the SoC station; Step S24: After each station is burned, a GPIO pin of the SoC station will send feedback information of burning completion to the microcontroller through the serial port; Step S25: After receiving the information, the single-chip microcomputer disconnects the SoC storage enable pin connection of the SoC station and connects the next SoC station whose detection pin level is high; Step S26: When all SoC station programs whose SoC station detection pin level is high on the aging board are burned, the single-chip microcomputer cuts off the Flash power supply through the Flash power control pin, and sends several square waves to the LED display circuit through the GPIO, indicating that the entire board station program has been burned; The online and offline hybrid burning method comprises the following steps: Step S31: The Flash storage chip is placed in the socket of the aging board, and the host computer is connected to the JTAG terminal on any SoC station on the aging board through JTAG; Step S32: the single-chip microcomputer detects that the JTAG pin 10 of the SoC station, that is, the JTAG detection pin level is low, then the single-chip microcomputer changes to slave mode, that is, device mode, and the SoC station is in master mode, that is, host mode; Step S33: The host computer first erases the contents of the Flash storage chip, and re-burns the aging program code, and adds a GPIO feedback prompt after the burning is completed. When the burning of any station is completed, the SoC on the station will send a print message of the burning completion to the host computer through JTAG, and the host computer will display a prompt that the program burning of the station is completed; Step S34: the aging board is powered off, the connection between the host computer and JTAG is disconnected, and then the aging board is powered on again; Step S35: The single-chip microcomputer detects the level of the SoC station detection pin on the aging board, that is, a high level indicates that a SoC chip is placed in the station and is successfully identified; Step S36: the single-chip microcomputer detects the station with the SoC chip on the aging board, sequentially controls the connection of the SoC storage enable pins, and burns the program to the SoC station; Step S37: After each station is burned, a GPIO pin of the station will send feedback information of burning completion to the microcontroller through the serial port; Step S38: After receiving the information, the single-chip microcomputer disconnects the SoC storage enable pin connection of the station and connects the next SoC station whose detection pin level is high; Step S39: When all SoC station programs whose SoC station detection pin level is high on the aging board are burned, the microcontroller cuts off the Flash power supply through the Flash power control pin and sends several square waves to the LED display circuit through GPIO, indicating that the entire board station program has been burned.

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