A master control device, a slave control device, and a quantum computing system

Abstract

The present disclosure relates to a master control device, a slave control device and a quantum computing system, the master control device comprising: a communication port configured to receive first timing data transmitted by a timing editing device; a first processing module configured to embed a master clock in the first timing data to obtain second timing data; and a first optical fiber port configured to transmit the second timing data to each slave control device; wherein the slave control device is connected to the master control device through an optical fiber link. The master control device, the slave control device and the quantum computing system provided by the present disclosure can transmit the second timing data to each slave control device through the optical fiber link, thereby not only solving the problem of large signal attenuation caused by long-distance transmission of coaxial cables, but also solving the problems of line complexity and high cost caused by the coaxial cables.

Description

Technical Field

[0001] This disclosure relates to the field of quantum computing, and more particularly to a master control device, a slave control device, and a quantum computing system. Background Technology

[0002] In systems such as quantum computing, quantum precision measurement, and radar, it is often necessary for each slave control device to simultaneously complete the corresponding operations instructed by the master control device. However, due to potential asynchrony between the internal local clocks of the slave control devices, or between the local clocks of the master and slave control devices, the slave control devices may be unable to complete the corresponding operation instructions simultaneously or in a more coordinated manner according to the master control device's commands, thereby reducing the practicality and reliability of the system. Therefore, enabling each slave control device to complete its corresponding task at the same time has become one of the urgent problems to be solved.

[0003] Based on the above problems, there is an urgent need in the existing technology for a solution that can synchronize the clocks of the master control device and each slave control device. Summary of the Invention

[0004] In view of this, the present disclosure proposes a master control device, a slave control device, and a quantum computing system.

[0005] According to one aspect of this disclosure, a master control device is provided in a quantum computing system. The quantum computing system includes a master control device and slave control devices. The master control device includes: a communication port for receiving first timing data sent by a timing editing device, the first timing data including first timing parameters for generating a slave clock, the slave clock being the clock of the slave control device; a first processing module for embedding the master clock into the first timing data to obtain second timing data, the master clock being the clock of the master control device; and a first optical fiber port for sending the second timing data to each slave control device; wherein the slave control devices are connected to the master control device via optical fiber links.

[0006] Furthermore, the optical fiber link is a single-mode optical fiber link.

[0007] Furthermore, the first timing parameters include at least one of the following: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameter, wherein the channel includes a communication channel between the master control device and the slave control device, or a communication channel between the timing editing device and the master control device.

[0008] Furthermore, the communication port is used to receive the first timing data after a preset delay based on the channel's delay parameter.

[0009] Furthermore, the first optical fiber port includes: a plurality of first optical fiber sub-ports, used to send the second timing data to each of the slave control devices.

[0010] Furthermore, the first processing module is configured to: embed the master clock into the first timing data, and convert the first timing data including the master clock into serial second timing data.

[0011] According to another aspect of this disclosure, a slave control device in a quantum computing system is also provided. The quantum computing system includes a master control device and a slave control device. The slave control device includes: a second optical fiber port for receiving second timing data sent by the master control device, the second timing data being generated by the master control device by embedding a master clock into first timing data sent by a timing editing device, wherein the first timing data includes first timing parameters of the slave clock; and a second processing module for generating a slave clock based on the second timing data, wherein the master clock is the clock of the master control device, the slave clock is the clock of the slave control device, and the slave control device is connected to the master control device via an optical fiber link.

[0012] Furthermore, the optical fiber link is a single-mode optical fiber link.

[0013] Furthermore, the first timing parameters include at least one of the following: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameter, wherein the channel includes a communication channel between the master control device and the slave control device, or a communication channel between the timing editing device and the master control device.

[0014] Furthermore, the second fiber optic port is used to receive the second timing data after a preset delay based on the channel's delay parameters.

[0015] Furthermore, the second processing module is used to: obtain a master clock based on the second timing data; and generate a slave clock based on the master clock and the first timing parameters.

[0016] According to another aspect of this disclosure, a quantum computing system is also provided, the quantum computing system comprising: a timing editing device for generating first timing data, the first timing data including first timing parameters for generating a slave clock, the slave clock being a clock of a slave control device; a master control device for embedding a master clock into the first timing data sent by the timing editing device to generate second timing data, and sending the second timing data to each slave control device through a first optical fiber port, wherein the master clock is the clock of the master control device; and at least one slave control device for receiving the second timing data sent by the master control device through a second optical fiber port, and generating a slave clock based on the second timing data, wherein the slave control device is connected to the master control device through an optical fiber link.

[0017] This disclosure provides a master control device, slave control devices, and a quantum computing system. By transmitting second-series data to each slave control device via fiber optic links, it not only solves the problem of significant signal attenuation over long distances caused by coaxial cables but also addresses the associated circuitry complexity and high costs. This leads to reduced costs and energy savings in quantum computing, quantum precision measurement, and radar systems. Furthermore, the master control device can simultaneously send a master clock to the slave control devices while transmitting the second-series data. This allows the slave control devices to acquire the second-series data using a master clock synchronized with the master control device, ensuring that each slave control device can more accurately obtain the timing parameters within the second-series data. This generates precise slave clocks to control the operation of each module within the slave control devices, improving operational accuracy and preventing jitter when the slave control devices acquire signals sent by the master control device.

[0018] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0020] Figure 1 This is a schematic diagram of the structure of a quantum computing system provided in an embodiment of this disclosure.

[0021] Figure 2 This is a schematic diagram illustrating the connection relationship between a master control device and multiple slave control devices, provided in an embodiment of this disclosure.

[0022] Figure 3 This is a schematic diagram of another main control device provided in an embodiment of the present disclosure.

[0023] Figure 4 This is a schematic diagram of the structure of a control device provided in an embodiment of the present disclosure.

[0024] Figure 5 This is a schematic diagram of another slave control device provided in an embodiment of this disclosure.

[0025] Figure 6 This is a schematic diagram of another quantum computing system provided in an embodiment of the present disclosure.

[0026] Figure 7 This is a schematic diagram of a timing pulse in a standard mode provided in an embodiment of this disclosure.

[0027] Figure 8 A schematic diagram of a timing pulse in an advanced mode provided in an embodiment of this disclosure. Detailed Implementation

[0028] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0029] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0030] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0031] Existing quantum computing, quantum precision measurement, and radar systems typically include a master control device and multiple slave control devices. In multi-qubit quantum computing systems, the manipulation of qubits usually requires multiple slave control devices to perform corresponding operations simultaneously. However, since both the master control device and each slave control device operate under their own local clock, there is a high probability that the clocks of the master control device and the slave control devices are asynchronous when the slave control devices receive data signals from the master control device. That is, the slave control devices obtain data sent by the master control device through a clock that is asynchronous with the master control device, resulting in a decrease in the operational accuracy of the slave control devices when processing the data signals sent by the master control device. In digital circuits, the slave control device processes external input trigger signals using its internal local clock. This means the slave control device typically uses this clock to directly acquire external trigger signals (equivalent to data signals sent by the master control device). Since the external trigger signal and the slave control device's local clock are generated from different clock sources (i.e., clock asynchrony is possible), when the slave control device acquires the trigger signal from the master control device based on its local clock, the trigger signal from the master control device will change over time within the slave control device's local clock cycle. This results in jitter within one clock cycle when the slave control device acquires the trigger signal based on its local clock.

[0032] In addition to the drawbacks mentioned above, since the master control device and each slave control device typically transmit data signals via coaxial cables, if there is a long distance between them, the data signal received by the slave control device will experience significant attenuation. For example, a digital array radar is an array of radar elements in space. In a digital array radar, the digital array needs to digitize the signal of each transceiver channel and transmit the signal to the backend for unified processing. Each digital array requires a master control device to control each array element (equivalent to a slave control device) according to a timing sequence to achieve beam transmission and reception. The master control device typically transmits pre-lead control signals to each array element via coaxial cables. While this method is simple, signal attenuation increases significantly when the distance between the master control device and each array element is large, potentially causing the array element to be unable to perform the corresponding operations based on the received signal. In this situation, although the signal attenuation can be reduced by adding a power amplifier and increasing the power of the main control device's output data signal, the addition of a power amplifier will increase the system's manufacturing cost and complicate the internal circuitry, increasing the complexity of wiring. Increasing the power of the main control device's output data signal will increase the system's energy consumption.

[0033] Based on the above-mentioned defects, see Figures 1-2 , Figure 4 as well as Figure 6 As shown, this disclosure provides a main control device 2. The main control device 2 includes a communication port 21, a first processing module 22, and a first optical fiber port 23.

[0034] Furthermore, communication port 21 is used to receive first timing data sent by timing editing device 1, the first timing data including first timing parameters for generating a slave clock. The slave clock is the clock of slave control device 3. For example, communication port 21 is a gigabit Ethernet port.

[0035] Furthermore, the first processing module 22 is used to embed a master clock into the first timing data to obtain second timing data. The master clock is the clock of the main control device. For example, the first processing module 22 embeds the master clock into the first timing data using clock embedding technology to generate second timing data containing the master clock.

[0036] For example, the first timing parameter includes at least one of the following: the number of timing pulses, the period length of the timing pulses, the pulse width of the timing pulses, and the channel delay parameter. The channel includes a communication channel between the master control device 2 and the slave control device 3 (see [reference]). Figure 6 The network channel in the middle), or the communication channel between timing editing device 1 and main control device 2 (see...). Figure 6 (Fiber optic links L1-L3 in the middle).

[0037] For example, in order for the slave control device 3 to generate a determined slave clock based on the second timing data, the first timing parameter may include at least the period length of the timing pulse and the pulse width of the timing pulse.

[0038] Optionally, when the aforementioned channel indicates a communication channel between the main control device 2 and the timing editing device 1, a channel delay parameter can be included in the first timing data. This channel delay parameter allows the main control device 2 to receive the first timing data after a preset time. Optionally, the trigger input / output port 25 on the main control device (e.g., Figure 3 (As shown in the diagram) is driven after a preset time, thereby controlling the time when the main control device 2 receives the first timing data through the communication port 21. The preset time can be set according to the actual application scenario.

[0039] For example, in a digital array radar, each array element (equivalent to the slave control device 3 mentioned above) needs to transmit a beam based on the data signal sent by the master control device 2 after 0.2 seconds. This can be achieved by setting a channel delay parameter so that the trigger input / output port 25 of the master control device 2 receives the first timing data sent by the timing editing device 1 through the control communication interface 21 0.2 seconds after a standard time. In this scenario, the standard time is the moment when the master control device 2 receives the first timing data when the channel delay parameter is 0.

[0040] Furthermore, the first fiber optic port 23 is used to send the second timing data to each slave control device.

[0041] For example, the second timing data is sent from the control device 3 to the corresponding slave control device 3 via the first fiber optic port 23. Since the slave control device 3 is connected to the master control device 2 via a fiber optic link (see...), Figure 6 If the fiber optic links L1-L3 are connected, then the first fiber optic port 23 sends the second timing data to the corresponding slave control device 3 by sending the second timing data to the corresponding fiber optic link. (See also...) Figure 1 As shown, the first optical fiber port 23 sends the second timing data to the slave control device X1 through optical fiber link L1, sends the second timing data to the slave control device X2 through optical fiber link L2, and sends the second timing data to the slave control device X3 through optical fiber link L3. Each slave control device can correspond to one optical fiber link.

[0042] Optionally, the fiber optic link is a single-mode fiber optic link. In fiber optic communication, single-mode fiber is a type of fiber that directly transmits optical signals in a lateral mode. Single-mode fiber offers high data transmission speeds and can achieve transmission distances exceeding 5 kilometers. Therefore, in long-distance transmission applications, using a single-mode fiber optic link to connect the master and slave control devices enhances anti-interference capabilities during signal transmission and broadens the transmission bandwidth, thereby enabling convenient deployment of multi-node, long-distance timing control systems. Optionally, dual-mode fiber can also be used in short-distance transmission scenarios.

[0043] Furthermore, the control device 3 can generate a slave clock based on the first timing parameters and the master clock.

[0044] For example, the slave control device 3 recovers the master clock of the master control device 2 based on the second timing data through the second processing module, and obtains the first timing parameters in the second timing data according to the master clock to obtain various parameters of the slave clock (such as the number of timing pulses, the period length of the timing pulses, and the pulse width of the timing pulses), and generates the slave clock. The slave control device can control the corresponding modules or components to work according to the prescribed timing sequence according to the slave clock.

[0045] For example, the timing editing device 1 sets the first timing parameters through control software related to quantum measurement and control (such as arbitrary waveform editing software, data acquisition software, etc.), and sends the first timing data containing the first timing parameters to the main control device 2 via network communication. Optionally, the main control device 2 uses its communication port 21 (e.g., Figure 3 (As shown in the diagram) Receives first timing data. For example, the aforementioned slave control device 3 is a synchronous control system used to generate a slave clock based on the first timing parameters sent by the master control device to control the controlled devices to operate, thereby achieving the purpose of the master control device simultaneously controlling multiple slave control devices 3 to operate. Each slave control device 3 can coordinate its operation according to a specific timing sequence based on the second timing data sent by the master control device 2.

[0046] The master control device provided in this disclosure sends second timing data to each slave control device via an optical fiber link. This not only solves the problem of significant signal attenuation during long-distance transmission caused by coaxial cables, but also addresses the issues of increased wiring complexity and cost. This, in turn, reduces the cost of systems such as quantum computing, quantum precision measurement, and radar, while conserving energy. Furthermore, the master control device can embed a master clock into the first timing data to generate second timing data. This allows the slave control devices to obtain the master control device's clock data (master clock) based on the second timing data and to collect the second timing data accordingly. This ensures that each slave control device can collect the second timing data using a clock synchronized with the master control device, more accurately obtaining the timing parameters within the second timing data. This generates precise clock signals to control the operation of each module within the slave control devices, improving operational accuracy and preventing jitter when the slave control devices collect the trigger signal.

[0047] See Figures 2-3 As shown, in some embodiments of this disclosure, the first optical fiber port 23 includes a plurality of first optical fiber sub-ports 231, which are used to send second timing data to each slave control device 3. Thus, parallel control of multiple slave control devices 3 can be achieved.

[0048] For example, Figure 6 The master control device 2 sends the second timing data to the slave control device X1 via the first fiber optic sub-port D1 and the fiber optic link L1, sends the second timing data to the slave control device X2 via the first fiber optic sub-port D2 and the fiber optic link L2, and sends the second timing data to the slave control device X3 via the first fiber optic sub-port D3 and the fiber optic link L3.

[0049] In some embodiments of this disclosure, the main control device 2 is able to set the channel parameters of each fiber optic link connected thereto, including channel calibration accuracy.

[0050] Furthermore, the main control device 2 has an automatic channel calibration function. Under normal circumstances, the main control device 2 can calibrate the channel status of multiple fiber optic links connected to it to a preset state. In this preset state, the test accuracy of each channel is better than preset data (e.g., 500ps). If a more precise calibration accuracy is required in the current application scenario (e.g., the test accuracy of each channel needs to be better than 100ps), the channel calibration accuracy can be improved by manually setting the channel calibration accuracy.

[0051] The main control device provided in this disclosure can not only automatically calibrate the differences between the connected channels to maintain the state of each channel in a state that meets the requirements for data transmission, but also further improve the performance of each channel and reduce the system calibration error by manually adjusting the channel calibration accuracy, so that the main control device can be applied to systems with high clock accuracy requirements.

[0052] See Figure 3 As shown, in some embodiments of this disclosure, the first processing module 22 includes: a standard clock generation module 211, a timestamp module 212, and a plurality of first high-speed serial interfaces 214.

[0053] Furthermore, the standard clock generation module 211 is used to generate a master clock based on a preset clock source.

[0054] For example, the preset clock source can be set according to the actual situation. Optionally, the preset clock source can be the internal clock source of the main control device 2, or a high-precision clock source such as a GPS signal connected to the main control device 2 through serial port 24, PPS input port 26, or reference clock input port 27.

[0055] Optionally, the standard clock generation module 211 can be an LMK04828 chip, which is an ultra-low phase noise clock chip that can provide the main control device 2 with a clock with good phase noise performance. Optionally, the standard clock generation module 211 generates the main clock according to the clock control command output by the clock control module 215.

[0056] Furthermore, the timestamp module 212 is used to add timestamp information to the first timing data. Its time source is the clock output by the standard clock generation module 211. That is, the time source of the timestamp module 212 can also come from the internal local clock of the main control device 2, or from a high-precision clock source such as the GPS signal connected to the serial port 24, PPS input port 26, or reference clock input port 27.

[0057] Furthermore, multiple first communication modules 213 are used to send the first timing data with timestamp information to the corresponding first high-speed serial interface 214. Optionally, the first communication module 213 is used to convert the first timing data with timestamp information into a form that can be transmitted between the master control device 2 and the slave control device 3.

[0058] Furthermore, multiple first high-speed serial interfaces 214 are used to receive data sent by the first communication module 213, and embed the master clock into the first timing data through clock embedding technology, so that the first timing data includes the master clock, and convert the first timing data with the embedded master clock into serial second timing data.

[0059] For example, multiple first high-speed serial interfaces 214 are respectively connected to a slave control device 3 through a first optical fiber sub-port 231. The first high-speed serial interface 214 is used to convert parallel data (first timing data) into serial data (second timing data) embedded with the master clock of the master control device 2, and send the converted serial data to the corresponding slave control device 3.

[0060] Furthermore, the first fiber optic port 23 is used to send the second timing data to each slave control device 3. Optionally, the first fiber optic port 23 is used to send the second timing data to the corresponding slave control device 3 via a single-mode fiber optic link. Since the second timing data includes the master clock, when a slave control device 3 receives the second timing data, it can recover the master clock based on the second timing data and collect the first timing parameters in the second timing data based on the master clock. This allows the slave control device 3 to collect the first timing parameters in the second timing data according to a clock synchronized with the master control device 2. Essentially, each slave control device 3 can collect the second timing data according to a clock synchronized with the master control device 2, thereby achieving time synchronization between each slave control device 3 and the master control device 2, and thus solving the jitter phenomenon caused by asynchronous clock signals within a clock cycle.

[0061] See Figure 1 as well as Figure 4 As shown, according to another aspect of this disclosure, a slave control device 3 in a quantum computing system is also provided, the slave control device including: a second optical fiber port 31 and a second processing module 32.

[0062] Furthermore, the second fiber optic port 31 is used to receive second timing data sent by the master control device 2. The second timing data is generated by the master control device 2 embedding the master clock into the first timing data sent by the timing editing device 1. The first timing data includes first timing parameters of the slave clock, and the second timing data includes the first timing parameters of the slave clock and the master clock.

[0063] For example, the second fiber optic port 31 receives corresponding second timing data according to the fiber optic link to which it is connected. See also Figure 6 As shown, the second fiber optic port 31 of the slave control device X1, which is connected to the master control device via fiber optic link L1, is used to receive the second timing data from fiber optic link L1. The second fiber optic port 31 of the slave control device X2, which is connected to the master control device via fiber optic link L2, is used to receive the second timing data from fiber optic link L2. The second fiber optic port 31 of the slave control device X3, which is connected to the master control device via fiber optic link L3, is used to receive the second timing data from fiber optic link L3.

[0064] For example, the master clock mentioned above is the clock of the master control device, and the slave control device is connected to the master control device through a fiber optic link.

[0065] For example, the first timing parameter includes at least one of the following: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameter. The channel includes a communication channel between the master control device and the slave control device, or a communication channel between the timing editing device and the master control device.

[0066] Optionally, when the aforementioned channel indicates a communication channel between the master control device 2 and the slave control device 3, the channel delay parameter can be included in the second timing data. This channel delay parameter allows the slave control device 3 to receive the timing data after a preset time delay. The preset time can be set according to the actual application scenario.

[0067] For example, in a digital array radar, each array element (equivalent to the slave control device mentioned above) needs to transmit a beam based on the data signal sent by the master control device 2 after 0.2 seconds. This can be achieved by setting a channel delay parameter, so that the slave control device 3 receives the second timing data sent by the master control device 2 0.2 seconds after a standard time. In this scenario, the standard time is the moment when the channel delay parameter is 0, at which the slave control device 3 receives the second timing data.

[0068] Furthermore, the second processing module 32 is used to obtain the master clock based on the second timing data, and to generate a slave clock based on the master clock and the first timing parameters. For example, the slave clock is the clock of the slave control device 3.

[0069] For example, the slave control device 3 recovers the master clock of the master control device 2 based on the second timing data through the second processing module 32, and obtains various parameters of the slave clock (such as the number of timing pulses, the period length of the timing pulses, and the pulse width of the timing pulses) by acquiring the first timing parameters from the second timing data based on the master clock, and generates the slave clock. The slave control device 3 can control the corresponding modules or components to work on time according to the slave clock.

[0070] For details of the above content, please refer to the corresponding sections above, and we will not repeat them here.

[0071] The slave control device provided in this disclosure connects to the master control device via a fiber optic link. This not only solves the problem of significant signal attenuation during long-distance transmission caused by coaxial cables, but also addresses the issues of increased wiring complexity and cost. This, in turn, enables cost reduction and energy conservation in systems such as quantum computing, quantum precision measurement, and radar. Furthermore, the slave control device provided in this disclosure can acquire second-sequence data based on the master clock, ensuring that each slave control device can acquire second-sequence data using a clock synchronized with the master control device. This allows for more accurate acquisition of timing parameters within the second-sequence data, generating precise slave clock control for each module within the slave control device, improving operational accuracy, and preventing jitter during trigger signal acquisition.

[0072] See Figures 4-5 As shown, in some embodiments, the second processing module 32 is used to: obtain the master clock based on the second timing data, and generate the slave clock based on the master clock and the first timing parameters.

[0073] Furthermore, the second processing module 32 includes: a data recovery module 321, a clock control module 322, and a clock chip 323.

[0074] Optionally, the data recovery module 321 is used to recover the master clock based on the second timing data.

[0075] For example, the data recovery module 321 includes a second high-speed serial interface 3211, a second communication module 3212, an ARM communication interface 3213, and a time information processing module 3214. The second high-speed serial interface 3211 receives second timing data input from the second optical fiber port 31 and sends it to the second communication module 3212. The second communication module 3212 parses the data signal output from the second high-speed serial interface 3211 according to the data transmission protocol and sends the parsed data signal to the time information processing module 3214 via the ARM communication interface 3213, so that the time information processing module 3214 can recover the master clock in the second timing signal.

[0076] Optionally, the clock information processing module 3214 is used to recover the master clock in the second timing signal through CDR (Clock and Data Recovery) technology. For ease of understanding, the following is a brief explanation of CDR technology.

[0077] CDR technology mainly includes two aspects: First, it provides clock signals to each circuit at the receiver end. This is equivalent to the main control device 2 embedding the master clock into the second timing data through clock embedding technology, and then sending the second timing data with the embedded master clock to each slave control device 3. Second, it makes decisions on the received signals to facilitate data signal recovery and subsequent processing. This is equivalent to the clock information processing module 3214 recovering the master clock in the second timing signal. During the process of the main control device 2 sending the second timing data to the slave control device 3, the waveform of the optical signal will be distorted to a certain extent after transmitting a certain distance in the optical fiber link. Since there is no clock signal transmitted along with the optical signal, the signal received by the receiving end (such as the slave control device 3) is a series of pulses of varying lengths. The main method for clock recovery is PLL (phase-locked loop). The PLL method recovers the clock signal based on the feedback principle. It compares the phase error between the output signal of the voltage-controlled oscillator (VCO) and a reference signal (such as the master clock in the second timing data received from control device 3), generating a corresponding phase error voltage to ensure the VCO frequency matches the signal rate. The VCO then outputs the recovered clock signal (such as the master clock signal). The PLL circuit includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). A commonly used phase detector is an edge-triggered type, which detects the phase by comparing the edges of two input signals (such as the master clock in the second timing data and the VCO output signal). Since the phase detector output voltage is an AC signal, it cannot directly control the VCO. Therefore, a loop filter is needed to filter the voltage signal. The loop filter primarily removes high-frequency components from the voltage signal to obtain the control voltage for the VCO, thereby changing the frequency of the VCO output signal. After obtaining the correct clock signal using a PLL, the received signal (such as second timing data) can be acquired (e.g., sampled) to recover the data signal.

[0078] Furthermore, the clock control module 322 is used to collect second timing data based on the master clock recovered by the clock information processing module 3214 to obtain the first timing parameters (i.e., the timing parameters set by the timing editing device 1 mentioned above).

[0079] Furthermore, the clock chip 323 is used to generate a slave clock based on the first timing parameters, that is, the clock chip 323 generates a corresponding slave clock based on the data in the timing parameters. The slave clock is used to instruct the corresponding device to perform the corresponding operation.

[0080] Optionally, the clock information processing module 3214 is also used to send the recovered master clock to the second communication module 3212. The second communication module 3212 outputs a 1pps signal according to the master clock. The 1pps signal and the slave clock generated by the clock chip 323 are simultaneously output to the corresponding device through the SMA interface. The device can calibrate its internal clock according to the 1pps signal.

[0081] The slave control device provided in this disclosure receives second timing data that includes the master clock. Therefore, upon receiving the second timing data, the slave control device can recover the master clock from the second timing data and acquire the second timing data based on the master clock within the second timing data, thus synchronizing the master clock with the slave clock. If each slave control device can acquire the second timing data based on the master clock, time synchronization between each slave control device and the master control device can be achieved, thereby resolving the jitter phenomenon caused by asynchronous clock signals within a clock cycle. Furthermore, the slave control device can recover the master clock from the second timing data using CDR technology, ensuring that even if the waveform of the second timing data experiences a certain degree of distortion during transmission through the fiber optic link, the slave control device will not be affected and can still obtain an accurate master clock, acquiring the second timing data based on the master clock.

[0082] In another aspect of this disclosure, a quantum computing system is also provided, which includes a timing editing device 1, a master control device 2, and at least one slave control device 3.

[0083] Furthermore, the timing editing device 1 is used to generate first timing data, which includes first timing parameters for generating a slave clock, wherein the slave clock is the clock of the slave control device 3.

[0084] Furthermore, the master control device 2 is used to embed a master clock into the first timing data sent by the timing editing device 1, generate second timing data, and send the second timing data to each slave control device 3 through the first optical fiber port 23, wherein the master clock is the clock of the master control device 2.

[0085] Furthermore, at least one slave control device 3 is used to receive second timing data sent by the master control device 2 through the second optical fiber port 31, and generate a slave clock according to the second timing data, wherein the slave control device 3 is connected to the master control device 2 through an optical fiber link.

[0086] The quantum computing system disclosed herein connects the master control device and each slave control device via fiber optic links. This not only solves the problem of significant signal attenuation during long-distance transmission caused by coaxial cables, but also addresses the issues of increased wiring complexity and cost. This, in turn, reduces the cost of quantum computing, quantum precision measurement, radar, and other systems, saving energy. Furthermore, the master control device in this quantum computing system can simultaneously send a master clock to the slave control devices while transmitting the second timing data. This allows the slave control devices to acquire the second timing data based on a master clock synchronized with the master control device. This ensures that each slave control device can more accurately obtain the timing parameters in the second timing data, generating a precise slave clock to control the operation of each module within the slave control device. This improves the operational accuracy of the slave control devices and avoids jitter when the slave control devices acquire the trigger signal.

[0087] See Figures 7-8 As shown, in some embodiments of this disclosure, the timing editing device described above includes a standard mode and an advanced mode. See also... Figure 7 As shown, the clock signal generated based on the timing parameters output in this standard mode has equal periods and pulse widths for each pulse, and the pulse period, pulse width, and channel delay parameters can be set according to the actual application scenario. (See also...) Figure 8 As shown, the clock signal generated based on the timing parameters output in advanced mode can be more flexibly generated according to the actual application scenario. That is, the generated clock signal may include at least one pulse whose period and / or pulse width are different from other pulses, or it may generate a clock signal in which the period and pulse width of each pulse are the same. The period, pulse width of each pulse and the channel delay parameters of the clock signal can be set according to the actual application scenario.

[0088] The quantum computing system disclosed herein includes a timing editing device in both a standard mode and an advanced mode. In standard mode, the timing editing device can quickly generate first timing parameters based on input data, saving time and improving the efficiency of the quantum computing system. In advanced mode, the timing editing device can set parameters such as the period and pulse width of each pulse to generate the first timing parameters, making the slave clock generated based on the first timing parameters more closely match the actual application scenario.

[0089] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A master control device in a quantum computing system, characterized in that, The quantum computing system includes a master control device and a slave control device, wherein the master control device includes: A communication port is used to receive first timing data sent by a timing editing device. The first timing data includes first timing parameters for generating a slave clock, wherein the slave clock is the clock of a slave control device. The first processing module is used to embed a master clock into the first timing data to obtain the second timing data, wherein the master clock is the clock of the main control device; A first fiber optic port is used to send the second timing data to each slave control device, so that each slave control device generates a slave clock according to the second timing data; wherein, generating a slave clock according to the second timing data includes: obtaining a master clock according to the second timing data; and generating a slave clock according to the master clock and the first timing parameters; The slave control device is connected to the master control device via an optical fiber link; The master clock is generated by the standard clock generation module in the first processing module based on a preset clock source. The first timing parameters include: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameters, wherein the channel includes a communication channel between the master control device and the slave control device. The channel delay parameter is used to indicate the preset time delay required for receiving the second timing data from the second fiber optic port in the control device.

2. The main control device according to claim 1, characterized in that, The optical fiber link is a single-mode optical fiber link.

3. The main control device according to claim 1, characterized in that, The communication port is used to receive the first timing data after a preset delay based on the channel's delay parameter.

4. The main control device according to claim 1, characterized in that, The first optical fiber port includes: a plurality of first optical fiber sub-ports, used to send the second timing data to each of the slave control devices.

5. The main control device according to claim 4, characterized in that, The first processing module is used for: The master clock is embedded in the first timing data, and the first timing data including the master clock is converted into serial second timing data.

6. A slave control device in a quantum computing system, characterized in that, The quantum computing system includes a master control device and a slave control device, wherein the slave control device includes: The second fiber optic port is used to receive second timing data sent by the main control device. The second timing data is generated by the main control device embedding a master clock into the first timing data sent by the timing editing device. The first timing data includes first timing parameters of the slave clock. The master clock is generated by the main control device according to a preset clock source. The second processing module is used to generate a slave clock based on the second timing data. Wherein, the master clock is the clock of the master control device, the slave clock is the clock of the slave control device, and the slave control device is connected to the master control device via an optical fiber link; The first timing parameters include: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameters, wherein the channel includes a communication channel between the master control device and the slave control device. The second fiber optic port is used to receive the second timing data after a preset delay based on the channel's delay parameters; The second processing module is used for: The master clock is obtained based on the second timing data; A slave clock is generated based on the master clock and the first timing parameters.

7. The control device according to claim 6, characterized in that, The optical fiber link is a single-mode optical fiber link.

8. A quantum computing system, characterized in that, The quantum computing system includes: A timing editing device is used to generate first timing data, the first timing data including first timing parameters for generating a slave clock, the slave clock being a clock of a slave control device; The main control device is used to embed a master clock into the first timing data sent by the timing editing device, generate second timing data, and send the second timing data to each slave control device through the first optical fiber port. The master clock is the clock of the main control device, and the master clock is generated by the main control device according to a preset clock source. At least one slave control device is configured to receive the second timing data sent by the master control device through a second optical fiber port, and generate a slave clock based on the second timing data, wherein generating the slave clock based on the second timing data includes: obtaining a master clock based on the second timing data; and generating a slave clock based on the master clock and the first timing parameters. The slave control device is connected to the master control device via an optical fiber link; The first timing parameters include: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameters, wherein the channel includes a communication channel between the master control device and the slave control device. The second fiber optic port is used to receive the second timing data after a preset delay based on the channel's delay parameters.

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