A test vector generation device and method

Abstract

The present application relates to a test vector generation device and method, belonging to the technical field of integrated circuit testing. Among them, a test vector generation device includes: a functional model module, a test pattern algorithm module, a test vector description module, a test vector calculation module, and a vector data output module. The functional model module is used to establish a test functional model according to the interface information obtained from the memory to be tested; the test pattern algorithm module is used to provide test pattern calculation logic; the test vector description module is used to provide vector data information of a storage address and provide pin definitions; the test vector calculation module is used to calculate test vector data of each storage address of the memory to be tested; the vector data output module is used to output test vector data. This device can conveniently and quickly generate test vector data applied to memory function testing, solves the technical problem of the long time in the test vector generation process, and improves the test efficiency of the memory.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technologies, and particularly to a test vector generation device and method. Background Art

[0002] Memory is an important category of integrated circuits and an important medium for realizing large-capacity data storage and transmission. It is mainly used to store data, instructions, programs and other information. With the continuous development of modern mobile storage technologies and the storage market, semiconductor memory has become the most widely used storage device at present, and memory testing has become increasingly important in the field of integrated circuit testing. Memory testing can be used on the one hand to determine whether the product quality is qualified, and on the other hand to obtain data through testing for improving the manufacturing process of the memory.

[0003] The complexity of memory chips and the diversity of storage cell types further determine the difficulty of testing. The particularity of the memory structure also determines that the testing of this type of chip cannot adopt direct physical detection, but needs to continuously read and write data to the storage cells and compare with the theoretical data state, so that the physical faults of the memory are transformed into a logically displayable form.

[0004] Like other digital circuits, memory testing includes DC parameter testing, AC parameter testing and functional testing. Among them, the most important test is the read / write logic function test to detect faults in storage cells, including functional faults caused by reasons such as bad metal connections, bad components, and chip logic errors. Functional testing is to detect by applying test vectors to the memory, and various memory faults and defects are detected through read / write operations. The test vectors represent the logic functions of the memory chips under test. For large-capacity memories, to ensure their fault coverage rate, the amount of data of the test vectors required for their functional testing is huge, and the time required for the vector generation process is relatively long, which directly affects the testing efficiency of the memory to a great extent. Summary of the Invention

[0005] To solve the technical problem of the relatively long time in the test vector generation process, this application provides a test vector generation device and method.

[0006] In a first aspect, this application provides a test vector generation device, including: a function model module, a test pattern algorithm module, a test vector description module, a test vector calculation module, and a vector data output module;

[0007] The function model module is used to obtain interface information from the memory to be tested and establish a test function model of the memory to be tested according to the interface information;

[0008] The test pattern algorithm module is used to provide the test pattern calculation logic of the memory to be tested;

[0009] The test vector description module is used to provide vector data information of a storage address of the memory to be tested, and provide pin definitions of the memory to be tested;

[0010] The test vector calculation module is used to extract specific pin signals of the memory to be tested according to the vector data information of the one storage address and the pin definitions, and calculate test vector data of each storage address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model, and the test pattern calculation logic;

[0011] The vector data output module is used to output test vector data of each storage address of the memory to be tested;

[0012] Furthermore, the interface information includes address information, data information, and control information;

[0013] The function model module is used to establish a test function model of the memory to be tested according to the address information, the data information, and the control information;

[0014] Furthermore, the function model module includes: an address register unit, an address decoding unit, a data register unit, a read data unit, a write data unit, a data storage array, and a control logic unit;

[0015] The address register unit is used to save the address information;

[0016] The address decoding unit is used to parse and map the address information;

[0017] The data register unit is used to register the data information;

[0018] The read data unit is used to complete the driving work of reading data of the memory to be tested;

[0019] The write data unit is used to complete the driving work of writing data of the memory to be tested;

[0020] The data storage array is used to store the data information, and complete data storage of the storage address corresponding to the address information through mapping of the address information;

[0021] The control logic unit is used to control the working logic of the memory to be tested according to the control information;

[0022] Furthermore, the test pattern algorithm module includes: a test pattern algorithm library, a pattern algorithm generator, a control unit, an address unit, and a data unit;

[0023] The test pattern algorithm library is used to store at least one test pattern algorithm;

[0024] The pattern algorithm generator is used to output a test pattern sequence under the action of the test pattern algorithm, and the test pattern sequence includes a control data sequence, an address data sequence, and a test data sequence;

[0025] The control unit is used to store the control data sequence;

[0026] The address unit is used to store the address data sequence;

[0027] The data unit is used to store the test data sequence;

[0028] Furthermore, the test pattern algorithm library includes at least one of an all-zeros and all-ones test pattern algorithm, a checkerboard test pattern algorithm, a marching test pattern algorithm, and a roaming test pattern algorithm;

[0029] The test pattern algorithm is used to test any storage address of the memory to be tested;

[0030] Furthermore, the test pattern algorithm library further includes an extension interface for the test pattern algorithm;

[0031] The extension interface is used to add and / or optimize and improve the test pattern algorithm in the test pattern algorithm library;

[0032] Furthermore, the specific pin signals include: control terminal pin signals, address terminal pin signals, and data terminal pin signals;

[0033] The order of calibration of the specific pin signals is the control terminal pin signal, the address terminal pin signal, and the data terminal pin signal in sequence;

[0034] Furthermore, the control terminal pin signals include an output enable pin signal, a read / write control pin signal, and a chip select pin signal;

[0035] The order of calibration of the control terminal pin signals is the output enable pin signal, the read / write control pin signal, and the chip select pin signal in sequence;

[0036] Furthermore, the device is used for static random access memory testing.

[0037] In a second aspect, the present application provides a test vector generation method, including:

[0038] Obtain interface information from the memory to be tested, and establish a test function model of the memory to be tested according to the interface information;

[0039] Obtain the test pattern calculation logic of the memory to be tested;

[0040] Obtain the vector data information of a storage address of the memory to be tested, and obtain the pin definition of the memory to be tested;

[0041] Extract the specific pin signals of the memory to be tested according to the vector data information of the storage address and the pin definition, and calculate the test vector data of each storage address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model, and the test pattern calculation logic;

[0042] Output the test vector data of each storage address of the memory to be tested.

[0043] In a third aspect, an electronic device is provided, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus;

[0044] The memory is used to store a computer program;

[0045] The processor is configured to implement the steps of the test vector generation method described in the embodiments of the second aspect when executing the program stored on the memory.

[0046] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the test vector generation method described in the embodiments of the second aspect are implemented.

[0047] The above technical solutions provided by the embodiments of the present application have the following advantages compared with the prior art:

[0048] The test vector generation device provided by the embodiments of the present application uses the function model module of the device to extract the interface information of the memory to be tested, uses the vector data information of a storage address provided by the test vector description module and the pin definition of the memory to be tested, combines the test pattern calculation logic provided by the test pattern algorithm module, and uses the test vector calculation module to calibrate the specific pin signals of the memory to be tested, and then calculates the test vector data of each storage address under the action of different test pattern algorithms, providing a convenient and fast test vector data source for completing the function test of the memory, thus greatly saving the time for the user to write test vectors, solving the technical problem of the long time in the test vector generation process, improving the test efficiency of the memory, and saving the test cost. Description of the Drawings

[0049] The drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments that conform to the present invention, and are used together with the specification to explain the principles of the present invention.

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0051] Figure 1 The structural schematic diagram of a test vector generation device provided by an embodiment of the present application;

[0052] Figure 2 The schematic diagram of a function model module provided by an embodiment of the present application;

[0053] Figure 3 The principle block diagram of a test pattern algorithm module provided by an embodiment of the present application;

[0054] Figure 4 The flow schematic diagram of a test vector generation method provided by an embodiment of the present application;

[0055] Figure 5 The flow schematic diagram of another test vector generation method provided by an embodiment of the present application;

[0056] Figure 6 The structural schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0058] The first embodiment of the present application provides a test vector generation device, as Figure 1 , including: a function model module 101, a test pattern algorithm module 102, a test vector description module 103, a test vector calculation module 104, and a vector data output module 105.

[0059] Among them, the function model module 101 is used to obtain interface information from the memory to be tested and establish a test function model of the memory to be tested according to the interface information; the test pattern algorithm module 102 is used to provide the test pattern calculation logic of the memory to be tested; the test vector description module 103 is used to provide the vector data information of a storage address of the memory to be tested, as well as provide the pin definition of the memory to be tested; the test vector calculation module 104 is used to extract the specific pin signals of the memory to be tested according to the vector data information and pin definition of a storage address, and calculate the test vector data of each storage address of the memory to be tested according to the specific pin signals, test function model and test pattern calculation logic of the memory to be tested; the vector data output module 105 is used to output the test vector data of each storage address of the memory to be tested. The storage address can be referred to as a storage address unit or a storage unit.

[0060] In this embodiment, the function model module 101, the test pattern algorithm module 102, and the test vector description module 103 are the basis of the test vector calculation module 104. The test pattern calculation logic is obtained according to the test pattern algorithm. The test vector description module 103 mainly provides all pin definitions of the memory, the Timing information used in the test process, and the main part of the test vector data, that is, the read / write row vector data of a storage address in a single test cycle, namely the vector write data and the expected response data row of a storage address, provides the signal calibration function of the memory chip pins for the test vector calculation module, completes the pin signal calibration function through the vector data read / write row of a storage address, and provides a pin signal interface for the import of the vector pattern algorithm provided by the test pattern algorithm module. The memory chip pin signals further include the control end pin signals, address end pin signals, and data end pin signals of the memory chip.

[0061] Based on the pin signals calibrated by the test vector description module 103, the test vector calculation module 104 combines the function model module 101 and the test pattern algorithm module 102 to calculate the test vector pattern sequence of the memory under test, that is, according to the test requirements, select a pattern algorithm from the memory test pattern algorithm library accordingly, and calculate the test input data and expected response data of all storage units of the memory chip pins in different address orders. Among them, the test input data is generally represented by 0 or 1, and the expected response data is generally represented by L or H or Z or X.

[0062] The vector data output module 105 forms a data file from the test vector pattern sequence generated by the test vector calculation module and outputs a complete test vector data file of the memory under test.

[0063] This test vector generation device extracts the interface information of the memory to be tested using the functional model module, uses the vector data information of a storage address provided by the test vector description module and the pin definitions of the memory to be tested, combines the test pattern algorithm module to provide test pattern calculation logic, uses the test vector calculation module to calibrate the specific pin signals of the memory to be tested, and then calculates the test vector data of each storage address under the action of different test pattern algorithms, providing a convenient and fast test vector data source for completing the functional test of the memory, thus greatly saving the time for users to write test vectors, solving the technical problem of the long time in the test vector generation process, improving the test efficiency of the memory, and saving test costs.

[0064] In one embodiment, the interface information includes address information, data information, and control information. The functional model module is used to establish a test functional model of the memory to be tested according to the address information, data information, and control information.

[0065] In this embodiment, when generating the memory test vector, generality and convenience are considered. By extracting the control information, address information, and data information using the functional model module and combining different test pattern algorithms, based on the read / write row vectors of the vector data of a single storage address, the memory test vector data under different test pattern algorithms can be quickly expanded and generated. The configuration of this memory test vector generation device is simple, which can quickly improve the efficiency of generating memory test vectors, provide a fast generation device for users to complete the writing of large-scale vector data of the memory, provide a test vector data file with high complexity and large data scale for completing the functional test of the memory, greatly improve the memory test efficiency, and save test costs.

[0066] Among them, the control information can further include enable control, read / write control, and chip select control, and the read and write operations of the memory circuit are realized through the cooperation of the enable signal, read / write control signal, and chip select signal.

[0067] In one embodiment, as Figure 2 , the functional model module 101 includes: an address register unit 201, an address decoding unit 202, a data register unit 203, a read data unit 204, a write data unit 205, a data storage array 206, and a control logic unit 207.

[0068] Among them, the address register unit 201 is used to store address information, the address decoding unit 202 is used to parse and map the address information, the data register unit 203 is used to store data information, the read data unit 204 is used to complete the driving work of reading data from the memory to be tested, the write data unit 205 is used to complete the driving work of writing data to the memory to be tested, the data storage array 206 is used to store data information, and through the mapping of the address information, the data storage of the storage address corresponding to the address information is completed, and the control logic unit 207 is used to control the working logic of the memory to be tested according to the control information.

[0069] In this embodiment, the data storage array 206 is the data storage core of the memory. When the memory is powered on, the stored data information will not be lost. The address decoding unit 202 decodes the address information in the address register to determine the address information of the unit to be accessed or read; the write data unit 205 and the read data unit 204 implement the write and read operations of the memory based on the read / write control logic of the control logic unit. Each read / write operation can only act on one storage address of the memory, and all data to be written to the memory and read from the memory are stored in the data register unit 203.

[0070] Specifically, the address register unit 201 is mainly used to store the address information of the memory; the address decoding unit 202 is used to complete the parsing and mapping of the memory address information; the data register unit 203 is used to complete the storage function of the memory data, where the memory data further includes input data, expected response data, and actual acquisition data; the read data unit 204 and the write data unit 205 respectively complete the driving work of reading and writing data from the memory; the data storage array 206 is mainly used for storing data information, and through the mapping of the address information, the data storage of the corresponding storage address is completed; the control logic unit 207 mainly implements the working logic control function of the memory chip, where the working logic control further includes the enable control, read / write control, and chip select logic control of the memory chip.

[0071] In one embodiment, as Figure 3 , the test pattern algorithm module 102 includes: a test pattern algorithm library 301, a pattern algorithm generator 302, a control unit 303, an address unit 304, and a data unit 305.

[0072] The test pattern algorithm library 301 is used to store at least one test pattern algorithm; the pattern algorithm generator 302 is used to output a test pattern sequence under the action of the test pattern algorithm, and the test pattern sequence includes a control data sequence, an address data sequence, and a test data sequence; the control unit 303 is used to store the control data sequence; the address unit 304 is used to store the address data sequence; the data unit 305 is used to store the test data sequence. Among them, the test data sequence includes an input data sequence and an expected response data sequence.

[0073] In this embodiment, the test pattern algorithm module is mainly used to provide a test pattern algorithm library for memory test vectors and generate test pattern sequences under different test pattern algorithms. Among them, the test pattern algorithm can effectively detect stuck-at faults, transition faults, address decoding faults, and state coupling faults existing in the memory.

[0074] The control unit 303 is mainly used to store the control data sequence of all storage addresses of the memory chip to be tested; the address unit 304 is mainly used to store the storage address data sequence of the memory unit to be tested; the data unit 305 is mainly used to generate the input data and the expected response data sequence corresponding to the storage address of the memory. The data sequences of the control unit, the address unit, and the data unit together form a test pattern sequence. Among them, the control data, the address data, and the input data sequence of the data module are the data written into the memory unit, generally represented by 0 / 1; the expected response data is the expected value of reading the memory data, generally represented by L / H / Z / X. By extracting the control terminal pin information, the address terminal pin information, and the data terminal pin information of the memory chip to be tested and combining them with the test input data and the expected response data generated by the test pattern algorithm, a series of test vector graphic sequences representing the memory logic function are output.

[0075] In one embodiment, such as Figure 3 , the test pattern algorithm library 301 includes at least one of an all-zeros all-ones test pattern algorithm, a checkerboard test pattern algorithm, a march test pattern algorithm, and a galloping test pattern algorithm.

[0076] The test pattern algorithm is used to test the full-function storage addresses of the memory to be tested. The full-function storage addresses are all storage address units. That is to say, the data of all storage address units of the memory to be tested are calculated according to the test pattern algorithm, and the test is carried out according to the test pattern algorithm.

[0077] The all-zeros all-ones test pattern algorithm is also called the MSCAN test pattern algorithm, the checkerboard test pattern algorithm is also called the CheckBoard test pattern algorithm, the march test pattern algorithm is also called the March test pattern algorithm, and the galloping test pattern algorithm is also called the GALPAT test pattern algorithm.

[0078] In this embodiment, the test pattern algorithm library includes MSCAN (all zeros and all ones, or all 0s and all 1s) test pattern algorithms, CheckBoard (checkerboard) test pattern algorithms, March (marching) test pattern algorithms, GALPAT (roaming) test pattern algorithms, etc. In use, any one of them can be selected, or multiple test pattern algorithms can be selected. The test pattern sequence output by the test pattern algorithm generator under the action of the pattern algorithm includes control data, address data, and test data, which are stored in the control unit, address unit, and data unit respectively.

[0079] According to the working processes of different test pattern algorithms, it is possible to generate different unit address sequences of all storage addresses in the memory and different test data, so as to be able to complete the data writing and reading tests of different sequences of all storage address units, effectively detect the faults of the memory, and complete the efficient and comprehensive functional test of the memory.

[0080] In one embodiment, the test pattern algorithm library further includes an extension interface for the test pattern algorithm. The extension interface is used to add and / or optimize the test pattern algorithms in the test pattern algorithm library.

[0081] In this embodiment, the function model module is used to extract interface information such as the control information, address information, and data information of the memory, and the test vector description module is used to establish the control pin signals, address pin signals, and data pin signals of the memory chip with vector read / write rows calibrated. Combining different test pattern algorithms provided by the test pattern algorithm module, the control data, address data, and read / write data under the action of different test pattern algorithms are calculated to form a series of test vector graphic sequences covering all test units of the memory, providing a test vector data source for completing the functional test of the memory. Thus, it greatly saves the time for users to write test vectors, improves the test efficiency of the memory, and saves the test cost. The test vector data under the action of the four test pattern algorithms can detect different fault states, and at the same time provide an extensible interface for the test pattern algorithm, leaving room for adding or improving the test pattern algorithm. The existing test pattern algorithms can be optimized or new test pattern algorithms can be added through the extension interface.

[0082] In one embodiment, the specific pin signals include: control terminal pin signals, address terminal pin signals, and data terminal pin signals, and the calibration order of the specific pin signals is successively the control terminal pin signals, address terminal pin signals, and data terminal pin signals.

[0083] In one embodiment, the control terminal pin signals include output enable pin signals, read / write control pin signals, and chip select pin signals, and the calibration order of the control terminal pin signals is successively the output enable pin signals, read / write control pin signals, and chip select pin signals.

[0084] In one embodiment, the present test vector generation device is used for static random access memory testing. Static random access memory, also known as Static Random-Access Memory (SRAM for short), is a type of random access memory. The so-called "static" means that as long as this memory remains powered on, the data stored inside can be constantly maintained.

[0085] The present test vector generation device is applicable to static random access memory chips and can randomly and at any time write or read the information of all storage addresses in the memory or the information of any at least one storage address.

[0086] Based on the same concept, a second embodiment of the present application provides a test vector generation method, as Figure 4 , including:

[0087] Step 401: Obtain interface information from the memory to be tested and establish a test function model of the memory to be tested according to the interface information.

[0088] Step 402: Obtain the test pattern calculation logic of the memory to be tested.

[0089] Step 403: Obtain the vector data information of a storage address of the memory to be tested and obtain the pin definition of the memory to be tested.

[0090] Step 404: Extract the specific pin signals of the memory to be tested according to the vector data information of a storage address and the pin definition, and calculate the test vector data of each storage address of the memory to be tested according to the specific pin signals, test function model and test pattern calculation logic of the memory to be tested.

[0091] Step 405: Output the test vector data of each storage address of the memory to be tested.

[0092] The present test vector generation method, by obtaining interface information, combining the test pattern calculation logic, calibrating all the pins of the memory to be tested according to the pin definition and the vector data information of a storage address, and expanding and generating the test vector data of each storage address under the test pattern calculation logic, and then outputting the test vector data, thus greatly saving the time for users to write test vectors, solving the technical problem of the long time in the test vector generation process, improving the test efficiency of the memory, and saving the test cost.

[0093] In one embodiment, a test vector generation method, as Figure 5 , including:

[0094] Step 501: Establish a memory test function model according to the memory chip manual.

[0095] Step 502, extract interface information from the memory test function model.

[0096] Step 503, establish a memory vector read / write example line according to the interface information, and complete the calibration of the test pin signals.

[0097] Step 504, select the corresponding test pattern algorithm from the test pattern algorithm library.

[0098] Step 505, based on the calibrated pin signals, vector read / write example lines, and combined with the test pattern algorithm, expand the test vector data lines of all memory addresses of the memory to generate a test vector data file.

[0099] Step 506, output the memory test vector data file.

[0100] In this embodiment, a memory function model is established according to the memory chip manual to be tested, interface information of the memory (the interface information includes control information, address information, data information, etc.) is extracted from the function model, a memory test vector read / write data example line is established according to the interface information, the calibration of the test pin signals is completed, the corresponding test pattern algorithm is selected from the test pattern algorithm library, and the test vector data read / write lines of all memory addresses of the memory are expanded based on the calibrated pin signals, test pattern algorithm, and test vector read / write data example lines to generate a test vector data file, and the memory test vector data file is output, thus greatly saving the time for the user to write test vectors, solving the technical problem of the long time in the test vector generation process, improving the test efficiency of the memory, and saving the test cost.

[0101] As Figure 6 shown, the third embodiment of the present application provides an electronic device, including a processor 111, a communication interface 112, a memory 113, and a communication bus 114. Among them, the processor 111, the communication interface 112, and the memory 113 complete mutual communication through the communication bus 114.

[0102] The memory 113 is used to store a computer program.

[0103] In one embodiment, when the processor 111 is used to execute the program stored in the memory 113, it implements the test vector generation method provided by any one of the foregoing method embodiments. Among them, a test vector generation method includes:

[0104] Obtain interface information from the memory to be tested, and establish a test function model of the memory to be tested according to the interface information;

[0105] Obtain the test pattern calculation logic of the memory to be tested;

[0106] Obtain the vector data information of a storage address of the memory to be tested, and obtain the pin definition of the memory to be tested;

[0107] Extract the specific pin signals of the memory to be tested according to the vector data information of the storage address and the pin definition, and calculate the test vector data of each storage address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model and the test pattern calculation logic;

[0108] Output the test vector data of each storage address of the memory to be tested.

[0109] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0110] The communication interface is used for communication between the above terminal and other devices.

[0111] The memory can include a Random Access Memory (RAM), or can also include a non-volatile memory, such as at least one disk memory. Optionally, the memory can also be at least one storage device located far from the aforementioned processor.

[0112] The above-mentioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0113] The fourth embodiment of this application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the test vector generation method provided in any of the foregoing method embodiments are implemented.

[0114] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state drive (SSD)).

[0115] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article, or device including the element.

[0116] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A test vector generation device, characterized in that, Including: A function model module, a test pattern algorithm module, a test vector description module, a test vector calculation module, and a vector data output module; The function model module is used to obtain interface information from the memory to be tested and establish a test function model of the memory to be tested according to the interface information; The test pattern algorithm module is used to provide the test pattern calculation logic of the memory to be tested; The test vector description module is used to provide vector data information of a storage address of the memory to be tested and provide the pin definition of the memory to be tested; The test vector calculation module is used to extract the specific pin signals of the memory to be tested according to the vector data information of the storage address and the pin definition, and calculate the test vector data of each storage address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model, and the test pattern calculation logic; The vector data output module is used to output the test vector data of each storage address of the memory to be tested; Wherein, the interface information includes address information, data information, and control information; The function model module is used to establish a test function model of the memory to be tested according to the address information, the data information, and the control information; Wherein, the function model module includes: an address register unit, an address decoding unit, a data register unit, a read data unit, a write data unit, a data storage array, and a control logic unit; The address register unit is used to save the address information; The address decoding unit is used to parse and map the address information; The data register unit is used to register the data information; The read data unit is used to complete the driving work of reading data from the memory to be tested; The write data unit is used to complete the driving work of writing data to the memory to be tested; The data storage array is used to store the data information and complete the data storage of the storage address corresponding to the address information through the mapping of the address information; The control logic unit is used to control the working logic of the memory to be tested according to the control information; Wherein, the test pattern algorithm module includes: a test pattern algorithm library, a pattern algorithm generator, a control unit, an address unit, and a data unit; The test pattern algorithm library is used to store at least one test pattern algorithm; The pattern algorithm generator is used to output a test pattern sequence under the action of the test pattern algorithm, and the test pattern sequence includes a control data sequence, an address data sequence, and a test data sequence; The control unit is used to store the control data sequence; The address unit is used to store the address data sequence; The data unit is used to store the test data sequence.

2. The device according to claim 1, characterized in that The test pattern algorithm library includes at least one of an all-zeros and all-ones test pattern algorithm, a checkerboard test pattern algorithm, a march test pattern algorithm, and a walk test pattern algorithm; The test pattern algorithm is used to test any storage address of the memory to be tested.

3. The device according to claim 2, characterized in that, The test pattern algorithm library also includes an extension interface for the test pattern algorithm; The expansion interface is used to add and / or optimize the test graphic algorithms in the test graphic algorithm library.

4. The device according to claim 1, wherein The specific pin signals include: control terminal pin signals, address terminal pin signals, and data terminal pin signals; The calibration order of the specific pin signals is successively the control terminal pin signals, the address terminal pin signals, and the data terminal pin signals.

5. The device according to claim 4, characterized in that, The control terminal pin signals include output enable pin signals, read / write control pin signals, and chip select pin signals; The calibration order of the control terminal pin signals is successively the output enable pin signals, the read / write control pin signals, and the chip select pin signals.

6. The device according to claim 1, characterized in that The device is used for static random access memory testing.

7. A test vector generation method, characterized in that, Applied to the test vector generation device according to any one of claims 1-6, comprising: Obtaining interface information from the memory to be tested, and establishing a test function model of the memory to be tested according to the interface information; Obtaining the test graphic calculation logic of the memory to be tested; Obtaining the vector data information of a storage address of the memory to be tested, and obtaining the pin definition of the memory to be tested; Extracting the specific pin signals of the memory to be tested according to the vector data information of the storage address and the pin definition, and calculating the test vector data of each storage address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model, and the test graphic calculation logic; Outputting the test vector data of each storage address of the memory to be tested.

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