Array substrate, display panel and display device

Abstract

This application provides an array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area located around the display area. At least a portion of the film layer in the display area has a first through-hole extending along the thickness direction of the array substrate. The array substrate includes a substrate and an active layer. The active layer is disposed on one side of the substrate and includes multiple semiconductor portions extending along a first direction. The display area includes a first sub-region and a second sub-region located on both sides of the first through-hole in the first direction. The maximum size of the first sub-region in the first direction is smaller than the maximum size of the second sub-region in the first direction. At least two semiconductor portions are located within the first sub-region and are interconnected. In this application embodiment, connecting at least two semiconductor portions located within the first sub-region improves the electrostatic discharge capability of the semiconductor portions located within the first sub-region and reduces the risk of thin-film transistor characteristic differences due to insufficient electrostatic discharge.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the development of modern display technology, users' requirements for display devices are gradually increasing. Existing display devices are mainly divided into liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs). During the manufacturing process of display devices, they are often susceptible to external influences, such as static electricity, which can affect the final display effect. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display device that can increase the electrostatic discharge capability of the semiconductor portion in the first sub-region.

[0004] In a first aspect, embodiments of this application provide an array substrate having a display area and a non-display area located around the display area. At least a portion of the film layer in the display area is formed with a first through-hole extending along the thickness direction of the array substrate. The array substrate includes a substrate and an active layer. The active layer is disposed on one side of the substrate and includes a plurality of semiconductor portions extending along a first direction.

[0005] The display area includes a first sub-region and a second sub-region located on both sides of the first through-hole in a first direction. The maximum size of the first sub-region in the first direction is smaller than the maximum size of the second sub-region in the first direction. At least two semiconductor units are located in the first sub-region and are interconnected.

[0006] In some embodiments, the active layer further includes a conductive portion for connecting at least two semiconductor portions located in the first sub-region, the conductive portion being disposed on at least one side of the semiconductor portion along a first direction.

[0007] In some embodiments, the conductive portion is disposed around at least a portion of the outer periphery of the first through hole.

[0008] In some embodiments, the conductive portion extends into the second sub-region and is spaced apart from the semiconductor portion within the second sub-region.

[0009] In some embodiments, at least a portion of the semiconductor portion located in the first sub-region extends into the non-display area, and the conductive portion is located in the non-display area.

[0010] In some embodiments, the conductive portion extends along the second direction, and multiple semiconductor portions are arranged side by side along the second direction.

[0011] In some embodiments, the average width of the semiconductor portion located in the first sub-region is greater than the average width of the semiconductor portion located in the second sub-region.

[0012] In some embodiments, the display area further includes a third sub-region located on at least one side of the first sub-region and the second sub-region in a second direction, wherein the average width of the semiconductor portion located in the second sub-region is greater than the average width of the semiconductor portion located in the third sub-region.

[0013] In some embodiments, the array substrate further includes a gate metal layer, which is located on the same layer as the active layer of the substrate. The gate metal layer includes a gate, and the semiconductor portion includes a channel region and a connection region. The orthogonal projection of the channel region onto the substrate lies within the orthogonal projection of the gate onto the substrate. The width of the channel region located in the first sub-region is the same as the width of the channel region located in the second sub-region, and the width of the connection region located in the first sub-region is greater than the width of the connection region located in the second sub-region.

[0014] In some embodiments, at least one semiconductor unit located in the first sub-region is connected to at least one semiconductor unit located in the second sub-region.

[0015] In some embodiments, the thickness of the semiconductor portion located in the first sub-region is greater than the thickness of the semiconductor portion located in the second sub-region.

[0016] Secondly, embodiments of this application provide a display panel including the array substrate of any of the foregoing embodiments.

[0017] Thirdly, embodiments of this application provide a display device including a display panel from any of the foregoing embodiments.

[0018] The present application provides an array substrate, a display panel, and a display device that connects at least two semiconductor sections located in a first sub-region into one unit, and integrates two or more semiconductor sections into one interconnected unit, thereby increasing the total length of a single semiconductor section located in the first sub-region, thereby improving the electrostatic discharge capability of the semiconductor sections located in the first sub-region, reducing the risk of thin-film transistor characteristic differences due to insufficient electrostatic discharge, and improving the display effect of the final formed display panel. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application;

[0021] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure at point AA;

[0022] Figure 3 yes Figure 1 A magnified structural diagram of region Q in the middle region;

[0023] Figure 4 yes Figure 1 A magnified structural diagram of region P in the middle;

[0024] Figure 5 This is another structural schematic diagram of an array substrate provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of another structure of an array substrate provided in an embodiment of this application;

[0026] Figure 7 yes Figure 1 Another enlarged structural diagram of the central region P;

[0027] Figure 8 This is a schematic diagram of another structure of an array substrate provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0029] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0030] Marker explanation:

[0031] 1. Substrate;

[0032] 2. Active layer; 21. Semiconductor section; 211. Channel region; 212. Connector region; 22. Conductive section;

[0033] 3. Gate metal layer; 31. Gate;

[0034] AA, Display area; AA1, First sub-area; AA2, Second sub-area; AA3, Third sub-area; NA, Non-display area; HL, First through hole;

[0035] ED1, first edge; ED2, second edge;

[0036] X, the first direction; Y, the second direction. Detailed Implementation

[0037] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0038] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0039] With the development of display panels, more and more photosensitive devices need to be integrated into the display panels. For example, light-transmitting holes are formed in the display panels, and photosensitive elements such as cameras are placed in the light-transmitting holes. The light-transmitting holes are usually set in the display area of ​​the display panel, and external light is transmitted to the photosensitive elements through the light-transmitting holes to realize the light-sensing function.

[0040] In the manufacturing process of display panels, multiple functional film layers need to be formed on the substrate, including metal layers, active layers, planarization layers, and so on. During the fabrication of the active layer, the multiple semiconductor sections must be fabricated to avoid light-transmitting holes. Therefore, the total length of the semiconductor sections near the light-transmitting holes differs from the length of semiconductor sections in other areas, resulting in varying electrostatic discharge capabilities among the different semiconductor sections. The semiconductor sections near the light-transmitting holes have weaker electrostatic discharge capabilities, leading to differences in the characteristics of thin-film transistors formed at different locations, ultimately affecting the display effect and yield rate of the display panel.

[0041] To resolve the above issues, please refer to [link / reference]. Figure 1 and Figure 2This application provides an array substrate having a display area AA and a non-display area NA located around the display area AA. At least a portion of the film layer in the display area AA is formed with a first through hole HL extending along the thickness direction of the array substrate. The array substrate includes a substrate 1 and an active layer 2. The active layer 2 is disposed on one side of the substrate 1 and includes a plurality of semiconductor portions 21 extending along a first direction X.

[0042] The display area AA includes a first sub-area AA1 and a second sub-area AA2 located on both sides of the first through hole HL in the first direction X. The maximum size of the first sub-area AA1 in the first direction X is smaller than the maximum size of the second sub-area AA2 in the first direction X. At least two semiconductor portions 21 are located in the first sub-area AA1 and are connected to each other.

[0043] It is understandable that the display area AA in the array substrate corresponds to the display area AA in the display panel, the non-display area NA in the array substrate corresponds to the non-display area NA in the display panel, and the first through hole HL formed in the array substrate is located in the display area AA of the array substrate and corresponds to the light-transmitting hole in the display panel. That is, the photosensitive element can be located at the position corresponding to the first through hole HL.

[0044] The active layer 2 is located on one side of the substrate 1 and is patterned. The active layer 2 includes multiple semiconductor portions 21 extending along a first direction X, which typically corresponds to the length direction of the array substrate. It should be noted that... Figure 1 The multiple traces extending along the first direction represent the extension direction of a single semiconductor section. However, the extension direction of a single semiconductor section 21 is usually complex and varied. For example, the specific routing of the semiconductor section 21 located in the first sub-region AA1 and the semiconductor section 21 located in the second sub-region AA2 can be referred to respectively. Figure 3 and Figure 4 The structure shown.

[0045] It should be noted that the extension along the first direction X mentioned in the embodiments of this application refers to the general extension direction of the single semiconductor section 21 as a whole. However, the specific direction of the single semiconductor section 21 at a local location may extend along the first direction X or along other directions. The embodiments of this application do not limit this.

[0046] Please see Figure 1 and Figure 4 The display area AA has a first edge ED1 and a second edge ED2 in the first direction X. The first through hole HL is usually set close to the first edge ED1 or the second edge ED2. In this embodiment, the first through hole HL is set close to the first edge ED1 as an example.

[0047] The first sub-region AA1 is located between the first via HL and the first edge ED1, and the second sub-region AA2 is located between the first via HL and the second edge ED2. Because the lengths of the first via HL and the first edge ED1 in the first direction X are too close, the extension length of the semiconductor portion 21 in the first sub-region AA1 in the first direction X is typically much smaller than the extension length of the semiconductor portion 21 in the second sub-region AA2 in the first direction X. This results in the electrostatic discharge capability of the semiconductor portion 21 in the first sub-region AA1 being much smaller than that of the semiconductor portion 21 in the second sub-region AA2.

[0048] In this embodiment, at least two semiconductor sections 21 located in the first sub-region AA1 are connected together, and two or more semiconductor sections 21 are integrated into one interconnected section, thereby increasing the total length of a single semiconductor section 21 located in the first sub-region AA1, thereby improving the electrostatic discharge capability of the semiconductor section 21 located in the first sub-region AA1, reducing the risk of thin-film transistor characteristic differences due to insufficient electrostatic discharge, and improving the display effect of the final display panel.

[0049] like Figure 1 and Figure 4 As shown, in some embodiments, the active layer 2 further includes a conductive portion 22 for connecting at least two semiconductor portions 21 located within the first sub-region AA1. The conductive portion 22 is disposed on at least one side of the semiconductor portion 21 along the first direction X.

[0050] The conductive portion 22 is used to connect different semiconductor portions 21 together, thereby increasing the total length of the semiconductor portions 21 located in the first sub-region AA1. The conductive portion 22 is disposed on one or both sides of the semiconductor portion 21 along the first direction X. In this embodiment, the conductive portion 22 is generally not used to form a thin-film transistor. Therefore, the conductive portion 22 is disposed at the edge of the semiconductor portion 21 in the first direction X, thereby minimizing the overlap between the conductive portion 22 and the gate 31 in the thickness direction of the array substrate. The material used to fabricate the conductive portion 22 can be the same as or different from the material used to fabricate the semiconductor portion 21. Optionally, the conductive portion 22 and the semiconductor portion 21 are supported by the same material, and they can be fabricated together in the same masking process.

[0051] In this embodiment, at least two semiconductor sections 21 within the first sub-region AA1 are interconnected through the conductive section 22, thereby increasing the total length of a single semiconductor section 21 within the first sub-region AA1, improving the electrostatic discharge capability of the semiconductor section 21 within the first sub-region AA1, and enhancing reliability.

[0052] Please see Figure 5 In some embodiments, the conductive portion 22 is disposed around at least a portion of the outer periphery of the first through hole HL.

[0053] The first through-hole HL can have various shapes, including but not limited to circular holes, square holes, or other irregularly shaped holes. In this embodiment, a circular hole is used as an example. Since the outer periphery of the first through-hole HL has an arc-shaped structure and a certain curvature, the length of the conductive part 22 can be increased within a certain range by surrounding the outer periphery of the first through-hole HL, thereby increasing the total length of the semiconductor part 21 connected to the conductive part 22 and increasing its electrostatic discharge capability.

[0054] In some embodiments, the conductive portion 22 extends into the second sub-region AA2 and is spaced apart from the semiconductor portion 21 within the second sub-region AA2.

[0055] like Figure 5 As shown in this embodiment, the conductive portion 22 is disposed around the first through-hole HL and extends into the second sub-region AA2. This design can further increase the length of the conductive portion 22, enabling the connected semiconductor portion 21 to have a stronger electrostatic discharge capability. Simultaneously, the conductive portion 22 is spaced apart from the semiconductor portion 21 in the second sub-region AA2 to prevent the conductive portion 22 from connecting with the semiconductor portion 21 in the second sub-region AA2. Optionally, the conductive portion 22 is disposed completely around the first through-hole HL.

[0056] Please see Figure 6 In some embodiments, at least a portion of the semiconductor portion 21 located in the first sub-region AA1 extends into the non-display region NA, and the conductive portion 22 is located in the non-display region NA.

[0057] The semiconductor portion 21 located in the first sub-region AA1 is connected as one unit through the conductive portion 22. In this embodiment, at least a portion of the semiconductor portion 21 located in the first sub-region AA1 is extended into the non-display area NA, and the conductive portion 22 is disposed in the non-display area NA. This avoids the arrangement of the conductive portion 22 affecting the arrangement of the semiconductor portion 21 located in the first sub-region AA1. Furthermore, disposing of the conductive portion 22 in the non-display area NA allows the conductive portion 22 to have more arrangement options to meet the needs of different actual situations.

[0058] In some embodiments, the conductive portion 22 extends along the second direction Y, and multiple semiconductor portions 21 are arranged side by side along the second direction Y.

[0059] In this embodiment, the multiple semiconductor sections 21 arranged side-by-side along the second direction Y refers to the multiple semiconductor sections 21 extending as a whole along the first direction X and arranged side-by-side along the second direction Y, where the first direction X intersects the second direction Y. It is understood that in this embodiment, the extension of the conductive section 22 along the second direction Y means that the general extension direction of a single conductive section 22 is the second direction Y, but the specific orientation of local locations of the conductive section 22 is not limited in this embodiment. Optionally, the first direction X is perpendicular to the second direction Y.

[0060] It should be noted that all semiconductor units 21 located in the first sub-region AA1 can be connected as one unit through only one conductive part 22, or the first sub-region AA1 can be divided into multiple parts, and the multiple parts can be arranged side by side along the second direction Y, wherein multiple semiconductor units 21 in each part are connected through one conductive part 22. This application does not limit this.

[0061] Please see Figure 1 and Figure 7 In some embodiments, the average width of the semiconductor portion 21 located in the first sub-region AA1 is greater than the average width of the semiconductor portion 21 located in the second sub-region AA2.

[0062] As can be seen from the foregoing, in order to improve the electrostatic discharge capability of the semiconductor section 21 in the first sub-region AA1 and the semiconductor section 21 in the second sub-region AA2, multiple semiconductor sections 21 in the first sub-region AA1 are connected together, thereby increasing the total length of the semiconductor section 21 in the first sub-region AA1.

[0063] Furthermore, with such Figure 4 In comparison, the embodiments of this application also moderately increase the width of the semiconductor portion 21 located in the first sub-region AA1, so that the average width of the semiconductor portion 21 located in the first sub-region AA1 is greater than the average width of the semiconductor portion 21 located in the second sub-region AA2, thereby improving the electrostatic discharge capability of the semiconductor portion 21 in the first sub-region AA1, making it closer to the electrostatic discharge capability of the semiconductor portion 21 in the second sub-region AA2, ensuring that the characteristics of the thin film transistors finally formed in the first sub-region AA1 and the second sub-region AA2 tend to be consistent, and guaranteeing the product yield.

[0064] Please see Figure 1 In some embodiments, the display area AA further includes a third sub-area AA3 located on at least one side of the first sub-area AA1 and the second sub-area AA2 in the second direction Y, wherein the average width of the semiconductor portion 21 located in the second sub-area AA2 is greater than the average width of the semiconductor portion 21 located in the third sub-area AA3.

[0065] The third sub-region AA3 is the area in the display area AA other than the first sub-region AA1 and the second sub-region AA2. Typically, the area of ​​the third sub-region AA3 is much larger than the sum of the areas of the first sub-region AA1 and the second sub-region AA2. The length of a single semiconductor part 21 located in the third sub-region AA3 is also usually much larger than that of a single semiconductor part 21 located in the first sub-region AA1, and slightly larger than that of a single semiconductor part 21 located in the second sub-region AA2.

[0066] Since the length of a single semiconductor portion 21 in the second sub-region AA2 is usually not much different from the length of a single semiconductor portion 21 in the third sub-region AA3, the embodiments of this application only need to slightly adjust the width of the semiconductor portion 21 in the second sub-region AA2 and the semiconductor portion 21 in the third sub-region AA3 to ensure that the electrostatic discharge capability of the semiconductor portion 21 in the two regions is basically the same, thereby ensuring the yield of the final product.

[0067] Please see Figure 1 , Figure 2 as well as Figure 7 In some embodiments, the array substrate further includes a gate metal layer 3, which is located on the same layer as the active layer 2 on the substrate 1. The gate metal layer 3 includes a gate 31, and the semiconductor portion 21 includes a channel region 211 and a connection region 212. The orthographic projection of the channel region 211 on the substrate 1 lies within the orthographic projection of the gate 31 on the substrate 1. The width of the channel region 211 located in the first sub-region AA1 is the same as the width of the channel region 211 located in the second sub-region AA2, and the width of the connection region 212 located in the first sub-region AA1 is greater than the width of the connection region 212 located in the second sub-region AA2.

[0068] Both the gate metal layer 3 and the active layer 2 are used to form a thin-film transistor. In addition, a source-drain layer may be included, which includes a source and a drain, respectively connected to the source region and drain region in the active layer. The gate metal layer 3 may be located between the active layer 2 and the substrate 1, or it may be located on the side of the active layer 2 away from the substrate 1. This application embodiment does not limit this.

[0069] The gate metal layer 3 includes a gate 31, which is disposed corresponding to the channel region 211 of the semiconductor section 21. The connection region 212 is used to connect different channel regions 211. Typically, thin-film transistors are disposed in both the first sub-region AA1 and the second sub-region AA2, and the performance of the thin-film transistors is related to the size of the gate 31 and the size of the channel region 211.

[0070] Therefore, in order to ensure that the performance of the thin-film transistor located in the first sub-region AA1 is the same as that of the thin-film transistor located in the second sub-region AA2, the width of the channel region 211 in the first sub-region AA1 is set to be the same as the width of the channel region 211 in the second sub-region AA2. At the same time, in order to reduce the difference in electrostatic discharge capability between the semiconductor portions 21 in the first sub-region AA1 and the second sub-region AA2, the width of the connection region 212 in the first sub-region AA1 is also set to be greater than the width of the connection region 212 in the second sub-region AA2, so that the average width of the semiconductor portions 21 in the first sub-region AA1 is greater than the average width of the semiconductor portions 21 in the second sub-region AA2.

[0071] Please see Figure 8 In some embodiments, at least one semiconductor unit 21 located in the first sub-region AA1 is connected to at least one semiconductor unit 21 located in the second sub-region AA2.

[0072] Typically, the semiconductor portion 21 located in the first sub-region AA1 and the semiconductor portion 21 located in the second sub-region AA2 are spaced apart, resulting in a significant difference in length and electrostatic discharge capability between them. In this embodiment, at least one semiconductor portion 21 located in the first sub-region AA1 is connected to at least one semiconductor portion 21 located in the second sub-region AA2, such that the length of at least a portion of the semiconductor portion 21 in the first sub-region AA1 is close to the length of the semiconductor portions 21 in the second sub-region AA2 and the third sub-region AA3. This gives at least a portion of the semiconductor portion 21 in the first sub-region AA1 a stronger electrostatic discharge capability, improving reliability.

[0073] In some embodiments, the semiconductor portion 21 located at the edge of the first sub-region AA1 along the second direction Y is connected to the semiconductor portion 21 located in the second sub-region AA2. The semiconductor portion 21 located at the edge of the first sub-region AA1 along the second direction Y is close to the edge of the first via HL in the second direction Y, so the semiconductor portion 21 located at the edge of the first sub-region AA1 can extend around the outer periphery of the first via HL and connect with the semiconductor portion 21 located in the second sub-region AA2.

[0074] In some embodiments, the thickness of the semiconductor portion 21 located in the first sub-region AA1 is greater than the thickness of the semiconductor portion 21 located in the second sub-region AA2.

[0075] This application embodiment improves the electrostatic discharge capability of the semiconductor portion 21 within the first sub-region AA1 by increasing the thickness of the semiconductor portion 21. Optionally, the semiconductor portion 21 within the first sub-region AA1 can be formed through two masking processes, while the semiconductor portion 21 within the second sub-region AA2 can be formed through only one masking process, so that the thickness of the semiconductor portion 21 within the first sub-region AA1 is greater than the thickness of the semiconductor portion 21 within the second sub-region AA2.

[0076] Secondly, please refer to Figure 9 This application provides a display panel including the array substrate of any of the foregoing embodiments. The display panel can be a liquid crystal display panel or an organic light-emitting display panel; this application is not limited to either. The figure shows a liquid crystal display panel, which also includes a color filter substrate and a liquid crystal layer located between the array substrate and the color filter substrate. The display panel provided in this application has the beneficial effects of the array substrate provided in this application. For details, please refer to the specific descriptions of the array substrate in the above embodiments; these descriptions will not be repeated here.

[0077] Thirdly, please refer to Figure 10 This application provides a display device, which includes the display panel of any of the foregoing embodiments. The illustrated embodiments only use a mobile phone as an example to illustrate the display device. It is understood that the display device provided in this embodiment can be other display devices with display functions, such as computers, televisions, and in-vehicle display devices, and this invention does not impose specific limitations on them.

[0078] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0079] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. An array substrate, characterized by, An array substrate includes a display region and a non-display region located at a periphery of the display region, at least part of a film layer located in the display region is formed with a first through hole penetrating in a thickness direction of the array substrate, the array substrate includes: a substrate; an active layer disposed on a side of the substrate, the active layer includes a plurality of semiconductor portions extending in a first direction; the display region includes a first sub-region and a second sub-region located on both sides of the first through hole in the first direction, a maximum dimension of the first sub-region in the first direction is less than a maximum dimension of the second sub-region in the first direction; wherein at least two of the semiconductor portions located in the first sub-region are connected as one, two or more of the semiconductor portions are integrated as one connected to each other, and the semiconductor portions are arranged side by side in a second direction intersecting the first direction.

2. The array substrate of claim 1, wherein, The active layer further includes a conductive portion for connecting at least two of the semiconductor portions located in the first sub-region, the conductive portion is arranged on at least one side of the semiconductor portion in the first direction.

3. The array substrate of claim 2, wherein, The conductive portion is arranged around at least part of an outer periphery of the first through hole.

4. The array substrate of claim 2, wherein, At least part of the conductive portion extends into the second sub-region and is arranged spaced apart from the semiconductor portion in the second sub-region.

5. The array substrate of claim 2, wherein, At least part of the semiconductor portion located in the first sub-region extends into the non-display region, and the conductive portion is located in the non-display region.

6. The array substrate of claim 2, wherein, The conductive portion extends in the second direction.

7. The array substrate of claim 2, wherein, An average width of the semiconductor portion located in the first sub-region is greater than an average width of the semiconductor portion located in the second sub-region.

8. The array substrate of claim 1, wherein, The display region further includes a third sub-region located on at least one side of the first sub-region and the second sub-region in the second direction, an average width of the semiconductor portion located in the second sub-region is greater than an average width of the semiconductor portion located in the third sub-region.

9. The array substrate of claim 7, wherein, Further including a gate metal layer located on the same side of the substrate as the active layer, the gate metal layer includes a gate electrode; The semiconductor portion includes a channel region and a connection region, a normal projection of the channel region on the substrate is located within a normal projection of the gate electrode on the substrate; wherein a width of the channel region located in the first sub-region is the same as a width of the channel region located in the second sub-region, and a width of the connection region located in the first sub-region is greater than a width of the connection region located in the second sub-region.

10. The array substrate of claim 1, wherein, At least one of the semiconductor portions located in the first sub-region is connected to at least one of the semiconductor portions located in the second sub-region.

11. The array substrate of claim 1, wherein, The semiconductor portion located at an edge of the first sub-region in the second direction is connected to the semiconductor portion located in the second sub-region, the first direction intersects the second direction.

12. The array substrate of claim 1, wherein, A thickness of the semiconductor portion located in the first sub-region is greater than a thickness of the semiconductor portion located in the second sub-region.

13. A display panel, characterized by An array substrate as claimed in any one of claims 1 to 12.

14. A display device comprising: A display panel as claimed in claim 13.

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