Operations in memory

Abstract

Apparatus and methods may be related to performing operations in a memory. These operations may be performed in the background while the memory device performs various operations. For example, a comparison operation may be performed by the memory device while the memory device reads data. The results of the comparison operation may be stored in a register of the memory device. The register may be accessible externally from the memory device.

Description

Technical Field

[0001] The present disclosure relates generally to memory, and more particularly, to apparatus and methods associated with performing operations in memory. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also utilized as a volatile and non-volatile data storage device for a wide range of electronic applications including, but not limited to, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players), movie players, and other electronic devices. Memory cells may be arranged in an array, where the array is used in a memory device.

[0004] Various computing systems include a number of processing resources coupled to a memory (e.g., a memory system) that is accessed in association with executing a set of instructions (e.g., a program, application, etc.). The processing resources can execute the instructions to perform a number of operations. For example, the processing resources can execute a database to store and search for data. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory device according to several embodiments of the present disclosure.

[0006] Figure 2 is a block diagram of an apparatus in the form of a memory device including registers according to several embodiments of the present disclosure.

[0007] Figure 3 FIG. 4 is a block diagram of a sensing circuit system according to several embodiments of the present disclosure.

[0008] Figure 4 An example flow chart illustrating a method for performing operations in memory according to several embodiments of the present disclosure.

[0009] Figure 5 An example machine of a computer system is illustrated within which a set of instructions, for causing the machine to perform the various methodologies discussed herein, may be executed. DETAILED DESCRIPTION

[0010] The present disclosure includes apparatus and methods related to performing operations in memory. In some instances, an operation can be performed in memory while the memory is performing a different operation, such as a refresh operation, a read operation, and / or a write operation, among other operations. Performing an operation while the memory is performing other operations may be referred to as performing a background operation in the memory.

[0011] Performing background operations in memory can be more efficient than performing the same operations in memory (e.g., not in the background) because performing background operations utilizes data latched in the sensing circuitry to perform the operations. For example, data read from the memory array can be latched in the sensing circuitry before the data is provided via a data line (e.g., DQ). While the data is latched in the sensing circuitry, the data can also be used to perform operations. Thus, data stored in the sensing circuitry can be used for a variety of purposes, which may include performing background operations in memory. The term "background operations" is not intended to limit the types of operations that can be performed, but rather describes the performance of any type of operation in conjunction with any other type of operation.

[0012] The results of performing background operations can be stored in registers of the memory device. The registers can be made available to report the results of the background operations. By storing the results of the background operations and making them accessible at different times, the results made available can differ from the responses to commands that provide the results via the DQs to perform the operations. For example, a read operation can provide accessed data in response to an inferred read operation, while a background operation can provide results independently of the inference of the background operation, provided that the results are stored in the memory device and can be retrieved from the memory device at any time.

[0013] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 103 according to several embodiments of the present disclosure. As used herein, for example, memory device 103, memory array 110, and / or host 102 may also be individually considered a "apparatus."

[0014] In this example, system 100 includes a host 102 coupled to a memory device 103 via an interface 104. Computing system 100 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or an Internet of Things (IoT)-enabled device, among various other types of systems. Host 102 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 103. System 100 may include separate integrated circuits, or both host 102 and memory device 103 may be on the same integrated circuit. For example, host 102 may be a system controller of a memory system including multiple memory devices 103, wherein system controller 102 provides access to the respective memory devices 103 by another processing resource, such as a central processing unit (CPU). Host 102 may also be an AI chip configured for AI processing.

[0015] exist Figure 1 , host 102 is responsible for executing an operating system (OS) and / or various applications that may be loaded thereon (e.g., from memory device 103 via control circuitry 105). The OS and / or various applications may be loaded from memory device 103 by providing access commands from host 102 to memory device 103 to access data comprising the OS and / or various applications. Host 102 may also access data utilized by the OS and / or various applications by providing access commands to memory device 103 to retrieve such data utilized in the execution of the OS and / or various applications.

[0016] For the sake of clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory array 110 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. Array 110 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although in Figure 1 A single array 110 is shown in FIG. 1 , but embodiments are not so limited. For example, memory device 103 may include several arrays 110 (eg, arrays of DRAM cells).

[0017] Memory device 103 includes address circuitry 106 to latch address signals provided via interface 104. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such a protocol may be custom or proprietary, or interface 104 may employ a standardized protocol such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or the like. The address signals are received and decoded by row decoder 108 and column decoder 112 to access memory array 110. Data can be read from memory array 110 by sensing voltage and / or current changes on sense lines using sense circuitry 111. Sense circuitry 111 may include, for example, sense amplifiers that can read and latch a page (e.g., a row) of data from memory array 110. I / O circuitry 107 may be used for bidirectional data communication with host 102 via interface 104. Read / write circuitry 113 is used to write data to or read data from memory array 110. As examples, circuitry 113 may include various drivers, latch circuitry, and the like.

[0018] Control circuitry 105 decodes signals provided by host 102. The signals may be commands provided by host 102. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory array 110 (including data read operations, data write operations, and data erase operations). In various embodiments, control circuitry 105 is responsible for executing instructions from host 102. Control circuitry 105 may include a state machine, a sequencer, and / or some other type of control circuitry, which may be implemented in hardware, firmware, software, or any combination of the three. In some examples, host 102 may be a controller external to memory device 103. For example, host 102 may be a memory controller coupled to a processing resource of a computing device. Data may be provided to and / or from memory array 110 via data lines 116.

[0019] The sensing circuitry 111 can be configured to perform operations. For example, the sensing circuitry 111 can be configured to compare bits from a first data value with bits from a second data value. Memory cells coupled to a plurality of sense lines and select lines can store bits, which can be referred to as a memory array row. The bits comprising a memory array row can be subdivided so that a memory array row can contain multiple data values. For example, a memory array row can contain multiple data values, where each of the data values ​​contains eight bits. Each of the data values ​​can also be referred to as a bit vector. Although the data values ​​are described as bit vectors containing eight bits, the data values ​​can contain more or fewer bits than those described herein.

[0020] The sensing circuitry 111 may be configured to perform background operations. For example, the sensing circuitry 111 may compare data values ​​while simultaneously refreshing the data values ​​stored in corresponding memory cells.

[0021] The sensing circuitry 111 may store the results of the operations performed by the sensing circuitry in registers. The registers may include, for example, multi-purpose registers (MPRs) and / or static RAM (SRAM). The registers may be accessed by the host 102 via, for example, a DDR interface of the interface 104. Although the examples described herein provide the registers as MPRs and / or SRAMs, the registers may include other types of memory including volatile and non-volatile memory.

[0022] Although the operations are shown as being performed by the sensing circuitry 111, the operations may also be performed digitally in an analog manner or in processing resources implemented "below" the array. Performing the operations in an analog manner may include activating multiple rows of the memory array 210 and determining whether the sensed voltage is substantially equal to a threshold value (e.g., Vdd / 2) or 0. If the sensed voltage deviates from the expected voltage, then the values ​​stored by the memory cells coupled to the row are substantially unequal. If the sensed voltage does not deviate from the expected voltage, then the values ​​stored by the memory cells are substantially equal.

[0023] The processing resources may be configured as a complementary metal oxide semiconductor (CMOS) below the memory array 110. The processing resources (e.g., the CMOS below the array) may include several logic blocks configured to, for example, perform various functions using data values ​​stored in the memory array 110. The processing resources may be further coupled to the sense amplifiers 111 and / or data lines such that the processing resources can provide data to the sense amplifiers 111 and / or data lines that couple the memory array 110 to the I / O circuitry 107. The processing resources (e.g., the CMOS below the array) may be described as residing in the memory array 110 in a different layer than that containing the sensing circuitry and / or array or memory cells. The processing resources may be configured to perform background operations to compare data values ​​while refreshing the data values ​​stored in the corresponding memory cells.

[0024] Figure 2 2 is a block diagram of an apparatus in the form of a memory device 203 including registers 222, according to several embodiments of the present disclosure. Memory device 203 includes a memory array 210, a row decoder 208 coupled to memory array 210, and a column decoder 212 also coupled to memory array 210. Memory device 203 also includes sense circuitry 211 coupled to memory array 210 and column decoder 212. Memory device 203 further includes registers 222, shown as SRAM 222. Memory device 203 also includes interfaces 204-1, 204-2, and 204-3.

[0025] Interface 204-1 may be a command interface. Interface 204-2 may be an address interface. Interface 204-3 may be a data interface. Interface 204-1 may receive background operation commands, for example, from a host. Data interface 204-3 may receive data corresponding to the background operation commands.

[0026] For example, if the background operation command received via command interface 204-1 is a command requesting a search for data stored in memory array 210, the data provided via data interface 204-3 may be the data being searched. The searched data may be provided to SRAM 222. The searched data may be stored in SRAM 222. The data may also be stored in sensing circuitry 211.

[0027] In some examples, commands received via command interface 204-1 may select between several preferences. For example, a background command may include a selection of whether the background command is to be performed during a write operation, a read operation, and / or a refresh operation.

[0028] Figure 2 The example depicts a background command being executed concurrently with a refresh operation. Performing a refresh operation may include reading a row of data from memory cells in memory array 210 and storing the row of data in sensing circuitry 211. The row of data may then be restored to the memory cells. Refreshing memory cells may prevent data loss and / or data corruption due to charge leakage, such as occurs during a DRAM refresh operation.

[0029] The refresh operation may include refreshing one or more rows of memory cells that have been interleaved with the read and write operations. For example, during a first duration, a first row of memory cells may be refreshed. During a second duration, a second row of memory cells may be read. During a third duration, a third row of memory cells may also be refreshed.

[0030] Performing background operations may include searching for data concurrently with refreshing, reading, and / or writing memory cells. Memory array 210 may be searched while data read from the memory array is stored in sensing circuitry 211 and / or while data is stored in memory array 210.

[0031] Performing background operations may include providing row addresses, column addresses, data, and / or results of comparison operations to SRAM 222. SRAM 222 may receive row addresses from row decoder 208. SRAM 222 may receive column addresses from column decoder 212. SRAM 222 may receive search data from data interface 204-5. As used herein, the term "search data" describes the data being searched. For example, the search data may provide the data being searched. SRAM 222 may receive the results of the search from sensing circuitry 211.

[0032] In some examples, sensing circuitry 211 may compare the search data with data read from memory array 210. The search data and the data read from memory array 210 may be stored in sensing circuitry 211.

[0033] In response to comparing the search data with the data read from the memory array 210, the sense circuitry 211 may provide a signal to the SRAM to latch the row address, column address, and / or search data. The sense circuitry 211 may also provide an indication of the column associated with a match between the search data and the data read from the memory cell to the column decoder 212. The column decoder 212 may encode or decode the column information provided by the sense circuitry 211 to generate a column address corresponding to the column associated with a match between the search data and the data read from the memory array 210. If a mismatch is identified, the sense circuitry 211 may refrain from providing the indication of the column to the column controller.

[0034] Row decoder 208 may provide an indication of a row address to SRAM 222. Row decoder 208 may provide an indication of a row address because reading data from memory array 210 to latch data in sensing circuitry 211 includes accessing the data using the corresponding row address. Row decoder 208 may provide the row address to SRAM 222 regardless of whether a match is identified by sensing circuitry 211. Providing the row address, column address, and / or search data to SRAM 222 does not include storing the row address, column address, and / or search data in SRAM 222. SRAM 222 may store data (e.g., row address, column address, and / or search data) provided in response to receiving a signal from sensing circuitry 211 indicating a match. If a mismatch is indicated, the row address, column address, and / or search data provided to SRAM 222 may not be stored by SRAM 222.

[0035] In some examples, the sensing circuitry 211 may identify multiple matches between the search data and the data read from the memory array 210. The sensing circuitry 211 may provide multiple signals indicating the identification of multiple matches to the SRAM 222. The SRAM 222 may latch / store multiple row addresses and / or column addresses along with the search data to record the matches. For example, the SRAM 222 may store multiple entries, each of which includes the search data, a column address, and / or a row address. The SRAM 222 may also store the search data, multiple column addresses, and multiple row addresses, wherein the multiple column addresses and multiple row addresses may include column / row address pairs that define a match. Although the examples described herein identify matches using row and column addresses, matches may also be identified using row or column addresses.

[0036] In some embodiments, background operations, including search operations, may be performed intermittently. For example, background operations performed concurrently with refresh operations may be limited to those performed during refresh operations and not during read, write, or erase operations. Under the condition that the memory array 210 is not refreshed in its entirety at any given time, but may be refreshed intermittently with read, write, and / or erase operations, background operations may also be performed intermittently with read, write, and / or erase operations.

[0037] Background operations performed concurrently with refresh operations may be exhaustive. That is, the entire memory array 210 may be searched while the entire memory array 210 is being refreshed over time. In some examples, the memory array 210 may be searched by refreshing portions of the memory array 210 storing data. However, background operations performed concurrently with read, write, and / or erase operations may not be exhaustive, as the entire memory array 210 may not be written, read, or erased within a certain amount of time. Therefore, the background operations received by the control circuitry may describe the time limits for performing the background operations.

[0038] Memory device 203 can process multiple background operations simultaneously. For example, memory device 203 can process a first background operation concurrently with a read operation and a second background operation concurrently with a refresh operation. Memory device 203 can receive and / or process multiple commands while performing a background operation. Given the nature of background operations and the uncertainty of when the results of background operations are available, SRAM 222 can be utilized to allow the host to access the results of background operations without synchronizing responses containing the results between memory device 203 and the host.

[0039] Figure 3FIG2 is a block diagram of sensing circuitry 311 according to several embodiments of the present disclosure. Sensing circuitry 311 is shown coupled to SRAM 322. Sensing circuitry 311 includes a row buffer 333 and comparators 332-1, 332-2, ..., 332-N. Sensing circuitry 311 also includes circuitry configured to store search data 331.

[0040] Row buffer 333 may include circuitry configured to latch / store rows of data read from the memory array. A data column may include a plurality of bits that may be subdivided to describe a plurality of data values ​​334-1, 334-2, ..., and 334-N, referred to as data values ​​334. Each of data values ​​334 may include five bits. In various embodiments, a data value may include more or less than five bits. For example, a data value may include 8, 16, or 32 bits, as well as other bit quantities that may comprise a data value.

[0041] In several examples, search data 331 may include the same amount of bits as each of the data values. In other examples, search data 331 may include fewer bits than data value 334 or more bits than data value 334. Although sensing circuitry is shown as storing a single instance of search data 331, in other examples, multiple instances of search data 331 may be stored in sensing circuitry 311. For example, the amount of instances of search data 331 may be equal to the amount of data value 334 and / or comparator 332.

[0042] Comparator 332 may include circuitry configured to compare bits of data value 334 with bits of search data 331. If a bit of any of data values ​​334 is equal to, greater than, or less than a bit of search data 331, comparator 332 may indicate a match between the corresponding data value and search data 331. Sense circuitry 311 may provide the indication of a match to SRAM 322.

[0043] In some examples, comparator 332 may also provide an indication of its match to a column decoder (eg, Figure 2 Column decoder 212 in FIG. The column decoder can be configured to convert an indication of a match into a column address. Converting from an indication into a column address can be described as encoding or decoding. Thus, comparator 332 can be configured to identify a match between data value 332 and search data 331 and identify the column of the memory array corresponding to the match. For example, if comparator 332-1 identifies a match, the indication from comparator 332-1 can identify that the memory cell coupled to the sense line corresponding to data value 334-1 stores data value 334-1. The indication of the sense line can be converted into an address corresponding to that sense line.

[0044] Figure 4Example flow chart illustrating a method for performing operations in memory according to several embodiments of the present disclosure.At 460, a first data value can be stored in sensing circuitry of a memory device including sensing circuitry, a memory array, and an SRAM cache.

[0045] At 462, the first data value can be compared to a plurality of data values ​​in the sensing circuitry. The data values ​​can be stored in memory cells coupled to a select line and a plurality of sense lines of the memory array. The comparison can be performed during a refresh operation. The first data value can be stored in the sensing circuitry.

[0046] At 464, the result of the comparison may be written to an SRAM cache of the memory device. The SRAM cache may be a register accessible by the host. At 466, data indicating the result may be read from the SRAM cache to another device external to the memory device. For example, access may be provided to the host.

[0047] Prior to comparing the first data value to the plurality of data values, the plurality of data values ​​may be latched in the sensing circuitry. The memory cell may be refreshed using the plurality of data values. The plurality of data values ​​may be latched prior to refreshing the memory cell.

[0048] The plurality of data values ​​may be rows of data from a memory array. For example, the plurality of data values ​​may be stored in memory cells coupled to the same select line. After comparing the first data value with the plurality of data values ​​during the same clock cycle used to perform a refresh operation of the memory cells storing the plurality of data values, the first data value may be compared with a different plurality of data values.

[0049] Different pluralities of data values ​​can be stored in different memory cells coupled to different select lines and a plurality of sense lines of the memory array such that the different pluralities of data values ​​constitute different data columns. The comparison can be performed during a refresh cycle different from a refresh cycle utilized to compare the first data value to the plurality of data values.

[0050] The data value comparison can be performed during the same clock cycle used to refresh the memory cell without interfering with the refreshing of the memory cell. The data value comparison and the refreshing of the memory cell can be separate operations performed simultaneously. For example, the comparison can be performed during the same clock cycle used to perform the refresh operation. The data value can be compared simultaneously with the refreshing of the memory cell because the data value can be compared in less time than the time required to refresh the memory cell. The data value can be compared during the refresh cycle because the data value is stored in the sensing circuitry as part of the refresh cycle and used for comparison.

[0051] The result of the comparison may include multiple matches between the first data value and the plurality of data values. For example, the first data value may match two or more data values ​​from a row of data values ​​(eg, a plurality of data values).

[0052] In various examples, a data value stored in a memory cell coupled to a select line and a plurality of sense lines of a memory array can be compared with a plurality of data values ​​stored in a different memory cell of the memory array coupled to a different select line and a plurality of sense lines. Both the data value and the plurality of data values ​​can be stored in the memory array. The comparison can be performed without latching both the data value and the plurality of data values ​​in the sensing circuitry. For example, the comparison can be performed using a single latch in a sense amplifier of the sensing circuitry rather than multiple latches in the sense amplifier of the sensing circuitry.

[0053] A column address corresponding to the result of the comparison operation can be provided to the SRAM. Signals can also be provided to the SRAM to latch the column address, row address, and data value of the memory array in response to the result of the comparison operation. The column address can be provided by a column decoder, and the row address can be provided by a row decoder. The row address and column address can be represented using bits that can contain data values ​​or just data. Bits can also be referred to as bit vectors.

[0054] Comparing the data value to the plurality of data values ​​may include simultaneously activating a select line and a different select line. Simultaneously activating the select line and the different select line may enable a memory cell storing the data value and a memory cell storing the plurality of data values ​​to be activated simultaneously. Simultaneously activating a memory cell coupled to the select line and a memory cell coupled to a different select line may enable a first charge stored in the memory cell coupled to the select line and a second charge stored in the memory cell coupled to the different select line to be combined in the sensing circuitry. Combining the charges may include combining the first charge stored in the first memory cell with the second charge stored in the second memory cell.

[0055] The sensing circuitry can latch multiple voltages provided via multiple sense lines in response to activating a select line and different select lines. If the latched voltage is VDD or 0, the sensing circuitry can identify a match. If the latched voltage is not VDD or 0, the sensing circuitry can identify a mismatch. For example, if the latched voltage is VDD / 2, the sensing circuitry can identify a mismatch. If a voltage representing 1 or 0 is expected, combining two different voltages, both representing 1 or 0, does not change the expected voltage identifying a matching bit. If a first voltage representing 1 and a second voltage representing 0 are combined, the voltage latched by the sensing circuitry would not be expected. The unexpected voltage can identify a bit as a mismatch. When the voltages are combined and moved to the sensing circuitry for comparison, the comparison bit and / or data value stored in the memory cell may not facilitate comparison as a background operation. The combined voltages can utilize the sensing circuitry in such a way that refresh operations, read operations, and / or write operations can be performed simultaneously.

[0056] Figure 5 An example machine illustrating a computer system 540 in which a set of instructions for causing the machine to perform the various methods discussed herein may be executed. In various embodiments, the computer system 540 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory device 103) or may be used to perform a controller (e.g., Figure 1 Controller 105) of the system (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0057] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" should also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0058] The example computer system 540 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0059] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements another instruction set, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 540 may further include a network interface device 508 for communicating via network 520.

[0060] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 540, with the main memory 504 and the processing device 502 also constituting machine-readable storage media.

[0061] In one embodiment, instructions 526 include implementing a Figure 1 The machine-readable storage medium 524 is a computer program product that stores instructions for the functionality of the host 102 and / or memory device 103. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0062] As used herein, "a number" of something may refer to one or more of such things. For example, a number of memory devices may refer to one or more memory devices. A "plurality" of something means two or more than two. Additionally, designators such as "N" as used herein, particularly with respect to reference numerals in the drawings, indicate that a number of the particular features so designated may be included with several embodiments of the present disclosure.

[0063] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number, and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. As will be appreciated, the elements shown in the various embodiments herein can be added, exchanged, and / or removed to provide several additional embodiments of the present disclosure. In addition, the proportions and relative scales of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.

[0064] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of the various embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and non-restrictive manner. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

[0065] In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This approach to disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure necessarily utilize more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus for performing an operation in a memory, comprising: Sensing circuit system (111, 211, 311); and control circuitry (105) coupled to the sensing circuitry and configured to: In the sensing circuitry and during a refresh cycle for refreshing memory cells, using a plurality of comparators (332-1, 332-2, ..., 332-N) to compare a first data value (331) with a plurality of data values ​​(334-1, 334-2, ..., 334-N) stored in the memory cells coupled to select lines and a plurality of sense lines of a memory array (110, 210), wherein the comparison of the first data value with the plurality of data values ​​is performed as a background operation and the number of the plurality of comparators is the same as the number of the plurality of data values, wherein the first data value is received from a host (102) and is not stored in the memory array; causing a result of the comparison of the first data value with the plurality of data values ​​to be written to a register; and The register is rendered accessible by the host.

2. The apparatus of claim 1 , wherein the control circuitry is further configured to cause the first data value to be compared during performance of a read operation or a write operation, wherein the comparing of the first data value and the performing of the read operation or the write operation are separate operations performed simultaneously.

3. The apparatus of claim 1, wherein the first data value is stored in the sensing circuitry.

4. The apparatus of claim 1 , wherein a plurality of instances of the first data value are stored in the sensing circuitry, and wherein the control circuitry is further configured to cause the plurality of instances of the first data value to be compared with the plurality of data values.

5. The apparatus of claim 1, wherein the register comprises static random access memory (SRAM) (222, 322).

6. The apparatus of any one of claims 1 to 5, wherein the result comprises a row address of a memory cell storing the first data value, a column address of the memory cell storing the first data value, and the first data value.

7. The apparatus of claim 6, further comprising a row decoder (108, 208) configured to provide the row address to the register.

8. The apparatus of claim 6, further comprising a column decoder (112, 212) configured to provide the column address to the register.

9. The apparatus of any one of claims 1-5, wherein the sensing circuitry is further configured to write the result to the register.

10. The apparatus of claim 6 , wherein the sensing circuitry is further configured to identify, from a plurality of sense lines of the memory array, a portion of the sense lines that corresponds to a second data value from the plurality of data values ​​stored in a portion of the memory cells, wherein the second data value matches the first data value.

11. The apparatus of claim 10, wherein the control circuitry is further configured to cause generation of the column address based on the identified portion of the sense line.

12. A method of performing an operation in a memory, comprising: storing a first data value (331) in sensing circuitry (111, 211, 311) of a memory device (103, 203), the memory device (103, 203) comprising the sensing circuitry, a memory array (110, 210), and a static random access (SRAM) cache register (222, 322); comparing, in the sensing circuitry during a refresh operation to refresh memory cells, a first data value with a plurality of data values ​​(334-1, 334-2, ..., 334-N) stored in the memory cells coupled to select lines and a plurality of sense lines of the memory array using a plurality of comparators (332-1, 332-2, ..., 332-N), wherein the comparison of the first data value with the plurality of data values ​​is performed as a background operation and the number of the plurality of comparators is the same as the number of the plurality of data values, wherein the first data value is received from a host (102) and is not stored in the memory array; writing data indicative of a result of the comparison of the first data value with the plurality of data values ​​into the SRAM cache register of the memory device; as well as The data indicative of the result from the SRAM cache register is read to another device external to the memory device.

13. The method of claim 12, further comprising: Prior to refreshing the memory cell with the latched plurality of data values, the plurality of data values ​​are latched in the sensing circuitry.

14. The method of claim 13 , further comprising comparing, in the sensing circuitry during a refresh cycle different from a refresh cycle used to compare the first data value to the plurality of data values, the first data value to a different plurality of data values ​​(334-1, 334-2, ..., 334-N) stored in different memory cells coupled to different select lines of the memory array and the plurality of sense lines.

15. The method of any one of claims 12 to 14, wherein the comparing is performed during a same clock cycle as the refresh operation.

16. The method of any one of claims 12 to 14, wherein the result comprises a plurality of matches between the first data value and the plurality of data values.

17. An apparatus for performing an operation in a memory, comprising: a memory array (110, 210) configured to store a particular data value (331) and a plurality of data values ​​(334-1, 334-2, ..., 334-N); and Sensing circuitry (111, 211, 311) coupled to the memory array and configured to: During a refresh of memory cells of the memory array, comparing the particular data value stored in the memory cell coupled to a select line and a plurality of sense lines of the memory array with the plurality of data values ​​stored in different memory cells of the memory array coupled to different select lines and the plurality of sense lines using a plurality of comparators (332-1, 332-2, ..., 332-N), wherein the number of the plurality of comparators is the same as the number of the plurality of data values; providing a column address corresponding to a result of a comparison operation including a match between the particular data value and the plurality of data values ​​to a static random access memory (SRAM) (222, 322); Signals are provided to the SRAM to store first data including the column address, second data including a row address of a memory cell storing the specific data value, and the specific data value in response to the result of the comparison operation of the specific data value with the plurality of data values.

18. The apparatus of claim 17, wherein the sensing circuitry is further configured to simultaneously activate the select line and the different select line to compare the particular data value with the plurality of data values.

19. The apparatus of claim 18, wherein the sense circuitry is further configured to latch a plurality of charges provided via the plurality of sense lines in response to activating the select line and the different select line.

20. The apparatus of claim 19, wherein the sensing circuitry is further configured to identify the match in response to comparing the particular data value with the plurality of data values ​​when a sensed voltage corresponding to the plurality of charges is VDD or 0, and further configured to identify a mismatch when the sensed voltage is VDD / 2.

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