Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate, a trench gate portion provided in one main surface of the semiconductor substrate, a surface electrode covering the one main surface of the semiconductor substrate, and an interlayer insulating film insulating the trench gate portion from the surface electrode, the semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type provided above the drift region, a barrier region of the first conductivity type provided below at least a portion of the body region, and a pillar region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and being in Schottky contact with the surface electrode, the surface electrode being a silicon-containing alloy, and an angle formed by a top surface of the interlayer insulating film and a side surface of the interlayer insulating film being an acute angle.

Description

TECHNICAL FIELD

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Development of a kind of semiconductor device called a reverse conducting IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) is being made. The semiconductor substrate of such a semiconductor device has an IGBT range provided with an IGBT configuration and a diode range provided with a diode configuration. The diode configuration is connected in anti-parallel with respect to the IGBT configuration, and is able to act as a freewheeling diode.

[0003] Japanese Patent Application Publication No. 2018-125443 discloses a technology of forming an n-type barrier region below a p-type body region, with respect to such a semiconductor device. The barrier region is electrically connected with an emitter electrode via a pillar region extending from the surface of the semiconductor substrate. The pillar region is configured to be in Schottky contact with a surface electrode to suppress a leak current. Since the barrier region is electrically connected with the emitter electrode via the pillar region, the potential of the barrier region is maintained at a potential close to that of the emitter electrode. Thereby, the voltage of a forward action to a pn junction constituted by the body region and the barrier region is suppressed to be low, and the amount of holes injected from the body region to the drift region is reduced, and the reverse recovery characteristics are improved. SUMMARY

[0004] PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] As a material of the emitter electrode of such a semiconductor device, in order to achieve good electrical characteristics, an alloy containing silicon (for example, aluminum silicon (AlSi)) is used. Therefore, as also pointed out in Japanese Patent Application Publication No. 2018-125443, a case where silicon contained in the emitter electrode is precipitated to the surface of the semiconductor substrate to form a silicone nodule becomes a problem. In particular, if such a silicone nodule is precipitated to the formation position of the pillar region, the barrier height between the pillar region and the surface electrode varies, and a problem of an increase in a leak current occurs.

[0006] The present specification provides a technology of controlling the precipitation position of a silicone nodule, and suppressing precipitation of a silicone nodule at the formation position of a pillar region.

[0007] MEANS FOR SOLVING THE PROBLEMS

[0008] The semiconductor device disclosed in this specification can include a semiconductor substrate, a trench gate portion provided in one main surface of the semiconductor substrate, a surface electrode covering the one main surface of the semiconductor substrate, and an interlayer insulating film insulating the trench gate portion and the surface electrode. The semiconductor substrate can include a drift region of a first conductivity type, a body region of a second conductivity type provided above the drift region, a barrier region of the first conductivity type provided below at least a portion of the body region, and a pillar region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and in Schottky contact with the surface electrode. The surface electrode is a silicon-containing alloy. An angle formed by a top surface and a side surface of the interlayer insulating film is an acute angle.

[0009] According to the structure of the semiconductor device, silicon balls are selectively precipitated at positions in the one main surface of the semiconductor substrate corresponding to end portions below the side surface of the interlayer insulating film. Thus, the precipitation of silicon balls at the formation position of the pillar region is suppressed.

[0010] The manufacturing method of the semiconductor device disclosed in this specification can be applied to a manufacturing method of a semiconductor device including a semiconductor substrate, a trench gate portion provided in one main surface of the semiconductor substrate, a surface electrode covering the one main surface of the semiconductor substrate, and an interlayer insulating film insulating the trench gate portion and the surface electrode, the semiconductor substrate including a drift region of a first conductivity type, a body region of a second conductivity type provided above the drift region, a barrier region of the first conductivity type provided below at least a portion of the body region, and a pillar region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and in Schottky contact with the surface electrode, the surface electrode being a silicon-containing alloy. The manufacturing method can include a step of forming the interlayer insulating film on the one main surface of the semiconductor substrate on which the trench gate portion is formed, a step of patterning a mask on the interlayer insulating film at a position corresponding to the trench gate portion, and a step of etching a portion of the interlayer insulating film using an isotropic etching technique so that an angle formed by a top surface and a side surface of the interlayer insulating film is an acute angle.

[0011] According to the manufacturing method of the semiconductor device, silicon balls are selectively precipitated at positions in the one main surface of the semiconductor substrate corresponding to end portions below the side surface of the interlayer insulating film. Thus, the precipitation of silicon balls at the formation position of the pillar region is suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1A plan view schematically shows a semiconductor device according to this embodiment.

[0013] Figure 2 A cross-sectional view schematically showing the boundary between the IGBT region and the diode region divided in the element region of the semiconductor device of this embodiment is similar to the Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0014] Figure 3 An enlarged cross-sectional view schematically showing a main portion of an interlayer insulating film of the semiconductor device according to the present embodiment.

[0015] Figure 4 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0016] Figure 5 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0017] Figure 6 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0018] Figure 7 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0019] Figure 8 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0020] Figure 9 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0021] Figure 10 A cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device of this embodiment is similar to Figure 1 The cross-sectional view of the main parts corresponds to the position of the II-II line.

[0022] Figure 11A main part cross-sectional view schematically showing a manufacturing process of the semiconductor device of the present embodiment is a main part cross-sectional view of a position corresponding to the II-II line of FIG. Figure 1

[0023] Figure 12 A main part cross-sectional view schematically showing a manufacturing process of the semiconductor device of the present embodiment is a main part cross-sectional view of a position corresponding to the II-II line of FIG. Figure 1

[0024] Figure 13 A main part cross-sectional view schematically showing a manufacturing process of the semiconductor device of the present embodiment is a main part cross-sectional view of a position corresponding to the II-II line of FIG. Figure 1

[0025] Figure 14 A main part cross-sectional view schematically showing a manufacturing process of the semiconductor device of the present embodiment is a main part cross-sectional view of a position corresponding to the II-II line of FIG. Figure 1 DETAILED DESCRIPTION

[0026] Hereinafter, the semiconductor device of the present embodiment will be described with reference to the drawings. In each drawing, as for a general constituent element, only one constituent element is added with a reference sign for the sake of making the drawing clear, and other constituent elements are omitted from the addition of the reference sign.

[0027] Figure 1 A plan view schematically showing the semiconductor device 1 of the present embodiment. The semiconductor device 1 is a kind of semiconductor device called reverse conducting IGBT, and is manufactured using a semiconductor substrate 10. The semiconductor substrate 10 has an element region 10A and a peripheral region 10B located around the element region 10A. The element region 10A of the semiconductor substrate 10 is divided into an IGBT range 102 provided with an IGBT configuration and a diode range 104 provided with a diode configuration. As an example, the IGBT range 102 and the diode range 104 are alternately repeatedly arranged in the element region 10A in the y direction when viewed from a direction orthogonal to the surface of the semiconductor substrate 10 (hereinafter, referred to as "plan view"). In the semiconductor substrate 10 corresponding to the peripheral region 10B, a peripheral withstand voltage configuration such as a guard ring is formed. Further, on the semiconductor substrate 10 corresponding to the peripheral region 10B, a plurality of small signal pads 28 are provided. As a kind of the small signal pads 28, for example, a gate pad for inputting a gate signal, a temperature sensing pad for outputting a temperature sensing signal, and a current sensing pad for outputting a current sensing signal can be cited.

[0028] Figure 2 A main part cross-sectional view schematically showing a manufacturing process of the semiconductor device of the present embodiment is a main part cross-sectional view of a position corresponding to the II-II line of FIG. Figure 1 ​​​​a main partial cross-sectional view corresponding to the II-II line. Figure 2 corresponding to the boundary of the IGBT range 102 and the diode range 104. As shown, the semiconductor device 1 is provided with a semiconductor substrate 10 that is a silicon substrate, a collector electrode 22 provided so as to cover the back surface of the semiconductor substrate 10, an emitter electrode 24 provided so as to cover the surface of the semiconductor substrate 10, a trench gate portion 30 provided on the surface of the semiconductor substrate 10, and an interlayer insulating film 40 that insulates the trench gate portion 30 from the emitter electrode 24. The emitter electrode 24 is composed of an alloy containing aluminum and silicon, i.e., aluminum silicon (AlSi).

[0029] The semiconductor substrate 10 has a p + type collector region 11, an n - type drift region 13, a p + type body region 14, an n + type emitter region 17, and an n type cathode region 18.

[0030] The collector region 11 is disposed on a portion of the back layer portion of the semiconductor substrate 10, at a position exposed on the back surface of the semiconductor substrate 10. The collector region 11 is in ohmic contact with the collector electrode 22 that covers the back surface of the semiconductor substrate 10. The collector region 11 is formed on the back layer portion of the semiconductor substrate 10 by ion implantation of boron to the back surface of the semiconductor substrate 10 using an ion implantation technique.

[0031] The cathode region 18 is disposed on a portion of the back layer portion of the semiconductor substrate 10, at a position exposed on the back surface of the semiconductor substrate 10. The cathode region 18 is in ohmic contact with the collector electrode 22 that covers the back surface of the semiconductor substrate 10. The cathode region 18 is formed on the back layer portion of the semiconductor substrate 10 by ion implantation of phosphorus to the back surface of the semiconductor substrate 10 using an ion implantation technique.

[0032] Thus, the collector region 11 and the cathode region 18 are disposed in close proximity to each other on the back layer portion of the semiconductor substrate 10. The semiconductor substrate 10 divides the range in which the collector region 11 is formed into the IGBT range 102 and the range in which the cathode region 18 is formed into the diode range 104, in accordance with the presence or absence of the emitter region 17 on the surface layer portion of the semiconductor substrate 10.

[0033] The buffer region 12 is provided on the surface of the collector region 11 and the cathode region 18, is disposed between the collector region 11 and the drift region 13, and is disposed between the cathode region 18 and the drift region 13. The buffer region 12 is a region in which the concentration of n-type impurities is higher than that of the drift region 13. The buffer region 12 is formed by ion implantation of phosphorus into the back surface of the semiconductor substrate 10 using an ion implantation technique.

[0034] The drift region 13 is provided on the surface of the buffer region 12, is disposed between the buffer region 12 and the body region 14. The drift region 13 is a remaining portion after forming other semiconductor regions within the semiconductor substrate 10.

[0035] The body region 14 is provided on the surface of the drift region 13, is disposed in the surface layer portion of the semiconductor substrate 10, and is disposed at a position exposed to the surface of the semiconductor substrate 10. The body region 14 is in ohmic contact with the emitter electrode 24 that covers the surface of the semiconductor substrate 10. In addition, the body region 14 can also have a contact region in which the concentration of p-type impurities is higher in order to improve the ohmic characteristics with the emitter electrode 24. The body region 14 is formed in the surface layer portion of the semiconductor substrate 10 by ion implantation of boron into the surface of the semiconductor substrate 10 using an ion implantation technique.

[0036] The barrier region 15 is provided within the body region 14, extends and spreads in the planar direction of the semiconductor substrate 10 in a manner that contacts both side surfaces of the adjacent trench gate portion 30. The barrier region 15 is disposed across the body region 14 in the thickness direction of the semiconductor substrate 10. In addition, the barrier region 15 can also be disposed below the entirety of the body region 14, that is, between the drift region 13 and the body region 14. Furthermore, the barrier region 15 can also be selectively formed only in the diode range 104 and not formed in the IGBT range 102. The barrier region 15 is formed in the surface layer portion of the semiconductor substrate 10 by ion implantation of phosphorus into the surface of the semiconductor substrate 10.

[0037] The pillar region 16 is provided within the body region 14, penetrates a portion of the body region 14 from the surface of the semiconductor substrate 10, and extends to the barrier region 15. The pillar region 16 is disposed at a position separated from the side surface of the trench gate portion 30 between the adjacent trench gate portions 30. The pillar region 16 is in Schottky contact with the emitter electrode 24 that covers the surface of the semiconductor substrate 10. Thus, the barrier region 15 is electrically connected to the emitter electrode 24 via the pillar region 16. In addition, the pillar region 16 can also be selectively formed only in the diode range 104 and not formed in the IGBT range 102 in the case where the barrier region 15 is selectively formed only in the diode range 104. The pillar region 16 is formed in the surface layer portion of the semiconductor substrate 10 by ion implantation of phosphorus into the surface of the semiconductor substrate 10.

[0038] The emitter region 17 is provided on the surface of the body region 14, is disposed in the surface layer portion of the semiconductor substrate 10, and is disposed so as to be exposed on the surface of the semiconductor substrate 10. The emitter region 17 is in ohmic contact with the side surface of the trench gate portion 30 and the emitter electrode 24. The emitter region 17 is selectively formed in the IGBT range 102 of the semiconductor substrate 10 and is not formed in the diode range 104 of the semiconductor substrate 10. The emitter region 17 is formed in the surface layer portion of the semiconductor substrate 10 by ion implantation of phosphorus to the surface of the semiconductor substrate 10 using an ion implantation technique.

[0039] The trench gate portion 30 is provided in the trench TR1 formed in the surface of the semiconductor substrate 10 and has the gate electrode 32 and the gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34 and is insulated from the emitter electrode 24 by the interlayer insulating film 40. The trench gate portion 30 penetrates the body region 14 from the surface of the semiconductor substrate 10 and reaches the drift region 13. In this example, the trench gate portion 30 extends in the x direction in the element region 10A of the semiconductor substrate 10. That is, the trench gate portion 30 has a shape in which the x direction is the long side direction and the y direction is the short side direction. Further, in this example, a plurality of trench gate portions 30 are arranged in the y direction at a prescribed interval each in the element region 10A of the semiconductor substrate 10. In this way, the plurality of trench gate portions 30 have a strip-like layout when viewed in plan. In addition, the layout of the plurality of trench gate portions 30 is not particularly limited. Instead of this example, the plurality of trench gate portions 30 can have a lattice-like layout when viewed in plan. The plurality of trench gate portions 30 are formed in both the IGBT range 102 and the diode range 104. In addition, the trench gate portion 30 of the plurality of trench gate portions 30 that is disposed in the diode range 104 can be used as a dummy gate. In the case of being used as a dummy gate, the gate electrode 32 thereof can not be electrically connected to the gate wiring and can be applied with a voltage of a different magnitude and / or phase from the gate voltage. In the case of being used as a dummy gate, for example, the gate electrode 32 thereof can be short-circuited to the emitter electrode 24.

[0040] Figure 3 An enlarged sectional view of the interlayer insulating film 40 provided on the surface of the trench gate portion 30 is shown. In addition, Figure 3 A view in which a sectional plane parallel to the yz plane is enlarged is shown. Further, Figure 3 In this example, the interlayer insulating film 40 disposed in the diode range 104 is shown, but the interlayer insulating film 40 disposed in the IGBT range 102 also has the same structure.

[0041] The interlayer insulating film 40 is formed so as to cover the surface of the gate electrode 32 completely and is wider than the width of the short side direction (y direction) of the trench gate portion 30. The interlayer insulating film 40 has a top surface 42 and a side surface 44. The top surface 42 extends substantially in parallel to the surface of the semiconductor substrate 10. The side surface 44 has an upper side surface 44a and a lower side surface 44b. The upper side surface 44a demarcates the upper side in the side surface 44 and is contiguous to the top surface 42 and is formed in a concave curved surface. The lower side surface 44b demarcates the lower side in the side surface 44 and is contiguous to the surface of the semiconductor substrate 10 via the gate insulating film 34 and is formed in a flat plane. In addition, since the gate insulating film 34 is extremely thin, the lower side surface 44b can be said to be substantially contiguous to the surface of the semiconductor substrate 10. As will be described later, the upper side surface 44a has a concave curved surface form reflecting processing based on isotropic etching, and the lower side surface 44b has a flat plane form reflecting processing based on anisotropic etching.

[0042] Since the upper side surface 44a is formed in a concave curved surface, the angle of the corner portion 46 formed by the top surface 42 and the upper side surface 44a is an acute angle. As will be described later, if the angle of the corner portion 46 is formed as an acute angle, it is possible to control so that silicon balls are selectively precipitated at a position in the surface of the semiconductor substrate 10 corresponding to the end portion of the side surface of the interlayer insulating film 40 on the lower side (a position enclosed by the broken line 48).

[0043] The semiconductor device 1 is capable of controlling the on-off of the current flowing from the collector electrode 22 to the emitter electrode 24 in the IGBT range 102 based on the gate voltage applied to the gate electrode 32 of the trench gate portion 30. Furthermore, in the semiconductor device 1, the diode configuration formed in the diode range 104 is capable of functioning as a freewheeling diode. In particular, in the semiconductor device 1, by providing the barrier region 15 and the pillar region 16, the reverse recovery characteristics in diode operation are improved. The diode operation will be described below.

[0044] If a higher potential than the collector electrode 22 is applied to the emitter electrode 24, a backflow current flows in the IGBT range 102 and the diode range 104, respectively. Hereinafter, a case where the potential of the emitter electrode 24 is gradually increased from the same potential as the collector electrode 22 will be described. If the potential of the emitter electrode 24 is increased, the Schottky junction of the pillar region 16 and the emitter electrode 24 is turned on. Thus, electrons flow from the collector electrode 22 to the emitter electrode 24. In this way, when the potential of the emitter electrode 24 is relatively low, the Schottky barrier diode is turned on, and a current flows from the emitter electrode 24 to the collector electrode 22.

[0045] When the Schottky barrier diode is conducting, the potential of the barrier region 15 is maintained at a potential close to that of the emitter electrode 24, so the voltage acting in the forward direction of the pn junction formed by the body region 14 and the barrier region 15 is suppressed to a low level. Therefore, when the potential of the emitter electrode 24 is relatively low, the pn diode does not conduct. If the potential of the emitter electrode 24 becomes relatively high, the current flowing through the Schottky barrier diode increases. As the current flowing through the Schottky barrier diode increases, the potential difference between the emitter electrode 24 and the barrier region 15 increases, and the voltage acting in the forward direction of the pn junction formed by the body region 14 and the barrier region 15 also increases, causing holes to be injected from the body region 14 through the barrier region 15. As a result, holes flow from the emitter electrode 24 toward the collector electrode 22. On the other hand, electrons flow from the collector electrode 22 toward the emitter electrode 24. Thus, when the potential of the emitter electrode 24 is relatively high, the pn diode conducts.

[0046] As described above, when the potential of the emitter electrode 24 rises, the Schottky barrier diode turns on first, thereby delaying the timing of the pn diode turning on. As a result, when the return current flows, the amount of holes injected from the body region 14 into the drift region 13 is suppressed. Thereafter, if a higher potential than that of the emitter electrode 24 is applied to the collector electrode 22, the pn diode performs a reverse recovery operation. At this time, since the amount of holes injected from the body region 14 into the drift region 13 is suppressed, the reverse current when the pn diode performs a reverse recovery operation also becomes smaller. In this way, in the semiconductor device 1, by providing the barrier region 15 and the pillar region 16, the reverse recovery characteristics in the diode operation are improved.

[0047] Next, a method for manufacturing the semiconductor device 1 will be described with reference to the accompanying drawings. Figure 4 As shown in FIG. 1 , a semiconductor substrate 10 is prepared in which various semiconductor regions are formed on the surface of the semiconductor substrate 10. Alternatively, at least a portion of the various semiconductor regions may be formed after performing the steps described below.

[0048] Then, if Figure 5 As shown, trench TR1 is formed from the surface of semiconductor substrate 10 through body region 14 and reaching drift region 13 by anisotropic dry etching. Next, gate insulating film 34 is formed on the inner surface of trench TR1 and the surface of semiconductor substrate 10 by thermal oxidation.

[0049] Then, if Figure 6As shown, a polysilicon gate electrode 32 is formed within trench TR1 using CVD technology, thereby forming a trench gate portion 30. The gate electrode 32 is formed so as to partially fill trench TR1. In other words, the surface of the gate electrode 32 is positioned deeper than the surface of the semiconductor substrate 10. This is because the gate electrode 32 is formed away from the corner formed by the surface of the semiconductor substrate 10 and the side of the trench TR1 to suppress leakage current. As a result, a groove corresponding to the position of the gate electrode 32 is formed on the surface of the semiconductor substrate 10.

[0050] Then, if Figure 7 As shown, an interlayer insulating film 40 is formed using CVD technology to cover the entire surface of the semiconductor substrate 10. Silicon oxide containing a large amount of boron, phosphorus, etc. is used for the interlayer insulating film 40. A groove corresponding to the position of the gate electrode 32 is formed on the surface of the interlayer insulating film 40.

[0051] Then, if Figure 8 As shown, the surface of the interlayer insulating film 40 is fluidized and flattened by an annealing process. As an example, the annealing temperature at this time is approximately 950°C.

[0052] Then, if Figure 9 As shown, a photoresist mask 52 is patterned on the surface of the interlayer insulating film 40 using photolithography and etching techniques. The mask 52 is selectively arranged corresponding to the position where the trench gate portion 30 is to be formed.

[0053] Then, if Figure 10 As shown, a portion of the interlayer insulating film 40 is etched using an isotropic etching technique (e.g., Chemical Dry Etching (CDE) technique). At this time, the interlayer insulating film 40 present under the mask 52 is etched isotropically from the transverse direction, and the side surface of the interlayer insulating film 40 is processed into a concave curved surface. This portion becomes the upper side surface 44a of the interlayer insulating film 40 (see Figure 3 ).

[0054] Then, if Figure 11 As shown, a portion of the interlayer insulating film 40 is etched using an anisotropic etching technique (e.g., Reactive Ion Etching (RIE) technique) to expose the surface of the semiconductor substrate 10 between the masks 52. At this time, the side surface of the interlayer insulating film 40 that exists under the mask 52 is processed into a flat plane. This portion becomes the lower side surface 44b of the interlayer insulating film 40 (see FIG. Figure 3 ).

[0055] Then, if Figure 12As shown, the mask 52 is removed using a wet etching technique. The interlayer insulating film 40 formed through these processes is configured such that the angle formed by the corner portion 46 composed of the top surface 42 and the upper side surface 44a is an acute angle.

[0056] Next, as shown in FIG. 6, the emitter electrode 24 is formed using a sputtering technique in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. Figure 13 As shown in FIG. 7, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 8. Figure 14 As shown in FIG. 9, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 10. As shown in FIG. 11, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 12.

[0057] As shown in FIG. 13, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 14. Figure 14 As shown in FIG. 15, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 16. As shown in FIG. 17, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 18.

[0058] As shown in FIG. 19, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 20. As shown in FIG. 21, the emitter electrode 24 is formed in a manner to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40. The emitter electrode 24 is formed of aluminum-silicon. The silicon included in the emitter electrode 24 at this time is described with reference to FIG. 22.

[0059] Next, the emitter electrode 24 is processed in a manner to remove the emitter electrode 24 on the peripheral region 10B (see FIG. 23) of the semiconductor substrate 10, and a protective film (for example, a polyimide film) is formed on the peripheral region 10B (see FIG. 24) of the semiconductor substrate 10. Finally, after the semiconductor substrate 10 is thinned, various semiconductor regions and the collector electrode 22 are formed on the back surface of the semiconductor substrate 10, and the semiconductor device 1 is completed. Figure 1 Figure 1

[0060] As described above, according to the manufacturing method of the present embodiment, the occurrence of silicon balls 62 at the formation position of the column region 16 is suppressed. The occurrence of silicon balls 62 at the formation position of the column region 16, and the variation in the height of the potential barrier between the column region 16 and the emitter electrode 24 are suppressed. That is, in the semiconductor device 1, the height of the potential barrier between the column region 16 and the emitter electrode 24 is stable, and thus the problem of an increase in the leakage current is suppressed. The semiconductor device 1 can have high reliability.

[0061] The technical elements disclosed in this specification are listed below. In addition, each of the technical elements below functions independently.

[0062] The semiconductor device disclosed in this specification can include a semiconductor substrate, a trench gate portion provided in one main surface of the semiconductor substrate, a surface electrode covering the one main surface of the semiconductor substrate, and an interlayer insulating film insulating the trench gate portion and the surface electrode. As a kind of the semiconductor device, a reverse conducting IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is exemplified. In addition, the trench gate portion can be a dummy gate. The semiconductor substrate can have a drift region of a first conductivity type, a body region of a second conductivity type provided above the drift region, a barrier region of the first conductivity type provided below at least a part of the body region, and a column region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and in Schottky contact with the surface electrode. The surface electrode is a silicon-containing alloy. As an example, the surface electrode can be aluminum silicon. An angle formed by the top surface and the side surface of the interlayer insulating film is an acute angle.

[0063] A part of the side surface adjacent to the top surface can be configured in a concave curved surface. In this case, the angle formed by the top surface and the side surface of the interlayer insulating film is further reduced.

[0064] The manufacturing method of a semiconductor device disclosed in this specification can be applied to a manufacturing method of a semiconductor device that includes a semiconductor substrate, a trench gate portion provided in one main surface of the semiconductor substrate, a surface electrode covering the one main surface of the semiconductor substrate, and an interlayer insulating film insulating the trench gate portion from the surface electrode, the semiconductor substrate including a drift region of a first conductivity type, a body region of a second conductivity type provided above the drift region, a barrier region of the first conductivity type provided below at least a portion of the body region, and a pillar region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and in Schottky contact with the surface electrode, the surface electrode being a silicon-containing alloy. As a kind of the semiconductor device, a reverse conducting IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is exemplified. Further, the trench gate portion can be a dummy gate. The manufacturing method can include a step of forming the interlayer insulating film on the one main surface of the semiconductor substrate on which the trench gate portion is formed, a step of patterning a mask on the interlayer insulating film at a position corresponding to the trench gate portion, and a step of etching a portion of the interlayer insulating film using an isotropic etching technique so that an angle formed by a top surface and a side surface of the interlayer insulating film is an acute angle.

[0065] The above detailed description of the embodiments of the present application is merely illustrative, and does not limit the claims. The technology recited in the claims includes various modifications and changes of the above-described embodiments. The technical elements described in the specification or the drawings are technically useful either alone or in various combinations, and are not limited to the combinations recited in the claims at the time of filing. Furthermore, the technology exemplified in the specification or the drawings simultaneously achieves multiple objects, and achieving one of the objects itself has technical utility.

Claims

1. A semiconductor device characterized by comprising: a semiconductor substrate; a trench gate portion provided in one main surface of the semiconductor substrate; a surface electrode covering above the one main surface of the semiconductor substrate; and an interlayer insulating film insulating the trench gate portion from the surface electrode, the interlayer insulating film being positioned above the one main surface of the semiconductor substrate; the semiconductor substrate having: a drift region of a first conductivity type; a body region of a second conductivity type provided above the drift region; a barrier region of the first conductivity type provided below at least a part of the body region; and a pillar region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and being in Schottky contact with the surface electrode; the surface electrode being an alloy containing silicon; an angle formed by a top surface of the interlayer insulating film and a side surface of the interlayer insulating film being an acute angle; the top surface and the side surface of the interlayer insulating film both being in contact with the surface electrode, the angle formed by the top surface of the interlayer insulating film and the side surface of the interlayer insulating film being formed as an acute angle so that silicon in the surface electrode diffused along a grain boundary of the surface electrode is selectively precipitated as silicon balls at a position on the one main surface of the semiconductor substrate corresponding to an end portion of the side surface of the interlayer insulating film on a lower side.

2. The semiconductor device according to claim 1, characterized in that a part of the side surface adjacent to the top surface is constituted by a concave curved surface.

3. The semiconductor device according to claim 1 or 2, characterized in that the surface electrode is aluminum silicon.

4. A manufacturing method of a semiconductor device, the semiconductor device comprising a semiconductor substrate, a trench gate portion provided in one main surface of the semiconductor substrate, a surface electrode covering above the one main surface of the semiconductor substrate, and an interlayer insulating film insulating the trench gate portion from the surface electrode, the semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type provided above the drift region, a barrier region of the first conductivity type provided below at least a part of the body region, and a pillar region of the first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and being in Schottky contact with the surface electrode, the surface electrode being an alloy containing silicon, the manufacturing method of the semiconductor device being characterized by comprising: a step of forming the interlayer insulating film on the one main surface of the semiconductor substrate on which the trench gate portion is formed; a step of patterning a mask on the interlayer insulating film corresponding to a position on which the trench gate portion is formed; and a step of etching a part of the interlayer insulating film using an isotropic etching technique so that an angle formed by a top surface of the interlayer insulating film and a side surface of the interlayer insulating film is an acute angle, the angle formed by the top surface of the interlayer insulating film and the side surface of the interlayer insulating film being formed as an acute angle so that silicon in the surface electrode diffused along a grain boundary of the surface electrode is selectively precipitated as silicon balls at a position on the one main surface of the semiconductor substrate corresponding to an end portion of the side surface of the interlayer insulating film on a lower side. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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