An FFT implementation device for a communication system and an implementation method thereof

Abstract

The present invention discloses an FFT implementation device for a communication system and an implementation method thereof, which includes a controller, a data memory, an FFT arithmetic unit, a multiplier, and a twiddle factor memory. The FFT arithmetic unit includes a plurality of sub-FFT calculation units corresponding to a set of sub-FFT point numbers. Each sub-FFT calculation unit is used to implement the sub-FFT operation of any sub-FFT point number in the set of sub-FFT point numbers, and the product of the sub-FFT point numbers of each sub-FFT calculation unit is equal to the FFT point number required by the communication system. When the point numbers required by different modes in a multi-mode communication system are not powers of 2, the FFT implementation device of the present invention can be implemented without redundancy, without first implementing the FFT operation with a point number that is a power of 2, and there is no loss in system performance; at the same time, the number of iterations of the sub-FFT is reduced and the delay is lower.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to an FFT implementation device for a communication system and an implementation method thereof. Background Art

[0002] In the field of mobile communication technologies, both the physical layer of the Long-Term Evolution fourth-generation mobile communication system (4G LTE) and the fifth-generation mobile communication system (5G NR) adopt orthogonal frequency division multiplexing (OFDM) technology as their core technology. In downlink communication, both 4G LTE and 5G NR adopt orthogonal frequency division multiple access (OFDMA) technology; in uplink communication, 4G LTE adopts single-carrier frequency division multiple access (SC-FDMA) technology, and 5G NR supports both the SC-FDMA technology of 4G LTE and OFDMA technology (i.e., the same as downlink communication). Modulation and demodulation in the above OFDMA technology and SC-FDMA technology are both implemented through discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT). When DFT and IDFT are implemented in hardware, the amount of computation is large and the circuit is complex. Therefore, fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) are generally used to replace them. The IFFT operation can be implemented through the FFT operation. Therefore, only the implementation of FFT needs to be concerned about.

[0003] In a multi-mode communication system, different communication modes (such as 4G LTE, 5G NR, etc.) require support for FFT operations with different numbers of points. For example, according to the 4G LTE protocol requirements, 34 kinds of point numbers of FFT operations need to be supported, and the maximum number of points is 1200; according to the 5G NR protocol requirements, 4096-point FFT operations need to be supported. Therefore, in the multi-mode mobile communication system of 4G LTE and 5G NR, the above 35 kinds of point numbers of FFT operations need to be supported simultaneously. These 35 kinds of point numbers are 12, 24, 36, 48, 60, 72, 96, 108, 120, 144, 180, 192, 216, 240, 288, 300, 324, 360, 384, 432, 480, 540, 576, 600, 648, 720, 768, 864, 900, 960, 972, 1080, 1152, 1200, and 4096 respectively. Among them, the first 34 point numbers are those that 4G LTE needs to support, and the last point number 4096 is what 5G NR needs to support. When the multi-mode communication system implements the FFT operation, different FFT implementation devices can be used to implement the FFT operations with the required number of points in each communication mode respectively, but the area and power consumption will increase, which is obviously not the optimal choice. The optimal choice should be to share a set of FFT implementation devices to implement the FFT operations with the required number of points in each communication mode, that is, this FFT implementation device can simultaneously meet the requirements of the FFT operations with the required number of points in each communication mode. For example, the FFT operations with the point numbers required by 4G LTE and the FFT operations with the point numbers required by 5G NR in the multi-mode mobile communication system can share an FFT implementation device, and this FFT implementation device simultaneously supports 34 kinds of point numbers of FFT operations of 4G LTE and 1 kind of point number of FFT operations of 5G NR.

[0004] Generally, the FFT operations under 4G LTE have the following implementation methods:

[0005] It is iteratively implemented through the radix-2 or radix-4 FFT operation. With this method, the FFT operation of 5G NR can also be implemented. For the N-point FFT operation, the so-called radix-2 FFT divides the N-point sequence to be operated into two parts each time until it is finally decomposed into 2-point DFT operations; the radix-4 FFT divides the N-point sequence to be operated into four parts each time until it is finally decomposed into 4-point DFT operations. When using the radix-2 or radix-4 FFT operation to implement the FFT operations under 4G LTE and 5G NR, there are the following disadvantages respectively, including:

[0006] (1) When implementing the FFT operation under 4G LTE, since the 34 FFT point numbers of 4G LTE are not powers of 2, it cannot be "accurately" implemented through the radix-2 or radix-4 FFT operation ("accurately" means that no redundant 0s need to be added, that is, the correct calculation can be performed). For another example, to implement a 12-point FFT operation, using the radix-2 FFT to implement it, it is necessary to first implement a 16-point FFT operation, and then supplement 4 0s at the end of the input 12-point data to calculate the 16-point FFT operation, and delete the added 0s when outputting. Obviously, this method will cause performance loss.

[0007] (2) When implementing the FFT operation under 5G NR, since the supported point number 4096 of 5G NR is the 12th power of 2, the 4096-point FFT operation of 5G NR can be implemented by iterating the radix-2 or radix-4 FFT operation. However, using the radix-2 FFT requires 12 iterations, and using the radix-4 FFT requires 6 iterations. The number of iterations is large, and the processing delay increases, so the 4096-point FFT operation cannot be implemented with low latency.

[0008] Therefore, in the prior art, when using the same FFT implementation device to implement the FFT operations of the point numbers required by 4G LTE and 5G NR, there are problems of redundancy and large delay. This problem exists in multi-mode mobile communication systems, and the same problem also exists in other multi-mode communication systems. Summary of the Invention

[0009] Object of the Invention: Aiming at the problems existing in the prior art, the present invention discloses an FFT implementation device for a communication system and its implementation method, which solves the problems of redundancy and large delay when using the same FFT implementation device to implement the FFT operations of different mode-required point numbers in a multi-mode communication system.

[0010] Technical Solution: To achieve the above object of the invention, the present invention adopts the following technical solution:

[0011] An FFT implementation device for a communication system includes a controller, a data memory, an FFT arithmetic unit, a multiplier, and a twiddle factor memory, wherein:

[0012] The FFT arithmetic unit includes a plurality of sub-FFT calculation units corresponding to a set of preset sub-FFT point numbers. The inputs of all sub-FFT calculation units are connected to the data memory. The output of one sub-FFT calculation unit is connected to the data memory, and the outputs of the remaining sub-FFT calculation units are connected to the multiplier. Each sub-FFT calculation unit is used to implement the sub-FFT operation of any one of the sub-FFT point numbers in the set of preset sub-FFT point numbers. The product of the sub-FFT point numbers of all sub-FFT calculation units is equal to the FFT point number required by the communication system;

[0013] The twiddle factor memory is used to store twiddle factors;

[0014] The multiplier is connected to the rotation factor memory for performing complex multiplication operations on the outputs of each sub-FFT calculation unit connected thereto and the rotation factors in the rotation factor memory;

[0015] The data memory is connected to the multiplier for storing the outputs of the sub-FFT calculation unit and the multiplier connected thereto;

[0016] The controller is respectively connected to the data memory, the FFT arithmetic unit, the multiplier, and the rotation factor memory for configuring the data memory, the FFT arithmetic unit, and the rotation factor memory, and controlling the data memory, the FFT arithmetic unit, the multiplier, and the rotation factor memory.

[0017] Further, the FFT arithmetic unit includes a first sub-FFT calculation unit, a second sub-FFT calculation unit, a third sub-FFT calculation unit, and a fourth sub-FFT calculation unit;

[0018] The rotation factor memory includes a first rotation factor storage unit, a second rotation factor storage unit, and a third rotation factor storage unit;

[0019] The multiplier includes a first complex multiplication unit, a second complex multiplication unit, and a third complex multiplication unit, where: the first complex multiplication unit is connected to the first sub-FFT calculation unit and the first rotation factor storage unit, the second complex multiplication unit is connected to the second sub-FFT calculation unit and the second rotation factor storage unit, and the third complex multiplication unit is connected to the third sub-FFT calculation unit and the third rotation factor storage unit;

[0020] The data memory includes a first data storage unit, a second data storage unit, a third data storage unit, a fourth data storage unit, a fifth data storage unit, a sixth data storage unit, and a seventh data storage unit, where: the second data storage unit is connected to the first data storage unit and the first sub-FFT calculation unit, the third data storage unit is connected to the first complex multiplication unit and the second sub-FFT calculation unit, the fourth data storage unit is connected to the second complex multiplication unit and the fifth data storage unit, the fifth data storage unit is connected to the fourth data storage unit and the third sub-FFT calculation unit, the sixth data storage unit is connected to the third complex multiplication unit and the fourth sub-FFT calculation unit, and the seventh data storage unit is connected to the fourth sub-FFT calculation unit.

[0021] Further, the product of the number of sub-FFT points of the first sub-FFT calculation unit and the number of sub-FFT points of the second sub-FFT calculation unit is less than or equal to a first threshold, the product of the number of sub-FFT points of the third sub-FFT calculation unit and the number of sub-FFT points of the fourth sub-FFT calculation unit is less than or equal to a second threshold, and the product of the first threshold and the second threshold is equal to the maximum number of FFT points required by the communication system.

[0022] Further, the depth of the first rotation factor storage unit is at least the first threshold value;

[0023] The depth of the second rotation factor storage unit is at least the product of the first threshold value and the second threshold value;

[0024] The depth of the third rotation factor storage unit is at least the second threshold value.

[0025] Further, the depths of the first data storage unit, the fourth data storage unit, and the seventh data storage unit are all at least twice the product of the first threshold value and the second threshold value;

[0026] The depths of the second data storage unit and the third data storage unit are at least twice the first threshold value;

[0027] The depths of the fifth data storage unit and the sixth data storage unit are at least twice the second threshold value.

[0028] Further, the rotation factor memory is implemented by a RAM.

[0029] Further, a lookup table is stored in the controller. The lookup table includes a number of entries, and each entry includes the number of FFT points required by the communication system and the number of sub-FFT points corresponding to each sub-FFT calculation unit when implementing the number of FFT points.

[0030] Further, the set of the set sub-FFT points is {1, 2, 3, 4, 5, 6, 8, 9}.

[0031] An FFT implementation method for a communication system includes the following steps:

[0032] The controller initializes the data memory, the FFT arithmetic unit, and the rotation factor memory according to the number of FFT points required by the communication system and the number of sub-FFT points of each sub-FFT calculation unit when implementing the number of FFT points;

[0033] The first sub-FFT calculation unit reads the data to be operated from the data memory, performs a sub-FFT operation on the data to be operated with the corresponding number of sub-FFT points to obtain a result, inputs the result into the multiplier, inputs the rotation factor in the rotation factor memory into the multiplier, performs a complex multiplication operation on the result and the rotation factor in the multiplier to obtain a first sub-FFT iteration result, and stores the first sub-FFT iteration result in the data memory;

[0034] The next sub-FFT calculation unit reads the current sub-FFT iteration result from the data memory, performs a sub-FFT operation with the corresponding number of sub-FFT points on the current sub-FFT iteration result to obtain the next result, inputs the next result into the multiplier, inputs the rotation factor from the rotation factor memory into the multiplier, performs a complex multiplication operation between the next result and the rotation factor in the multiplier to obtain the next sub-FFT iteration result, and stores the next sub-FFT iteration result in the data memory; repeat the above process until the last sub-FFT calculation unit reads the previous sub-FFT iteration result from the data memory, performs a sub-FFT operation with the corresponding number of sub-FFT points on the previous sub-FFT iteration result to obtain the last sub-FFT iteration result, and stores the last sub-FFT iteration result in the data memory;

[0035] Read the last sub-FFT iteration result from the data memory as the FFT operation result corresponding to the required number of FFT points.

[0036] Further, a lookup table is stored in the controller, and the controller indexes from the lookup table the required number of FFT points of the communication system and the number of sub-FFT points of each sub-FFT calculation unit when implementing the number of FFT points.

[0037] Advantageous effects: Compared with the prior art, the present invention has the following advantageous effects:

[0038] In the FFT implementation device of the present invention, the FFT arithmetic unit includes a plurality of sub-FFT calculation units corresponding to a set of preset sub-FFT point numbers, each sub-FFT calculation unit is used to implement a sub-FFT operation with any sub-FFT point number in the set of preset sub-FFT point numbers, and the product of the sub-FFT point numbers of each sub-FFT calculation unit is equal to the required number of FFT points of the communication system;

[0039] In the FFT implementation device of the present invention, the number of FFT points is decomposed into a plurality of sub-FFT point numbers, and the sub-FFT point numbers can be arbitrarily selected from the set of preset sub-FFT point numbers for combination. Compared with the prior art, there is no redundancy and the delay is low: when the required number of points in different modes of a multi-mode communication system is not a power of 2, the FFT implementation device of the present invention can be directly implemented without redundancy, without first implementing the FFT operation with a number of points that is a power of 2, and the system performance is not lost; at the same time, the number of iterations of the sub-FFT is reduced and the delay is lower. Description of the Drawings

[0040] Figure 1 It is a structural diagram of an FFT implementation device in an embodiment of the present invention;

[0041] Figure 2 It is a specific structural diagram of an FFT implementation device in an embodiment of the present invention;

[0042] Figure 3 This is a flowchart of a method for implementing FFT in an embodiment of the present invention. Specific implementation manner

[0043] The present invention will be further described below with reference to the accompanying drawings.

[0044] Embodiment 1:

[0045] This embodiment discloses an FFT implementation device for a communication system, including a controller 1, a data memory 2, an FFT arithmetic unit 3, a multiplier 4, and a twiddle factor memory 5, where:

[0046] The FFT arithmetic unit 3 includes a plurality of sub-FFT calculation units corresponding to a set of sub-FFT point numbers. The inputs of all sub-FFT calculation units are connected to the data memory 2. The output of one sub-FFT calculation unit is connected to the data memory 2, and the outputs of the remaining sub-FFT calculation units are connected to the multiplier 4. Each sub-FFT calculation unit is used to implement a sub-FFT operation of any sub-FFT point number in the set of sub-FFT point numbers. The product of the sub-FFT point numbers of all sub-FFT calculation units is equal to the FFT point number required by the communication system;

[0047] The twiddle factor memory 5 is used to store twiddle factors;

[0048] The multiplier 4 is connected to the twiddle factor memory 5 and is used to implement a complex multiplication operation between the output of each sub-FFT calculation unit connected thereto and the twiddle factor in the twiddle factor memory 5;

[0049] The data memory 2 is connected to the multiplier 4 and is used to store the outputs of the sub-FFT calculation unit and the multiplier 4 connected thereto;

[0050] The controller 1 is respectively connected to the data memory 2, the FFT arithmetic unit 3, the multiplier 4, and the twiddle factor memory 5, and is used to configure the data memory 2, the FFT arithmetic unit 3, and the twiddle factor memory 5, and to control the data memory 2, the FFT arithmetic unit 3, the multiplier 4, and the twiddle factor memory 5.

[0051] In the FFT implementation device of the present invention, the FFT point number is decomposed into a plurality of sub-FFT point numbers, and the sub-FFT point numbers can be arbitrarily selected from the set of sub-FFT point numbers for combination. Compared with the prior art, there is no redundancy and the delay is low: when the point numbers required by different modes in a multi-mode communication system are not powers of 2, the FFT implementation device described in this embodiment can be directly implemented without redundancy, instead of first implementing an FFT operation with a point number that is a power of 2, and the system performance is not lost; at the same time, the number of iterations of the sub-FFT is reduced and the delay is lower.

[0052] Further, the FFT calculator 3 includes a first sub-FFT calculation unit 31, a second sub-FFT calculation unit 32, a third sub-FFT calculation unit 33, and a fourth sub-FFT calculation unit 34;

[0053] The rotation factor memory 5 includes a first rotation factor storage unit 51, a second rotation factor storage unit 52, and a third rotation factor storage unit 53;

[0054] The multiplier 4 includes a first complex multiplier unit 41, a second complex multiplier unit 42, and a third complex multiplier unit 43, where: the first complex multiplier unit 41 is connected to the first sub-FFT calculation unit 31 and the first rotation factor storage unit 51, the second complex multiplier unit 42 is connected to the second sub-FFT calculation unit 32 and the second rotation factor storage unit 52, and the third complex multiplier unit 43 is connected to the third sub-FFT calculation unit 33 and the third rotation factor storage unit 53;

[0055] The data memory 2 includes a first data storage unit 21, a second data storage unit 22, a third data storage unit 23, a fourth data storage unit 24, a fifth data storage unit 25, a sixth data storage unit 26, and a seventh data storage unit 27, where: the second data storage unit 22 is connected to the first data storage unit 21 and the first sub-FFT calculation unit 31, the third data storage unit 23 is connected to the first complex multiplier unit 41 and the second sub-FFT calculation unit 32, the fourth data storage unit 24 is connected to the second complex multiplier unit 42 and the fifth data storage unit 25, the fifth data storage unit 25 is connected to the fourth data storage unit 24 and the third sub-FFT calculation unit 33, the sixth data storage unit 26 is connected to the third complex multiplier unit 43 and the fourth sub-FFT calculation unit 34, and the seventh data storage unit 27 is connected to the fourth sub-FFT calculation unit 34.

[0056] Further, the product of the sub-FFT point numbers of the first sub-FFT calculation unit 31 and the second sub-FFT calculation unit 32 is less than or equal to a first threshold, the product of the sub-FFT point numbers of the third sub-FFT calculation unit 33 and the fourth sub-FFT calculation unit 34 is less than or equal to a second threshold, and the product of the first threshold and the second threshold is equal to the maximum FFT point number required by the communication system.

[0057] Further, the depth of the first rotation factor storage unit 51 is at least the first threshold;

[0058] The depth of the second rotation factor storage unit 52 is at least the product of the first threshold and the second threshold;

[0059] The depth of the third rotation factor storage unit 53 is at least the second threshold.

[0060] Further, the depths of the first data storage unit 21, the fourth data storage unit 24, and the seventh data storage unit 27 are all at least twice the product of the first threshold and the second threshold;

[0061] The depths of the second data storage unit 22 and the third data storage unit 23 are at least twice the first threshold;

[0062] The depths of the fifth data storage unit 25 and the sixth data storage unit 26 are at least twice the second threshold.

[0063] Further, the rotation factor memory 5 is implemented using RAM.

[0064] In this embodiment, implementing the rotation factor memory 5 using RAM can avoid the irrecoverable fatal problems caused by ROM errors, making the FFT implementation device more robust.

[0065] Further, a lookup table is stored in the controller 1. The lookup table includes a number of entries, and each entry includes the FFT points required by the communication system and the corresponding sub-FFT points of each sub-FFT calculation unit when implementing the FFT points.

[0066] In this embodiment, directly searching for the FFT points required by the communication system and the corresponding sub-FFT points of each sub-FFT calculation unit when implementing the FFT points from the lookup table does not require logical calculations, reducing the design complexity and increasing the configuration flexibility.

[0067] Further, the set of the set sub-FFT points is {1, 2, 3, 4, 5, 6, 8, 9}.

[0068] Embodiment 2:

[0069] This embodiment discloses an FFT implementation device for a communication system, which can be used to implement FFT operations with different numbers of points under 4G LTE and 5G NR. The number of calculation points supported for implementation satisfies the following conditions:

[0070] N = N1 * N2 * N3 * N4 (1-1)

[0071] Wherein, N is the FFT points supported for implementation, and N1, N2, N3, and N4 are the sub-FFT points when calculating the N-point FFT respectively. Since the maximum number of FFT points in 4G LTE and 5G NR is 4096, N1, N2, N3, and N4 simultaneously satisfy the following conditions:

[0072] 1) The value ranges of N1, N2, N3, and N4, that is, the set of the set sub-FFT points, is {1, 2, 3, 4, 5, 6, 8, 9}

[0073] 2) N1 ≥ N2, N1 ≥ N3

[0074] 3) N1 * N2 ≤ 64, N3 * N4 ≤ 64

[0075] When the number of sub - FFT points is 1, it represents a direct connection, that is, no sub - FFT operation is required; when the number of sub - FFT points takes other values, it represents performing sub - FFT operations of 2 points, 3 points, 4 points, 5 points, 6 points, 8 points, or 9 points respectively. For example, if N1 = 8, it means the corresponding sub - FFT performs an 8 - point sub - FFT operation.

[0076] Based on the above - mentioned operation principle of the N - point FFT, an FFT implementation device in a communication system disclosed in this embodiment includes: a controller 1, a data memory 2, an FFT arithmetic unit 3, a multiplier 4, and a rotation factor memory 5. Among them, the controller 1 is respectively connected to the data memory 2, the FFT arithmetic unit 3, the multiplier 4, and the rotation factor memory 5. The output end of the data memory 2 is connected to the input end of the FFT arithmetic unit 3. The output end of the FFT arithmetic unit 3 is connected to the input end of the multiplier 4 and the input end of the data memory 2. The output end of the rotation factor memory 5 is connected to the input end of the multiplier 4. The output end of the multiplier 4 is connected to the input end of the data memory 2.

[0077] The FFT arithmetic unit 3 includes 4 sub - FFT calculation units, namely the first sub - FFT calculation unit 31, the second sub - FFT calculation unit 32, the third sub - FFT calculation unit 33, and the fourth sub - FFT calculation unit 34. The first sub - FFT calculation unit 31, the second sub - FFT calculation unit 32, the third sub - FFT calculation unit 33, and the fourth sub - FFT calculation unit 34 are all the same units and can be used to implement sub - FFT operations of 1 point, 2 points, 3 points, 4 points, 5 points, 6 points, 8 points, and 9 points. The 1 - point sub - FFT means no sub - FFT operation is performed. Through the FFT arithmetic unit 3, the N - point FFT operation can be flexibly decomposed into at most 4 parallel - executed sub - FFT operations. Through the above - mentioned sub - FFT operations, the FFT operations with the number of points within 4096 required by 4G LTE and 5G NR can be implemented in the same FFT implementation device, without redundancy and with a reduced number of iterations and a reduced processing delay, and the FFT operation can be implemented with low latency. The specific number of calculation points of the first sub - FFT calculation unit 31, the second sub - FFT calculation unit 32, the third sub - FFT calculation unit 33, and the fourth sub - FFT calculation unit 34 are configured by the controller 1 as follows:

[0078] The controller 1 configures the number of calculation points of the first sub - FFT calculation unit 31 as N1, and the first sub - FFT calculation unit 31 performs an N1 - point sub - FFT operation;

[0079] The controller 1 configures the number of calculation points of the second sub - FFT calculation unit 32 as N2, and the second sub - FFT calculation unit 32 performs an N2 - point sub - FFT operation;

[0080] The controller 1 configures the number of calculation points of the third sub-FFT calculation unit 33 as N3, and the third sub-FFT calculation unit 33 performs an N3-point FFT operation;

[0081] The controller 1 configures the number of calculation points of the fourth sub-FFT calculation unit 34 as N4, and the fourth sub-FFT calculation unit 34 performs an N4-point FFT operation.

[0082] There are 3 rotation factor tables in the rotation factor memory 5, which are stored using 3 rotation factor storage units respectively, namely the first rotation factor storage unit 51, the second rotation factor storage unit 52, and the third rotation factor storage unit 53, where:

[0083] The first rotation factor storage unit 51 stores N1*N2 rotation factors. Since the maximum value of N1*N2 is 64, the depth of the first rotation factor storage unit 51 is at least 64, and each rotation factor value is where the range of s1 is 0 to N1 - 1, the range of w1 is 0 to N2 - 1, and N1*N2 ≤ 64;

[0084] The second rotation factor storage unit 52 stores N rotation factors. Since the maximum value of N is 4096, the depth of the second rotation factor storage unit 52 is at least 4096, and each rotation factor value is where the range of s2 is 0 to N1*N2 - 1, the range of w2 is 0 to N3*N4 - 1, N1*N2 ≤ 64, and N3*N4 ≤ 64;

[0085] The third rotation factor storage unit 53 stores N3*N4 rotation factors. Since the maximum value of N3*N4 is 64, the depth of the third rotation factor storage unit 53 is at least 64, and each rotation factor value is where the range of s3 is 0 to N3 - 1, the range of w3 is 0 to N4 - 1, and N3*N4 ≤ 64.

[0086] The three rotation factor storage units can be implemented using RAM. The CPU (Central Processing Unit) externally connected to the FFT implementation device described in this embodiment configures the three rotation factor tables stored in the rotation factor memory 5 through the CPU interface provided by the controller 1. In the prior art, the rotation factor storage units are all implemented using ROM. When implemented on a chip, the data in the ROM is fixed and unchangeable, and there is a probability of error when implementing the ROM on a chip. The rotation factor tables in the rotation factor storage unit are the core modules of the FFT implementation device. Once an error occurs, the entire FFT implementation device will be incorrect, and since the ROM data is fixed and cannot be rewritten, the error cannot be recovered. In view of the problems existing in the rotation factor tables in the prior art, in this embodiment, the rotation factor memory 5 is designed to be implemented using RAM, and the externally connected CPU can freely read and write and configure the data in the three rotation factor tables through the controller 1, saving the calculation logic resources for generating rotation factors, and can avoid the irrecoverable fatal problem caused by ROM errors, making the FFT implementation device more robust.

[0087] The multiplier 4 includes 3 complex multiplication units, namely the first complex multiplication unit 41, the second complex multiplication unit 42, and the third complex multiplication unit 43, where:

[0088] The first complex multiplication unit 41, whose input terminals are respectively connected to the output terminal of the first sub-FFT calculation unit 31 and the output terminal of the first rotation factor storage unit 51, to complete the complex multiplication operation between the result of the N1-point sub-FFT operation output by the first sub-FFT calculation unit 31 and the rotation factor of the first rotation factor storage unit 51;

[0089] The second complex multiplication unit 42, whose input terminals are respectively connected to the output terminal of the second sub-FFT calculation unit 32 and the output terminal of the second rotation factor storage unit 52, to complete the complex multiplication operation between the result of the N2-point sub-FFT operation output by the second sub-FFT calculation unit 32 and the rotation factor of the second rotation factor storage unit 52;

[0090] The third complex multiplication unit 43, whose input terminals are respectively connected to the output terminal of the third sub-FFT calculation unit 33 and the output terminal of the third rotation factor storage unit 53, to complete the complex multiplication operation between the result of the N3-point sub-FFT operation output by the third sub-FFT calculation unit 33 and the rotation factor of the third rotation factor storage unit 53.

[0091] The multiplier 4 receives the multiplication enable signal of the controller 1, activates three complex multiplication units to execute in parallel, and simultaneously completes the multiplication operations between the results of the N1-point FFT operation, the results of the N2-point FFT operation, the results of the N3-point FFT operation and the rotation factors. Only three complex multiplication units are required in this embodiment. Compared with the prior art that uses more cascaded sub-FFT operations, fewer complex multiplication units are used in this embodiment, and the processing delay is reduced.

[0092] The data memory 2 includes seven data storage units, namely the first data storage unit 21, the second data storage unit 22, the third data storage unit 23, the fourth data storage unit 24, the fifth data storage unit 25, the sixth data storage unit 26 and the seventh data storage unit 27, where:

[0093] The first data storage unit 21 is used to store the data to be operated waiting for the N-point FFT operation;

[0094] The input end of the second data storage unit 22 is connected to the output end of the first data storage unit 21, and its output end is connected to the input end of the first sub-FFT calculation unit 31. It is used to store the rearranged data of the data to be operated in the first data storage unit 21 and input the rearranged data into the first sub-FFT calculation unit 31 for the N1-point FFT operation;

[0095] The input end of the third data storage unit 23 is connected to the output end of the first complex multiplication unit 41, and its output end is connected to the input end of the second sub-FFT calculation unit 32. It is used to store the calculation result of the first complex multiplication unit 41 and input the calculation result into the second sub-FFT calculation unit 32 for the N2-point FFT operation;

[0096] The input end of the fourth data storage unit 24 is connected to the output end of the second complex multiplication unit 42 and is used to store the calculation result of the second complex multiplication unit 42;

[0097] The input end of the fifth data storage unit 25 is connected to the output end of the fourth data storage unit 24, and its output end is connected to the input end of the third sub-FFT calculation unit 33. It is used to store the rearranged data of the data in the fourth data storage unit 24 and input the rearranged data into the third sub-FFT calculation unit 33 for the N3-point FFT operation;

[0098] The input end of the sixth data storage unit 26 is connected to the output end of the third complex multiplication unit 43, and its output end is connected to the input end of the fourth sub-FFT calculation unit 34. It is used to store the calculation result of the third complex multiplication unit 43 and input the calculation result into the fourth sub-FFT calculation unit 34 for the N4-point FFT operation;

[0099] The seventh data storage unit 27, whose input end is connected to the output end of the fourth sub-FFT calculation unit 34, is used to store the result of the N4-point sub-FFT operation in the fourth sub-FFT calculation unit 34, and is read out in order by the controller 1 as the result of the N-point FFT operation.

[0100] The depths of the first data storage unit 21, the fourth data storage unit 24, and the seventh data storage unit 27 are at least 8196 in this embodiment, which is at least twice the maximum FFT point number 4096, and are used for ping-pong reading and writing operations; the depths of the second data storage unit 22, the third data storage unit 23, the fifth data storage unit 25, and the sixth data storage unit 26 are at least 128 in this embodiment, which is twice the maximum value 64 of N1*N2 and N3*N4, and are used for ping-pong reading and writing operations. Through the ping-pong reading and writing operations of the 7 data storage units, the storage and rearrangement of the data to be operated, the storage of the intermediate calculation results, and the storage of the result of the final output N-point FFT operation are completed. Each data path is seamlessly connected, and the reading and writing of each data storage unit are conflict-free through the logical control of the controller 1. In this embodiment, the total depth of the data memory 2 is at least 6.125 times the maximum FFT point number 4096, realizing full pipelining operation with limited storage resources. Among the 4 sub-FFTs in this embodiment, only the storage of the results of the N2-point sub-FFT operation and the N4-point sub-FFT operation respectively after being multiplied by the twiddle factors requires a large storage space with a depth of 8196, and the storage of the results of the N1-point sub-FFT operation and the N3-point sub-FFT operation respectively after being multiplied by the twiddle factors only requires a small storage space with a depth of 128. This is the key to ensuring that the storage resources are controlled within an appropriate range in the case of realizing full pipelining operation in this embodiment.

[0101] The controller 1 is used to receive the configuration information of the external CPU interface, and the configuration information includes the FFT calculation type and the initialization data of the rotation factor table. A lookup table with a depth of 64 is stored in the controller 1, supporting 64 entries, so it supports up to 64 FFT calculation types at most. The value range of the FFT calculation type is any integer from 0 to 63. The controller 1 receives the FFT calculation type configured by the external CPU interface, takes the FFT calculation type as the index (address) of the lookup table, and indexes N, N1, N2, N3, and N4 in the lookup table. There is no need for hardware to calculate N, N1, N2, N3, and N4, which reduces the design complexity. This configuration method is flexible and changeable. It can configure all 64 lookup table entries at one time to support 64 FFT calculation types, and supports using eight sub-FFT operations (1-point, 2-point, 3-point, 4-point, 5-point, 6-point, 8-point, or 9-point FFT operations) to mix and implement various required-point FFT operations under 4G LTE and 5G NR in this embodiment. In this embodiment, the lookup table needs to support 35-point FFT operations of 4G LTE and 5G NR. The first 34 entries of the lookup table can be configured as the FFT calculation types of 4G LTE, the 35th entry can be configured as the FFT calculation type of 5G NR, and the remaining 29 entries can all be configured as 1, indicating that no FFT operation is performed. When using, do not index the entries from 35 to 63. This method of configuring the lookup table means that the current FFT implementation device can support 35 FFT operations. The specific lookup table is shown in Table 1.

[0102] Table 1 Lookup Table

[0103]

[0104]

[0105] After the controller 1 indexes N, N1, N2, N3, and N4 in the lookup table, it sends the FFT point number N and the sub-FFT point numbers N1, N2, N3, and N4 to the data memory 2, the FFT arithmetic unit 3, and the rotation factor memory 5, and configures the data memory 2, the FFT arithmetic unit 3, and the rotation factor memory 5 respectively.

[0106] In addition, the controller 1 sends read enable, write enable, read address, and write address to each data storage unit in the data memory 2, sends a multiplication enable signal to the multiplier 4, sends the initialization data of the rotation factor table to the rotation factor memory 5, and sends read enable and read address to the rotation factor memory 5 to control the rotation factor in the rotation factor memory 5 to be read out to the multiplier 4.

[0107] In this embodiment, the FFT implementation device realizes the FFT operation of the required number of points under the conditions agreed in this embodiment without redundancy by flexibly using 8 sub-FFT operations (1-point, 2-point, 3-point, 4-point, 5-point, 6-point, 8-point or 9-point) and the lookup table with 64 entries in the controller 1, and by means of the ping-pong read-write operation of 7 data storage units in the data memory 2, instead of first implementing the FFT operation with the number of points being a power of 2 and then completing the FFT operation with the supported number of points under 4G LTE and 5G NR by padding with zeros.

[0108] The data memory 2, the FFT arithmetic unit 3 and the multiplier 4 can be implemented in a pipelined manner when implemented with a chip, so that the overall FFT implementation device is a pipelined device. Therefore, the FFT implementation device described in this embodiment can control the FFT operation speed by changing the bit width of the input data to be operated and the clock supported by the system when implemented with a digital chip, so as to adapt to the FFT operation speed required by various communication systems.

[0109] Embodiment 3:

[0110] This embodiment discloses an FFT implementation method for a communication system, including the following steps:

[0111] The controller 1 initializes the data memory 2, the FFT arithmetic unit 3 and the rotation factor memory 5 according to the FFT number of points required by the communication system and the sub-FFT number of points of each sub-FFT calculation unit when implementing the FFT number of points;

[0112] The first sub-FFT calculation unit reads the data to be operated from the data memory 2, performs the sub-FFT operation of the corresponding sub-FFT number of points on the data to be operated to obtain a result, inputs the result into the multiplier 4, inputs the rotation factor in the rotation factor memory 5 into the multiplier 4, performs a complex multiplication operation on the result and the rotation factor in the multiplier 4 to obtain the first sub-FFT iteration result, and stores the first sub-FFT iteration result in the data memory 2;

[0113] The next sub-FFT calculation unit reads the current sub-FFT iteration result from the data memory 2, performs a sub-FFT operation with the corresponding number of sub-FFT points on the current sub-FFT iteration result to obtain the next result, inputs the next result into the multiplier 4, inputs the rotation factor from the rotation factor memory 5 into the multiplier 4, performs a complex multiplication operation on the next result and the rotation factor in the multiplier 4 to obtain the next sub-FFT iteration result, and stores the next sub-FFT iteration result in the data memory 2; repeat the above process until the last sub-FFT calculation unit reads the previous sub-FFT iteration result from the data memory 2, performs a sub-FFT operation with the corresponding number of sub-FFT points on the previous sub-FFT iteration result to obtain the last sub-FFT iteration result, and stores the last sub-FFT iteration result in the data memory 2;

[0114] Read the last sub-FFT iteration result from the data memory 2 as the FFT operation result with the number of FFT points required by the communication system.

[0115] Furthermore, a lookup table is stored in the controller 1. The controller 1 indexes from the lookup table to obtain the number of FFT points required by the communication system and the number of sub-FFT points of each sub-FFT calculation unit when implementing the number of FFT points.

[0116] Embodiment 4:

[0117] Based on the FFT implementation device described in Embodiment 2, this embodiment proposes an FFT implementation method for a communication system, including the following steps:

[0118] Step 1: Initialize the FFT implementation device according to the required number of FFT points N, including:

[0119] Step 101: Input the FFT calculation type into the controller 1. The controller 1 uses the FFT calculation type as the index of the lookup table in the controller 1 and reads out the number of FFT points N and the 4 sub-FFT points N1, N2, N3, and N4 from the lookup table. Among them, the lookup table in the controller 1 is pre-configured by an external CPU according to the CPU interface provided by the controller 1.

[0120] Specifically, the value range of the FFT calculation type is any integer from 0 to 63. The controller 1 reads the content of the lookup table using the input FFT calculation type as the index (address) of the lookup table, and obtains N, N1, N2, N3, and N4. Then, the controller 1 transfers N, N1, N2, N3, and N4 to the data memory 2, the FFT arithmetic unit 3, and the twiddle factor memory 5. Among them, N1 is transferred to the first sub-FFT calculation unit 31, N2 is transferred to the second sub-FFT calculation unit 32, N3 is transferred to the third sub-FFT calculation unit 33, and N4 is transferred to the fourth sub-FFT calculation unit 34.

[0121] Step 102: The CPU externally connected to the FFT implementation device initializes the twiddle factor tables in the three twiddle factor storage units in the twiddle factor memory 5 through the CPU interface provided by the controller 1.

[0122] Specifically, the externally connected CPU can calculate the specific twiddle factors in the three twiddle factor tables based on N, N1, N2, N3, and N4, and then write the twiddle factors into the three twiddle factor tables in the twiddle factor memory 5 through the controller 1 to complete the initialization of the three twiddle factor tables. When locating a fault, the externally connected CPU can read the data of the three twiddle factor tables through the CPU interface of the controller 1 to determine whether the three twiddle factor tables are initialized successfully.

[0123] Through steps 101 to 102, the initialization of the FFT implementation device in this embodiment is completed.

[0124] Before specifically introducing the subsequent operation steps of this embodiment, first introduce the read process and write process of the seven data storage units in the data memory 2 and the read process of the three twiddle factor storage units in the twiddle factor memory 5. Define data_mem_write and data_mem_read to illustrate the write process and read process of the seven data storage units respectively, and define twiddle_mem_read to illustrate the read process of the three twiddle factor storage units respectively.

[0125] Define the general write process data_mem_write for each data storage unit in the data memory 2 as:

[0126] data_mem_write(MEM_DEPTH1, VALID1, SWITCH_SIZE)

[0127] The inputs include: the depth MEM_DEPTH1 of the current data storage unit; the indication signal VALID1 indicating whether the current written data is valid; the maximum space SWITCH_SIZE for the ping-pong operation switching of the current data storage unit

[0128] The outputs include: write enable wr_enable; write address wr_addr

[0129] Specifically:

[0130] (1) When VALID1 is FALSE, that is, when the indication signal is invalid, no write enable is generated, that is, wr_enable = FALSE;

[0131] When VALID1 is TRUE, that is, when the indication signal is valid, a write enable is generated, that is, wr_enable = TRUE, and the write address wr_addr starts from 0 and increments by 1 step each time a write is performed;

[0132] (2) When the write address wr_addr is greater than SWITCH_SIZE - 1, the write address wr_addr becomes MEM_DPETH1 / 2, and then the write address wr_addr starts from MEM_DPETH1 / 2 and increments by 1 step each time a write is performed;

[0133] (3) When the write address wr_addr is greater than MEM_DEPTH1 / 2 + SWITCH_SIZE - 1, the write address wr_addr becomes 0, and returns to (1) to continue writing data.

[0134] Define the general read process data_mem_read for each data storage unit in data memory 2 as:

[0135] data_mem_read(MEM_DEPTH1, BURST_SIZE, STEP)

[0136] The inputs include: the depth MEM_DEPTH1 of the current data storage unit; the size BURST_SIZE of continuous burst reads of the current data storage unit. When the number of data stored in the data storage unit reaches BURST_SIZE, BURST_SIZE data are continuously read out; the size STEP by which the read address increments each time a read is performed

[0137] The outputs include: read enable rd_enable; read address rd_addr

[0138] Specifically:

[0139] (1) When the number of data stored in the data storage unit is BURST_SIZE, a read enable rd_enable is generated, that is, rd_enable = TRUE, the starting address start_addr1 is 0, and the read address rd_addr starts from start_addr1 and the read address rd_addr increases by STEP each time a read is performed;

[0140] (2) When the read address rd_addr is greater than BURST_SIZE - 1, the starting address start_addr1 is incremented by 1. The read address rd_addr starts from start_addr1, and each time a read is performed, the read address rd_addr is incremented by STEP;

[0141] (3) Repeat (2) until BURST_SIZE data are read, then change the starting address start_addr1 = MEM_DPETH1 / 2;

[0142] (4) Repeat (1)(2)(3) until BURST_SIZE data are read again, then change the starting address start_addr1 = 0, and sequentially repeat (1)(2)(3)(4) to continue reading data.

[0143] Define the general read process twiddle_mem_read for each twiddle factor storage unit in the twiddle factor memory 2 as:

[0144] twiddle_mem_read(MEM_DEPTH2, VALID2, STEP)

[0145] The inputs include: the depth MEM_DEPTH2 of the current twiddle factor memory; the enable indication signal VALID2 for reading the twiddle factor; the size STEP by which the read address is incremented each time a read is performed

[0146] The outputs include: the read enable tw_rd_enable; the read address tw_rd_addr

[0147] Specifically:

[0148] (1) When VALID2 is FALSE, no read enable is generated, i.e., tw_rd_enable = FALSE;

[0149] When VALID2 = TRUE, a read enable tw_rd_enable is generated, i.e., tw_rd_enable = TRUE. The starting address tw_start_addr is 0, and the read address tw_rd_addr starts from tw_start_addr. Each time a read is performed, the read address tw_rd_addr is incremented by STEP;

[0150] (2) When the read address rd_addr is greater than MEM_DEPTH - 1, the starting address tw_start_addr is incremented by 1. The read address tw_rd_addr starts from tw_start_addr, and each time a read is performed, the read address tw_rd_addr is incremented by STEP.

[0151] The calculation result obtained by performing complex multiplication on the output of the first sub-FFT calculation unit 31, i.e., the result of the N1-point sub-FFT operation, and the rotation factor output by the first rotation factor storage unit 51 is referred to as the first sub-FFT iteration result; the calculation result obtained by performing complex multiplication on the output of the second sub-FFT calculation unit 32, i.e., the result of the N2-point sub-FFT operation, and the rotation factor output by the second rotation factor storage unit 52 is referred to as the second sub-FFT iteration result; the calculation result obtained by performing complex multiplication on the output of the third sub-FFT calculation unit 33, i.e., the result of the N3-point sub-FFT operation, and the rotation factor output by the third rotation factor storage unit 53 is referred to as the third sub-FFT iteration result; the output of the fourth sub-FFT calculation unit 34, i.e., the result of the N4-point sub-FFT operation is referred to as the fourth sub-FFT operation result.

[0152] Step 2: The controller 1 controls the data to be operated to perform the N1-point sub-FFT operation and stores the first sub-FFT iteration result in the third storage unit 23. This step is described in detail in 201 to 206:

[0153] Step 201: The controller 1 controls the valid input data to be written into the first data storage unit 21 according to the indication signal of whether the input data is valid, to obtain the data to be operated.

[0154] Specifically, the controller 1 controls the valid input data to be written into the first data storage unit 21 by controlling the write enable and write address of the first data storage unit 21, and the write enable and write address are obtained through the following writing process:

[0155] data_mem_write(8192, “indication signal of whether the input data is valid”, N)

[0156] Among them, 8192 is the depth of the first data storage unit 21, and N is the maximum space for the ping-pong operation switching of the first data storage unit 21.

[0157] Step 202: The controller 1 reads the data to be operated from the first data storage unit 21 and writes it into the second data storage unit 22.

[0158] Specifically, the controller 1 reads the data to be operated from the first data storage unit 21 by controlling the read enable and read address of the first data storage unit 21, and the read enable and read address are obtained through the following reading process:

[0159] data_mem_read(8192, N, N3 * N4)

[0160] Among them, 8192 is the depth of the first data storage unit 21, N is the size of consecutive burst reads of the first data storage unit 21, and N3*N4 is the size by which the read address increments each time a read is performed.

[0161] Specifically, the controller 1 controls the data read out from the first data storage unit 21 to be written into the second data storage unit 22, which is completed by controlling the write enable and write address of the second data storage unit 22. The write enable and write address are obtained through the following write process:

[0162] data_mem_write(128, "Whether the data read from the first data storage unit 21 is valid", N1*N2)

[0163] Among them, 128 is the depth of the second data storage unit 22, "Whether the data read from the first data storage unit 21 is valid" is an indication signal for whether the data written to the second data storage unit 22 is valid. If the first data storage unit 21 has data output, it means that the data read from the first data storage unit 21 is valid, and N1*N2 is the maximum space for the ping-pong operation switching of the second data storage unit 22.

[0164] Step 203: The controller 1 reads out the data in the second data storage unit 22 and transmits it to the first sub-FFT calculation unit 31.

[0165] Specifically, the controller 1 reads out the data in the second data storage unit 22, which is completed by the controller 1 generating the read enable and read address of the second data storage unit 22. The read enable and read address are obtained through the following read process:

[0166] data_mem_read(128, N1*N2, N2)

[0167] Among them, 128 is the depth of the second data storage unit 22, N1*N2 represents the size of consecutive burst reads of the second data storage unit 22, and N2 represents the size by which the read address increments each time a read is performed.

[0168] Then the controller 1 transmits the data read out from the second data storage unit 22 to the first sub-FFT calculation unit 31.

[0169] The controller 1 writes data into and reads data from the first data storage unit 21 and the second data storage unit 22 to achieve the effect of rearranging every N data to be calculated, and to prepare for performing N1-point FFT operations N2*N3*N4 times on every N data to be calculated. If only the first data storage unit 21 is used for rearrangement, the read address generated by the controller 1 has a complex logic and requires secondary processing, and the general read process defined above cannot be used. Therefore, in order to make the read process of the controller 1 consistent and facilitate simple design, a second data storage unit 22 with a depth of 128 is introduced as an intermediate storage, and the idea of using storage resources to simplify the logic complexity is used to simplify the design.

[0170] Step 204: The first sub-FFT calculation unit 31 receives the data output by the second data storage unit 22 and completes the N1-point FFT operation.

[0171] Step 205: The controller 1 transmits the output of the first sub-FFT calculation unit 31 and the twiddle factor output by the first twiddle factor storage unit 51 to the first complex multiplication unit 41 for complex multiplication.

[0172] Specifically, every time the first sub-FFT calculation unit 31 outputs a valid piece of data, the controller 1 reads a twiddle factor from the first twiddle factor storage unit 51 as the output of the first twiddle factor storage unit 51.

[0173] Specifically, the controller 1 reads a twiddle factor from the first twiddle factor storage unit 51, which is completed by controlling the read enable and read address of the first twiddle factor storage unit 51. The read enable and read address are obtained through the following read process:

[0174] twiddle_mem_read(64, "Whether the data output by the first sub-FFT calculation unit 31 is valid", N2)

[0175] Among them, 64 is the depth of the first twiddle factor storage unit 51, "Whether the data output by the first sub-FFT calculation unit 31 is valid" is the enable indication signal for reading the twiddle factor of the first twiddle factor storage unit 51. If the first sub-FFT calculation unit 31 has data output, it means that the data output by the first sub-FFT calculation unit 31 is valid, and N2 represents the size of the read address increment for each read.

[0176] Step 206: The controller 1 stores the output of the first complex multiplication unit 41 into the third data storage unit 23.

[0177] Specifically, the controller 1 stores the output of the first complex multiplication unit 41 into the third data storage unit 23, which is completed by controlling the write enable and write address of the third data storage unit 23. The write enable and write address are obtained through the following write process:

[0178] data_mem_write(128, "Whether the data output by the first complex multiplication unit 41 is valid", N1 * N2)

[0179] Among them, 128 is the depth of the third data storage unit 23, "Whether the data output by the first complex multiplication unit 41 is valid" is the indication signal for whether the data written to the third data storage unit 23 is valid. If the first complex multiplication unit 41 has data output, it means that the data output by the first complex multiplication unit 41 is valid, and N1 * N2 is the maximum space for the ping-pong operation switching of the third data storage unit 23.

[0180] Complete the N1-point FFT operation through steps 201 to 206 and store the first sub-FFT iteration result in the third data storage unit 23.

[0181] Step 3: The controller 1 controls the first sub-FFT iteration result to perform the N2-point FFT operation and stores the second sub-FFT iteration result in the fourth data storage unit 24. This step is described in detail in 301 to 304:

[0182] Step 301: The controller 1 reads the first sub-FFT iteration result from the third data storage unit 23 and outputs it to the second sub-FFT calculation unit 32.

[0183] Specifically, the controller 1 reads the first sub-FFT iteration result from the third data storage unit 23 by controlling the read enable and read address of the third data storage unit 23. The read enable and read address are obtained through the following read process:

[0184] data_mem_read(128, N1 * N2, N1)

[0185] Among them, 128 is the depth of the third data storage unit 23, N1 * N2 is the size of the continuous burst read of the third data storage unit 23, and N1 is the size by which the read address increases each time a read is performed.

[0186] The controller 1 writes and reads the first sub-FFT iteration result from the third data storage unit 23 to achieve the effect of rearranging every N1 * N2 first sub-FFT iteration results, and to prepare for performing the N1-time N2-point FFT operation on every N1 * N2 first sub-FFT iteration results.

[0187] Step 302: The second sub-FFT calculation unit 32 receives the data output by the third data storage unit 23 and completes the N2-point FFT operation.

[0188] Step 303: The controller 1 transmits the output of the second sub-FFT calculation unit 32 and the rotation factor output by the second rotation factor storage unit 52 to the second complex multiplication unit 42 for complex multiplication.

[0189] Specifically, every time the second sub-FFT calculation unit 32 outputs a valid piece of data, the controller 1 reads out a twiddle factor from the second twiddle factor storage unit 52 as the output of the second twiddle factor storage unit 52.

[0190] Specifically, the controller 1 reads out a twiddle factor from the second twiddle factor storage unit 52 by controlling the read enable and read address of the second twiddle factor storage unit 52. The read enable and read address are obtained through the following read process:

[0191] twiddle_mem_read(4096, "Whether the data output by the second sub-FFT calculation unit 32 is valid", N3 * N4)

[0192] Among them, 4096 is the depth of the second twiddle factor storage unit 52, "Whether the data output by the second sub-FFT calculation unit 32 is valid" is the enable indication signal for reading the twiddle factor of the second twiddle factor storage unit 52. If the second sub-FFT calculation unit 32 has data output, it means the data output by the second sub-FFT calculation unit 32 is valid, and N3 * N4 represents the size of the increment of the read address for each read.

[0193] Step 304: The controller 1 stores the output of the second complex multiplication unit 42 into the fourth data storage unit 24.

[0194] Specifically, the controller 1 stores the output of the second complex multiplication unit 42 into the fourth data storage unit 24 by controlling the write enable and write address of the fourth data storage unit. The write enable and write address are obtained through the following write process:

[0195] data_mem_write(8192, "Whether the data output by the second complex multiplier 42 is valid", N)

[0196] Among them, 8192 is the depth of the fourth data storage unit 24, "Whether the data output by the second complex multiplier 42 is valid" is the indication signal for whether the data written to the fourth data storage unit 24 is valid. If the second complex multiplier 42 has data output, it means the data output by the second complex multiplier 42 is valid, and N is the maximum space for the ping-pong operation switching of the fourth data storage unit 24.

[0197] Through steps 301 to 304, the N2-point FFT operation is completed and the result of the second sub-FFT iteration is stored in the fourth data storage unit 24.

[0198] Step 4: The controller 1 controls the second sub-FFT iteration result to perform an N3-point sub-FFT operation and stores the third sub-FFT iteration result in the sixth data storage unit 26. This step is described in detail in 401-405:

[0199] Step 401: The controller 1 reads the second sub-FFT iteration result from the fourth data storage unit 24 and writes it into the fifth data storage unit 25.

[0200] Specifically, the controller 1 reads the second sub-FFT iteration result from the fourth data storage unit 24, which is completed by controlling the read enable and read address of the fourth data storage unit 24. The read enable and read address are obtained through the following read process:

[0201] data_mem_read(8192, N, N1*N2)

[0202] Among them, 8192 is the depth of the fourth data storage unit 24, N is the size of continuous burst reads of the fourth data storage unit 24, and N1*N2 is the size by which the read address increases each time a read is performed.

[0203] Specifically, the controller 1 controls the data read from the fourth data storage unit 24 to be written into the fifth data storage unit 25, which is completed by controlling the write enable and write address of the fifth data storage unit 25. The write enable and write address are obtained through the following write process:

[0204] data_mem_write(128, “Whether the data read from the fourth data storage unit 24 is valid”, N3*N4)

[0205] Among them, 128 is the depth of the fifth data storage unit 25, “Whether the data read from the fourth data storage unit 24 is valid” is the indication signal for whether the data written into the fifth data storage unit 25 is valid. If the fourth data storage unit 24 has data output, it means that the data read from the fourth data storage unit 24 is valid, and N3*N4 is the maximum space for ping-pong operation switching in the fifth data storage unit 25.

[0206] Step 402: The controller 1 reads the second FFT iteration data in the fifth storage unit 25 and transmits it to the third sub-FFT calculation unit 33.

[0207] Specifically, the controller 1 reads the second sub-FFT iteration data in the fifth storage unit 25, which is completed by the controller 1 generating the read enable and read address of the fifth data storage unit 25. The read enable and read address are obtained through the following read process:

[0208] data_mem_read(128, N3*N4, N4)

[0209] Among them, 128 is the depth of the fifth data storage unit 25, N3*N4 represents the size of consecutive burst reads of the fifth data storage unit 25, and N4 represents the size of the read address increment for each read.

[0210] Then the controller 1 transfers the data read from the fifth data storage unit 25 to the third sub-FFT calculation unit 33.

[0211] The controller 1 writes and reads the second sub-FFT iteration results to and from the fourth data storage unit 24 and the fifth data storage unit 25 to achieve the effect of rearranging every N second sub-FFT iteration results, and to prepare for performing N3-point FFT operations on every N second sub-FFT iteration results N1*N2*N4 times. If only the fourth data storage unit 24 is used for storage and rearrangement, the read address generation logic of the controller 1 is complex and requires secondary processing, and the general read process defined above cannot be used. Therefore, in order to make the read process of the controller 1 consistent and facilitate simple design, a fifth data storage unit 25 with a depth of 128 is introduced as an intermediate storage, using the idea of simplifying the logic complexity by using storage resources to simplify the design.

[0212] Step 403: The third sub-FFT calculation unit 33 receives the data output from the fifth data storage unit 25 and completes the N3-point FFT operation.

[0213] Step 404: The controller 1 transfers the output of the third sub-FFT calculation unit 33 and the twiddle factor output from the third twiddle factor storage unit 53 to the third complex multiplication unit 43 for complex multiplication.

[0214] Specifically, for each valid data output by the third sub-FFT calculation unit 33, the controller 1 reads a twiddle factor from the third twiddle factor storage unit 53 as the output of the third twiddle factor storage unit 53.

[0215] Specifically, the controller 1 reads a twiddle factor from the third twiddle factor storage unit 53, which is completed by controlling the read enable and read address of the third twiddle factor storage unit 53. The read enable and read address are obtained through the following read process:

[0216] twiddle_mem_read(64, "Whether the data output by the third sub-FFT calculation unit 33 is valid", N4)

[0217] Among them, 64 is the depth of the third twiddle factor storage unit 53, "Whether the data output by the third sub-FFT calculation unit 33 is valid" is the enable indication signal for reading the twiddle factor of the third twiddle factor storage unit 53. If the third sub-FFT calculation unit 33 has data output, it means that the data output by the third sub-FFT calculation unit 33 is valid, and N4 represents the size of the read address increment for each read.

[0218] Step 405: The controller 1 stores the output of the third complex multiplication unit 43 into the sixth data storage unit 26.

[0219] Specifically, the controller 1 stores the output of the third complex multiplication unit 43 into the sixth data storage unit 26 by controlling the write enable and write address of the sixth data storage unit 26. The write enable and write address are obtained through the following writing process:

[0220] data_mem_write(128, "Whether the data output by the third complex multiplication unit 43 is valid", N3 * N4)

[0221] Among them, 128 is the depth of the sixth data storage unit 26, "Whether the data output by the third complex multiplication unit 43 is valid" is the indication signal of whether the data written to the sixth data storage unit 26 is valid. If the third complex multiplication unit 43 has data output, it means that the data output by the third complex multiplication unit 43 is valid, and N3 * N4 is the maximum space for the ping-pong operation switching of the sixth data storage unit 26.

[0222] Through steps 401 to 405, the N3-point sub-FFT operation is completed and the result of the third sub-FFT iteration is stored in the sixth data storage unit 26.

[0223] Step Five: The controller 1 controls the result of the third sub-FFT iteration to perform the N4-point sub-FFT operation and stores the result of the fourth sub-FFT iteration in the seventh data storage unit 27, and is read out in order by the controller 1, which is the final result of the N-point FFT operation of the data to be operated. This step is described in detail in 501 to 504:

[0224] Step 501: The controller 1 reads out the result of the third sub-FFT iteration in the sixth data storage unit 26 and transmits it to the fourth sub-FFT calculation unit 34.

[0225] Specifically, the controller 1 reads out the result of the third iteration in the sixth data storage unit 26 by generating the read enable and read address of the sixth data storage unit 26 by the controller 1. The read enable and read address are obtained through the following reading process:

[0226] data_mem_read(128, N3 * N4, N3)

[0227] Among them, 128 is the depth of the sixth data storage unit 26, N3 * N4 represents the size of the continuous burst read of the sixth data storage unit 26, and N3 represents the size of the read address increment for each read.

[0228] Then the controller 1 transmits the data read from the sixth data storage unit 26 to the fourth sub-FFT calculation unit 34.

[0229] The controller 1 writes the result of the third sub-FFT iteration into and reads out the sixth data storage unit 26 to achieve the effect of rearranging every N3*N4 results of the third sub-FFT iteration, and to prepare for performing N3 N4-point sub-FFT operations on every N3*N4 results of the third sub-FFT iteration.

[0230] Step 502: The fourth sub-FFT calculation unit 34 receives the data output by the sixth data storage unit 26 and completes the N4-point sub-FFT operation.

[0231] Step 503: The result of the fourth sub-FFT iteration does not perform complex multiplication and is directly transmitted from the fourth sub-FFT calculation unit 34 to the data memory 2 and written into the seventh data storage unit 27 under the control of the controller 1.

[0232] Specifically, the controller 1 writes the result of the fourth sub-FFT iteration into the seventh data storage unit 27 by controlling the write enable and write address of the seventh data storage unit 27. The write enable and write address are obtained through the following write process:

[0233] data_mem_write(8192, “Whether the data output by the fourth sub-FFT calculation unit 34 is valid”, N)

[0234] Among them, 8192 is the depth of the seventh data storage unit 27, “Whether the data output by the fourth sub-FFT calculation unit 34 is valid” is the indication signal for whether the data written into the seventh data storage unit 27 is valid. If the fourth sub-FFT calculation unit 34 has data output, it means that the data output by the fourth sub-FFT calculation unit 34 is valid, and N is the maximum space for the ping-pong operation switching of the seventh data storage unit 27.

[0235] Step 504: The controller 1 reads out the result of the fourth sub-FFT iteration from the seventh data storage unit 27 as the final result of the N-point FFT operation of the data to be operated.

[0236] Specifically, after performing 4 sub-FFT operations, the result of the N-point FFT operation has been obtained. However, due to the disorder of the calculation of the result of the N-point FFT operation, an output with ordered sequence is required. Therefore, the result of the N-point FFT operation is first stored in the seventh data storage unit 27, and then the controller 1 controls the read enable and read address of the seventh data storage unit 27 to read out the result of the N-point FFT operation from the seventh data storage unit 27 with ordered sequence.

[0237] Specifically, the reading out of the result of the N-point FFT operation from the seventh data storage unit 27 is completed by the controller 1 by controlling the read enable and read address of the seventh data storage unit 27. The read enable and read address are obtained through the following read process:

[0238] data_mem_read(8192, N, N3*N4)

[0239] Among them, 8196 is the depth of the seventh data storage unit 27, N represents the size of continuous burst read of the seventh data storage unit 27, and N3*N4 represents the size of the read address increment for each read.

[0240] The read result is the final result of the N-point FFT operation of the data to be operated.

[0241] The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. An FFT implementation device for a communication system, characterized in that, It includes a controller (1), a data memory (2), an FFT arithmetic unit (3), a multiplier (4), and a twiddle factor memory (5), where: The FFT arithmetic unit (3) includes a number of sub-FFT calculation units corresponding to a set of preset sub-FFT point numbers. The inputs of all sub-FFT calculation units are connected to the data memory (2). The output of the last sub-FFT calculation unit is connected to the data memory (2). The outputs of the remaining sub-FFT calculation units are connected to the multiplier (4). Each sub-FFT calculation unit is used to implement the sub-FFT operation of any one of the sub-FFT point numbers in the set of preset sub-FFT point numbers. The product of the sub-FFT point numbers of all sub-FFT calculation units is equal to the FFT point number required by the communication system. The set of preset sub-FFT point numbers is {1, 2, 3, 4, 5, 6, 8, 9}; The twiddle factor memory (5) is used to store twiddle factors; The multiplier (4) is connected to the twiddle factor memory (5) and is used to perform complex multiplication operations on the output of each sub-FFT calculation unit connected to it and the twiddle factors in the twiddle factor memory (5); The data memory (2) is connected to the multiplier (4) and is used to store the outputs of the sub-FFT calculation units and the multiplier (4) connected to it; The controller (1) is respectively connected to the data memory (2), the FFT arithmetic unit (3), the multiplier (4), and the twiddle factor memory (5), and is used to configure the data memory (2), the FFT arithmetic unit (3), and the twiddle factor memory (5), and to control the data memory (2), the FFT arithmetic unit (3), the multiplier (4), and the twiddle factor memory (5).

2. The FFT implementation device for a communication system according to claim 1, wherein, The FFT arithmetic unit (3) includes a first sub-FFT calculation unit (31), a second sub-FFT calculation unit (32), a third sub-FFT calculation unit (33), and a fourth sub-FFT calculation unit (34); The twiddle factor memory (5) includes a first twiddle factor storage unit (51), a second twiddle factor storage unit (52), and a third twiddle factor storage unit (53); The multiplier (4) includes a first complex multiplication unit (41), a second complex multiplication unit (42), and a third complex multiplication unit (43), where: The first complex multiplication unit (41) is connected to the first sub-FFT calculation unit (31) and the first twiddle factor storage unit (51). The second complex multiplication unit (42) is connected to the second sub-FFT calculation unit (32) and the second twiddle factor storage unit (52). The third complex multiplication unit (43) is connected to the third sub-FFT calculation unit (33) and the third twiddle factor storage unit (53); The data memory (2) includes a first data storage unit (21), a second data storage unit (22), a third data storage unit (23), a fourth data storage unit (24), a fifth data storage unit (25), a sixth data storage unit (26), and a seventh data storage unit (27), where: the second data storage unit (22) is connected to the first data storage unit (21) and the first sub-FFT calculation unit (31), the third data storage unit (23) is connected to the first complex multiplication unit (41) and the second sub-FFT calculation unit (32), the fourth data storage unit (24) is connected to the second complex multiplication unit (42) and the fifth data storage unit (25), the fifth data storage unit (25) is connected to the fourth data storage unit (24) and the third sub-FFT calculation unit (33), the sixth data storage unit (26) is connected to the third complex multiplication unit (43) and the fourth sub-FFT calculation unit (34), and the seventh data storage unit (27) is connected to the fourth sub-FFT calculation unit (34).

3. The FFT implementation device for a communication system according to claim 2, wherein The product of the number of sub-FFT points of the first sub-FFT calculation unit (31) and the number of sub-FFT points of the second sub-FFT calculation unit (32) is less than or equal to the first threshold, and the product of the number of sub-FFT points of the third sub-FFT calculation unit (33) and the number of sub-FFT points of the fourth sub-FFT calculation unit (34) is less than or equal to the second threshold. The product of the first threshold and the second threshold is equal to the maximum number of FFT points required by the communication system.

4. The FFT implementation device for a communication system according to claim 3, characterized in that, The depth of the first rotation factor storage unit (51) is at least the first threshold; The depth of the second rotation factor storage unit (52) is at least the product of the first threshold and the second threshold; The depth of the third rotation factor storage unit (53) is at least the second threshold.

5. The FFT implementation device for a communication system according to claim 3, wherein The depths of the first data storage unit (21), the fourth data storage unit (24), and the seventh data storage unit (27) are all at least twice the product of the first threshold and the second threshold; The depths of the second data storage unit (22) and the third data storage unit (23) are at least twice the first threshold; The depths of the fifth data storage unit (25) and the sixth data storage unit (26) are at least twice the second threshold.

6. The FFT implementation device for a communication system according to claim 1 or 2, characterized in that, The rotation factor memory (5) is implemented using RAM.

7. The FFT implementation device for a communication system according to claim 1 or 2, characterized in that, The controller (1) stores a lookup table, which includes several entries. Each entry includes the number of FFT points required by the communication system and the corresponding number of sub-FFT points of each sub-FFT calculation unit when implementing the number of FFT points.

8. A method for implementing FFT in a communication system, characterized in that, Including the following steps: The controller (1) initializes the data memory (2), the FFT arithmetic unit (3), and the rotation factor memory (5) according to the number of FFT points required by the communication system and the number of sub-FFT points of each sub-FFT calculation unit when implementing the number of FFT points; sets the set of sub-FFT points as {1, 2, 3, 4, 5, 6, 8, 9}; The first sub-FFT calculation unit reads the data to be operated from the data memory (2), performs a sub-FFT operation on the data to be operated with the corresponding number of sub-FFT points to obtain a result, inputs the result into the multiplier (4), inputs the rotation factor from the rotation factor memory (5) into the multiplier (4), performs a complex multiplication operation on the result and the rotation factor in the multiplier (4) to obtain the first sub-FFT iteration result, and stores the first sub-FFT iteration result in the data memory (2); The next sub-FFT calculation unit reads the current sub-FFT iteration result from the data memory (2), performs a sub-FFT operation on the current sub-FFT iteration result with the corresponding number of sub-FFT points to obtain the next result, inputs the next result into the multiplier (4), inputs the rotation factor from the rotation factor memory (5) into the multiplier (4), performs a complex multiplication operation on the next result and the rotation factor in the multiplier (4) to obtain the next sub-FFT iteration result, and stores the next sub-FFT iteration result in the data memory (2); Repeat the above process until the last sub-FFT calculation unit reads the previous sub-FFT iteration result from the data memory (2), performs a sub-FFT operation on the previous sub-FFT iteration result with the corresponding number of sub-FFT points to obtain the last sub-FFT iteration result, and stores the last sub-FFT iteration result in the data memory (2); Read the last sub-FFT iteration result from the data memory (2) as the FFT operation result corresponding to the required number of FFT points.

9. A method for implementing FFT in a communication system according to claim 8, characterized in that, A lookup table is stored in the controller (1), and the controller (1) indexes from the lookup table to obtain the number of FFT points required by the communication system and the number of sub-FFT points of each sub-FFT calculation unit when implementing the number of FFT points.

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