Method for determining flash FPGA threshold voltage using readout circuit

Abstract

The present invention discloses a method for determining the threshold voltage of a flash-type FPGA using a readout circuit, and relates to the field of flash-type FPGAs. The method applies a gate voltage corresponding to a configuration operation to the gate of a flash switch unit, and a read current-to-voltage module applies a constant reference voltage to its drain terminal, thereby outputting a first voltage related to the current flowing through the flash switch unit to ground. The first voltage is compared with the second voltage output by the reference power supply-to-voltage module, thereby accurately reading the readout current of the flash switch unit, thereby enabling accurate judgment of the threshold voltage of the flash switch unit after erasure and programming, thereby providing a basis for the system control circuit to adjust the threshold voltage, ensuring the consistency of the threshold voltage distribution after erasure and programming, and providing high-precision delay parameters for the superior programmability of the flash-type FPGA.

Description

Technical Field

[0001] The present invention relates to the field of flash type FPGAs, and in particular to a method for determining the threshold voltage of a flash type FPGA by using a readout circuit. Background Art

[0002] A flash type FPGA is a programmable logic circuit based on flash memory technology. A programmable wiring switch matrix is composed of flash switch units (flash cells). Signals are input and output from the source and drain of the flash switch unit respectively. As Figure 1 shown, the dashed box is a flash switch unit. By configuring the flash switch unit, different paths of the flash switch unit are selected, thereby realizing the programmable logic function of the user.

[0003] After programming the flash switch unit, electrons enter the floating gate, and the threshold voltage of the flash switch unit becomes higher; after erasing the flash switch unit, the electrons are driven out of the floating gate, and the threshold voltage of the flash switch unit becomes higher. When the voltage V of the gate is greater than Vth, it shows a logic level of 1. For a P-type device, it will be turned off, and for an N-type device, it will be turned on. When the voltage V of the gate is less than Vth, it shows a logic level of 0. For a P-type device, it will be turned on, and for an N-type device, it will be turned off. Since the flash switch unit belongs to non-volatile memory, when the circuit is powered off and then powered on again, the electron state in the floating gate of the flash switch unit remains unchanged, and the conduction state of the flash switch unit remains unchanged. There is no need to reload data from the peripheral configuration chip like an SRAM type FPGA. Therefore, the flash type FPGA has a fast startup speed, and the circuit can quickly enter the working state after power-on. So it has become the mainstream of programmable logic devices and is widely used in the fields of signal processing and control.

[0004] Since the wiring switch matrix in the flash type FPGA is realized by flash switch units, the consistency of the driving capabilities of the flash switch units after erasing and programming is the premise and foundation for the layout and wiring of EDA software. For a flash type FPGA with a working frequency of 350 MHz, the driving capability requirement of the flash switch unit is a current of 200 μA, and the driving capability difference of each flash switch unit is within 5% and 10 μA of the current. The driving capability of the flash switch unit is evaluated and measured by the threshold voltage distribution of the flash switch unit after erasing and programming. Moreover, the threshold voltage distribution of the flash switch units in the flash type FPGA has more stringent requirements than that of a flash memory used solely for information storage. As Figure 2As shown, the threshold voltage distribution range of the flash switch cells that are programmed to be turned on in a flash FPGA is shown as 210, and the threshold voltage distribution range of the flash switch cells that do not need to be programmed to be turned on and remain in an erased closed state is shown as 220. In a flash memory, the threshold voltage distribution range of the flash switch cells that are programmed to be turned on is shown as 230, and the threshold voltage distribution range of the flash switch cells that do not need to be programmed to be turned on and remain in an erased closed state is shown as 240. In a flash FPGA, the minimum threshold voltage HL_Vth of the flash cells that are programmed to be turned on must ensure that the driving signal capability meets the requirements, while also ensuring that the threshold voltage distribution range HL_Vth to HH_Vth is as narrow as possible. The maximum threshold voltage LH_Vth of each flash cell that does not need to be programmed to be turned on and remain in an erased closed state must ensure that the leakage current between the source and drain is below the nanoamp level, thereby reducing the power consumption of the flash FPGA. Therefore, determining the threshold voltage of the flash switch cells after erasure and programming, and thus adjusting the threshold voltage distribution, becomes a key point in optimizing the performance of the flash FPGA. Summary of the Invention

[0005] In response to the above problems and technical requirements, the inventors have proposed a method for determining the threshold voltage of a flash FPGA using a readout circuit. The technical solution of the present invention is as follows:

[0006] A method for determining a flash type FPGA threshold voltage using a readout circuit, the readout circuit comprising a read current to voltage module, a reference power supply to voltage module, and a comparison module;

[0007] The read current-to-voltage module includes a first transimpedance amplifier and a constant voltage source. The non-inverting input of the first transimpedance amplifier is connected to the reference voltage Vref, and the inverting input is connected to the drain of the flash switch unit. The source of the flash switch unit is grounded, and the gate obtains the gate voltage. The input of the constant voltage source is connected to the reference voltage Vref, and the output is connected to the drain of the flash switch unit. The output of the first transimpedance amplifier is connected to the comparison module as the output of the read current-to-voltage module.

[0008] The reference power supply voltage conversion module includes a second transimpedance amplifier and a voltage-controlled current source. The in-phase input terminal of the second transimpedance amplifier is connected to the reference voltage Vref, and the inverting input terminal is connected to the voltage controlled by the variable voltage V B The output end of the second transimpedance amplifier is also connected to the comparison module as the output end of the reference power supply voltage conversion module; the method includes:

[0009] A gate voltage corresponding to a configuration operation is applied to the gate of the flash switch unit. The configuration operation is a programming operation or an erasing operation. The first voltage output by the read current-to-voltage module is related to the read current Icell of the flash switch unit. The second voltage output by the reference power supply-to-voltage module is related to the variable voltage V B Related, adjust the variable voltage V according to the output of the comparison module B , until a readout current Icell of the flash switch unit that meets the accuracy requirement is read out, and the threshold voltage of the flash switch unit is determined according to the readout current Icell.

[0010] A further technical solution is that, when the configuration operation is a programming operation, the gate voltage applied to the gate of the flash switch unit is the same as the operating voltage.

[0011] A further technical solution is that when the configuration operation is an erase operation, the gate voltage applied to the gate of the flash switch unit is Vref+V1, where V1 is a typical value of the threshold voltage of the flash switch unit after erasure.

[0012] A further technical solution is that the read current-to-voltage module includes a first operational amplifier unit, an NMOS transistor N44, and an NMOS transistor N55. The drain of N44 is connected to the core power supply VDD, the source of N44 is connected to the drain of N45, the source of N45 is grounded GND, the gate of N44 is connected to the output of the first operational amplifier unit, and the gate of N45 is connected to the bias voltage Vbias; the two input terminals of the first operational amplifier unit are respectively connected to the reference voltage Vref and the drain of the flash switch unit, and the drain of N45 is also connected to the drain of the flash switch unit;

[0013] The first operational amplifier unit and N44 form a first transimpedance amplifier, the two input terminals of the first operational amplifier unit serve as the two input terminals of the first transimpedance amplifier, and the gate of N44 serves as the output terminal of the first transimpedance amplifier;

[0014] The first operational amplifier unit and N44 simultaneously form a constant voltage source, an input terminal of the first operational amplifier unit connected to the reference voltage Vref serves as an input terminal of the constant voltage source, and the source of N44 serves as an output terminal of the constant voltage source;

[0015] The current flowing through N44 is equal to the read current Icell of the flash switch unit, so that the first voltage output by the read current-to-voltage module is:

[0016] VP=Vref+[(1 / K) *Icell *(L / M) N44 ] 1 / 2 ;

[0017] Wherein, K is the process parameter of the NMOS tube, and (L / M) N44 is the width-to-length ratio of N44.

[0018] A further technical solution is that the second transimpedance amplifier includes a second operational amplifier unit and an NMOS transistor N15; the two input terminals of the second operational amplifier unit are respectively connected to the reference voltage Vref and the output terminal of the voltage-controlled current source as the two input terminals of the second transimpedance amplifier, the gate of N15 is connected to the output terminal of the second operational amplifier unit and serves as the output terminal of the second transimpedance amplifier, the drain of N15 is connected to the core power supply VDD, and the source is connected to the voltage-controlled current source;

[0019] The voltage controlled current source is at a variable voltage V B The current supplied to the second transimpedance amplifier under the action of is Iref, and the second voltage output by the reference power supply to voltage module is:

[0020] VN= Vref+[(1 / K) *Iref*(L / M) N15 ] 1 / 2 ;

[0021] Where K is the process parameter of NMOS tube, (L / M) N15 is the width-to-length ratio of N15.

[0022] A further technical solution is that the voltage-controlled current source includes a third operational amplifier unit, an NMOS tube N14 and a resistor R1, and one input terminal of the third operational amplifier unit is connected to a variable voltage V B The other input terminal is connected to the common terminal of N14 and R1, the output terminal of the third operational amplifier unit is connected to the gate of N14, the drain of N14 is connected to the source of N15 and an input terminal of the second operational amplifier unit, and the voltage-controlled current source is at a variable voltage V B The current supplied to the second transimpedance amplifier under the action of Iref = V B / R1.

[0023] Its further technical solution is to adjust the variable voltage V B Including: selecting several reference current points Iref in a preset reference current range with a preset current step, and adjusting the variable voltage V accordingly B =Iref*R1.

[0024] A further technical solution is that the programming operation and the erasing operation correspond to different reference current ranges and current steps.

[0025] A further technical solution is that the third operational amplifier unit includes PMOS transistors P1, P3, P4, P5, P6, P9, P10 and P12, and NMOS transistors N2, N7, N8, N11 and N13, and capacitor C1;

[0026] The sources of P1, P3, P5, P10 and P12 are all connected and connected to the core power supply VDD. The gates of P1, P3, P5, P10 and P12 are all connected and connected to the drain of P1. The drain of P1 is also connected to the drain of N2 and the gate output bias voltage Vbias. The drain of P3 is connected to the gate of P6 and the source of P4. The gate of P4 is used as an input terminal of the third operational amplifier unit to connect to the common terminal of N14 and R1; the drain of P5 is connected to the source of P6 and the source of P9, the drain of P6 is connected to the drain of N7, the drain of P9 is connected to the drain of N8, and the gates of N7 and N8 are connected; the drain of P10 is connected to the gate of P9 and the drain of N11. The gate of N11 is connected to the variable voltage V as an input terminal of the third operational amplifier unit. B , the drain of N11 is connected to the drain of P12 and the drain of N13 through capacitor C1, the drain of N11 is also connected to the gate of N13, the drain of P4, the source of N7, the source of N8, the source of N11 and the source of N13 are all grounded GND, and the drain of N13 is used as the output end of the third operational amplifier unit to connect to the gate of N14.

[0027] Its further technical solution is that the comparison module includes a first differential input stage, a second high gain stage and an output driver stage, the two differential input ends of the first differential input stage are respectively connected to the output end of the reading current conversion module and the output end of the reference power supply conversion module, the second high gain stage includes a PMOS tube P30 and an NMOS tube N31, the source of P30 is connected to the core power supply VDD, the drain of P30 is connected to the drain of N31, the source of N31 is grounded GND, the gate of P30 is connected to the output end of the first differential input stage, and the gate of N31 is connected to the bias voltage Vbias; the output driver stage includes a PMPS tube P32 and an NMOS tube N33, the source of P32 is connected to VDD, the drain is connected to the drain of N33, the source of N33 is connected to GND, the gate of P32 is connected to the gate of N33 and connected to the drain of P30, and the drain of P32 is connected to the output end of the comparison module.

[0028] The beneficial technical effects of the present invention are:

[0029] The present application discloses a method for determining the threshold voltage of a flash-type FPGA using a readout circuit. The method uses the readout circuit to apply a constant voltage to the drain terminal of the flash switch unit, then reads the current flowing through the flash switch unit to ground, and compares it with the high-precision reference current provided by the voltage-controlled current source in the reference power supply to voltage module. This allows the readout current of the flash switch unit to be accurately read, thereby enabling accurate judgment of the threshold voltage of the flash switch unit after erasure and programming, thereby providing a basis for the system control circuit to adjust the threshold voltage of the flash switch unit, ensuring the consistency of the threshold voltage distribution of the flash switch unit after erasure and programming, and providing high-precision delay parameters for the superior programmability of the flash-type FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a typical wiring switch matrix composed of flash switch units in flash type FPGA.

[0031] Figure 2 This is a comparative diagram of the requirements of flash FPGA and flash memory for the threshold voltage distribution of flash switch units.

[0032] Figure 3 It is a structural diagram of the readout circuit of this application.

[0033] Figure 4 FIG. 4 is a circuit diagram of a current-to-voltage conversion module in an embodiment.

[0034] Figure 5 FIG. 4 is a circuit diagram of a reference power supply to voltage conversion module in an embodiment.

[0035] Figure 6 FIG. 4 is a circuit diagram of a comparison module in an embodiment.

[0036] Figure 7 3 is a schematic diagram of the corresponding relationship between the readout current Icell and the threshold voltage obtained by using the readout circuit of the present application. DETAILED DESCRIPTION

[0037] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0038] This application discloses a method for determining the threshold voltage of a flash type FPGA using a readout circuit. Please refer to Figure 3 The readout circuit shown in the figure is a structural diagram of the readout circuit, which includes a read current to voltage module, a reference power supply to voltage module and a comparison module. The readout circuit is connected to the flash switch unit in the flash type FPGA. In actual application, Figure 3 and4 As shown, the readout circuit is connected to the switch unit array in the flash type FPGA. The switch unit array includes a plurality of flash switch units. The sources of these plurality of flash switch units are grounded respectively. The drains of these plurality of flash switch units are connected and connected to the readout circuit respectively. These plurality of flash switch units are controlled by different word lines WL <0> ~ WL <n>, one of the flash switch units is turned on and selected through a word line. This application only takes the use of a readout circuit to determine the threshold voltage of a selected flash switch unit as an example.

[0039] The read current-to-voltage module includes a first transimpedance amplifier (TIA1) and a constant voltage source. The non-inverting input of the first transimpedance amplifier (TIA1) is connected to a reference voltage (Vref), and the inverting input is connected to the drain of the flash switch unit. The source of the flash switch unit is grounded, and the gate receives the gate voltage. The constant voltage source has an input connected to the reference voltage (Vref) and an output connected to the drain of the flash switch unit. The output of the first transimpedance amplifier (TIA1) serves as the output of the read current-to-voltage module and is connected to a comparison module to output a first voltage (VP).

[0040] The reference power supply voltage conversion module includes a second transimpedance amplifier TIA2 and a voltage-controlled current source. The in-phase input terminal of the second transimpedance amplifier TIA2 is connected to the reference voltage Vref, and the inverting input terminal is connected to the variable voltage V B The output terminal of the second transimpedance amplifier TIA2 is also connected to the comparison module as the output terminal of the reference power supply voltage conversion module to output the second voltage VN.

[0041] The comparison module is constructed based on the structure of the comparator CMP, which outputs corresponding Data based on the input first voltage VP and second voltage VN.

[0042] The method for determining the threshold voltage of a flash type FPGA using the readout circuit includes:

[0043] In the read current-to-voltage module, since the voltages at the non-inverting input and the inverting input of the first transimpedance amplifier TIA1 are equal, the read current-to-voltage module applies a constant voltage Vref to the drain of the flash switch unit, thereby obtaining the read current Icell of the selected flash switch unit and outputting a first voltage VP related to the read current Icell of the flash switch unit.

[0044] Since the typical values of the threshold voltage after performing the erase operation and the program operation on the flash switch unit are quite different, and the current is also quite different, a gate voltage corresponding to the configuration operation is applied to the gate of the flash switch unit. The configuration operation is a programming operation or an erase operation, and the gate voltages applied during the programming operation and the erase operation are different.

[0045] The second voltage VN output by the reference power supply voltage conversion module is the same as the variable voltage V B The comparison module compares the input first voltage VP and the second voltage VN and outputs the corresponding high and low level Data. The variable voltage V is adjusted according to the output of the comparison module. B , so that the second voltage VN gradually approaches the first voltage VP, so that the variable voltage V B A readout current Icell that meets the accuracy requirements is obtained. Since the readout current Icell of the flash switch unit is related to the threshold voltage, after reading the readout current Icell that meets the accuracy requirements, the threshold voltage of the flash switch unit after performing the corresponding configuration operation can be determined. If the threshold voltage does not meet the requirements, timely adjustment can be made. The corresponding relationship between the readout current Icell and the threshold voltage can be pre-configured.

[0046] In one embodiment, please refer to Figure 4 The read current-to-voltage module includes a first op amp unit, an NMOS transistor N44, and an NMOS transistor N55. The drain of N44 is connected to the core power supply VDD, the source of N44 is connected to the drain of N45, and the source of N45 is connected to ground GND. The gate of N44 is connected to the output of the first op amp unit, and the gate of N45 is connected to the bias voltage Vbias. The two inputs of the first op amp unit are respectively connected to the reference voltage Vref and the drain of the flash switch unit. The drain of N45 is also connected to the drain of the flash switch unit.

[0047] exist Figure 4 In the circuit shown, the first op amp unit and N44 form a first transimpedance amplifier. N44 serves as the current input stage of the first transimpedance amplifier. The two input terminals of the first op amp unit serve as the two input terminals of the first transimpedance amplifier, and the gate of N44 serves as the output terminal of the first transimpedance amplifier. Changes in the Icell of the flash switch unit cause changes in the gate voltage VG1 of N44, which in turn changes the VP output by the read current-to-voltage module.

[0048] In addition, the first operational amplifier unit and N44 simultaneously form a constant voltage source, an input terminal of the first operational amplifier unit connected to the reference voltage Vref serves as the input terminal of the constant voltage source, and the source of N44 serves as the output terminal of the constant voltage source and is connected to the drain of the flash switch unit.

[0049] The first op amp unit includes PMOS transistors P35, P37, P38, P39, and P42, as well as NMOS transistors N36, N40, N41, and N43, and capacitor C3. P35 and N36 provide bias current for the read current-to-voltage module, while P37, P38, P39, N40, N41, P42, and N43 form a two-stage op amp. The sources of P35, P37, and P42 are connected and connected to the core power supply VDD. The gates of P35, P37, and P42 are connected and connected to the drain of P35. The drain of P35 is connected to the drain and gate of N36, and the drain of P37 is connected to the source of P38 and the source of P39. The gates of P38 and P39 serve as the two inputs of the first op amp unit, respectively. The gate of P38 serves as the inverting input for connecting to the drain of the flash switch unit, and the gate of P39 serves as the non-inverting input for connecting to Vref. The drain of P38 is connected to the drain of N40, the gate of N40, and the gate of N41. The drain of P39 is connected to the drain of N41 and the gate of N43. The drain of N41 is also connected to the drain of N43 and the drain of P42 via capacitor C3. The sources of N36, N40, N41, and N43 are grounded to GND. The drain of N43 serves as the output of the first op amp unit, connected to the gate of N44, and outputs VP.

[0050] based on Figure 4 From the structure shown, it can be seen that the current flowing through N44 is equal to the read current Icell of the flash switch unit. Therefore, the gate voltage of N44 can be obtained through the current formula of the saturated region NMOS tube, that is, the first output voltage VP is:

[0051] VP=Vref+[(1 / K) *Icell *(L / M) N44 ] 1 / 2 ;

[0052] Where K is the process parameter of NMOS tube, (L / M) N44 is the width-to-length ratio of N44.

[0053] In one embodiment, Figure 5 As shown, in the reference power supply to voltage module, the second transimpedance amplifier TIA2 includes a second operational amplifier unit and an NMOS tube N15. N15 is the current input stage of the second transimpedance amplifier TIA2. The two input terminals of the second operational amplifier unit are respectively connected to the reference voltage Vref and the output terminal of the voltage-controlled current source as the two input terminals of the second transimpedance amplifier TIA2. The gate of N15 is connected to the output terminal of the second operational amplifier unit and serves as the output terminal of the second transimpedance amplifier TIA2. The drain of N15 is connected to the core power supply VDD and the source is connected to the voltage-controlled current source. The specific circuit of the second operational amplifier unit can be the same as that of the first operational amplifier unit, and this embodiment will not be repeated. Similar to the first transimpedance amplifier, the voltage-controlled current source is at a variable voltage V B The change in the current Iref supplied to the second transimpedance amplifier TIA2 under the action of will cause the gate voltage VG2 of N15 to change, that is, the VN output by the reference power supply to voltage module changes. Then, the gate voltage of N15 can be obtained by the current formula of the saturated region NMOS transistor, that is, the second voltage output by the reference power supply to voltage module is:

[0054] VN= Vref+[(1 / K) *Iref*(L / M) N15 ] 1 / 2 ;

[0055] Wherein, K is the process parameter of the NMOS transistor, and (L / M) N15 is the width-to-length ratio of N15.

[0056] like Figure 5 As shown, the voltage-controlled current source includes a third operational amplifier unit, an NMOS transistor N14, and a resistor R1. One input terminal of the third operational amplifier unit is connected to the variable voltage VB, and the other input terminal is connected to the common terminal of N14 and R1. The output terminal of the third operational amplifier unit is connected to the gate of N14, and the drain of N14 is connected to the source of N15 and an input terminal of the second operational amplifier unit. Since the voltages of the two input terminals of the third operational amplifier unit are equal, the voltage at VF2 is equal to the variable voltage VB, so the current Iref flowing through the resistor R1 = V B / R1. Since N14 and R1 are connected in series, the current on N14 is also Iref = V B / R1, equivalent to Figure 3 In the voltage controlled current source, the variable voltage V B The current supplied to the second transimpedance amplifier TIA2 is Iref = V B / R1, the second voltage VN output by the reference power supply voltage conversion module is:

[0057] VN= Vref+[(1 / K) * (V B / R1)*(L / M) N15 ] 1 / 2 .

[0058] like Figure 5 As shown, the third op amp unit includes PMOS transistors P1, P3, P4, P5, P6, P9, P10, and P12, as well as NMOS transistors N2, N7, N8, N11, and N13, and capacitor C1. P3, P4, P5, P6, N7, N8, P9, P10, N11, P12, and N13 form a symmetrical two-stage op amp. The sources of P1, P3, P5, P10, and P12 are all connected and connected to the core power supply VDD. The gates of P1, P3, P5, P10, and P12 are all connected and connected to the drain of P1. The drain of P1 is also connected to the drain of N2 and the gate output bias voltage Vbias. The drain of P3 is connected to the gate of P6 and the source of P4. The gate of P4 serves as an input terminal of the third op amp unit and is connected to the common terminal of N14 and R1. The drain of P5 is connected to the source of P6 and the source of P9, the drain of P6 is connected to the drain of N7, the drain of P9 is connected to the drain of N8, and the gates of N7 and N8 are connected. The drain of P10 is connected to the gate of P9 and the drain of N11. The gate of N11 is connected to the variable voltage V as an input terminal of the third operational amplifier unit. B The drain of N11 is connected to the drain of P12 and the drain of N13 via capacitor C1. The drain of N11 is also connected to the gate of N13. The drain of P4, the source of N7, the source of N8, the source of N11, and the source of N13 are all grounded to GND. The drain of N13 serves as the output of the third op amp unit and is connected to the gate of N14.

[0059] Please refer to Figure 6 The comparison module includes a first differential input stage, a second high-gain stage, and an output driver stage. The two differential input terminals of the first differential input stage are respectively connected to the output terminal of the current-to-voltage conversion module to obtain VP and to the output terminal of the reference power supply-to-voltage conversion module to obtain VN. In one embodiment, the first differential input stage includes PMOS transistors P25 and P26 and NMOS transistors N27, N28, and N29. The source of P25 is connected to the source of P26 and to VDD, the gate of P25 is connected to the gate of P26 and to the drain of P25, the drain of P25 is also connected to the drain of N27, the drain of P26 is also connected to the drain of N28, the source of N27 is connected to the source of N28 and to the drain of N29, the source of N29 is grounded GND, the gate of N29 is connected to the bias voltage Vbias, the gate of N27 obtains VP, and the gate of N28 obtains VN. The second high-gain stage includes a PMOS transistor P30 and an NMOS transistor N31. The source of P30 is connected to the core power supply VDD, the drain of P30 is connected to the drain of N31, the source of N31 is grounded GND, and the gate of P30 is connected to the output of the first differential input stage, that is, to the drain of P26. The gate of N31 is connected to the bias voltage Vbias. The output driver stage includes a PMOS transistor P32 and an NMOS transistor N33. The source of P32 is connected to VDD, the drain is connected to the drain of N33, and the source of N33 is connected to GND. The gate of P32 is connected to the gate of N33 and to the drain of P30. The drain of P32 is connected to the output of the comparison module to output Data. The comparison module compares the inputs VP and VN and outputs Data accordingly, as described above:

[0060] VP=Vref+[(1 / K) *Icell *(L / M) N44 ] 1 / 2 ;

[0061] VN= Vref+[(1 / K) * (V B / R1)*(L / M) N15 ] 1 / 2 ;

[0062] From the above, we can see that the forms of VP and VN are the same. We can further set the width-to-length ratio of N44 and N15 to be the same, that is, (L / M) N44 =(L / M) N15 , then by adjusting the variable voltage V B When VN approaches VP, it is actually equivalent to making Iref = V B / R1 approaches Icell, and the final Iref = V B / R1 confirms to obtain Icell.

[0063] Therefore, when adjusting the variable voltage V B When VN approaches VP, the actual operation is: select several reference current points Iref with preset current steps within the preset reference current range, and adjust the variable voltage V accordingly. B =Iref*R1. As mentioned above, the difference between the threshold voltage and current is large during programming and erasing operations, so the reference current range and current step corresponding to programming and erasing operations are different.

[0064] Specifically, taking Vref=1.0V as an example, in the above process, when the configuration operation is a programming operation, since the typical value of the threshold voltage of the flash switch unit after the programming operation is about 3.5V, the gate voltage applied to the gate of the flash switch unit is the same as the operating voltage. The operating voltage of the gate of the flash switch unit is 0V during normal operation, so the gate voltage V GS =0V. In one example, the preset reference current range corresponding to the programming operation is 190uA~210uA, and the corresponding current step is 10uA. Then, three reference current points Iref are selected as 190uA, 200uA and 210uA respectively, and V is adjusted accordingly. B =190uA *R1, V B =200uA *R1, V B =210uA*R1, to read the read current Icell of the flash switch unit after the programming operation. In fact, the current step can be reduced to further improve the accuracy.

[0065] Please combine Figure 7 When the configuration operation is an erase operation, the typical value of the threshold voltage of the flash switch unit after the erase operation is around -3.5V. Since the working voltage of the gate of the flash switch unit is 0V during normal operation, the turn-off current of the flash switch unit after the erase operation is at the nA level. If the working voltage of 0V is still applied to the gate of the flash switch unit at this time, the circuit will not be able to meet the nA level reading accuracy. According to the voltage-current formula of the flash switch unit saturation region, when the configuration operation is an erase operation, the gate voltage applied to the gate of the flash switch unit is designed to be Vref+V1. V1 is the typical value of the threshold voltage of the flash switch unit after erasure, such as -3.5V. Then, when the drain voltage V DS =Vref=1.0V, the gate voltage V GS =-2.5V. At this time, the flash switch unit is in the subthreshold conduction state. The preset reference current range corresponding to the erase operation is 1.0uA~1.2uA, and the corresponding current step is 0.2uA. Then, two reference current points Iref are selected as 1.0uA and 1.2uA respectively, and V is adjusted accordingly. B =1.0uA*R1、V B =1.2uA * R1, to read the read current Icell of the flash switch unit after the erase operation. In fact, the current step can be reduced to further improve the accuracy.

[0066] The above description is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.< / n>

Claims

1. A method for determining the threshold voltage of a flash type FPGA using a readout circuit, characterized in that: The readout circuit includes a read current-to-voltage module, a reference power supply-to-voltage module, and a comparison module; The read current-to-voltage module includes a first transimpedance amplifier and a constant voltage source, wherein the non-inverting input terminal of the first transimpedance amplifier is connected to the reference voltage Vref, and the inverting input terminal is connected to the drain of the flash switch unit, the source of the flash switch unit is grounded, and the gate obtains the gate voltage; the input terminal of the constant voltage source is connected to the reference voltage Vref, and the output terminal is connected to the drain of the flash switch unit, and the output terminal of the first transimpedance amplifier is connected to the comparison module as the output terminal of the read current-to-voltage module; The reference power supply voltage conversion module includes a second transimpedance amplifier and a voltage-controlled current source, wherein the non-inverting input terminal of the second transimpedance amplifier is connected to the reference voltage Vref, and the inverting input terminal is connected to the voltage controlled by the variable voltage V B The voltage-controlled current source, the output end of the second transimpedance amplifier is also connected to the comparison module as the output end of the reference power supply voltage conversion module; The method comprises: A gate voltage corresponding to a configuration operation is applied to the gate of the flash switch unit, where the configuration operation is a programming operation or an erasing operation. The first voltage output by the read current-to-voltage module is related to the read current Icell of the flash switch unit, and the second voltage output by the reference power supply-to-voltage module is related to the variable voltage V B Related, according to the output of the comparison module to adjust the variable voltage V B , until a readout current Icell of the flash switch unit that meets the accuracy requirement is read out, and the threshold voltage of the flash switch unit is determined according to the readout current Icell.

2. The method according to claim 1, characterized in that When the configuration operation is a programming operation, the gate voltage applied to the gate of the flash switch unit is the same as the operating voltage.

3. The method according to claim 1, characterized in that When the configuration operation is an erase operation, the gate voltage applied to the gate of the flash switch unit is Vref+V1, where V1 is a typical value of the threshold voltage of the flash switch unit after erasure.

4. The method according to any one of claims 1 to 3, characterized in that: The read current-to-voltage module includes a first operational amplifier unit, an NMOS transistor N44, and an NMOS transistor N55. The drain of N44 is connected to the core power supply VDD, the source of N44 is connected to the drain of N45, the source of N45 is grounded GND, the gate of N44 is connected to the output of the first operational amplifier unit, and the gate of N45 is connected to the bias voltage Vbias. The two input terminals of the first operational amplifier unit are respectively connected to the reference voltage Vref and the drain of the flash switch unit. The drain of N45 is also connected to the drain of the flash switch unit. The first operational amplifier unit and N44 form the first transimpedance amplifier, the two input terminals of the first operational amplifier unit serve as the two input terminals of the first transimpedance amplifier, and the gate of N44 serves as the output terminal of the first transimpedance amplifier; The first operational amplifier unit and N44 simultaneously form the constant voltage source, an input terminal of the first operational amplifier unit connected to the reference voltage Vref serves as the input terminal of the constant voltage source, and the source of N44 serves as the output terminal of the constant voltage source; The current flowing through N44 is equal to the read current Icell of the flash switch unit, so that the first voltage output by the read current-to-voltage module is: VP=Vref+[(1 / K) *Icell *(L / M) N44 ] 1 / 2 ; Where K is the process parameter of NMOS tube, (L / M) N44 is the width-to-length ratio of N44.

5. The method according to any one of claims 1 to 3, characterized in that: The second transimpedance amplifier includes a second operational amplifier unit and an NMOS transistor N15; the two input terminals of the second operational amplifier unit are respectively connected to the reference voltage Vref and the output terminal of the voltage-controlled current source as the two input terminals of the second transimpedance amplifier, the gate of N15 is connected to the output terminal of the second operational amplifier unit and serves as the output terminal of the second transimpedance amplifier, the drain of N15 is connected to the core power supply VDD, and the source is connected to the voltage-controlled current source; The voltage controlled current source has a variable voltage V B The current provided to the second transimpedance amplifier under the action of is Iref, and the second voltage output by the reference power supply to voltage module is: VN= Vref+[(1 / K) *Iref*(L / M) N15 ] 1 / 2 ; Where K is the process parameter of NMOS tube, (L / M) N15 is the width-to-length ratio of N15.

6. The method according to claim 5, characterized in that The voltage-controlled current source includes a third operational amplifier unit, an NMOS tube N14 and a resistor R1. One input terminal of the third operational amplifier unit is connected to a variable voltage V B , the other input end is connected to the common end of N14 and R1, the output end of the third operational amplifier unit is connected to the gate of N14, the drain of N14 is connected to the source of N15 and an input end of the second operational amplifier unit, and the voltage-controlled current source is connected to the variable voltage V B The current supplied to the second transimpedance amplifier is Iref = V B / R1.

7. The method according to claim 6, characterized in that The adjustable variable voltage V B Including: selecting several reference current points Iref in a preset reference current range with a preset current step, and adjusting the variable voltage V accordingly B =Iref*R1.

8. The method according to claim 7, characterized in that The reference current range and current step corresponding to the programming operation and the erase operation are different.

9. The method according to claim 6, characterized in that The third operational amplifier unit includes PMOS transistors P1, P3, P4, P5, P6, P9, P10 and P12, NMOS transistors N2, N7, N8, N11 and N13, and capacitor C1; The sources of P1, P3, P5, P10 and P12 are all connected and connected to the core power supply VDD, the gates of P1, P3, P5, P10 and P12 are all connected and connected to the drain of P1, the drain of P1 is also connected to the drain of N2 and the gate output bias voltage Vbias, the drain of P3 is connected to the gate of P6 and the source of P4, the gate of P4 is used as an input terminal of the third operational amplifier unit to connect to the common terminal of N14 and R1; the drain of P5 is connected to the source of P6 and the source of P9, the drain of P6 is connected to the drain of N7, the drain of P9 is connected to the drain of N8, and the gates of N7 and N8 are connected; the drain of P10 is connected to the gate of P9 and the drain of N11, and the gate of N11 is used as an input terminal of the third operational amplifier unit to connect to the variable voltage V B , the drain of N11 is connected to the drain of P12 and the drain of N13 through capacitor C1, the drain of N11 is also connected to the gate of N13, the drain of P4, the source of N7, the source of N8, the source of N11 and the source of N13 are all grounded GND, and the drain of N13 is used as the output end of the third operational amplifier unit to connect to the gate of N14.

10. The method according to any one of claims 1 to 3, characterized in that: The comparison module includes a first differential input stage, a second high gain stage and an output driver stage. The two differential input ends of the first differential input stage are respectively connected to the output end of the read current-to-voltage module and the output end of the reference power supply-to-voltage module. The second high gain stage includes a PMOS transistor P30 and an NMOS transistor N31. The source of P30 is connected to the core power supply VDD, the drain of P30 is connected to the drain of N31, the source of N31 is grounded GND, the gate of P30 is connected to the output end of the first differential input stage, and the gate of N31 is connected to the bias voltage Vbias; the output driver stage includes a PMPS transistor P32 and an NMOS transistor N33. The source of P32 is connected to VDD, the drain is connected to the drain of N33, the source of N33 is connected to GND, the gate of P32 is connected to the gate of N33 and to the drain of P30, and the drain of P32 is connected to the output end of the comparison module.

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