Method for obtaining depletion voltage

Abstract

The application provides a depletion voltage acquisition method for acquiring a depletion voltage when electrons in a two-dimensional electron gas channel of a semiconductor device are depleted, and the method comprises the following steps: acquiring a capacitance-reverse bias voltage characteristic curve of the semiconductor device; acquiring a second-order differential of capacitance with respect to reverse bias voltage in the capacitance-reverse bias voltage characteristic curve, and obtaining a second-order differential characteristic curve of the semiconductor device; and acquiring the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted according to the second-order differential characteristic curve of the semiconductor device. This method is simple and intuitive, can quickly acquire the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted, and is convenient for researchers to use the method for rapid testing, accelerates the research and development progress, and improves the research and development competitiveness of enterprises.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a depletion voltage acquisition method. BACKGROUND

[0002] Two-dimensional electron gas (2DEG) exists in some heterostructures, for semiconductor abrupt heterojunction, due to the existence of conduction band bottom energy mutation ΔEc, then there is a "spike" and "notch" near the interface; in fact, for the effect of conduction band electrons in the heterojunction, the "spike" is also the potential barrier of the electron, and the "notch" is also the potential well of the electron. Therefore, in fact, the electric field in the "spike" has the effect of driving electrons, that is, forming a depletion layer; the electric field in the "notch" has the effect of driving holes and accumulating electrons, and under suitable conditions, an electron accumulation layer (i.e. a surface conductive channel) can be formed. If the depth of the "notch" potential well is large enough, the electrons in it can only move in the plane in all directions (i.e. close to the heterojunction interface), that is, two-dimensional motion of electrons; further, if the effective mass concept is introduced, these electrons can be considered as classical free electrons, so that the electrons in the heterojunction potential well can be regarded as a "two-dimensional electron gas" with a certain effective mass.

[0003] The depletion layer, also known as the depletion region, the barrier layer, or the potential barrier region, is a high-resistance region in the junction area where the number of carriers is very small under the dual influence of drift motion and diffusion. The width of the depletion layer is related to the material properties, temperature, and the size of the bias voltage. Under reverse bias, the voltage drop on the depletion region increases, most of the carriers are pushed away from the junction, leaving more charged ions, so the depletion region becomes wider, the electric field becomes stronger, increasing the drift component of the current and reducing the diffusion component. In this case, the carrier density (mainly minority carriers) is very small, and only a very small reverse saturation current flows.

[0004] The process of obtaining the depletion voltage when the electrons in the two-dimensional electron gas channel are depleted in the prior art is very cumbersome. For a semiconductor device with multiple two-dimensional electron gas channels and a Schottky contact electrode, after the C-V (capacitance-voltage) characteristic curve is obtained by testing, the depletion voltage corresponding to the depletion of the electrons in each channel can be obtained only through multiple steps of calculation, which is complex and not intuitive and convenient. SUMMARY

[0005] To solve the above technical problems, the present application designs a depletion voltage acquisition method, which can quickly obtain the depletion voltage when the electrons in the two-dimensional electron gas channel in the semiconductor device are depleted.

[0006] The present application designs a depletion voltage acquisition method for obtaining the depletion voltage when the electrons in the two-dimensional electron gas channel in the semiconductor device are depleted, which comprises:

[0007] obtaining a capacitance-reverse bias voltage characteristic curve of the semiconductor device;

[0008] obtaining a second-order differential of capacitance with respect to voltage in the capacitance-reverse bias voltage characteristic curve, and obtaining a second-order differential characteristic curve of the semiconductor device;

[0009] obtaining a depletion voltage at which electrons in a two-dimensional electron gas channel of the semiconductor device are depleted according to the second-order differential characteristic curve of the semiconductor device.

[0010] In one embodiment, the obtaining of the depletion voltage at which electrons in a two-dimensional electron gas channel of the semiconductor device are depleted according to the second-order differential characteristic curve of the semiconductor device comprises:

[0011] establishing a two-dimensional coordinate system, the abscissa of the two-dimensional coordinate system being a reverse bias voltage, the second-order differential characteristic curve having a wave crest, and the second-order differential characteristic curve having a plurality of intersection points with the abscissa of the two-dimensional coordinate system, the intersection points being located on opposite sides of the wave crest;

[0012] the abscissa value of the intersection point adjacent to one side of the origin of the two-dimensional coordinate system of the wave crest being the depletion voltage at which electrons in a two-dimensional electron gas channel of the semiconductor device are depleted.

[0013] In one embodiment, the semiconductor device comprises an ohmic contact electrode and a Schottky contact electrode; and the obtaining of the capacitance-reverse bias voltage characteristic curve of the semiconductor device comprises:

[0014] grounding the ohmic contact electrode of the semiconductor device;

[0015] applying a voltage to the Schottky contact electrode of the semiconductor device;

[0016] performing a capacitance-voltage characteristic test on the semiconductor device by using a capacitance-voltage tester to obtain the capacitance-reverse bias voltage characteristic curve.

[0017] In one embodiment, the semiconductor device further comprises:

[0018] a first AlGaN / AlN / GaN heterostructure, a first two-dimensional electron gas channel being present at the interface between the AlN layer and the GaN layer in the first AlGaN / AlN / GaN heterostructure;

[0019] a second AlGaN / AlN / GaN heterostructure on a surface of the first AlGaN / AlN / GaN heterostructure, a second two-dimensional electron gas channel existing at an interface between the AlN layer and the GaN layer in the second AlGaN / AlN / GaN heterostructure;

[0020] a third AlGaN / AlN / GaN heterostructure on a surface of the second AlGaN / AlN / GaN heterostructure away from the first AlGaN / AlN / GaN heterostructure, a third two-dimensional electron gas channel existing at an interface between the AlN layer and the GaN layer in the third AlGaN / AlN / GaN heterostructure;

[0021] a difference between the electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel, and the electron concentration in the third two-dimensional electron gas channel is less than a preset value;

[0022] the Schottky contact electrode is on a surface of the third AlGaN / AlN / GaN heterostructure away from the second AlGaN / AlN / GaN heterostructure; and the ohmic contact electrode is on a surface of the third AlGaN / AlN / GaN heterostructure away from the second AlGaN / AlN / GaN heterostructure and is located at a periphery of the Schottky contact electrode.

[0023] In one of the embodiments, the thickness of the AlGaN layer in the first AlGaN / AlN / GaN heterostructure is the same as the thickness of the AlGaN layer in the third AlGaN / AlN / GaN heterostructure, and is less than the thickness of the AlGaN layer in the second AlGaN / AlN / GaN heterostructure.

[0024] In one of the embodiments, the thickness of the GaN layer in the first AlGaN / AlN / GaN heterostructure, the thickness of the GaN layer in the second AlGaN / AlN / GaN heterostructure, and the thickness of the GaN layer in the third AlGaN / AlN / GaN heterostructure are the same; and the thickness of the AlN layer in the first AlGaN / AlN / GaN heterostructure, the thickness of the AlN layer in the second AlGaN / AlN / GaN heterostructure, and the thickness of the AlN layer in the third AlGaN / AlN / GaN heterostructure are the same.

[0025] In one of the embodiments, the first AlGaN / AlN / GaN heterostructure, the second AlGaN / AlN / GaN heterostructure and the third AlGaN / AlN / GaN heterostructure are all unintentionally doped heterostructures, and the background carrier concentration of the first AlGaN / AlN / GaN heterostructure, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure are all 0.5*10 16 cm -3 ~1.5*10 16 cm -3 .

[0026] In one of the embodiments, the electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel and the electron concentration in the third two-dimensional electron gas channel are all the same.

[0027] In one of the embodiments, the semiconductor device further comprises:

[0028] a substrate;

[0029] a buffer layer on the substrate; the first AlGaN / AlN / GaN heterostructure is on the surface of the buffer layer away from the substrate.

[0030] In one of the embodiments, the semiconductor device further comprises a nucleation layer between the substrate and the buffer layer.

[0031] The depletion voltage acquisition method has the following beneficial effects:

[0032] The depletion voltage acquisition method first acquires the capacitance-reverse bias voltage characteristic curve of the semiconductor device through testing; then the second-order differential of the capacitance with respect to the reverse bias voltage in the capacitance-reverse bias voltage characteristic curve is obtained, and the second-order differential characteristic curve of the semiconductor device is obtained; according to the second-order differential characteristic curve of the semiconductor device, the depletion voltage when the electrons in the two-dimensional electron gas channel are depleted is acquired. This method is simple and intuitive, and can quickly acquire the depletion voltage when the electrons in the two-dimensional electron gas channel are depleted, which facilitates researchers to use this method for rapid testing, speeds up the research and development progress, and improves the enterprise research and development competitiveness. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a flow chart of the depletion voltage acquisition method in one of the embodiments of the present application.

[0034] Figure 2is a capacitance-reverse bias voltage characteristic curve of a semiconductor device in a depletion voltage acquisition method in an embodiment of the present application.

[0035] Figure 3 is a flow chart of a step of acquiring a depletion voltage when electrons in a two-dimensional electron gas channel of a semiconductor device are depleted according to a second order differential characteristic curve of the semiconductor device in a depletion voltage acquisition method in an embodiment of the present application.

[0036] Figure 4 is Figure 2 a second order differential characteristic curve of capacitance with respect to reverse bias voltage in a capacitance-reverse bias voltage characteristic curve.

[0037] Figure 5 is a flow chart of a step of acquiring a capacitance-reverse bias voltage characteristic curve of a semiconductor device in a depletion voltage acquisition method in an embodiment of the present application.

[0038] Figure 6 is a structure diagram of a semiconductor device in a depletion voltage acquisition method in an embodiment of the present application.

[0039] Figure 7 is a structure diagram of a first AlGaN / AlN / GaN heterostructure, a second AlGaN / AlN / GaN heterostructure and a third AlGaN / AlN / GaN heterostructure stacked in a semiconductor device in a depletion voltage acquisition method in an embodiment of the present application.

[0040] BRIEF DESCRIPTION OF DRAWINGS

[0041] 1. first AlGaN / AlN / GaN heterostructure; 11, GaN layer of the first AlGaN / AlN / GaN heterostructure; 12, AlN layer of the first AlGaN / AlN / GaN heterostructure; 13, AlGaN layer of the first AlGaN / AlN / GaN heterostructure; 2, second AlGaN / AlN / GaN heterostructure; 21, GaN layer of the second AlGaN / AlN / GaN heterostructure; 22, AlN layer of the second AlGaN / AlN / GaN heterostructure; 23, AlGaN layer of the second AlGaN / AlN / GaN heterostructure; 3, third AlGaN / AlN / GaN heterostructure; 31, GaN layer of the third AlGaN / AlN / GaN heterostructure; 32, AlN layer of the third AlGaN / AlN / GaN heterostructure; 33, AlGaN layer of the third AlGaN / AlN / GaN heterostructure; 4, substrate; 5, nucleation layer; 6, buffer layer; 7, ohmic contact electrode; 8, Schottky contact electrode. DETAILED DESCRIPTION

[0042] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, the specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in many different ways from what is described herein, and should not be construed as being limited to the embodiments set forth herein, but should be understood to include all possible embodiments.

[0043] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are merely for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application.

[0044] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implying a specific number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0045] In the present application, unless otherwise specifically defined and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0046] In the present application, unless otherwise specifically defined and limited, the first feature "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0047] It is to be understood that when an element such as a layer, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] In order to make the objects, technical solutions and advantages of the present application clearer, the following further describes the present application with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0049] Two-dimensional electron gas (2DEG) exists in some heterostructures. For a semiconductor abrupt heterojunction, due to the existence of conduction band bottom energy mutation ΔEc, a "spike" and a "notch" appear near the interface; in fact, for the effect of the conduction band electrons in the heterojunction, the "spike" is the potential barrier for the electrons, and the "notch" is the potential well for the electrons. Therefore, in fact, the electric field in the "spike" has the effect of driving the electrons, i.e., forming a depletion layer; the electric field in the "notch" has the effect of driving holes and accumulating electrons, and under suitable conditions, an electron accumulation layer (i.e., a surface conductive channel) can be formed. If the depth of the "notch" potential well is large enough, the electrons in the "notch" can only move in the plane in all directions (i.e., move close to the heterojunction interface), i.e., two-dimensional motion of the electrons; further, if the effective mass concept is introduced, these electrons can be considered as classical free electrons, so that the electrons in the heterojunction potential well can be regarded as a "two-dimensional electron gas" (2DEG) with a certain effective mass.

[0050] Depletion layer, also known as depletion region, barrier layer, or potential barrier region, refers to a high-resistance region in the junction region where the number of charge carriers is very small under the dual influence of drift motion and diffusion. The width of the depletion layer is related to the properties of the material itself, temperature, and the size of the bias voltage. Under reverse bias, the voltage drop across the depletion region increases, most of the charge carriers are pushed away from the junction, leaving more charged ions, so the depletion region becomes wider, the electric field becomes stronger, increasing the drift component of the current and reducing the diffusion component. In this case, the carrier density (mainly minority carriers) is very small, and only a very small reverse saturation current flows.

[0051] The prior art for obtaining the depletion voltage of the two-dimensional electron gas channel when the electrons are depleted mostly follows the following approach. When the device is reverse biased, the width of the space charge region at the Schottky contact is completely determined by the applied DC bias voltage, so that a capacitance-voltage test can be used for a Schottky diode device, and the carrier distribution can be calculated from the resulting C-V characteristic curve. The relationship between the space charge region at the Schottky contact and the reverse bias voltage is the key to the capacitance-voltage test. The differential capacitance can be defined as formula (1):

[0052]

[0053] where Q m represents the amount of charge contained in the Schottky metal, and Q s represents the amount of charge contained in the semiconductor material. The negative sign indicates that when a reverse bias is applied to the Schottky diode, the semiconductor is negatively charged due to the ionization of the majority impurities, and at this time the total charge in the metal is positive. When actually performing the capacitance-voltage test on the device, a small AC signal is superimposed on the DC bias voltage, and the frequency range of this signal is generally 10 kHz to 1 MHz. Due to the different trapping lifetimes of the surface and interior of the semiconductor material, the C-V characteristic curves measured by different frequencies of the small AC signal will be different.

[0054] When using the differential capacitance-voltage method to obtain the concentration distribution of the majority carriers of the semiconductor material, the accurate value of the area of the Schottky metal needs to be known. Since the space charge region not only expands vertically but also expands laterally, the effective contact area of the Schottky metal and the semiconductor material is greater than the actual contact area when performing the C-V test. The effective capacitance can be represented as formula (2):

[0055]

[0056] where r is the radius of the Schottky contact. b is a parameter that has a value different for different semiconductor materials.

[0057] The relationship between the effective doping concentration and the actual doping concentration can be represented as formula (3):

[0058] N A,eff = N A (1+bW / r) 3

[0059] When r≥100bW, it can be ensured that the contribution of bW / r in the brackets of formula (2) to the effective value is less than 1%. Therefore, when the area of the Schottky contact is large enough, the influence of the edge capacitance on the test can be ignored. When the doping concentration of the semiconductor material is N, in order to ignore the influence of the edge capacitance, the minimum radius of the Schottky contact is shown in formula (4):

[0060] r min = 0.037 (N / 10 16 ) -0.35 cm

[0061] Under the condition of applying a reverse bias voltage to the Schottky contact electrode, if an AC small signal v is increased from 0 V to a small positive voltage, the amount of charge in the Schottky metal will increase by dQ m Meanwhile, the amount of charge in the semiconductor material will also increase by dQ s , and the absolute values of dQ m and dQ s are the same. The amount of charge in the semiconductor can be given by the following equation (5):

[0062]

[0063] where A is the area of the Schottky electrode. When acceptor impurities can all be completely ionized, and N D = 0, p ≈ n ≈ 0, the expression on the right side of equation (5) can be obtained. In addition, the distribution of deep energy levels in the band gap cannot be measured using this method. The increase in the width of the space charge region dW results in an increase in the amount of charge in the semiconductor material dQ s . Substituting equation (5) into equation (1) gives the following equation (6):

[0064]

[0065] In addition, if a semiconductor device with a Schottky contact is regarded as a parallel plate capacitor, the capacitance value C can be expressed as the following equation (7):

[0066]

[0067] where ε0 is the dielectric constant in a vacuum, and ε S is the dielectric constant of the semiconductor material.

[0068] Taking the differential of both sides of equation (7) with respect to V and substituting equation (6) gives the following equations (8) and (9):

[0069]

[0070]

[0071] In the process of calculating the distribution of majority carriers in the semiconductor material by using formula (8) and formula (9), the accurate Schottky metal area needs to be known. In addition, it needs to be noted that the distribution of majority carrier concentration is obtained by using formula (8) and formula (9), instead of the distribution of doping concentration. Finally, the position W of each 2DEG channel boundary is determined according to formula (9), and then the corresponding device capacitance value when the electrons in each channel are depleted is obtained according to formula (7), and finally the corresponding reverse bias voltage when the electrons in each channel are depleted is obtained according to formula (6).

[0072] Therefore, for the semiconductor device with multiple two-dimensional electron gas channels and Schottky contact electrodes, after the C-V (capacitance-voltage) characteristic curve is obtained by testing, the depletion voltage when the electrons in each channel are depleted needs to be obtained through multiple steps of calculation, which is complex and not intuitive and convenient.

[0073] To solve the above technical problems, the present application designs a depletion voltage acquisition method, which can quickly obtain the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted.

[0074] The present application designs a depletion voltage acquisition method for obtaining the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted, as shown in the formula (6), the depletion voltage acquisition method comprises the following steps: Figure 1

[0075] S1: obtaining the capacitance-reverse bias voltage characteristic curve of the semiconductor device;

[0076] S2: obtaining the second-order derivative of the capacitance with respect to the reverse bias voltage in the capacitance-reverse bias voltage characteristic curve, and obtaining the second-order derivative characteristic curve of the semiconductor device;

[0077] S3: obtaining the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted according to the second-order derivative characteristic curve of the semiconductor device.

[0078] The depletion voltage acquisition method in the present application first obtains the capacitance-reverse bias voltage characteristic curve of the semiconductor device by testing; then the second-order derivative of the capacitance with respect to the reverse bias voltage in the capacitance-reverse bias voltage characteristic curve is obtained, and the second-order derivative characteristic curve of the semiconductor device is obtained; the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted is obtained according to the second-order derivative characteristic curve of the semiconductor device, which is simple and intuitive, and can quickly obtain the depletion voltage when the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted.

[0079] In one embodiment, as shown in the formula (7), the capacitance-reverse bias voltage characteristic curve of the semiconductor device obtained in the present embodiment is shown. Figure 2

[0080] Referring to​​Figure 1 and in combination Figure 3 In one embodiment, the depletion voltage at which the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted is obtained according to a second derivative characteristic curve of the semiconductor device, comprising:

[0081] S31: a two-dimensional coordinate system is established, the abscissa of the two-dimensional coordinate system is the reverse bias voltage, the second derivative characteristic curve has a wave crest, and the second derivative characteristic curve has a plurality of intersection points with the abscissa of the two-dimensional coordinate system, and the intersection points are located on the two sides of the wave crest opposite to each other;

[0082] S32: the abscissa value of the intersection point adjacent to one side of the origin of the two-dimensional coordinate system of the wave crest is the depletion voltage at which the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted.

[0083] Specifically, the second derivative characteristic curve (d 2 C / dV 2 -V characteristic curve) is shown in FIG. 1. Figure 4 wherein d 2 C / dV 2 is the ordinate, in the embodiment, the second derivative characteristic curve has a plurality of intersection points with the abscissa of the two-dimensional coordinate system, and the intersection points are located on the two sides of the wave crest opposite to each other, each wave crest corresponds to a channel, and each wave crest has one intersection point on each side, and the abscissa value of the intersection point adjacent to one side of the origin of the two-dimensional coordinate system of the wave crest is the depletion voltage at which the electrons in the two-dimensional electron gas channel of the semiconductor device are depleted.

[0084] In one embodiment, in combination Figures 1 to 4 and in reference to Figure 5 and Figure 6 , the semiconductor device comprises an ohmic contact electrode 7 and a Schottky contact electrode 8; as shown in FIG. 2, a flowchart for obtaining the capacitance-reverse bias voltage characteristic curve of the semiconductor device is shown, and the method for obtaining the capacitance-reverse bias voltage characteristic curve of the semiconductor device comprises: Figure 5

[0085] S51: grounding the ohmic contact electrode 7 of the semiconductor device;

[0086] S52: applying a voltage to the Schottky contact electrode 8 of the semiconductor device;

[0087] S53: using a capacitance-voltage tester to test the capacitance-voltage characteristics of the semiconductor device to obtain the capacitance-reverse bias voltage characteristic curve.

[0088] In one embodiment, as shown in Figure 6 and Figure 7 , the semiconductor device further comprises:

[0089] ​A first AlGaN / AlN / GaN heterostructure 1 has a first two-dimensional electron gas channel at the interface between the AlN layer 12 and the GaN layer 11. A second AlGaN / AlN / GaN heterostructure 2 is located on the surface of the first AlGaN / AlN / GaN heterostructure 1, and a second two-dimensional electron gas channel is located at the interface between the AlN layer 22 and the GaN layer 21. A third AlGaN / AlN / GaN heterostructure 3 is located on the surface of the second AlGaN / AlN / GaN heterostructure 2 away from the first AlGaN / AlN / GaN heterostructure 1. On the surface, a third two-dimensional electron gas channel exists at the interface between the AlN layer 32 and the GaN layer 31 in the third AlGaN / AlN / GaN heterostructure 3; the difference between the electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel, and the electron concentration in the third two-dimensional electron gas channel is less than a preset value; the Schottky contact electrode 8 is located on the surface of the third AlGaN / AlN / GaN heterostructure 3 away from the second AlGaN / AlN / GaN heterostructure 2; the ohmic contact electrode 7 is located on the surface of the third AlGaN / AlN / GaN heterostructure 3 away from the second AlGaN / AlN / GaN heterostructure 2, and is located on the periphery of the Schottky contact electrode 8.

[0090] Specifically, such as Figure 6 As shown, in this embodiment, the surface shape of the ohmic contact electrode 7 is annular; the Schottky contact electrode 8 is located at the center of the annular shape of the ohmic contact electrode 7 and does not overlap with the ohmic contact electrode 7, and the surface shape of the Schottky contact electrode 8 can be circular.

[0091] In one embodiment, the electron concentrations in the first two-dimensional electron gas channel, the second two-dimensional electron gas channel, and the third two-dimensional electron gas channel are all the same.

[0092] Specifically, in order to make the electron concentration in the first two-dimensional electron channel, the electron concentration in the second two-dimensional electron channel, and the electron concentration in the third two-dimensional electron channel the same, and considering process error, the difference between the electron concentration in the first two-dimensional electron channel, the electron concentration in the second two-dimensional electron channel, and the electron concentration in the third two-dimensional electron channel should be as small as possible, that is, the preset value should be as small as possible.

[0093] It should be noted that the depletion voltage acquisition method of the present invention is not limited to the semiconductor devices applicable to the above embodiments, but is applicable to all other devices that meet the conditions.

[0094] Specifically, combining semiconductor device structures Figure 4In the second-order differential characteristic curve of the semiconductor device, the semiconductor device includes a first two-dimensional electron gas channel, a second two-dimensional electron gas channel and a third two-dimensional electron gas channel, each channel corresponds to a wave crest, and each wave crest has an intersection on each side, the horizontal coordinate value of the intersection on one side of the origin of the two-dimensional coordinate system is the depletion voltage when the electrons in the two-dimensional electron gas channel are depleted, that is, ① in the figure is the depletion voltage when the electrons in the first two-dimensional electron gas channel are depleted, ② is the depletion voltage when the electrons in the second two-dimensional electron gas channel are depleted, and ③ is the depletion voltage when the electrons in the third two-dimensional electron gas channel are depleted.

[0095] Please continue to refer to Figure 7 , Figure 7 is a schematic diagram of the first AlGaN / AlN / GaN heterostructure 1, the second AlGaN / AlN / GaN heterostructure 2 and the third AlGaN / AlN / GaN heterostructure 3 in the semiconductor device in the depletion voltage acquisition method of the application, in one embodiment, the thickness of the AlGaN layer 13 in the first AlGaN / AlN / GaN heterostructure 1 is the same as the thickness of the AlGaN layer 33 in the third AlGaN / AlN / GaN heterostructure 3, and both are less than the thickness of the AlGaN layer 23 in the second AlGaN / AlN / GaN heterostructure 2.

[0096] Specifically, the thickness of the AlGaN layer 13 in the first AlGaN / AlN / GaN heterostructure 1 and the thickness of the AlGaN layer 33 in the third AlGaN / AlN / GaN heterostructure 3 can include 6-10nm, for example, 6nm, 7nm, 8nm, 9nm or 10nm can be used; in this embodiment, the thickness of the AlGaN layer 13 in the first AlGaN / AlN / GaN heterostructure 1 and the thickness of the AlGaN layer 33 in the third AlGaN / AlN / GaN heterostructure 3 are both 8nm.

[0097] Specifically, the thickness of the AlGaN layer 23 in the second AlGaN / AlN / GaN heterostructure 2 can include 30-50nm, for example, 30nm, 35nm, 40nm, 45nm or 50nm can be used; in this embodiment, the thickness of the AlGaN layer 23 in the second AlGaN / AlN / GaN heterostructure 2 is 40nm.

[0098] Please continue to refer to Figure 7In one of the embodiments, the thickness of the GaN layer 11 in the first AlGaN / AlN / GaN heterostructure 1, the thickness of the GaN layer 21 in the second AlGaN / AlN / GaN heterostructure 2, and the thickness of the GaN layer 31 in the third AlGaN / AlN / GaN heterostructure 3 are the same; the thickness of the AlN layer 12 in the first AlGaN / AlN / GaN heterostructure 1, the thickness of the AlN layer 22 in the second AlGaN / AlN / GaN heterostructure 2, and the thickness of the AlN layer 32 in the third AlGaN / AlN / GaN heterostructure 3 are the same.

[0099] Specifically, the thickness of the GaN layer 11 in the first AlGaN / AlN / GaN heterostructure 1, the thickness of the GaN layer 21 in the second AlGaN / AlN / GaN heterostructure 2, and the thickness of the GaN layer 31 in the third AlGaN / AlN / GaN heterostructure 3 can include 8-12 nm, for example, 8 nm, 9 nm, 10 nm, 11 nm or 12 nm can be used; in this embodiment, the thickness of the GaN layer 11 in the first AlGaN / AlN / GaN heterostructure 1, the thickness of the GaN layer 21 in the second AlGaN / AlN / GaN heterostructure 2, and the thickness of the GaN layer 31 in the third AlGaN / AlN / GaN heterostructure 3 are all 10 nm.

[0100] Specifically, the thickness of the AlN layer 12 in the first AlGaN / AlN / GaN heterostructure 1, the thickness of the AlN layer 22 in the second AlGaN / AlN / GaN heterostructure 2, and the thickness of the AlN layer 32 in the third AlGaN / AlN / GaN heterostructure 3 can include 0.5-1.5 nm, for example, 0.5 nm, 0.8 nm, 1 nm, 1.2 nm or 1.5 nm can be used; in this embodiment, the thickness of the AlN layer 12 in the first AlGaN / AlN / GaN heterostructure 1, the thickness of the AlN layer 22 in the second AlGaN / AlN / GaN heterostructure 2, and the thickness of the AlN layer 32 in the third AlGaN / AlN / GaN heterostructure 3 are all 1 nm.

[0101] In one of the embodiments, the first AlGaN / AlN / GaN heterostructure 1, the second AlGaN / AlN / GaN heterostructure 2, and the third AlGaN / AlN / GaN heterostructure 3 are all unintentionally doped heterostructures, and the background carrier concentration of the first AlGaN / AlN / GaN heterostructure 1, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure 2, and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure 3 are all 0.5*10 16 cm -3 ~1.5*10 16 cm-3 .

[0102] Specifically, the background carrier concentration of the first AlGaN / AlN / GaN heterostructure 1, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure 2, and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure 3 can all be 0.5*10 16 cm -3 , 1*10 16 cm -3 , or 1.5*10 16 cm -3 , and the like.

[0103] Specifically, if the polarization charge at the AlGaN / GaN heterojunction interface considers both the spontaneous polarization effect and the piezoelectric polarization effect, and also considers the influence of piezoelectric polarization on the dielectric constant of the AlGaN / GaN heterojunction, then the total polarization intensity of the AlGaN / GaN heterojunction at the interface can be expressed as the following formula (10):

[0104]

[0105] Where a0 and a are the lattice constants of AlGaN and GaN, respectively; ε is the dielectric constant of AlGaN; n 2DEG is the concentration of electrons in the two-dimensional electron gas; ΔPSP is the difference between the spontaneous polarization intensity of GaN and the spontaneous polarization intensity of AlGaN; e ij and C ij are the piezoelectric coefficient and the elastic constant of AlGaN, respectively, i.e., e 31 and e 33 are the piezoelectric coefficients of AlGaN, and C 13 and C 33 are the elastic constants of AlGaN.

[0106] Then, the Poisson equation describing the charge distribution in the AlGaN / GaN heterostructure can be expressed as the following formula (11):

[0107]

[0108] Where ε 11 and ε 33 are the components of the dielectric constant in the form of a second-order tensor of the material in the direction perpendicular to the c-axis and in the direction parallel to the c-axis; represents the electrostatic potential; the charge ρ includes free charge and ionic charge; P is the polarization intensity; e 33 is the piezoelectric coefficient of AlGaN; C 33 is the elastic constant of AlGaN.

[0109] For AlGaN / GaN heterojunction material, there are a large number of negative polarization charges on the surface, if these negative polarization charges are not compensated by positive charges, the 2DEG near the AlGaN / GaN interface will be completely depleted. It is generally believed that these negative polarization charges are compensated by the donor-like surface states ionized on the surface of AlGaN / GaN heterojunction, and the ionized electrons gather near the AlGaN / GaN heterojunction interface to form 2DEG. In the present application, the surface donor state distribution n of the AlGaN / GaN heterojunction material is set as formula (11) shown below: surface The formula (12) is shown as follows:

[0110]

[0111] Wherein, n is the maximum value of the surface donor state density, n can be set to 0.5×10 16 cm -2 ·eV -1 ~1.5×10 16 cm -2 ·eV -1 , in the embodiment, n is preferably 1×10 16 cm -2 ·eV -1 ; E is the energy level; Eg is the band gap; CBM is the energy level of the conduction band bottom at the surface; E s determines the distribution range of the surface donor state, which can be set to 0.6; the highest energy level occupied by the surface donor state is set to 1eV below the conduction band bottom, that is, Φ c =1eV. By adjusting the thickness of each AlGaN barrier layer, the concentration of free electrons in the first two-dimensional electron gas channel, the second two-dimensional electron gas channel and the third two-dimensional electron gas channel at the AlN / GaN interface in the present application is close. For the first AlGaN / AlN / GaN heterostructure 1, the second AlGaN / AlN / GaN heterostructure 2 and the third AlGaN / AlN / GaN heterostructure 3 in the present application, they are all unintentionally doped heterostructures, so the semiconductor structure including the first AlGaN / AlN / GaN heterostructure 1, the second AlGaN / AlN / GaN heterostructure 2 and the third AlGaN / AlN / GaN heterostructure 3 can be an N-type semiconductor structure. The carrier distribution diagram of the semiconductor structure is shown in Figure 2 , and the corresponding energy band distribution diagram of the semiconductor structure is shown in Figure 3 ; wherein the background carrier concentration of the first AlGaN / AlN / GaN heterostructure 1, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure 2 and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure 3 can be 0.5×10 16 cm -3 ~1.5×1016 cm -3 between, specifically, the background carrier concentration of the first AlGaN / AlN / GaN heterostructure 1, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure 2 and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure 3 can be 0.5*10 16 cm -3 , 1*10 16 cm -3 or 1.5*10 16 cm -3 In the embodiment, the background carrier concentration of the first AlGaN / AlN / GaN heterostructure 1, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure 2 and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure 3 are preferably 1*10 16 cm -3 .

[0112] Please continue to refer to Figure 6 In one embodiment, the semiconductor device further comprises:

[0113] a substrate 4; a buffer layer 6, the buffer layer 6 is located on the substrate 4; a first AlGaN / AlN / GaN heterostructure 1 is located on the surface of the buffer layer 6 away from the substrate 4.

[0114] Specifically, the substrate 4 can include a silicon substrate, a silicon carbide substrate or a sapphire substrate; in the embodiment, the substrate 4 adopts a silicon carbide substrate.

[0115] Specifically, the buffer layer 6 can include a GaN layer or an AlN layer; in the embodiment, the buffer layer 6 adopts a GaN layer.

[0116] Specifically, the thickness of the buffer layer 6 can be between 2000-3000nm, for example, 2000nm, 2500nm or 3000nm can be adopted.

[0117] In one embodiment, the semiconductor device further comprises: a nucleation layer 5, the nucleation layer 5 is located between the substrate 4 and the buffer layer 6.

[0118] Specifically, the nucleation layer 5 can include a GaN layer or an AlN layer; in the embodiment, the nucleation layer 5 adopts an AlN layer.

[0119] The method for obtaining the depletion voltage in the application firstly obtains the capacitance-reverse bias voltage characteristic curve of the semiconductor device through testing; then the second order differential of the capacitance-reverse bias voltage characteristic curve can be obtained, and the second order differential characteristic curve of the semiconductor device can be obtained; according to the second order differential characteristic curve of the semiconductor device, the depletion voltage when the electrons in the two-dimensional electron gas channel are depleted can be obtained. This method is simple and intuitive, and can quickly obtain the depletion voltage when the electrons in the two-dimensional electron gas channel are depleted, which is convenient for researchers to use this method for rapid testing, accelerates the research and development progress, and improves the research and development competitiveness of enterprises.

[0120] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0121] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of depleting voltage acquisition, characterized by, The depletion voltage acquisition method is used to acquire the depletion voltage when electrons are depleted in a two-dimensional electron gas channel in a semiconductor device. The depletion voltage acquisition method includes: Obtain the capacitance-reverse bias voltage characteristic curve of the semiconductor device; Obtain the second derivative of the capacitance with respect to the reverse bias voltage in the capacitance-reverse bias voltage characteristic curve, and obtain the second derivative characteristic curve of the semiconductor device. Based on the second-order differential characteristic curve of the semiconductor device, the depletion voltage when electrons are depleted in the two-dimensional electron gas channel of the semiconductor device is obtained. The step of obtaining the depletion voltage when electrons are depleted in the two-dimensional electron gas channel of the semiconductor device based on the second-order differential characteristic curve of the semiconductor device includes: establishing a two-dimensional coordinate system, wherein the horizontal axis of the two-dimensional coordinate system is the reverse bias voltage, the second-order differential characteristic curve has a peak, and the second-order differential characteristic curve intersects the horizontal axis of the two-dimensional coordinate system at multiple points, the intersection points being located on opposite sides of the peak; the horizontal axis value of the intersection point on the side of the peak adjacent to the origin of the two-dimensional coordinate system is the depletion voltage when electrons are depleted in the two-dimensional electron gas channel of the semiconductor device.

2. The depletion voltage acquisition method of claim 1, wherein, The semiconductor device includes an ohmic contact electrode and a Schottky contact electrode; the method for obtaining the capacitance-reverse bias voltage characteristic curve of the semiconductor device includes: Ground the ohmic contact electrode of the semiconductor device; A voltage is applied to the Schottky contact electrode of the semiconductor device; The semiconductor device is subjected to capacitance-voltage characteristic testing using a capacitance-voltage tester to obtain the capacitance-reverse bias voltage characteristic curve.

3. The depletion voltage acquisition method according to claim 2, wherein The semiconductor device further includes: The first AlGaN / AlN / GaN heterostructure has a first two-dimensional electron gas channel at the interface between the AlN layer and the GaN layer. The second AlGaN / AlN / GaN heterostructure is located on the surface of the first AlGaN / AlN / GaN heterostructure, and a second two-dimensional electron gas channel exists at the interface between the AlN layer and the GaN layer in the second AlGaN / AlN / GaN heterostructure. The third AlGaN / AlN / GaN heterostructure is located on the surface of the second AlGaN / AlN / GaN heterostructure away from the first AlGaN / AlN / GaN heterostructure, and a third two-dimensional electron gas channel exists at the interface between the AlN layer and the GaN layer in the third AlGaN / AlN / GaN heterostructure. The difference between the electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel, and the electron concentration in the third two-dimensional electron gas channel is less than a preset value; The Schottky contact electrode is located on the surface of the third AlGaN / AlN / GaN heterostructure away from the second AlGaN / AlN / GaN heterostructure; and the ohmic contact electrode is located on the surface of the third AlGaN / AlN / GaN heterostructure away from the second AlGaN / AlN / GaN heterostructure and is located at the periphery of the Schottky contact electrode.

4. The depletion voltage acquisition method according to claim 3, wherein The thickness of the AlGaN layer in the first AlGaN / AlN / GaN heterostructure is the same as the thickness of the AlGaN layer in the third AlGaN / AlN / GaN heterostructure, and is less than the thickness of the AlGaN layer in the second AlGaN / AlN / GaN heterostructure.

5. The depletion voltage acquisition method of claim 4, wherein, The thickness of the GaN layer in the first AlGaN / AlN / GaN heterostructure, the thickness of the GaN layer in the second AlGaN / AlN / GaN heterostructure, and the thickness of the GaN layer in the third AlGaN / AlN / GaN heterostructure are the same; and the thickness of the AlN layer in the first AlGaN / AlN / GaN heterostructure, the thickness of the AlN layer in the second AlGaN / AlN / GaN heterostructure, and the thickness of the AlN layer in the third AlGaN / AlN / GaN heterostructure are the same.

6. The depletion voltage acquisition method of claim 3, wherein, The first AlGaN / AlN / GaN heterostructure, the second AlGaN / AlN / GaN heterostructure and the third AlGaN / AlN / GaN heterostructure are all unintentionally doped heterostructures, and the background carrier concentration of the first AlGaN / AlN / GaN heterostructure, the background carrier concentration of the second AlGaN / AlN / GaN heterostructure and the background carrier concentration of the third AlGaN / AlN / GaN heterostructure are all 0.5*10 16 cm -3 ~1.5*10 16 cm -3 ~2*10 7. The depletion voltage acquisition method of claim 3, wherein, The electron concentration in the first two-dimensional electron gas channel, the electron concentration in the second two-dimensional electron gas channel, and the electron concentration in the third two-dimensional electron gas channel are the same.

8. The depletion voltage acquisition method of claim 3, wherein, The semiconductor device further comprises: a substrate; a buffer layer located on the substrate; and 9. The depletion voltage acquisition method of claim 8, wherein, the first AlGaN / AlN / GaN heterostructure is located on the surface of the buffer layer away from the substrate. The semiconductor device further comprises a nucleation layer located between the substrate and the buffer layer.

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