Thermal processing method of silicon wafers using a horizontal heat treatment furnace

Abstract

Provided is a method for heat treating a silicon wafer using a horizontal heat treatment furnace, which can suppress metal contamination of a silicon wafer disposed in the vicinity of a heat retaining block provided for temperature uniformization of a wafer setting area. The method for heat treating a silicon wafer using a horizontal heat treatment furnace (100) of the present invention is configured to dispose a wafer boat (16) in a cylindrical furnace core tube (12), wherein (A) a wafer group (WF) is disposed on the wafer boat (16), (B) heat retaining blocks (a first heat retaining block (18A) and a second heat retaining block (18B)) are disposed on both sides of the wafer group (WF) in a direction of a central axis (X) of the furnace core tube on the wafer boat (16) so as to be apart from the wafer group (WF), and (C) pseudo wafers (20A, 20B, 20C, 20D) of high cleanliness are disposed on both sides of the first heat retaining block (18A) and the second heat retaining block (18B) in the direction of the central axis (X) of the furnace core tube on the wafer boat (16).

Description

Technical Field

[0001] This invention relates to a heat treatment method for silicon wafers using a horizontal heat treatment furnace. Background Technology

[0002] The process of thermally diffusing dopants such as phosphorus and boron into silicon wafers includes a process of attaching the dopants to the surface of the silicon wafer (precipitation) and a process of diffusing the dopants attached to the surface into the interior of the silicon wafer (diffusion). This diffusion process typically utilizes a horizontal heat treatment furnace (thermal diffusion furnace). In a horizontal heat treatment furnace, a boat containing multiple silicon wafers is placed inside a cylindrical core tube with a transverse central axis, with its main surface orthogonal to the central axis of the core tube. The silicon wafers are then heat-treated inside the core tube. A technique known to achieve temperature uniformity in the wafer arrangement area within the core tube is to place silicon-based insulating blocks (pseudo-blocks) on both sides of the multiple silicon wafers along the central axis of the core tube.

[0003] Patent Document 1 describes the following: "A method for heat treatment of a wafer, characterized in that, inside a tube of a thermal diffusion furnace, wafers are arranged side by side with their main surfaces orthogonal to the long side of the tube. When heat treatment is performed on the wafers in this state, on both sides of the homogenization zone before the wafers are placed inside the tube, on the side where the ambient gas flows in, there is a distance of at least 10 mm from the zone. Furthermore, on the side where the ambient gas flows out, heat-insulating blocks slightly smaller than the tube diameter are respectively arranged in close contact or separately (claim 1)." Furthermore, Patent Document 1 states that "the material of the heat-insulating blocks is high-purity silicon (claim 3)."

[0004] Patent document 1: Japanese Patent Application Publication No. 3-85725.

[0005] However, the inventors have discovered that when the same insulation block is reused in multiple heat treatment batches, the amount of metal contamination on the silicon wafers located at both ends of the multiple silicon wafers in each batch, i.e., the silicon wafers positioned near the insulation block, increases significantly with each batch. Metal-contaminated silicon wafers have a reduced lifespan and cannot be used as products, resulting in insufficient product yield. Therefore, it is desirable to suppress metal contamination on silicon wafers. Summary of the Invention

[0006] In view of the above problems, the object of the present invention is to provide a heat treatment method for silicon wafers using a horizontal heat treatment furnace, which can suppress metal contamination of silicon wafers near heat-insulating blocks disposed for temperature uniformity of the wafer setting area.

[0007] To address the aforementioned problems, the inventors conducted thorough research and made the following findings. First, the inventors believe that the increase in metal contamination on silicon wafers located near the insulation block may be due to metal contamination from the insulation block itself. Specifically, they believe that when the same insulation block is reused in multiple heat treatment cycles, metal contamination (Fe, Ni, Cu, etc.) from furnace core tubes, etc., gradually accumulates at the insulation block. During heat treatment, as the insulation block is heated, gases containing contaminating metals are generated from it. These contaminating gases diffuse and are supplied to the silicon wafers located near the insulation block. As a result, it is believed that the silicon wafers located near the insulation block are also contaminated with metal.

[0008] However, replacing the insulation block every time in multiple heat treatment batches is uneconomical. Furthermore, while considering performing a high-cleanliness treatment on the insulation block after each heat treatment batch (etching with a mixed acid solution of hydrofluoric acid and nitric acid, etc.) to remove contaminated metal, this is impractical for the following reasons: the insulation block is relatively thick, so fabricating a large etching tank to accommodate it would be costly; and etching a thick insulation block with a large surface area would result in excessive temperature rise during etching.

[0009] Therefore, the inventors conceived of placing highly clean dummy wafers on both sides of the insulation block along the central axis of the furnace core tube, thereby suppressing the diffusion of gases, including contaminated metals generated from the insulation block, to the silicon wafer disposed near the insulation block. Furthermore, various experimental results confirmed that by placing dummy wafers on both sides of the insulation block in this manner, the increase in metal contamination on the silicon wafer disposed near the insulation block can be suppressed.

[0010] The main solution of the present invention, based on the above findings, is as follows.

[0011] [1] A method for heat-treating silicon wafers using a horizontal heat treatment furnace, characterized in that a horizontal heat treatment furnace (100) is prepared, the horizontal heat treatment furnace (100) having a core tube (12) and a heater (14), the core tube (12) having a transverse central axis (X) and being cylindrical in shape, the heater (14) being positioned around the core tube (12) to heat the core tube (12), a cover (12A) being provided at one end of the core tube (12), and a gas inlet (12B) being provided at the other end of the core tube (12). A gas exhaust port (12C) is provided on the furnace wall near the aforementioned cover (12A) of the core tube (12). When the side of the aforementioned core tube (12) closer to the aforementioned cover (12A) is designated as the furnace opening side (H) and the side of the aforementioned core tube (12) closer to the aforementioned gas inlet (12B) is designated as the furnace inside side (S), the aforementioned cover (12A) is opened, and a crystal boat (16) is placed inside the aforementioned core tube (12) in the following states (A) to (C): (A) On the aforementioned crystal boat (16), multiple sheets are arranged in a manner in which the main surface is orthogonal (X) to the central axis of the aforementioned core tube (12). A silicon wafer is formed into a wafer group (WF). (B) A first insulating block with a cylindrical shape having an axis parallel to the central axis of the furnace core tube is disposed separately from the wafer group (WF) at a position on the furnace inner side (S) of the aforementioned wafer group (WF). A second insulating block (18B) with a cylindrical shape having an axis parallel to the central axis (X) of the aforementioned furnace core tube (12) is disposed separately from the wafer group (WF) at a position on the furnace opening side (H) of the aforementioned wafer group (WF). (C) The main surfaces of the two blocks are orthogonal to the central axis of the aforementioned furnace core tube (12). A first pseudo-wafer (20A) is positioned on the crystal boat (16) at a location closer to the furnace interior (S) than the first insulating block (18A). A second pseudo-wafer (20B) is positioned between the first insulating block (18A) and the wafer group (WF). A third pseudo-wafer (20C) is positioned between the second insulating block (18B) and the wafer group (WF). A fourth pseudo-wafer (20D) is positioned at a location closer to the furnace opening (H) than the second insulating block (18B). The Fe concentration of the first to fourth pseudo-wafers (20A, 20B, 20C, 20D) is less than 1×10⁻⁶. 11 atoms / cm 3 The concentrations of Ni and Cu are less than 5 × 10⁻⁶. 10 atoms / cm 3 The aforementioned cover (12A) is closed, gas is introduced into the aforementioned furnace core tube (12) through the aforementioned gas inlet (12B), the aforementioned gas is discharged through the aforementioned gas outlet (12C), and the aforementioned furnace core tube (12) is heated by the aforementioned heater (14), thereby performing heat treatment on the aforementioned multiple silicon wafers.

[0012] [2] In the heat treatment method of silicon wafer using a horizontal heat treatment furnace described above [1], the distance between the first heat-insulating block (18A) and the wafer group (WF) and the distance between the second heat-insulating block (18B) and the wafer group (WF) in the direction of the central axis (X) of the furnace core tube (12) are 5 mm or more.

[0013] [3] In the heat treatment method of silicon wafer using a horizontal heat treatment furnace described in [1] or [2] above, the distance between the first heat-insulating block (18A) and the first pseudo-wafer (20A), the distance between the first heat-insulating block (18A) and the second pseudo-wafer (20B), the distance between the second heat-insulating block (18B) and the third pseudo-wafer (20C), and the distance between the second heat-insulating block (18B) and the fourth pseudo-wafer (20D) in the direction of the central axis (X) of the furnace core tube (12) are less than 2 mm.

[0014] [4] In the heat treatment method of silicon wafer using a horizontal heat treatment furnace described above [3], the distances between the first heat-insulating block (18A) and the first pseudo-wafer (20A), the distances between the first heat-insulating block (18A) and the second pseudo-wafer (20B), the distances between the second heat-insulating block (18B) and the third pseudo-wafer (20C), and the distances between the second heat-insulating block (18B) and the fourth pseudo-wafer (20D) in the direction of the central axis (X) of the furnace core tube (12) are 0 mm.

[0015] [5] In any of the above [1] to [4] methods for heat treatment of silicon wafers using a horizontal heat treatment furnace, the first to fourth pseudo wafers (20A, 20B, 20C, 20D) are silicon wafers.

[0016] [6] In any of the above [1] to [5] methods for heat treatment of silicon wafers using a horizontal heat treatment furnace, the thickness of the first to fourth pseudo wafers (20A, 20B, 20C, 20D) is in the range of 1 to 5 mm.

[0017] [7] In any of the above [1] to [6] methods for heat treatment of silicon wafers using a horizontal heat treatment furnace, the diameters of the first to fourth pseudo wafers (20A, 20B, 20C, 20D) are equal to the diameters of the first and second heat preservation blocks (18A, 18B).

[0018] [8] In any of the above-mentioned [1] to [7] heat treatment methods for silicon wafers using a horizontal heat treatment furnace, the first and second heat-insulating blocks (18A, 18B) have a concentration of Fe, Ni, and Cu of 1×10⁻⁶. 11 atoms / cm 3 The above is composed of silicon.

[0019] [9] In any of the above [1] to [8] methods for heat treatment of silicon wafers using a horizontal heat treatment furnace, the diameters of the first and second heat-insulating blocks (18A, 18B) are equal to the diameters of the aforementioned plurality of silicon wafers.

[0020]

[10] In any of the above [1] to [9] heat treatment methods for silicon wafers using a horizontal heat treatment furnace, the width of the first and second heat insulation blocks (18A, 18B) along the central axis (X) of the furnace core tube (12) is in the range of 40 to 75 mm.

[0021]

[11] A method for manufacturing a silicon wafer, comprising the heat treatment method of the silicon wafer using a horizontal heat treatment furnace as described in any one of [1] to

[10] above.

[0022] Invention Effects

[0023] The heat treatment method for silicon wafers using a horizontal heat treatment furnace according to the present invention can suppress metal contamination of silicon wafers near heat-insulating blocks disposed for temperature uniformity of the wafer setting area. Attached Figure Description

[0024] Figure 1 This is a longitudinal sectional view of a horizontal heat treatment furnace 100 used to illustrate the heat treatment method for silicon wafers in a comparative example.

[0025] Figure 2 This is a longitudinal sectional view of a horizontal heat treatment furnace 100 used to illustrate a heat treatment method for silicon wafers according to an embodiment of the present invention.

[0026] Figure 3 (A) is a cross-sectional view perpendicular to the furnace center axis X of the crystal boat 16, and (B) is... Figure 2 Section II.

[0027] Figure 4 This is a chart showing the amount of Fe contamination in silicon wafers after heat treatment in Comparative Examples 1 and 2 and Invention Examples 1 to 4. Detailed Implementation

[0028] First, refer to Figure 1 and Figure 2 The structure of the horizontal heat treatment furnace 100 commonly used in the heat treatment methods for silicon wafers in the embodiments and comparative examples of the present invention will be described. The horizontal heat treatment furnace 100 includes a furnace core tube 12 and a heater 14.

[0029] The furnace core tube 12 is a cylindrical tube with a transverse central axis X. A cap 12A is provided at one end of the furnace core tube 12, and a gas inlet 12B is provided at the other end. Furthermore, a gas exhaust port 12C is provided on the furnace wall near the cap 12A of the furnace core tube 12. The inner diameter of the furnace core tube 12 (tube body) is generally in the range of 160~360mm. The furnace core tube 12 can be made of materials such as quartz or silicon carbide (SiC).

[0030] Heater 14 is located around furnace core tube 12 and heats furnace core tube 12. Heater 14 may also consist of a main heater located in the center of furnace core tube 12 and two auxiliary heaters located on both sides thereon.

[0031] like Figure 1 and Figure 2 As shown in this specification, the side of the cover 12A near the core tube 12 is referred to as "furnace opening side H", and the side of the gas inlet 12B near the core tube 12 is referred to as "furnace inlet side S".

[0032] in addition, Figure 1 and Figure 2 Although not illustrated, it could also be that a cylindrical heat spreader, made of quartz, silicon carbide (SiC), or the like, with a transverse central axis, is arranged around the core tube 12, with the core tube 12 located inside the heat spreader. In this case, a heater 14 is located around the core tube 12 and the heat spreader, and the heater 14 heats the heat spreader and the core tube 12.

[0033] In the heat treatment method for silicon wafers according to embodiments of the present invention, when performing heat treatment on silicon wafers, multiple silicon wafers are arranged and mounted in a wafer boat 16 to form a wafer group. The cover 12A of the furnace core tube 12 is opened, and the wafer boat 16 is placed into the furnace core tube 12 from the furnace opening side H. Afterwards, the cover 12A of the furnace core tube 12 is closed.

[0034] Subsequently, gas is introduced into the core tube 12 through the gas inlet 12B and discharged through the gas outlet 12C. The core tube 12 is then heated by the heater 14, thereby heat-treating multiple silicon wafers (wafer sets WF). In the case of a drive-in process that diffuses dopants adhering to the surface into the interior of the silicon wafer, the gas introduced into the core tube 12 includes trace amounts of oxygen (0.1~2 vol%), with the remainder consisting of Ar. Using a pump located outside the core tube 12, the gas is forcibly drawn from the core tube 12 through the gas outlet 12C, thereby discharging the atmospheric gas within the core tube 12. As a result, an atmospheric gas flow occurs within the core tube 12 from the furnace interior side S to the furnace opening side H. During the drive-in process, the atmospheric temperature within the core tube 12 can be in the range of 1200~1350°C and can be maintained within this range for 10~250 hours.

[0035] Crystal Boat 16 Figure 1 and Figure 2 Also refer to Figure 3 (A) has a groove 16A formed by a semi-cylindrical recess, where multiple silicon wafers are housed. The crystal boat 16 is positioned within the furnace core tube 12 with its long side aligned with the central axis X direction of the furnace core tube 12. For example... Figure 3 As shown in (A), the groove 16A, which is perpendicular to the long side of the crystal boat 16, has a semi-circular shape with the same radius of curvature as the silicon wafer it contains. For example, if the diameter of the silicon wafer is 150 mm, the radius of curvature is 75 mm. The crystal boat 16 can be made of silicon carbide (SiC).

[0036] In the heat treatment method for silicon wafers according to embodiments of the present invention, when the crystal boat 16 is placed inside the furnace core tube 12, the following states (A) to (C) are satisfied.

[0037] (A) First, as Figure 1 and Figure 2 As shown, multiple silicon wafers of the same diameter are arranged on the wafer boat 16 with their main faces orthogonal to the central axis X of the furnace core tube 12, forming a wafer group WF. The arrangement of the multiple silicon wafers is not particularly limited as long as they are configured so that none of the wafers are upside down. For example, a batch (e.g., 50 wafers) of silicon wafers can be arranged with the main faces of adjacent silicon wafers in contact with each other. Figure 1 and Figure 2 The example shown illustrates a configuration of four batches of silicon wafers. Furthermore, by arranging spacers (not shown) perpendicular to the long side of the groove 16A at equal intervals within the groove 16A, each batch of silicon wafers (WF) is housed within the groove 16A without tilting. However, this arrangement is not limited to this method; all silicon wafers housed within the groove 16A can also be arranged with their main surfaces in contact with each other. In this embodiment, the lower half of each silicon wafer contacts the groove 16A and is supported, while the upper half is located slightly above the upper end of the groove 16A, i.e., slightly above the wafer boat 16. However, the area of ​​contact between the silicon wafer and the groove 16A is not limited to the lower half, as long as it does not obstruct the upright position of each wafer.

[0038] (B) A first insulating block 18A, cylindrical in shape with an axis parallel to the central axis X of the furnace core tube 12, is disposed on the wafer boat 16 at a position S closer to the furnace interior than the wafer group WF. A second insulating block 18B, cylindrical in shape with an axis parallel to the central axis X of the furnace core tube 12, is disposed at a position H closer to the furnace opening than the wafer group WF. Without these first and second insulating blocks 18A and 18B, the furnace atmosphere temperature at both ends of the wafer placement area in the central axis X direction within the furnace core tube 12 decreases, and the homogenization length within the furnace core tube 12 becomes shorter. In this case, impurity diffusion at the silicon wafers located at both ends of the multiple silicon wafers is insufficient. In contrast, by arranging the first and second insulating blocks 18A and 18B, the homogenization length within the furnace core tube 12 can be lengthened, and temperature homogenization of the wafer placement area within the furnace core tube 12 can be achieved.

[0039] From the viewpoint of fully achieving temperature uniformity in the wafer setting area within the furnace core tube 12, the first and second insulation blocks 18A and 18B are preferably made of silicon.

[0040] Furthermore, from the same perspective, the diameters of the first and second insulation blocks 18A and 18B are preferably equal to the diameters of the multiple silicon wafers constituting the wafer assembly WF. For example, if the diameter of the silicon wafers is 150 mm, the diameters of the first and second insulation blocks 18A and 18B are also preferably 150 mm. In this embodiment, as... Figure 3 As shown in (B), the lower halves of the first and second insulation blocks 18A and 18B are supported by contact groove 16A, while the upper halves are located above the upper end of groove 16A, i.e., above crystal boat 16. However, the contact range between the first and second insulation blocks 18A and 18B and groove 16A is not limited to the lower halves as long as it does not obstruct the uprightness of each insulation block.

[0041] From the viewpoint of fully achieving temperature uniformity in the wafer arrangement area within the furnace core tube 12, the width of the first and second insulation blocks 18A and 18B along the central axis X of the furnace core tube 12 is preferably 40 mm or more. On the other hand, if the insulation blocks are too long, the product processing area in the heat spreader will be reduced, resulting in decreased productivity. Therefore, the width of the first and second insulation blocks 18A and 18B along the central axis X of the furnace core tube 12 is preferably 75 mm or less.

[0042] The distance (separation distance) between the first insulation block 18A and the wafer group WF, and the distance (separation distance) between the second insulation block 18B and the wafer group WF in the direction of the central axis X of the furnace core tube 12 are preferably 5 mm or more. This is because if the distance is less than 5 mm, there is a possibility of contamination at the wafer group WF, which is the product. Furthermore, this distance is preferably 10 mm or less. This is because if the distance exceeds 10 mm, the number of silicon wafers that can be set up as the product is limited, and productivity is hindered.

[0043] Regarding the first and second insulation blocks 18A and 18B, in this embodiment, the same insulation block is reused in multiple batches of heat treatment without replacement or high-cleanliness treatment (etching treatment based on a mixed acid solution of hydrofluoric acid and nitric acid, etc.). The reason for this is as explained. In this case, metal contamination, believed to originate from furnace core tubes, gradually accumulates in the insulation block. In the silicon of the first and second insulation blocks 18A and 18B, at least one of the concentrations of Fe, Ni, and Cu is 1 × 10⁻⁶. 11 atoms / cm 3 When the concentrations of all transition metals are 1×10⁻⁶, or when the concentrations of all transition metals are 1×10⁻⁶, the concentrations of all transition metals are 1×10⁻⁶. 11 atoms / cm 3 When doing the above, there are concerns about metal contamination from the insulation blocks.

[0044] In this case, Figure 1 In the comparative example of the silicon wafer heat treatment method shown, during multiple batches of heat treatment, gases containing contaminated metals generated from the first and second insulation blocks 18A and 18B are supplied to the silicon wafers disposed near the insulation blocks as the batches pass through. As a result, the silicon wafers disposed near the first and second insulation blocks 18A and 18B are also contaminated with metal, and their lifetime value decreases. Silicon wafers with lifetime values ​​below a predetermined value cannot be used as products, resulting in insufficient product yield.

[0045] (C) Therefore, in this invention, it is important to set up high-cleanliness pseudo-wafers 20A, 20B, 20C, and 20D on both sides of the first and second insulation blocks 18A and 18B in the X direction of the central axis of the furnace core tube 12.

[0046] This implementation method is in Figure 2 express. Figure 2In this embodiment, a first pseudo-wafer 20A is positioned on the crystal boat 16, on the inner side S of the first insulation block 18A, with its main surface orthogonal to the central axis X of the furnace core tube 12. A second pseudo-wafer 20B is positioned between the first insulation block 18A and the wafer group WF. A third pseudo-wafer 20C is positioned between the second insulation block 18B and the wafer group WF. A fourth pseudo-wafer 20D is positioned on the furnace opening side H of the second insulation block 18B. In this embodiment, gases containing contaminating metal generated from the first insulation block 18A are blocked by the first and second pseudo-wafers 20A and 20B, making it difficult to supply them to the wafer group WF. Furthermore, gases containing contaminating metal generated from the second insulation block 18B are blocked by the third and fourth pseudo-wafers 20C and 20D, making it difficult to supply them to the wafer group WF. As a result, metal contamination of the silicon wafers disposed near the first and second insulation blocks 18A and 18B can be suppressed. In particular, in this embodiment, it is important to provide dummy wafers on both sides of each insulation block 18A and 18B in the X direction of the central axis of the furnace core tube 12. This effectively suppresses the diffusion of gases, including contaminating metals generated from each insulation block.

[0047] From the viewpoint of more effectively suppressing the diffusion of gases, including those contaminating the metal, the distances between the first insulating block 18A and the first pseudo-wafer 20A, the distance between the first insulating block 18A and the second pseudo-wafer 20B, the distance between the second insulating block 18B and the third pseudo-wafer 20C, and the distance between the second insulating block 18B and the fourth pseudo-wafer 20D in the direction of the central axis X of the furnace core tube 12 are preferably 2 mm or less. Furthermore, these distances refer to "distances away".

[0048] From the viewpoint of further suppressing the diffusion of gases including contaminating metals, these distances are 0 mm, that is, the first and second pseudo wafers 20A and 20B are preferably in contact with the first insulation block 18A, and the third and fourth pseudo wafers 20C and 20D are preferably in contact with the second insulation block 18B.

[0049] Furthermore, the first to fourth pseudo wafers 20A, 20B, 20C, and 20D can each be a single pseudo wafer, or multiple pseudo wafers (e.g., 2 to 3 wafers) spaced apart from each other. When the first to fourth pseudo wafers 20A, 20B, 20C, and 20D are each composed of multiple pseudo wafers, the distance between adjacent pseudo wafers is preferably in the range of 0 to 2 mm.

[0050] From the viewpoint of not hindering the temperature uniformity of the wafer setting area within the furnace core tube 12, the first to fourth pseudo wafers 20A, 20B, 20C, and 20D are preferably silicon wafers.

[0051] The thickness of the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D is preferably within the range of 1 to 5 mm. This is because if the thickness is less than 1 mm, the pseudo-wafers may have difficulty standing on their own, and if the thickness exceeds 5 mm, the number of silicon wafers that can be used as products is limited, hindering productivity.

[0052] The diameters of the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D are preferably equal to the diameters of the first and second insulation blocks 18A and 18B. For example, if the diameters of the first and second insulation blocks 18A and 18B are 150 mm, the diameters of the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D are also preferably 150 mm. In this embodiment, as... Figure 3 As shown in (B), the lower half of each pseudo wafer 20A, 20B, 20C, and 20D is in contact with and supported by the groove 16A, while the upper half is located slightly above the upper end of the groove 16A, i.e., slightly above the crystal boat 16. However, the contact area between each pseudo wafer 20A, 20B, 20C, and 20D and the groove 16A is not limited to the lower half, as long as it does not obstruct the upright position of each pseudo wafer.

[0053] From the perspective of preventing metal contamination of silicon wafers located near insulation blocks 18A and 18B, the first to fourth pseudo wafers 20A, 20B, 20C, and 20D require high cleanliness; specifically, the Fe concentration needs to be less than 1 × 10⁻⁶. 11 atoms / cm 3 The concentrations of Ni and Cu need to be less than 5 × 10⁻⁶ respectively. 10 atoms / cm 3 More preferably, the concentrations of Fe, Ni, and Cu are less than 5 × 10⁻⁶. 10 atoms / cm 3 Further preferably, the concentrations of all transition metal elements are less than 5 × 10⁻⁶. 10 atoms / cm 3 The optimal concentration is less than 1×10⁻⁶ for each of the transition metal elements. 10 atoms / cm 3 .

[0054] The concentration of transition metal elements in the insulation block and the pseudo wafer can be determined by dissolving the surface layer of the insulation block and the pseudo wafer with acid, and then measuring the element concentration in the solution using ICP-MS or similar methods.

[0055] In this embodiment, during multiple heat treatment batches, the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D all require high cleanliness. Therefore, the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D are replaced with high-cleanliness pseudo-wafers in each batch, or a high-cleanliness treatment is performed on the used pseudo-wafers for each batch to remove transition metal elements. Specifically, transition metal elements are removed from the used pseudo-wafers by means of an etching process based on a mixed acid solution of hydrofluoric acid and nitric acid. As explained, the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D are smaller in size than the first and second insulation blocks 18A and 18B, making high-cleanliness treatment easy for all of them.

[0056] The silicon wafer manufacturing method according to embodiments of the present invention is characterized by including the above-described heat treatment method for silicon wafers using a horizontal heat treatment furnace according to embodiments of the present invention. For example, one embodiment of the silicon wafer manufacturing method includes a step of thermally diffusing dopants such as phosphorus and boron into a silicon wafer. This step includes a step of attaching the dopants to the surface layer of the silicon wafer (precipitation) and a step of diffusing the dopants attached to the surface layer into the interior of the silicon wafer (driving). In this driving step, the above-described heat treatment method for silicon wafers using a horizontal heat treatment furnace according to embodiments of the present invention can be employed. Example

[0057] Prepare with Figure 1 The diagram shows a horizontal heat treatment furnace with a structure. The furnace core tube, made of SiC, has an inner diameter of 220 mm. Furthermore, preparation... Figure 3 (A) shows the structure of the crystal boat. The groove of the crystal boat is a semi-cylindrical recess with a radius of 75 mm. A batch (50 sheets) of p-type silicon wafers with a diameter of 150 mm are prepared to be attached to the surface with phosphor glass. The silicon wafers are placed on the crystal boat with their main faces orthogonal to the central axis of the furnace core tube and adjacent to each other to form a wafer group.

[0058] A first insulating block, cylindrical in shape with an axis parallel to the central axis of the furnace core tube, is positioned on the wafer boat, closer to the furnace interior (S) than the wafer group and away from the wafer group. A second insulating block, also cylindrical in shape with an axis parallel to the central axis of the furnace core tube, is positioned on the furnace opening (H) than the wafer group and away from the wafer group. Each insulating block is a cylindrical silicon ingot with a diameter of 150 mm and a width of 40 mm, cut from a single-crystal silicon ingot manufactured by the CZ method. However, each insulating block is reused in multiple batches of heat treatment without being replaced or washed. Therefore, the concentration of transition metal elements in the insulating blocks used under the same conditions is determined according to the previously described method, with an Fe concentration of 2 × 10⁻⁶. 11 atoms / cm 3 The Ni concentration is 1×10 11 atoms / cm 3Cu concentration less than 5×10 10 atoms / cm 3 (Only when Cu is insufficient to detect the lower limit).

[0059] about Figure 2 The setup of the first to fourth pseudo wafers 20A, 20B, 20C, and 20D shown was performed under the following six conditions (Comparative Examples 1 and 2, and Invention Examples 1 to 4). The first to fourth pseudo wafers were silicon wafers with a diameter of 150 mm and a thickness of 1.2 mm cut from single-crystal silicon ingots manufactured by the CZ method, and subjected to the previously described high-cleanliness treatment. Therefore, for each pseudo wafer, the concentration of transition metal elements was measured using the previously described method, and the Fe concentration was less than 1 × 10⁻⁶. 11 atoms / cm 3 The Ni and Cu concentrations are both less than 5 × 10⁻⁶. 10 atoms / cm 3 The values ​​were all below the detection limit.

[0060] (Comparative Example 1)

[0061] Do not set pseudo wafers 20A, 20B, 20C, and 20D from the first to the fourth. Set the distance between the first insulation block 18A and the wafer group WF, and the distance between the second insulation block 18B and the wafer group WF to 4.2mm.

[0062] (Comparative Example 2)

[0063] The first and fourth pseudo-wafers 20A and 20D are not set; only the second and third pseudo-wafers 20B and 20C are set. The distance between the second pseudo-wafer 20B and the first insulation block 18A, and the distance between the third pseudo-wafer 20C and the second insulation block 18B, are set to 0.1 mm. The distance between the second pseudo-wafer 20B and the wafer set WF, and the distance between the third pseudo-wafer 20C and the wafer set WF, are both 4.2 mm. Therefore, the distance between the first insulation block 18A and the wafer set WF, and the distance between the second insulation block 18B and the wafer set WF, are 0.1 + 1.2 + 4.2 = 5.5 mm.

[0064] (Example 1 of the invention)

[0065] One pseudo-wafer each of the first to fourth pseudo-wafers 20A, 20B, 20C, and 20D is set up. The distance between the first and second pseudo-wafers 20A and 20B and the first insulation block 18A, and the distance between the third and fourth pseudo-wafers 20C and 20D and the second insulation block 18B, is 0.1 mm. The distance between the second pseudo-wafer 20B and the wafer group WF, and the distance between the third pseudo-wafer 20C and the wafer group WF, are both 4.2 mm. Therefore, the distance between the first insulation block 18A and the wafer group WF, and the distance between the second insulation block 18B and the wafer group WF, are both 0.1 + 1.2 + 4.2 = 5.5 mm.

[0066] (Example 2 of the invention)

[0067] Two pseudo-wafers 20A, 20B, 20C, and 20D are each set up. The distances between the first and second pseudo-wafers 20A and 20B closest to the first insulation block 18A and the first insulation block 18A, and the distances between the third and fourth pseudo-wafers 20C and 20D closest to the second insulation block 18B and the second insulation block 18B, are set to 0.1 mm. The distance between adjacent pseudo-wafers is also 0.1 mm. The distances between the second pseudo-wafer 20B closest to the wafer group and the wafer group WF, and the distances between the third pseudo-wafer 20C closest to the wafer group WF and the wafer group WF, are both 4.2 mm. Therefore, the distance between the first insulation block 18A and the wafer group WF, and the distance between the second insulation block 18B and the wafer group WF, are (0.1 + 1.2) × 2 + 4.2 = 6.8 mm.

[0068] (Example 3 of the invention)

[0069] Three pseudo-wafers 20A, 20B, 20C, and 20D are each set up. The distances between the first and second pseudo-wafers 20A and 20B closest to the first insulation block 18A and the first insulation block 18A, and the distances between the third and fourth pseudo-wafers 20C and 20D closest to the second insulation block 18B and the second insulation block 18B, are set to 0.1 mm. The distance between adjacent pseudo-wafers is also 0.1 mm. The distances between the second pseudo-wafer 20B closest to the wafer group and the wafer group WF, and the distances between the third pseudo-wafer 20C closest to the wafer group WF and the wafer group WF, are all 4.2 mm. Therefore, the distance between the first insulation block 18A and the wafer group WF, and the distance between the second insulation block 18B and the wafer group WF, are (0.1 + 1.2) × 3 + 4.2 = 8.1 mm.

[0070] (Example 4 of the invention)

[0071] Three pseudo-wafers 20A, 20B, 20C, and 20D are each set up. The distances between the first and second pseudo-wafers 20A and 20B closest to the first insulation block 18A and the first insulation block 18A, and the distances between the third and fourth pseudo-wafers 20C and 20D closest to the second insulation block 18B and the second insulation block 18B are set to 0 mm. The distance between adjacent pseudo-wafers is set to 0.1 mm. The distances between the second pseudo-wafer 20B closest to the wafer group and the wafer group WF, and the distances between the third pseudo-wafer 20C closest to the wafer group WF and the wafer group WF are both set to 4.2 mm. Therefore, the distance between the first insulation block 18A and the wafer group WF, and the distance between the second insulation block 18B and the wafer group WF are (0.1 + 1.2) × 3 - 0.1 + 4.2 = 8.0 mm.

[0072] In Comparative Examples 1 and 2 and Invention Examples 1-4, a crystal boat is placed inside a furnace core tube for heat treatment of the drive-in process. The gas introduced into the furnace core tube includes 0.5% oxygen by volume, with the remainder consisting of Ar. The atmosphere temperature inside the heat spreader is 1300°C and is maintained at this temperature for 230 hours.

[0073] [Determination of Metal Pollution Levels]

[0074] After heat treatment, the silicon wafers closest to the furnace interior and closest to the furnace opening were designated as "monitor wafers." The Fe concentration of these monitor wafers was measured using the SPV (Surface Photo-Voltage) method. The results were then displayed in [the relevant section]. Figure 4 express.

[0075] according to Figure 4 It can be seen that the Fe contamination level in Invention Examples 1-4 was suppressed to a sufficiently low level compared to Comparative Examples 1 and 2.

[0076] Industrial availability

[0077] The heat treatment method for silicon wafers using a horizontal heat treatment furnace of the present invention can be appropriately applied to the diffusion heat treatment of dopants such as phosphorus and boron from the surface layer to the interior of the silicon wafer.

[0078] Explanation of reference numerals in the attached figures

[0079] 100 Horizontal Heat Treatment Furnace

[0080] 12 furnace core tubes

[0081] 12A cover

[0082] 12B Gas Inlet

[0083] 12C gas exhaust port

[0084] 14 heaters

[0085] 16 Crystal Boats

[0086] 16A Slot

[0087] 18S First Insulation Block

[0088] 18H Second Insulation Block

[0089] 20A First Pseudo Wafer

[0090] 20B No. 2 pseudo wafer

[0091] 20C Third Pseudo Wafer

[0092] 20D 4th pseudo wafer

[0093] S-furnace inner side (gas inflow side)

[0094] H furnace opening side (gas outflow side)

[0095] WF wafer set (multiple silicon wafers)

[0096] The central axis of the X-shaped furnace core tube.

Claims

1. A method for heat treatment of silicon wafers using a horizontal heat treatment furnace, characterized in that, A horizontal heat treatment furnace is prepared, comprising a furnace core tube and a heater. The furnace core tube has a transverse central axis and is cylindrical in shape. The heater is located around the furnace core tube to heat it. A cover is provided at one end of the furnace core tube, and a gas inlet is provided at the other end of the furnace core tube. A gas exhaust port is provided on the furnace wall near the cover of the furnace core tube. When the side of the aforementioned furnace core tube closer to the aforementioned cover is designated as the furnace opening side, and the side of the aforementioned furnace core tube closer to the aforementioned gas inlet is designated as the furnace inner side, the aforementioned cover is opened, and a crystal boat is placed inside the aforementioned furnace core tube, resulting in the following states A to C. On the aforementioned crystal boat, multiple silicon wafers are arranged in a manner where their main faces are orthogonal to the central axis of the aforementioned furnace core tube, forming a wafer group. B is located on the aforementioned crystal boat, at a position closer to the furnace side than the aforementioned wafer group, with a first cylindrical heat-insulating block having an axis parallel to the central axis of the aforementioned furnace core tube, positioned away from the aforementioned wafer group. B is located at a position closer to the furnace opening side than the aforementioned wafer group, with a second cylindrical heat-insulating block having an axis parallel to the central axis of the aforementioned furnace core tube, positioned away from the aforementioned wafer group. The aforementioned first and second insulation blocks are composed of Fe, Ni, and Cu with a concentration of 1×10⁻⁶. 11 atoms / cm 3 The above is composed of silicon. C, with its main face orthogonal to the central axis of the aforementioned furnace core tube, places a first pseudo-wafer on the aforementioned crystal boat at a position closer to the furnace interior than the aforementioned first insulation block; places a second pseudo-wafer between the aforementioned first insulation block and the aforementioned wafer group; places a third pseudo-wafer between the aforementioned second insulation block and the aforementioned wafer group; and places a fourth pseudo-wafer at a position closer to the furnace opening than the aforementioned second insulation block. The Fe concentration of the aforementioned first to fourth pseudo-wafers is less than 1×10⁻⁶. 11 atoms / cm 3 The concentrations of Ni and Cu are less than 5 × 10⁻⁶. 10 atoms / cm 3 , Close the aforementioned cover. Gas is introduced into the furnace core tube through the aforementioned gas inlet, and the aforementioned gas is discharged through the aforementioned gas outlet. The furnace core tube is heated by the aforementioned heater, thereby performing heat treatment on the aforementioned multiple silicon wafers.

2. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1, characterized in that, The distance between the first insulation block and the wafer assembly and the distance between the second insulation block and the wafer assembly along the central axis of the furnace core tube are 5 mm or more.

3. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1 or 2, characterized in that, The distances between the first insulating block and the first pseudo-wafer, the first insulating block and the second pseudo-wafer, the second insulating block and the third pseudo-wafer, and the second insulating block and the fourth pseudo-wafer along the central axis of the furnace core tube are less than 2 mm.

4. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 3, characterized in that, The distances between the first insulating block and the first pseudo-wafer, the first insulating block and the second pseudo-wafer, the second insulating block and the third pseudo-wafer, and the second insulating block and the fourth pseudo-wafer along the central axis of the furnace core tube are 0 mm.

5. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1 or 2, characterized in that, The aforementioned pseudo wafers 1 to 4 are silicon wafers.

6. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1 or 2, characterized in that, The thickness of the aforementioned first to fourth pseudo wafers is in the range of 1 to 5 mm.

7. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1 or 2, characterized in that, The diameters of the aforementioned first to fourth pseudo wafers are equal to the diameters of the aforementioned first and second insulation blocks.

8. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1 or 2, characterized in that, The diameters of the aforementioned first and second insulation blocks are equal to the diameters of the aforementioned multiple silicon wafers.

9. The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in claim 1 or 2, characterized in that, The width of the first and second insulation blocks along the central axis of the furnace core tube is in the range of 40 to 75 mm.

10. A method for manufacturing a silicon wafer, characterized in that, The heat treatment method for silicon wafers using a horizontal heat treatment furnace as described in any one of claims 1 to 9.

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