Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device of the present invention includes: a heat sink; a semiconductor element joined to the heat sink via a first bonding material; a first lead frame joined to the heat sink via a second bonding material; a second lead frame joined to the semiconductor element via a third bonding material; and a molding resin, wherein in a cross-sectional shape obtained by cutting a boundary portion of the third bonding material and the molding resin with a plane perpendicular to one surface of the heat sink, of two angles formed by a straight line connecting end points of a bonding surface between the third bonding material and the semiconductor element and end points of a bonding surface between the third bonding material and the second lead frame and one surface of the semiconductor element, the angle on the third bonding material side is greater than 90° and less than 135°.

Description

Technical Field

[0001] The present application relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In recent years, semiconductor devices equipped with power semiconductor elements have been promoted to have larger capacities. Since a large current flows through the semiconductor element, it is necessary to enlarge the lead frame that serves as the main terminal connected to the semiconductor element via the bonding material. As the lead frame is enlarged, the thermal deformation force on the semiconductor element increases due to the difference in linear expansion coefficients of the semiconductor element, the lead frame and the bonding material. When the thermal deformation force increases, cracks sometimes occur in the semiconductor element. In order to reduce the thermal deformation force, a structure in which the semiconductor element, the lead frame and the bonding material are sealed with resin is generally adopted.

[0003] As semiconductor devices in which semiconductor elements, lead frames, and bonding materials are sealed with resin, transfer molded semiconductor devices sealed with thermosetting molding resins such as epoxy resins and gel-sealed semiconductor devices sealed with gel-like resins are used. In particular, transfer molded semiconductor devices are small and have excellent reliability, and therefore are widely used in power control and the like.

[0004] In addition to the structure of sealing the semiconductor element, lead frame and bonding material with a molding resin, in order to further suppress cracks generated in the semiconductor element, a structure is disclosed in which the thickness of the electrode of the main terminal bonded to the semiconductor element is locally thinned (for example, see Patent Document 1). By locally thinning the thickness of the electrode of the main terminal bonded to the semiconductor element, the thermal deformation force generated on the semiconductor element can be reduced, and the generation of cracks in the semiconductor element can be further suppressed.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2008-16529 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] In the above-mentioned Patent Document 1, the generation of cracks in the semiconductor element caused by the thermal deformation force generated on the semiconductor element can be further suppressed. However, since the electrode thickness of the main terminal joined to the semiconductor element is locally thinned, there is a problem that the structure of the main terminal becomes complicated, and it is difficult to achieve miniaturization and cost reduction of the semiconductor device. In addition, when more than two semiconductor elements are installed inside the resin-sealed semiconductor device, there is a problem that the electrode structure of the main terminal becomes more complicated and large-scale, and it is difficult to further achieve miniaturization and cost reduction of the semiconductor device.

[0010] Therefore, an object of the present application is to obtain a resin-sealed semiconductor device that can easily suppress the occurrence of cracks in a semiconductor element while achieving miniaturization and cost reduction.

[0011] Technical means for solving technical problems

[0012] The semiconductor device disclosed in the present application includes: a heat sink formed in a plate shape; a semiconductor element formed in a plate shape, the other surface of which is bonded to one surface of the heat sink via a first bonding material; a first lead frame, the other surface of which is bonded to one surface of the heat sink via a second bonding material; a second lead frame, the other surface of which is bonded to one surface of the semiconductor element via a third bonding material; and a molding resin, the molding resin exposing a portion of the first lead frame and a portion of the second lead frame to the outside, and sealing the heat sink, the semiconductor element, the first lead frame, and the second lead frame, wherein a boundary between the third bonding material and the molding resin is provided in a gap between one surface of the semiconductor element and another surface of the second lead frame, and in a cross-sectional shape obtained by cutting the boundary portion with a plane perpendicular to one surface of the heat sink, of two angles formed by a straight line connecting an end point of a bonding surface between the third bonding material and the semiconductor element and an end point of a bonding surface between the third bonding material and the second lead frame, and one surface of the semiconductor element, an angle on the third bonding material side is not less than 90° and not more than 135°.

[0013] Effects of the Invention

[0014] According to the semiconductor device disclosed in the present application, in the cross-sectional shape obtained after cutting the boundary portion of the third bonding material and the molding resin with a plane perpendicular to one surface of the heat sink, the angle formed by the straight line connecting the end points of the bonding surface of the third bonding material and the semiconductor element and the end points of the bonding surface of the third bonding material and the second lead frame and one surface of the semiconductor element, the angle on the third bonding material side is greater than 90° and less than 135°. Therefore, the structure of the second lead frame serving as the main terminal will not be complicated and enlarged, and the maximum stress at the maximum stress generating portion of the semiconductor element can be reduced. Therefore, the occurrence of cracks in the semiconductor element can be easily suppressed, and the miniaturization and low cost of the resin-sealed semiconductor device can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a plan view schematically showing the semiconductor device according to the first embodiment.

[0016] Figure 2 is Figure 1 A cross-sectional view of a main portion of the semiconductor device cut at the AA cross-sectional position.

[0017] Figure 3 This is a graph showing the maximum stress generated in a semiconductor element relative to the bonding angle.

[0018] Figure 4 It is a diagram showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

[0019] Figure 5 This is a cross-sectional view of main parts schematically showing the semiconductor device according to the first embodiment.

[0020] Figure 6 It is a top view illustrating a semiconductor device according to a comparative example.

[0021] Figure 7 It is a cross-sectional view illustrating a semiconductor device according to a comparative example.

[0022] Figure 8 It is a diagram showing the manufacturing process of the semiconductor device involved in the second embodiment of the present invention. DETAILED DESCRIPTION

[0023] Hereinafter, a semiconductor device according to an embodiment of the present application will be described with reference to the drawings. In addition, the same or corresponding components and parts in each figure are denoted by the same reference numerals for description.

[0024] Implementation method 1.

[0025] Figure 1 is a plan view schematically showing a semiconductor device 100 according to the first embodiment. Figure 2 is Figure 1 A cross-sectional view of a main part of the semiconductor device 100 cut at the AA cross-sectional position; Figure 3 is a graph showing the maximum stress value generated at the maximum stress generating portion 12 of the semiconductor element 2 with respect to the bonding angle 5. Figure 4 is a diagram showing a manufacturing process of the semiconductor device 100. Figure 5 1 is a cross-sectional view of main parts schematically showing another semiconductor device 100 according to the first embodiment. Figure 1 1 and 2 are diagrams showing a state where the mold resin 9 is removed, and the two-dot chain line represents the outer shape of the mold resin 9 . Figure 2 and Figure 5 Also shown is a molding resin 9. Figure 1 At the AA cross-section position, the semiconductor device 100 has a bilaterally symmetrical structure, so Figure 2 Only the right part of the AA section position is shown. Figure 2 The AA cross-sectional position is a cross-sectional position including the semiconductor element 2, but in the cross-sectional position including the configuration in Figure 1The same structure is also present in the cross section including the semiconductor element 1 next to the semiconductor element 2. In addition, these figures are schematically shown, and the dimensional relationship of each part of the actual semiconductor device 100 is different. The semiconductor device 100 is a resin-sealed semiconductor device 100 obtained by sealing the semiconductor elements 1 and 2 with a molding resin 9, and is used, for example, for power control.

[0026] <Semiconductor Device 100>

[0027] The semiconductor device 100 includes semiconductor elements 1 and 2 formed in a plate shape, a heat sink 3 formed in a plate shape, first lead frames 10 and 11, a second lead frame 6, and a molded resin 9. For example, the semiconductor element 1 is a switching element, and the semiconductor element 2 is a rectifying element. In the present embodiment, these two semiconductor elements 1 and 2 are provided, but the semiconductor device 100 is not limited to two semiconductor elements, and the semiconductor element may be one or more than three semiconductor elements depending on the purpose of the semiconductor device 100. In addition, the semiconductor elements 1 and 2 are semiconductors of a longitudinal structure having electrode pads (not shown) on both one surface and the other surface, but the semiconductor elements 1 and 2 are not limited to semiconductors of a longitudinal structure, and may be semiconductor elements of a transverse structure having electrode pads only on one surface.

[0028] The other side of the semiconductor elements 1 and 2 is bonded to one side 3a of the heat sink 3 via a first bonding material, i.e., a chip-under bonding material (not shown). The other side of the first lead frame 10 and 11 is bonded to one side 3a of the heat sink 3 via a second bonding material, i.e., a wire bonding material (not shown). The other side of the second lead frame 6 is bonded to an active face portion, i.e., an electrode pad, of one side of each of the semiconductor elements 1 and 2 via a third bonding material, i.e., a chip-on bonding material 4. The molding resin 9 exposes a portion of the first lead frames 10 and 11 and a portion of the second lead frame 6 to the outside, and the molding resin 9 seals the heat sink 3, the semiconductor elements 1 and 2, the first lead frames 10 and 11, and the second lead frame 6. The chip-under bonding material, the chip-on bonding material 4, and the wire bonding material are also sealed by the molding resin 9. The semiconductor elements 1 and 2 are connected to the outside of the semiconductor device 100 via the first lead frames 10 and 11 and the second lead frame 6 exposed to the outside.

[0029] Semiconductor element 1 is a switching element such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) that performs power conversion through switching action. IGBT drives the load by passing a large current to the load. Semiconductor element 2 is a rectifier element such as a return diode. The material of semiconductor elements 1 and 2 is, for example, silicon (Si). The material of semiconductor elements 1 and 2 is not limited to silicon, for example, as long as it is a material selected from the group consisting of gallium nitride materials such as silicon carbide (SiC), gallium nitride (GaN) and diamond. These materials are so-called wide bandgap semiconductor materials with a wider band gap than silicon. When a wide bandgap semiconductor material is used to form semiconductor elements 1 and 2, semiconductor elements 1 and 2 can be operated at a higher temperature than a semiconductor element made of silicon. That is, a wide bandgap semiconductor material is a semiconductor material suitable for passing a large current. In addition, when a wide bandgap semiconductor is used, the semiconductor device 100 can be miniaturized because the allowable current density is high and the power loss is low. Alternatively, the semiconductor device 100 may include a mixture of silicon semiconductor elements and wide-gap semiconductors.

[0030] The heat sink 3, the first lead frame 10, 11 and the second lead frame 6 are metals with excellent electrical conductivity and thermal conductivity, and are made, for example, by cutting or stamping. Among the metals with good electrical conductivity, copper materials such as pure copper or copper alloys with copper as the main component are most suitable as these materials in terms of resistance, processability, cost, etc. The other surface 3b of the heat sink 3 is not sealed by the molding resin 9 and is exposed to the outside of the molding resin 9. The heat generated by the semiconductor elements 1 and 2 is dissipated to the outside from the other surface 3b. The first lead frames 10 and 11, which serve as input and output terminals, are connected to the electrode pads on the other side of the semiconductor elements 1 and 2 via the heat sink 3. The second lead frame 6, which serves as the main terminal, is connected to the load outside the semiconductor device 100. A protrusion 7 protruding toward the semiconductor elements 1 and 2 is formed on the other surface of the second lead frame 6. When the protrusion 7 is formed on the second lead frame 6 by convex processing, the protrusion 7 can be easily formed on the other surface of the second lead frame 6. In addition, when the protrusion 7 is formed by embossing, a stepped recess 8 is formed on one surface of the second lead frame 6. The reason for providing the protrusion 7 will be described later.

[0031] The molding resin 9 uses a thermosetting resin material, such as an epoxy resin filled with hard inorganic powders such as fused silica having a small thermal expansion coefficient. The molding resin 9 does not need high thermal conductivity, so for the inorganic filler contained in the thermosetting resin, fused silica is the best among silicon oxides (silicon dioxide) because it has good fluidity when contained in the thermosetting resin and is easier to adjust the linear expansion coefficient. Although it depends on the heat dissipation of the semiconductor device 100, the heat generated during operation, and the operating temperature, the epoxy resin can use a general bisphenol-type or phenol-novolac-type epoxy resin. In addition, as long as the semiconductor elements 1 and 2 can be sealed and protected, the molding resin 9 is not limited to these materials. For example, as the operating temperature of the semiconductor elements 1 and 2 increases, a naphthalene-type or multifunctional resin with high heat resistance can be used as the molding resin 9.

[0032] It is preferable to use a resin having a linear expansion coefficient close to that of the heat sink 3, the first lead frames 10, 11, and the second lead frame 6 for the molding resin 9 in order to prevent the thermal deformation force generated on the semiconductor elements 1, 2 from increasing due to the difference in linear expansion coefficients between the molding resin 9 and the heat sink 3, the first lead frames 10, 11, and the second lead frame 6. In the case where the heat sink 3, the first lead frames 10, 11, and the second lead frame 6 are formed of pure copper, since the linear expansion coefficient of pure copper is 16 [ppm / K] to 17 [ppm / K], it is preferable that the linear expansion coefficient of the molding resin 9 is in the range of 15 [ppm / K] to 18 [ppm / K] which is close to the linear expansion coefficient of pure copper. The linear expansion coefficient of the molding resin 9 can be changed by adjusting the amount of the inorganic filler. By adjusting the linear expansion coefficient of the molding resin 9 so as to make it close to the linear expansion coefficient of pure copper, the thermal deformation force inside the semiconductor device 100 can be reduced, and thus the reliability of the semiconductor device 100 with respect to temperature cycles can be improved.

[0033] The off-chip bonding material is preferably a bonding material selected from the group consisting of a solder material, a sinterable filler with silver as the main component, a solder with silver as the main component, a material in which copper is dispersed in tin, and a gold-based alloy such as gold-tin and gold-germanium with gold as the main component. Since these bonding materials have high thermal conductivity and electrical conductivity, the heat sink 3 and the semiconductor elements 1 and 2 can be thermally and electrically connected. For example, a solder material is used as a wire bonding material to ensure electrical conduction between the heat sink 3 and the first lead frames 10 and 11. For example, a solder material is used as the on-chip bonding material 4 to ensure electrical conduction between the semiconductor elements 1 and 2 and the second lead frame 6. Since cracks are generated in the on-chip bonding material 4 when the strength of the on-chip bonding material 4 is low, when a solder material is used for the on-chip bonding material 4, a high-strength material having a tensile strength of about 40 MPa or more, i.e., a solder material, is most suitable as the on-chip bonding material 4.

[0034] <Comparative Example>

[0035] Before explaining the structure of the on-chip bonding material 4 which is the main part of the present application, Figure 6 as well as Figure 7 A comparative example will be described. Figure 6 is a plan view showing an outline of a semiconductor device 101 according to a comparative example. Figure 7 is a cross-sectional view of a semiconductor device 101 of a comparative example. Figure 6 BB is a cross-sectional view of a main portion of the semiconductor device 101 cut at the cross-sectional position BB. Figure 6 1 and 2 are diagrams showing a state where the mold resin 9 is removed, and the two-dot chain line represents the outer shape of the mold resin 9 . Figure 7 Also shown is a molding resin 9. Figure 6 At the BB cross-section position, the semiconductor device 101 has a bilaterally symmetrical structure, so Figure 7 Only the right side portion of the BB cross-section position is shown. Figure 7 The BB cross-sectional position is a cross-sectional position including the semiconductor element 2, but in the cross-sectional position including the configuration in Figure 6 The same structure is also present in the cross section including the semiconductor element 1 next to the semiconductor element 2. The semiconductor device 101 includes the semiconductor elements 1 and 2, the heat sink 3, the first lead frames 10 and 11, the second lead frame 6, and the molding resin 9, similarly to the semiconductor device 100.

[0036] The differences between the semiconductor device 101 and the semiconductor device 100 are described. The protrusion 7 is not formed on the other surface of the second lead frame 6. The chip bonding material 4a that bonds the semiconductor elements 1 and 2 to the second lead frame 6 is a low-strength material. The boundary portion between the chip bonding material 4a and the molding resin 9 in the gap between one surface of the semiconductor elements 1 and 2 and the other surface of the second lead frame 6 is cut with a plane perpendicular to one surface of the heat sink 3. In the cross-sectional shape obtained after cutting, of the two angles formed by the straight line connecting the end points of the bonding surface of the chip bonding material 4a and the semiconductor elements 1 and 2 and the end points of the bonding surface of the chip bonding material 4a and the second lead frame 6, and one surface of the semiconductor elements 1 and 2, the angle on the chip bonding material 4a side (hereinafter referred to as the bonding angle 5) is an acute angle. In addition, the chip bonding material 4a has low rigidity.

[0037] The semiconductor device 101 is configured such that the material strength of the die bonding material 4a is low, the die bonding material 4a has low rigidity and an acute bonding angle 5, and the semiconductor elements 1, 2, etc. are sealed by a molding resin 9. With such a configuration, the maximum stress generated at the maximum stress generating portion 12 of the semiconductor elements 1, 2 is reduced by utilizing the thermal deformation force generated on the semiconductor elements 1, 2 due to the difference in linear expansion coefficients between the semiconductor elements 1, 2, the second lead frame 6, and the die bonding material 4a, thereby suppressing the generation of cracks in the semiconductor elements 1, 2. However, since the die bonding material 4a with low strength, low rigidity, and an acute bonding angle 5 generates cracks in hundreds of cold and hot cycles, the life of the die bonding material 4a is shortened.

[0038] <Structure of On-Chip Bonding Material 4>

[0039] The structure of the on-chip bonding material 4, which is the main part of the present application, is described. A boundary between the on-chip bonding material 4 and the molding resin 9 is provided in the gap between one surface of the semiconductor elements 1, 2 and the other surface of the second lead frame 6, and in the cross-sectional shape obtained by cutting the boundary portion with a plane perpendicular to one surface of the heat sink 3, of the two angles formed by a straight line connecting the end points of the bonding surface of the on-chip bonding material 4 with the semiconductor elements 1, 2 and the end points of the bonding surface of the on-chip bonding material 4 with the second lead frame 6, and one surface of the semiconductor elements 1, 2, the bonding angle 5 on the side of the on-chip bonding material 4 is not less than 90° and not more than 135°. Figure 2 In the embodiment, the joint angle 5c is 90° and the joint angle 5f is 135°. The joint angle 5d and the joint angle 5e are joint angles 5 within the range of 90° to 135°. The joint angle 5a and the joint angle 5b are joint angles 5 smaller than 90°.

[0040] The stress generated when the semiconductor device 100 is thermally deformed is shown using Figure 3 The reason why the joining angle 5 is set to be not less than 90° and not more than 135° will be described. Figure 3 is to Figure 2 The maximum stress value generated at the maximum stress generating portion 12 of the semiconductor elements 1 and 2 is plotted with respect to the bonding angle 5 when the temperature cycle of -45°C to 150°C is repeatedly applied to the resin-sealed semiconductor device 100 shown. The linear expansion coefficient of the semiconductor elements 1 and 2 is 3 [ppm / K] to 5 [ppm / K], the linear expansion coefficient of the under-chip bonding material is 18 [ppm / K] to 20 [ppm / K], the linear expansion coefficient of the on-chip bonding material 4 is 21 [ppm / K] to 23 [ppm / K], the linear expansion coefficient of the heat sink 3 and the second lead frame 6 is 16 [ppm / K] to 17 [ppm / K], and the linear expansion coefficient of the molding resin 9 is 15 [ppm / K] to 18 [ppm / K].

[0041] By comparing the linear expansion coefficients of the materials, it can be seen that the linear expansion coefficients of the semiconductor elements 1 and 2 are the smallest, and the linear expansion coefficient of the die bonding material 4 is the largest. The semiconductor elements 1 and 2 are semiconductor materials and have the lowest strength in the semiconductor device 100, so it is necessary to reduce the stress generated on the semiconductor elements 1 and 2. When the temperature of the semiconductor device 100 changes from high temperature to low temperature, a larger contraction force is generated on the die bonding material 4 than on the semiconductor elements 1 and 2. Therefore, the maximum stress is generated at the maximum stress generating portion 12 of the semiconductor elements 1 and 2.

[0042] When the bonding angle 5 of the die bonding material 4 is an acute angle, since the bonding area between the die bonding material 4 and the second lead frame 6 is small, the proportion of the force that deforms only in the contraction direction accounts for the majority in the die bonding material 4. When the bonding angle 5 of the die bonding material 4 is 90° to 135°, since the bonding area between the die bonding material 4 and the second lead frame 6 increases, the proportion of the force that deforms in the expansion direction increases in the die bonding material 4. Therefore, the maximum stress at the maximum stress generating portion 12 of the semiconductor elements 1 and 2 decreases. When the bonding angle 5 of the die bonding material 4 is greater than 135°, since the proportion of the force that deforms in the expansion direction is too large, the maximum stress at the maximum stress generating portion 12 of the semiconductor elements 1 and 2 increases.

[0043] When the semiconductor device 100 changes temperature from low temperature to high temperature, the direction of the force generated by the temperature change is opposite, but the correlation between the bonding angle 5 and the maximum stress generated on the semiconductor elements 1 and 2 remains unchanged. Therefore, by setting the bonding angle 5 of the die bonding material 4 within the range of 90° to 135° while ensuring the rigidity of the die bonding material 4, the maximum stress of the maximum stress generating portion 12 of the semiconductor elements 1 and 2 can be reduced without making the structure of the second lead frame 6 complicated and large. By reducing the maximum stress of the maximum stress generating portion 12 of the semiconductor elements 1 and 2, a resin-sealed semiconductor device 100 can be obtained, which can easily suppress the occurrence of cracks in the semiconductor elements 1 and 2 and can achieve miniaturization and cost reduction.

[0044] In order to ensure the rigidity of the die bonding material 4, the thickness of the die bonding material 4 at the boundary portion between the die bonding material 4 and the molding resin 9 in the gap between one surface of the semiconductor elements 1 and 2 and the other surface of the second lead frame 6 is preferably 0.45 to 0.7 mm. In the present embodiment, from the die bonding material 4 composed of a solid having a fixed thickness (for example, 0.4 mm), protrusions 7 protruding toward the semiconductor elements 1 and 2 are formed on the other surface of the second lead frame 6, respectively, so that the thickness of the die bonding material 4 is set to 0.45 to 0.7 mm and the bonding angle 5 is set to 90° to 135°. During the reflow heating for bonding the second lead frame 6 and the semiconductor elements 1 and 2, the protrusion 7 presses the die bonding material 4 in contact with the protrusion 7, and the part of the die bonding material 4 pressed out by the pressing flows to the end point side of the bonding surface between the die bonding material 4 and the second lead frame 6 at the boundary portion, so that the bonding angle 5 is set to be greater than 90° and less than 135°. The on-chip bonding material 4 with high strength, high rigidity and a bonding angle 5 in the range of 90° to 135° will not generate cracks even in thousands of hot and cold cycles, so the life of the on-chip bonding material 4 is prolonged. Since the life of the on-chip bonding material 4 is prolonged, the semiconductor device 100 becomes high quality and the reliability of the semiconductor device 100 can be improved.

[0045] In the present embodiment, the shape of the protrusion 7 is a rectangular parallelepiped, but the shape of the protrusion 7 is not limited to a rectangular parallelepiped. If the thickness of the chip bonding material 4 and the bonding angle 5 at the boundary portion can be set arbitrarily, the shape and number of the protrusions 7 and the structure of the protrusions 7 may not be a rectangular parallelepiped. In addition, although an example of providing the protrusions 7 by convex processing is shown, the method of forming the protrusions 7 is not limited to convex processing, and the protrusions 7 may also be formed by cutting processing. In the case of forming the protrusions 7 by cutting processing, the stepped recessed portion 8 may not be formed.

[0046] In this embodiment, the portion where the end points of the bonding surface between the on-chip bonding material 4 and the semiconductor elements 1 and 2 and the end points of the bonding surface between the on-chip bonding material 4 and the second lead frame 6 are connected is represented by a straight line, but the portion connecting the end points is not limited to a straight line. The portion connecting the end points may also be a curve. Even if the portion connecting the end points is a curve, the maximum stress at the maximum stress generating portion 12 of the semiconductor elements 1 and 2 can be reduced by setting the bonding angle 5 of the on-chip bonding material 4 to a range of 90° to 135°.

[0047] In this embodiment, by forming a protrusion 7 on the other surface of the second lead frame 6, the thickness of the chip bonding material 4 at the boundary portion becomes 0.45 to 0.7 mm, and the bonding angle 5 is greater than 90° and less than 135°. In order to ensure the rigidity of the chip bonding material 4, a high-strength material can be used for the chip bonding material 4. In the case of using a high-strength material, there is no need to increase the thickness. The thickness of the chip bonding material 4 at the boundary portion can be less than 0.4 mm. Since it can be set to be less than the manufacturable thickness of the strip solder, Figure 5 As shown, it is not necessary to provide the protrusion 7 on the second lead frame 6. By adjusting the thickness and size of the die bonding material 4 before melting, the bonding angle 5 can be set within an appropriate range of 90° to 135°. By setting the bonding angle 5 of the die bonding material 4 within a range of 90° to 135° while ensuring the rigidity of the die bonding material 4, the maximum stress at the maximum stress generating portion 12 of the semiconductor elements 1 and 2 can be reduced.

[0048] <Method of Manufacturing Semiconductor Device 100>

[0049] use Figure 4 The following describes a method for manufacturing the semiconductor device 100. The semiconductor device 100 is manufactured through a first step (S11) as a die bonding step, a second step (S12) and a third step (S13) as reflow steps, and a fourth step (S14) as a transfer molding step.

[0050] The first step is a step of bonding the other surfaces of the semiconductor elements 1 and 2 formed in a plate shape to one surface 3a of the heat sink 3 formed in a plate shape via the under-chip bonding material. First, the under-chip bonding material is provided on one surface 3a of the heat sink 3 with a gap, and the semiconductor element 1 as a switching element and the semiconductor element 2 as a rectifying element are arranged on the under-chip bonding material. Then, the under-chip bonding material is melted, and the semiconductor elements 1 and 2 are bonded to one surface 3a of the heat sink 3.

[0051] The second step is a step of bonding the other surfaces of the first lead frames 10 and 11 to the one surface 3a of the heat sink 3 via the wire bonding material. First, the wire bonding material is provided at the ends of both sides of the one surface 3a of the heat sink 3, and the first lead frames 10 and 11 are arranged on the wire bonding material. Then, the wire bonding material is melted by reflow heating, and the first lead frames 10 and 11 are bonded to the one surface 3a of the heat sink 3 during the subsequent cooling.

[0052] The third step is a step of bonding the other surface of the second lead frame 6 to one surface of the semiconductor element 1 or 2 via the die bonding material 4. The die bonding material 4, which is a solid having a certain thickness, is sandwiched between the other surface of the second lead frame 6 and one surface of the semiconductor element 1 or 2, and then the die bonding material 4 is melted by reflow heating and then cooled, thereby bonding the other surface of the second lead frame 6 to one surface of the semiconductor element 1 or 2 via the die bonding material 4. When the chip bonding material 4 is melted and then cooled, the boundary portion between the chip bonding material 4 and the outer side of the chip bonding material 4 in the gap between one surface of the semiconductor elements 1 and 2 and the other surface of the second lead frame 6 is cut by a plane of a surface perpendicular to the heat sink 3. In the cross-sectional shape obtained after cutting, the angle of the chip bonding material 4 side is set to be greater than 90° and less than 135° among the two angles formed by the end points of the bonding surface of the chip bonding material 4 and the semiconductor elements 1 and 2, the straight line connecting the end points of the bonding surface of the chip bonding material 4 and the second lead frame 6, and one surface of the semiconductor elements 1 and 2.

[0053] The on-chip bonding material 4 is, for example, a strip solder of fixed thickness. By using a strip solder of fixed thickness instead of a solder having a non-fixed thickness and having recesses or protrusions, the cost of the solder can be suppressed. When the rigidity of the on-chip bonding material 4 is low, the on-chip bonding material 4 is prone to cracks. In order to ensure the rigidity of the on-chip bonding material 4, the thickness of the on-chip bonding material 4 at the boundary portion is preferably 0.45 to 0.7 mm. The manufacturable thickness of the strip solder is about 0.4 mm. Therefore, a protrusion 7 protruding toward the semiconductor elements 1 and 2, respectively, is formed on the other surface of the second lead frame 6 so that the thickness of the on-chip bonding material 4 is set to 0.45 to 0.7 mm. During reflow heating, the chip bonding material 4 in contact with the protrusion 7 is pressed, and the part of the chip bonding material 4 pressed out by the pressing flows to the side of the end point of the bonding surface of the chip bonding material 4 and the second lead frame 6 at the boundary part, and the thickness of the chip bonding material 4 is set to 0.45 to 0.7 mm, and the bonding angle 5 on the chip bonding material 4 side is set to be greater than 90° and less than 135°. By adjusting the size of the chip bonding material 4 before melting and the size of the protrusion 7 of the second lead frame 6, the amount of chip bonding material 4 used can be minimized, and the thickness and bonding angle 5 of the chip bonding material 4 after melting can be arbitrarily set. By configuring in this way, the rigidity of the chip bonding material 4 can be ensured, and the generation of cracks in the semiconductor elements 1 and 2 can be suppressed.

[0054] The fourth step is a step of exposing a portion of the first lead frames 10 and 11 and a portion of the second lead frame 6 to the outside and sealing the heat sink 3, semiconductor elements 1 and 2, the first lead frames 10 and 11, and the second lead frame 6 with a molding resin 9 made of a thermosetting resin.

[0055] In the present embodiment, in the third step, the other surface of the second lead frame 6 is bonded to one surface of the semiconductor element 1, 2 via the die bonding material 4, but the third step is not limited thereto. The third step may also be a step in which the temperature of the second lead frame 6 is raised after being mounted on the semiconductor element 1, 2, and the melted die bonding material 4 is dripped and supplied between the other surface of the second lead frame 6 and one surface of the semiconductor element 1, 2 and cooled. By setting such a step, the restriction of making the protrusion 7 of the second lead frame 6 contact with the die bonding material 4 before melting is eliminated, thereby expanding the freedom of the size of the protrusion 7 of the second lead frame 6. In addition, since the supply amount of the die bonding material 4 can be adjusted, the amount of die bonding material 4 used can be further reduced.

[0056] In addition, by making the wire bonding material serving as the second bonding material and the on-chip bonding material 4 serving as the third bonding material of the same type or using the same bonding material, there is no need to separately perform the second step (S12) and the third step (S13) serving as the reflow process, and all bonding involved in the second step and the third step can be performed in a single reflow process (S10).

[0057] As described above, in the semiconductor device 100 involved in embodiment 1, the boundary portion between the on-chip bonding material 4 and the molding resin 9 is cut by a plane perpendicular to one surface 3a of the heat sink 3. In the cross-sectional shape obtained after cutting, the angle of the on-chip bonding material 4 side formed by a straight line connecting the end points of the bonding surface between the on-chip bonding material 4 and the semiconductor elements 1, 2 and the end points of the bonding surface between the on-chip bonding material 4 and the second lead frame 6 and one surface of the semiconductor elements 1, 2 is greater than 90° and less than 135°. Therefore, the maximum stress at the maximum stress generating portion 12 of the semiconductor elements 1, 2 can be reduced without complicating and enlarging the structure of the second lead frame 6. Therefore, a resin-sealed semiconductor device 100 can be obtained, which can easily suppress the occurrence of cracks in the semiconductor elements 1, 2 while achieving miniaturization and low cost. In addition, when the protrusion 7 protruding toward the semiconductor elements 1 and 2 is formed on the other surface of the second lead frame 6 at the inner side of the boundary portion, the thickness of the die bonding material 4 at the boundary portion can be easily set to 0.45 to 0.7 mm, and the bonding angle 5 can be set to 90° to 135°. In addition, since the amount of die bonding material 4 used can be minimized, a cheaper semiconductor device 100 can be provided. In addition, when the protrusion 7 is formed on the second lead frame 6 by embossing, the protrusion 7 can be formed on the other surface of the second lead frame 6 relatively easily.

[0058] In addition, in the case of the on-chip bonding material 4 with high strength and high rigidity and a bonding angle 5 in the range of 90° to 135°, the on-chip bonding material 4 will not crack even in thousands of hot and cold cycles, so the life of the on-chip bonding material 4a can be extended. Since the life of the on-chip bonding material 4a is extended, the semiconductor device 100 becomes high quality and the reliability of the semiconductor device 100 can be improved.

[0059] In the manufacturing method of the semiconductor device 100 involved in embodiment 1, the chip bonding material 4 composed of a solid with a certain thickness is sandwiched between the other side of the second lead frame 6 and one side of the semiconductor element 1, 2, and then the chip bonding material 4 is melted by reflow heating and then cooled, so that the other side of the second lead frame 6 is bonded to the one side of the semiconductor element 1, 2 via the chip bonding material 4. Therefore, by using a strip solder with a fixed thickness instead of a solder with a non-fixed thickness having a recess or a protrusion, the cost of the solder can be suppressed. In addition, during reflow heating, the protrusion 7 presses the chip bonding material 4 connected to the protrusion 7, and the part of the chip bonding material 4 pressed out by the pressing flows to the side of the end point of the bonding surface between the chip bonding material 4 and the second lead frame 6 at the boundary part, thereby setting the bonding angle 5 on the chip bonding material 4 side to not less than 90° and not more than 135°. Therefore, it is easy to set the thickness of the chip bonding material 4 at the boundary part to 0.45~0.7mm and set the bonding angle 5 to not less than 90° and not more than 135°.

[0060] Implementation method 2.

[0061] A method for manufacturing the semiconductor device 100 according to the second embodiment will be described. Figure 8 1 is a diagram showing a manufacturing process of the semiconductor device 100. The manufacturing method of the semiconductor device 100 according to the second embodiment performs a first step (S11), a second step (S12), and a third step (S13) in a single step (S10).

[0062] The under-chip bonding material as the first bonding material, the wire bonding material as the second bonding material, and the on-chip bonding material 4 as the third bonding material are bonding materials made of the same or identical material. The bonding material made of the same or identical material is, for example, a bonding material made of solder. By using bonding materials made of the same or identical material, there is no need to separately implement the first step (S11) as the patch process and the second step (S12) and the third step (S13) as the reflow process, and all the bonding involved in the first process, the second process, and the third process can be implemented in one reflow process (S10).

[0063] As described above, in the method for manufacturing the semiconductor device 100 according to the second embodiment, since the under-chip bonding material, the wire bonding material, and the on-chip bonding material 4 are bonding materials made of the same or identical material, the first step (S11), the second step (S12), and the third step (S13) can be performed in one reflow step (S10), thereby improving the productivity of the semiconductor device 100. In addition, since the productivity of the semiconductor device 100 is improved, a more inexpensive semiconductor device 100 can be provided.

[0064] In addition, although the present application describes various exemplary embodiments and examples, the various features, methods and functions described in one or more embodiments are not limited to application to specific embodiments, but can also be applied to the embodiments alone or in various combinations.

[0065] Therefore, it is considered that numerous modifications not shown in the examples are also included in the technical scope disclosed in the present specification, for example, including the case where at least one component is modified, added or omitted, and the case where at least one component is extracted and combined with components of other embodiments.

[0066] Description of symbols

[0067] 1Semiconductor components

[0068] 2Semiconductor components

[0069] 3 Radiator

[0070] 3a One surface

[0071] 3b Another side

[0072] 4. Chip bonding materials

[0073] 4a On-chip bonding materials

[0074] 5Joint angle

[0075] 6 Second lead frame

[0076] 7 Protrusion

[0077] 8-step recess

[0078] 9 Molding resin

[0079] 10First lead frame

[0080] 11First lead frame

[0081] 12 Maximum stress occurrence location

[0082] 100Semiconductor devices

[0083] 101 semiconductor devices.

Claims

1. A semiconductor device, characterized in that: include: a heat sink formed into a plate shape; a semiconductor element formed in a plate shape, the other surface of the semiconductor element being bonded to one surface of the heat sink via a first bonding material; a first lead frame, the other surface of which is bonded to one surface of the heat sink via a second bonding material; a second lead frame, the other surface of which is bonded to one surface of the semiconductor element via a third bonding material; as well as a molding resin that exposes a portion of the first lead frame and a portion of the second lead frame to the outside and seals the heat sink, the semiconductor element, the first lead frame, and the second lead frame; A boundary between the third bonding material and the molding resin is provided in a gap between one surface of the semiconductor element and the other surface of the second lead frame. In a cross-sectional shape obtained by cutting the boundary portion with a plane perpendicular to one surface of the heat sink, of two angles formed by a straight line connecting an end point of a bonding surface between the third bonding material and the semiconductor element and an end point of a bonding surface between the third bonding material and the second lead frame, and one surface of the semiconductor element, an angle on the third bonding material side is not less than 90° and not more than 135°, A protrusion protruding toward the semiconductor element is formed on the other surface of the second lead frame at a portion inside the boundary portion. The third bonding material is pressed by the protrusion, and part of the third bonding material pressed out by the pressing flows to one side of the end point of the bonding surface between the third bonding material and the second lead frame at the boundary part, and the angle of the third bonding material side is set to be greater than 90° and less than 135°.

2. A method for manufacturing a semiconductor device, characterized in that: include: a first step of bonding the other surface of the semiconductor element formed in a plate shape to one surface of the heat sink formed in a plate shape via a first bonding material; a second step of bonding the other surface of the first lead frame to the one surface of the heat sink via a second bonding material; A third step of sandwiching a third bonding material composed of a solid having a fixed thickness between the other surface of the second lead frame and the one surface of the semiconductor element, and then melting the third bonding material by reflow heating and then cooling it, thereby bonding the other surface of the second lead frame to the one surface of the semiconductor element via the third bonding material, wherein when the third bonding material is melted and then cooled, in a cross-sectional shape obtained by cutting a boundary portion of the third bonding material provided in a gap between the one surface of the semiconductor element and the other surface of the second lead frame and the outer side of the third bonding material with a plane perpendicular to the one surface of the heat sink, of two angles formed by a straight line connecting end points of the bonding surface of the third bonding material and the semiconductor element and end points of the bonding surface of the third bonding material and the second lead frame, and the one surface of the semiconductor element, an angle on the third bonding material side is set to be not less than 90° and not more than 135°; and a fourth step of exposing a portion of the first lead frame and a portion of the second lead frame to the outside and sealing the heat sink, the semiconductor element, the first lead frame, and the second lead frame with a molding resin; On the other surface of the second lead frame, a protrusion that protrudes toward the semiconductor element is formed at a portion that is inner than the boundary portion, and presses the third bonding material connected to the protrusion during the reflow heating. The portion of the third bonding material pressed out by the pressing flows to the side of the end point of the bonding surface between the third bonding material and the second lead frame at the boundary portion, and the angle of the third bonding material side is set to be greater than 90° and less than 135°.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The second bonding material and the third bonding material are bonding materials made of the same type or the same material, The second step and the third step are performed in one process.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The first bonding material, the second bonding material and the second bonding material are bonding materials made of the same type or the same material, The first step, the second step, and the third step are performed in one process.

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