Method for manufacturing a semiconductor memory device

Abstract

A manufacturing method of a semiconductor memory device includes forming a preliminary memory cell array having a stacked structure and a cell pillar on a support structure, removing the support structure to expose a portion of each cell pillar, forming a protective layer covering the exposed portion of each cell pillar, forming a mask pattern exposing an opening defined between inclined surfaces of the protective layer, wherein the inclined surfaces are arranged between the cell pillars, and etching at least one conductive layer adjacent to the opening in the conductive layer, thereby isolating the at least one conductive layer into a selection line.

Description

Technical Field

[0001] This disclosure generally relates to a method for manufacturing a semiconductor memory device, and more specifically to a method for manufacturing a three-dimensional semiconductor memory device. Background Technology

[0002] A semiconductor memory device comprises multiple memory cells capable of storing data. The memory cells can be arranged in three dimensions to implement a three-dimensional semiconductor memory device. The memory cells can form multiple memory cell strings. Memory cell strings can be connected to word lines and select lines. Summary of the Invention

[0003] In one embodiment of this disclosure, a method for manufacturing a semiconductor memory device may be provided, the method comprising: forming a preliminary memory cell array on a support structure, the preliminary memory cell array having a stacked structure and cell pillars; removing the support structure to expose a portion of each cell pillar; forming a protective layer covering the exposed portion of each cell pillar; forming a mask pattern exposing an opening defined between inclined surfaces of the protective layer, wherein the inclined surfaces are disposed between the cell pillars; and etching at least one conductive layer in the conductive layer adjacent to the opening, thereby isolating the at least one conductive layer into a select line. Attached Figure Description

[0004] Embodiments will be described below with reference to the accompanying drawings; however, these embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein.

[0005] In the figures, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being between two elements, it can be the only element between those two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals refer to similar elements.

[0006] Figure 1 This is a circuit diagram showing a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0007] Figure 2A and Figure 2B This is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 3A The layout of the gate stack structure and channel structure of a semiconductor memory device according to embodiments of the present disclosure is shown, and Figure 3B The layout of the bit lines is shown.

[0009] Figure 4This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figures 5A to 5L This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figures 6A to 6C It shows the formation Figure 5F A cross-sectional view of an embodiment of the process for the impurity injection region shown.

[0012] Figures 7A to 7H This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 8 This is a block diagram illustrating the construction of a storage system according to an embodiment of the present disclosure.

[0014] Figure 9 This is a block diagram illustrating the construction of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0015] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0016] In the following text, the terms "first" and "second" are used to distinguish one component from another. These terms can be used to describe various components, but the components are not limited to these terms. Throughout the specification, the same reference numerals refer to the same elements. Therefore, even if a reference numeral is not mentioned or described with reference to one drawing, it may be mentioned or described with reference to another drawing. Furthermore, even if a reference numeral is not shown in one drawing, it may be mentioned or described with reference to another drawing.

[0017] This embodiment can provide a method for manufacturing a semiconductor memory device, which can improve the operating characteristics of the semiconductor memory device.

[0018] Figure 1 This is a circuit diagram illustrating the memory block BLK of a semiconductor memory device according to an embodiment of the present disclosure.

[0019] refer to Figure 1 A semiconductor memory device may include a memory block BLK. The memory block BLK may include multiple memory cell strings MS1 and MS2 connected to the source layer SL and multiple bit lines BL.

[0020] Each of the memory cell strings MS1 and MS2 may include: a plurality of memory cells MC connected in series; at least one source selection transistor SST; and at least one drain selection transistor DST. In one embodiment, each of the memory cell strings MS1 and MS2 may include one source selection transistor SST connected between the plurality of memory cells MC and the source layer SL. In another embodiment, each of the memory cell strings MS1 and MS2 may include two or more source selection transistors SST connected in series between the plurality of memory cells MC and the source layer SL. In one embodiment, each of the memory cell strings MS1 and MS2 may include one drain selection transistor DST connected between the plurality of memory cells MC and the bit line BL. In another embodiment, each of the memory cell strings MS1 and MS2 may include two or more drain selection transistors DST connected in series between the plurality of memory cells MC and the bit line BL.

[0021] Multiple memory cells MC can be connected to the source layer SL via source select transistor SST. Multiple memory cells MC can be connected to the bit line BL via drain select transistor DST.

[0022] The gates of source select transistors (SSTs) arranged at the same height can be connected to mutually isolated source select lines SSL1 and SSL2. The gates of drain select transistors (DSTs) arranged at the same height can be connected to mutually isolated drain select lines DSL1 and DSL2. The gates of memory cells (MCs) can be connected to multiple word lines (WLs). The word lines (WLs) can be arranged at different heights, and the gates of memory cells (MCs) arranged at the same height can be connected to a single word line (WL).

[0023] The figure illustrates a storage block BLK having a first source select line SSL1 and a second source select line SSL2 isolated from each other at the same height, and a first drain select line DSL1 and a second drain select line DSL2 isolated from each other at the same height. However, this disclosure is not limited thereto. In one embodiment, the storage block BLK may include three or more source select lines isolated from each other at the same height. Similarly, the storage block BLK may include three or more drain select lines isolated from each other at the same height.

[0024] Multiple memory cell strings MS1 and MS2 can be connected to each of the word lines WL. The multiple memory cell strings MS1 and MS2 may include a first group and a second group that can be independently selected by a first source select line SSL1 and a second source select line SSL2. The first group may include the first memory cell string MS1, and the second group may include the second memory cell string MS2.

[0025] The memory cells MC of the first memory cell string MS1 can be connected to the bit line BL via drain select transistors DST connected to the first drain select line DSL1. The memory cells MC of the second memory cell string MS2 can be connected to the bit line BL via drain select transistors DST connected to the second drain select line DSL2. One of the first memory cell strings MS1 and one of the second memory cell strings MS2 can be connected to a single bit line BL.

[0026] The memory cells MC of the first memory cell string MS1 can be connected to the source layer SL based on the gate signal applied to the first source select line SSL. The memory cells MC of the second memory cell string MS2 can be connected to the source layer SL based on the gate signal applied to the second source select line SSL2. Therefore, the multiple memory cell strings MS1 and MS2 can be isolated into groups that can be selected independently and simultaneously for each of the source select lines SSL1 and SSL2 during read or authentication operations. In one embodiment, during a read or authentication operation, one of the first source select line SSL1 and the second source select line SSL2 can be selected so that one group of the first set of first memory cell strings MS1 and the second set of second memory cell strings MS2 can be connected to the source layer SL. Therefore, in the embodiments of this disclosure, the channel resistance can be reduced compared to the case where the first memory cell string MS1 and the second memory cell string MS2 are simultaneously connected to the source layer SL during read or authentication operations. Therefore, in the embodiments of this disclosure, read interference can be reduced.

[0027] Figure 2A and Figure 2B This is a perspective view showing semiconductor memory devices 1A and 1B according to embodiments of the present disclosure. Figure 2A and Figure 2B Partial construction of each of semiconductor memory devices 1A and 1B is shown to aid in understanding the structure of each of semiconductor memory devices 1A and 1B.

[0028] refer to Figure 2A and Figure 2B Each of the semiconductor memory devices 1A and 1B may include: a peripheral circuit structure 10A or 10B; a memory cell array 5A or 5B; a source layer 20A or 20B; and a plurality of bit lines 80A or 80B.

[0029] The peripheral circuit structure 10A or 10B may include a substrate extending along a first direction D1 and a second direction D2. The peripheral circuit structure 10A or 10B may include peripheral circuitry for controlling the operation of the memory cell array 5A or 5B. After manufacturing the memory cell array 5A or 5B, the structure having the memory cell array 5A or 5B can be bonded to the peripheral circuit structure 10A or 10B. Therefore, thermal damage to the peripheral circuit structure 10A or 10B during the manufacturing of the memory cell array 5A or 5B can be prevented. Therefore, degradation of the operating characteristics of the peripheral circuit structure 10A or 10B can be reduced.

[0030] The memory cell array 5A or 5B can overlap with the peripheral circuit structure 10A or 10B. The memory cell array 5A or 5B can be arranged between the source layer 20A or 20B and multiple bit lines 80A or 80B.

[0031] The direction perpendicular to the plane extending along the first direction D1 and the second direction D2 is defined as the third direction D3. The arrangement of the memory cell array 5A or 5B, the source layer 20A or 20B, and the multiple bit lines 80A or 80B on the third direction D3 can be changed.

[0032] refer to Figure 2A The memory cell array 5A can overlap with the peripheral circuit structure 10A, and the source layer 20A is inserted between them. Multiple bit lines 80A can overlap with the peripheral circuit structure 10A, the source layer 20A and the memory cell array 5A, and the source layer 20A and the memory cell array 5A are inserted between the multiple bit lines 80A and the peripheral circuit structure 10A.

[0033] The memory cell array 5A may include: channel structures 60A1 and 60A2; and gate stack structure 90A surrounding the channel structures 60A1 and 60A2.

[0034] The gate stack structure 90A may include: source select lines 31A1, 31A2, 32A1, and 32A2; word line 40A; and drain select lines 51A1, 51A2, 52A1, and 52A2. The source select lines 31A1, 31A2, 32A1, and 32A2, the word line 40A, and the drain select lines 51A1, 51A2, 52A1, and 52A2 may be arranged spaced apart from each other. The conductive materials constituting the source select lines 31A1, 31A2, 32A1, and 32A2, the word line 40A, and the drain select lines 51A1, 51A2, 52A1, and 52A2 may be different. In one embodiment, source select lines 31A1, 31A2, 32A1, and 32A2, and drain select lines 51A1, 51A2, 52A1, and 52A2, may be formed of the same conductive material as word line 40A. However, this disclosure is not limited thereto. In another embodiment, source select lines 31A1, 31A2, 32A1, and 32A2, or drain select lines 51A1, 51A2, 52A1, and 52A2, may be formed of a conductive material different from the conductive material constituting word line 40A.

[0035] Source select lines 31A1, 31A2, 32A1, and 32A2 may be arranged between source layer 20A and multiple bit lines 80A. Source select lines 31A1, 31A2, 32A1, and 32A2 may include at least one first source select line and at least one second source select line. In one embodiment, source select lines 31A1, 31A2, 32A1, and 32A2 may include two first source select lines 31A1 and 32A1 and two second source select lines 31A2 and 32A2. First source select lines 31A1 and 32A1 may include a first source select line 31A1 of a first height and a first source select line 32A1 of a second height, and the first source select lines 31A1 and 32A1 are spaced apart from each other on a third direction D3. The second source selection lines 31A2 and 32A2 may include a second source selection line 31A2 of a first height and a second source selection line 32A2 of a second height, which are spaced apart from each other in a third direction D3. The first source selection line 31A1 and the second source selection line 31A2 of the first height may be spaced apart from each other in a first direction D1. The first source selection line 32A1 and the second source selection line 32A2 of the second height may be spaced apart from each other in the first direction D1.

[0036] Drain select lines 51A1, 51A2, 52A1, and 52A2 may be arranged between source select lines 31A1, 31A2, 32A1, and 32A2 and a plurality of bit lines 80A. Drain select lines 51A1, 51A2, 52A1, and 52A2 may include at least one first drain select line and at least one second drain select line. In one embodiment, drain select lines 51A1, 51A2, 52A1, and 52A2 may include two first drain select lines 51A1 and 52A1 and two second drain select lines 51A2 and 52A2. The first drain select lines 51A1 and 52A1 may include a third-height first drain select line 51A1 and a fourth-height first drain select line 52A1, which are spaced apart from each other on a third direction D3. The second drain selection lines 51A2 and 52A2 may include a third-height second drain selection line 51A2 and a fourth-height second drain selection line 52A2, which are spaced apart from each other in the third direction D3. The third-height first drain selection line 51A1 and the third-height second drain selection line 51A2 may be spaced apart from each other in the first direction D1. The fourth-height first drain selection line 52A1 and the fourth-height second drain selection line 52A2 may be spaced apart from each other in the first direction D1.

[0037] Each of the word lines 40A can be arranged between the first source select lines 31A1 and 32A1 and the first drain select lines 51A1 and 52A1, and can extend between the second source select lines 31A2 and 32A2 and the second drain select lines 51A2 and 52A2. The word lines 40A can be stacked and spaced apart from each other on a third direction D3.

[0038] Channel structures 60A1 and 60A2 may include as Figure 1 The channel layer of the channel regions of memory cell strings MS1 and MS2 shown. Channel structures 60A1 and 60A2 can contact the source layer 20A. Channel structures 60A1 and 60A2 can penetrate the gate stack structure 90A and extend toward the bit line 80A. Channel structures 60A1 and 60A2 can be connected to the bit line 80A via bit line contacts 70A1 and 70A2.

[0039] The channel structures 60A1 and 60A2 may include: a first channel structure 60A1 controlled by first source select lines 31A1 and 32A1; and a second channel structure 60A2 controlled by second source select lines 31A2 and 32A2. The first channel structure 60A1 can penetrate the first drain select lines 51A1 and 52A1, the word line 40A, and the first source select lines 31A1 and 32A1, and can contact the source layer 20A. The second channel structure 60A2 can penetrate the second drain select lines 51A2 and 52A2, the word line 40A, and the second source select lines 31A2 and 32A2, and can contact the source layer 20A. Each of the word lines 40A can extend to surround the first channel structure 60A1 and the second channel structure 60A2. Therefore, the first channel structure 60A1 and the second channel structure 60A2 can be simultaneously controlled by a single word line 40A.

[0040] Bit line contacts 70A1 and 70A2 may include: a first bit line contact 70A1 that contacts a first channel structure 60A1; and a second bit line contact 70A2 that contacts a second channel structure 60A2. A bit line 80A may be simultaneously connected to a first channel structure 60A1 and a second channel structure 60A2 via a pair of first bit line contacts 70A1 and second bit line contacts 70A2.

[0041] refer to Figure 2B The memory cell array 5B can overlap with the peripheral circuit structure 10B, with multiple bit lines 80B inserted between them. The source layer 20B can overlap with the peripheral circuit structure 10B, multiple bit lines 80B, and the memory cell array 5B, with multiple bit lines 80B and the memory cell array 5B inserted between the source layer 20B and the peripheral circuit structure 10B.

[0042] The memory cell array 5B may include: channel structures 60B1 and 60B2; and a gate stack structure 90B surrounding the channel structures 60B1 and 60B2.

[0043] The gate stack structure 90B may include: source select lines 30B1 and 30B2; word line 40B; and drain select lines 51B1, 51B2, 52B1, and 52B2. The source select lines 30B1 and 30B2, word line 40B, and drain select lines 51B1, 51B2, 52B1, and 52B2 can be varied. In the following text, the details of the relationships between these lines will be omitted. Figure 2A Description of overlapping components shown.

[0044] Drain select lines 51B1, 51B2, 52B1, and 52B2 can be arranged between multiple bit lines 80B and the source layer 20B. In one embodiment, drain select lines 51B1, 51B2, 52B1, and 52B2 may include two first drain select lines 51B1 and 52B1 and two second drain select lines 51B2 and 52B2. The first drain select lines 51B1 and 52B1 may include a first drain select line 51B1 of a first height and a first drain select line 52B1 of a second height, and the first drain select lines 51B1 and 52B1 are spaced apart from each other in the third direction D3. The second drain select lines 51B2 and 52B2 may include a second drain select line 51B2 of a first height and a second drain select line 52B2 of a second height, and the second drain select lines 51B2 and 52B2 are spaced apart from each other in the third direction D3. The first drain selection line 51B1 and the second drain selection line 51B2 at the first height can be spaced apart from each other in the first direction D1. The first drain selection line 52B1 at the second height and the second drain selection line 52B2 at the second height can be spaced apart from each other in the first direction D1.

[0045] Source select lines 30B1 and 30B2 can be arranged between drain select lines 51B1, 51B2, 52B1 and 52B2 and source layer 20B. In one embodiment, the conductive layer of the third height can be isolated into a line pattern, thereby defining the first source select line 30B1 and the second source select line 30B2.

[0046] Similar to a reference Figure 2A As described, the channel structures 60B1 and 60B2 may include a first channel structure 60B1 and a second channel structure 60B2, which may be controlled simultaneously by a bit line 80B.

[0047] Figure 3A The layout of the gate stack structure 90 and the channel structures 60[1] and 60[2] of a semiconductor memory device according to an embodiment of the present disclosure is shown, and Figure 3B The layout of bit line 80 is shown. Figure 3A The layout of the gate stack structure 90 and the channel structures 60[1] and 60[2] shown herein, and Figure 3B The layout of bit line 80 shown can be applied to Figure 2A The semiconductor memory device 1A shown is or Figure 2B The semiconductor memory device 1B shown is illustrated.

[0048] refer to Figure 3AThe gate stack 90 may surround the first channel structure 60[1] and the second channel structure 60[2]. The memory layer 61 may be arranged between the gate stack 90 and each of the first channel structure 60[1] and the second channel structure 60[2].

[0049] Storage layer 61 may include: a tunnel insulating layer 67 surrounding each of the first channel structure 60[1] and the second channel structure 60[2]; a data storage layer 65 surrounding the tunnel insulating layer 67; and a barrier insulating layer 63 surrounding the data storage layer 65. Data storage layer 65 may be formed as a material layer capable of storing data. In one embodiment, data storage layer 65 may be formed as a material layer capable of storing data that is altered by Fowler-Nordheim tunneling. The material layer may include a nitride layer capable of trapping charge. Barrier insulating layer 63 may include an oxide layer capable of blocking charge. Tunnel insulating layer 67 may be formed as a silicon oxide layer through which charge can tunnel.

[0050] The first channel structure 60[1] and the memory layer 61 surrounding the first channel structure 60[1] can form a first cell pillar 69[1]. The second channel structure 60[2] and the memory layer 61 surrounding the second channel structure 60[2] can form a second cell pillar 69[2]. A plurality of first cell pillars 69[1] and a plurality of second cell pillars 69[2] can penetrate the gate stack structure 90. A plurality of first cell pillars 69[1] and a plurality of second cell pillars 69[2] can be arranged in various ways on a plane extending along a first direction D1 and a second direction D2. In one embodiment, the first cell pillars 69[1] and the second cell pillars 69[2] can be arranged in a zigzag pattern to increase the arrangement density of the memory cell string.

[0051] The first selection line 35[1] and the second selection line 35[2] of the gate stack structure 90 can be arranged to be spaced apart from each other in a first direction D1. Each of the first selection line 35[1] and the second selection line 35[2] can extend in a second direction D2. The arrangement of the first selection line 35[1] and the second selection line 35[2] can be applied to Figure 2A The first source selection line 31A1 and the second source selection line 31A2 of the first height shown are illustrated and can be applied to... Figure 2A The second source selection line 32A1 at the second height and the second source selection line 32A2 at the second height are shown in the diagram. The layout of the first selection line 35[1] and the second selection line 35[2] can be applied to Figure 2B The first source selection line 30B1 and the second source selection line 30B2 are shown in the figure. The layout of the first selection line 35[1] and the second selection line 35[2] can be applied to Figure 2AThe first drain selection line 51A1 and the second drain selection line 51A2 of the third height shown are illustrated and can be applied to... Figure 2A The first drain selection line 52A1 and the second drain selection line 52A2 at the fourth height are shown in the diagram. The layout of the first selection line 35[1] and the second selection line 35[2] can be applied to Figure 2B The first drain selection line 51B1 and the second drain selection line 51B2 of the first height shown are illustrated and can be applied to... Figure 2B The first drain selection line 52B1 at the second height and the second drain selection line 52B2 at the second height are shown in the diagram.

[0052] The first selection line 35[1] and the second selection line 35[2] can be spaced apart from each other by means of a slit 37. The slit 37 can overlap with the word line 40 of the gate stack structure 90.

[0053] The first unit post 69[1] may include a slit-side first unit post adjacent to the slit 37, and the second unit post 69[2] may include a slit-side second unit post adjacent to the slit 37. When the width of the slit is made too wide or when the position of the slit is changed based on process errors, the sidewalls of the slit-side first unit post and the slit-side second unit post may be exposed by the slit. In one embodiment of this disclosure, the process of forming the slit 37 may be controlled such that the sidewalls of the slit-side first unit post and the slit-side second unit post are not exposed. The process of forming the slit 37 may be controlled by Figures 5G to 5I The implementation shown can be carried out, or it can be done through the following methods: Figure 7E The embodiment shown is carried out. By forming the slit 37 according to the embodiment of the present disclosure, the first selection line 35 [1] can be retained as a sidewall surrounding the first unit post on the slit side, and the second selection line 35 [2] can be retained as a sidewall surrounding the second unit post on the slit side. Therefore, according to the embodiment of the present disclosure, a selection transistor having a gate-all-around (GAA) structure can be defined at the intersection of the first unit post on the slit side and the first selection line 35 [1] and at the intersection of the second unit post on the slit side and the second selection line 35 [2].

[0054] refer to Figure 3B Bit lines 80 may overlap with gate stack structure 90. Each of the bit lines 80 may be simultaneously connected to a first channel structure 60 [1] and a second channel structure 60 [2] via a pair of first bit line contacts 70 [1] and second bit line contacts 70 [2]. The layout of the first bit line contacts 70 [1] and second bit line contacts 70 [2] may be varied based on the bit lines 80 and the first channel structure 60 [1] and second channel structure 60 [2].

[0055] The following describes a method for manufacturing a semiconductor memory device that enables the slits between select lines to self-align between cell pillars.

[0056] Figure 4 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0057] refer to Figure 4 A preliminary memory cell array can be provided through process ST1, which forms the preliminary memory cell array. The preliminary memory cell array may include conductive layers and interlayer insulating layers, which are alternately stacked on a support structure. At least one conductive layer adjacent to the support structure may form a select line.

[0058] After the initial memory cell array is formed, the peripheral circuitry can be bonded using bonding process ST3. Bonding process ST3 can be performed without isolating the at least one conductive layer adjacent to the support structure into a select line.

[0059] After the joining process ST3, the opening process ST5 of the unit column can be performed. The unit column can be opened by removing the supporting structure. The opened unit column can provide a non-uniform structure.

[0060] After process ST5, which opens the cell pillars, process ST7, which forms a protective layer, can be performed. A protective layer can be deposited to cover the non-uniform structure provided by the cell pillars. The protective layer can be deposited under conditions of poor step coverage. In one embodiment, the protective layer can be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD), which has a poorer step coverage than atomic layer deposition (ALD). The protective layer may include a material with etch selectivity relative to the interlayer insulating and conductive layers of the initial memory cell array. In one embodiment, the protective layer may include an amorphous carbon layer (ACL). The ACL can be deposited by plasma-enhanced chemical vapor deposition (PE-CVD).

[0061] Compared to the concave portion of an inhomogeneous structure, the protective layer deposited under conditions of poor step coverage can be formed relatively thickly on the convex portion of an inhomogeneous structure and can have a suspended structure.

[0062] After process ST7, which forms the protective layer, process ST9, which isolates the conductive layer into select lines, can be performed. A mask pattern can be formed on the protective layer using photolithography. Subsequently, the conductive layer can be isolated into select lines by using the mask pattern as an etching barrier. Although the protective layer is etched, it can be retained on the sidewalls of the unit pillars by using a protective layer with a different thickness based on its location. Therefore, the portion of the conductive layer overlapping the protective layer is exempt from etching. Thus, although the conductive layer is etched, the conductive layer constituting the select lines can be retained as sidewalls surrounding the unit pillars.

[0063] In the following implementation, the use of references will be described in more detail. Figure 4 The manufacturing process described is a method for manufacturing semiconductor memory devices.

[0064] Figures 5A to 5L This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0065] refer to Figure 5A ,pass Figure 4 The preliminary memory cell array 110 formed by process ST1 shown can be supported by support structure 101. The preliminary memory cell array 110 may include a stacked structure ST and cell pillars CP.

[0066] A stacked structure ST can be arranged between vertical insulating layers 133. The stacked structure ST may include a first surface SU1 facing the support structure 101; and a second surface SU2 facing in the opposite direction to the first surface SU1. The stacked structure ST may include an interlayer insulating layer 111 and a conductive layer 117, which are alternately stacked on the support structure 101. The interlayer insulating layer 111 and the conductive layer 117 may extend along a first direction D1 and a second direction D2. The interlayer insulating layer 111 and the conductive layer 117 may be arranged at heights spaced at different distances from the support structure 101.

[0067] Each of the conductive layers 117 may comprise a single conductive material or two or more different conductive materials. In one embodiment, each of the conductive layers 117 may comprise a metal barrier layer 113 and a metal layer 115. The metal barrier layer 113 may be disposed between each unit post CP and the metal layer 115. The metal barrier layer 113 may extend between each interlayer insulation layer 111 and the metal layer 115. However, embodiments of this disclosure are not limited thereto, and the conductive material of each conductive layer 117 may be different.

[0068] Each of the unit pillars CP may include: a first portion CP[1] that penetrates the stacked structure ST; and a second portion CP[2] that extends from the first portion CP[1] toward the support structure 101 in a third direction D3. The second portion CP[2] may be inserted into a trench 100 formed in the support structure 101. In one embodiment, the support structure 101 may be a silicon substrate having the trench 100.

[0069] Each of the unit pillars CP may include a storage layer 121, a channel layer 123, and a core insulating layer 125. The core insulating layer 125 may be disposed in the central region of the unit pillar CP. In other words, the core insulating layer 125 may be disposed in the central region of the first portion CP [1] and may extend to the central region of the second portion CP [2]. The channel layer 123 may surround the sidewall of the core insulating layer 125 and may extend along the bottom surface of the core insulating layer 125 facing the third direction D3. The storage layer 121 may extend along the outer wall of the channel layer 123 facing the support structure 101 and the stacked structure ST.

[0070] The channel layer 123 may include a semiconductor layer to provide memory cell strings MS1 and MS2 ( Figure 1 The channel region of each of the shown (shown). In one embodiment, channel layer 123 may include silicon. Storage layer 121 may include Figure 6A The barrier insulation layer 121A, data storage layer 121B, and tunnel insulation layer 121C are shown in the figure.

[0071] The preliminary memory cell array 110 can be formed using different processes. In one embodiment, the process of forming the preliminary memory cell array 110 may include: alternatingly stacking a first material layer and a second material layer on a support structure 101; forming a hole 120 penetrating the first material layer and the second material layer; etching the support structure 101 through the hole 120 to form a trench 100; forming a cell pillar CP that fills the hole 120 and extends into the trench 100; and forming a slit 131 penetrating the first material layer and the second material layer.

[0072] In one embodiment, the first material layer may be an interlayer insulating layer 111, and the second material layer may be selected from materials that are etch-selective relative to the interlayer insulating layer 111. In one embodiment, the interlayer insulating layer 111 may include silicon oxide, and the material that is etch-selective relative to silicon oxide may be silicon nitride. The second material layer formed of silicon nitride may be replaced with a conductive layer 117 via slit 131. After the second material layer is replaced with the conductive layer 117, a vertical insulating layer 133 may be used to fill slit 131.

[0073] refer to Figure 5BIt can form an isolation layer 135, which can penetrate Figure 5A Some conductive layers 117 are shown. The insulating layer 135 can penetrate at least one conductive layer in the conductive layer 117 adjacent to the second surface SU2 of the stacked structure ST. Figure 5A (As shown in the diagram). The conductive layer penetrated by the isolation layer 135 can be isolated into a first selection line 117S1. The isolation layer 135 can extend along the second direction D2 and can be formed of an insulating material. The first selection lines 117S1 arranged at the same height can be isolated from each other by means of the isolation layer 135.

[0074] The first selection line 117S1 can constitute a drain selection line or a source selection line. In the following description, based on an embodiment where the first selection line 117S1 constitutes a source selection line, reference will be made to... Figures 5C to 5L The subsequent processes are described, but this disclosure is not limited thereto.

[0075] refer to Figure 5C A recessed region 141 that exposes a portion of the inner wall of the channel layer 123 can be defined by etching a portion of the core insulating layer 125 of the unit pillar CP.

[0076] refer to Figure 5D A source layer 140 can be formed, which is connected to the channel layer 123 of the cell pillar CP. In one embodiment, the source layer 140 may include a doped semiconductor layer 143 and a conductive layer having a metal. The conductive layer having a metal may include a metal barrier layer 145 and a metal layer 147.

[0077] The doped semiconductor layer 143 may include: filling Figure 5C The recessed region 141 shown includes a pillar portion 143A and a horizontal portion 143B extending from the pillar portion 143A. The pillar portion 143A may contact and be surrounded by the channel layer 123. The horizontal portion 143B may extend to cover the stacked structure ST and the vertical insulating layer 133. The doped semiconductor layer 143 may include at least one of n-type impurities and p-type impurities. In one embodiment, the doped semiconductor layer 143 may include an n-type doped silicon layer.

[0078] A metal barrier layer 145 can be formed between the doped semiconductor layer 143 and the metal layer 147.

[0079] Subsequently, a first insulating layer 149 may be formed on the metal layer 147. The first insulating layer 149 may extend to cover the metal layer 147.

[0080] refer to Figure 5EThe peripheral circuit structure 170 can be arranged facing the first insulating layer 149. The peripheral circuit structure 170 may include: a substrate 151 having transistors 150; an insulating structure 161 covering the substrate 151; an interconnect structure 163; and a second insulating layer 169.

[0081] The substrate 151 may be a semiconductor substrate such as a silicon substrate or a germanium substrate. Each of the transistors 150 may be formed in an active region of the substrate 151, the active region being separated by an insulating layer 153. Each of the transistors 150 may include: a gate insulating layer 157 disposed on the active region; a gate electrode 159 disposed on the gate insulating layer 157; and a junction 155 formed on both sides of the gate electrode 159 in the active region. The transistors 150 may constitute peripheral circuitry for controlling the operation of a string of memory cells.

[0082] The insulating structure 161 may include two or more insulating layers. The interconnect structure 163 may be embedded in the insulating structure 161 and may be connected to the transistor 150. A second insulating layer 169 may be disposed on the insulating structure 161.

[0083] The peripheral circuit structure 170 can be bonded to the first insulating layer 149. In one embodiment, the second insulating layer 169 of the peripheral circuit structure 170 can be bonded to the first insulating layer 149.

[0084] refer to Figure 5F , Figure 5E The support structure 101 shown can be removed. Therefore, the second portion CP[2] of the cell pillar CP can be exposed. When the support structure 101 formed as a silicon substrate is removed, the storage layer 121 of the cell pillar CP can serve as an etch stop layer.

[0085] The support structure 101 can be removed, thereby defining the reference by the second part CP[2] of the unit column CP. Figure 4 The process ST5 shown describes a non-uniform structure. The second part CP[2] of the unit column CP can protrude further in the third direction D3 than the stacked structure ST, thus defining a non-uniform structure.

[0086] Subsequently, at least one of n-type and p-type impurities can be injected into a portion of the channel layer 123 constituting the second portion CP[2] of each unit pillar CP. In one embodiment, an impurity injection region 123N can be formed in a portion of the channel layer 123 of each unit pillar CP by injecting an n-type impurity into the channel layer 123.

[0087] refer to Figure 5GA protective layer 181 can be formed. The protective layer 181 can cover the second portion of CP of each unit pillar CP [2]. The protective layer 181 may include a material that has etch selectivity relative to the interlayer insulating layer 111 and the conductive layer 117. In one embodiment, the protective layer 181 may include an amorphous carbon layer.

[0088] Because protective layer 181 is based on reference Figure 4 The protective layer 181 is formed under the stepped coverage difference conditions described in process ST5, so it can have a suspended structure. The deposition thickness of the protective layer 181 can be controlled such that the space between the unit pillars CP is not completely filled by the protective layer 181. The protective layer 181 can be deposited such that the first opening 183 is defined by the protective layer 181 in the space between the unit pillars CP. The first opening 183 can be defined between the first inclined surface S1 and the second inclined surface S2 of the protective layer 181 that face each other between the unit pillars CP. Because the protective layer 181 has a suspended structure, the width WA of the first opening 183 can narrow as the first opening 183 moves away from the stacked structure.

[0089] The protective layer 181 may include a shielding pattern 181A, a protruding pattern 181B, and a horizontal pattern 181C. The protruding pattern 181B and the horizontal pattern 181C may extend from the shielding pattern 181A.

[0090] The shielding pattern 181A may be a portion of the protective layer 181 surrounding the sidewall SW of the second portion CP[2] of the unit post CP. The second portion CP[2] of the unit post CP may include a surface SU3 facing the third direction D3. The protruding pattern 181B may be a portion of the protective layer 181 disposed on the surface SU3 of the second portion CP[2]. The width of the protruding pattern 181B may widen as the protruding pattern 181B moves away from the second portion CP[2]. Specifically, the first width W1 of the protruding pattern 181B adjacent to the second portion CP[2] may be formed to be narrower than the second width W2 of the upper end of the protruding pattern 181B. Based on the structure of the protruding pattern 181B described above, a suspended structure can be defined.

[0091] The horizontal pattern 181C can be the portion of the protective layer 181 that overlaps with the stacked structure ST between the first inclined surface S1 and the second inclined surface S2. Because the protective layer 181 is deposited under conditions of poor step coverage, the thickness D1 of the protruding pattern 181 deposited on the surface SU3 of the second portion CP[2] can be thicker than the thickness D2 of the horizontal pattern 181C deposited on the first surface SU1 of the stacked structure ST.

[0092] refer to Figure 5HA mask pattern 185 can be formed on the protective layer 181 using a photolithography process. The mask pattern 185 can be a photoresist pattern. The mask pattern 185 may include a second opening 187.

[0093] The second opening 187 may extend in the second direction D2. The second opening 187 may overlap with the first opening 183. In one embodiment, the second opening 187 may expose the first opening 183, which overlaps with the insulating layer 135. However, the embodiments of this disclosure are not limited thereto, and the position and shape of the second opening 187 may be varied.

[0094] The width WB of the second opening 187 can be formed to be wider than the width WA of the first opening 183. In one embodiment, the sidewall 187S of the second opening 187 can overlap with the protruding pattern 181B.

[0095] According to one embodiment of this disclosure, the conductive layer 117 surrounding the unit post CP can be blocked by the shielding pattern 181A and protruding pattern 181B of the protective layer 181. Therefore, although the width WB of the second opening 187 is formed to be wider than the width WA of the first opening 183, a portion of the conductive layer 117 surrounding the unit post CP can be protected from subsequent etching processes by means of the protective layer 181.

[0096] According to embodiments of this disclosure, since it is not necessary to control the width WB of the second opening 187 to be less than or equal to the width WA of the first opening 183, the mask pattern 185 can be formed even without using a high-resolution exposure device.

[0097] refer to Figure 5I The slit 189 can be formed by etching a portion of the stacked structure ST through the second opening 187 and the first opening 183. The slit 189 can extend in the second direction D2.

[0098] exist Figure 5H At least one conductive layer in the conductive layer 117 of the stacked structure ST shown, adjacent to the first opening 183, can be isolated by the slit 189 to form a second select line 117S2. In one embodiment, the second select line 117S2 can constitute a drain select line. The conductive layer between the isolation layer 135 and the slit 189 can constitute a word line 117W. The word line 117W can extend to overlap with the isolation layer 135 and the slit 189.

[0099] A portion of the protective layer 181 can be etched during the etching process that forms the slit 189. The protective layer 181, with its suspended structure, is relative to the reference... Figure 5GThe regions have different thicknesses and widths, and the protective layer 181 can be retained at a reduced width W3 between the sidewall SW of the unit post CP and the first opening 183. More specifically, the portion of the protective layer 181 exposed by the second opening 187 may not be completely removed, and the reduced width W3 can be retained. The portion of the protective layer 181 retained between the sidewall SW of the unit post CP and the first opening 183 can protect the conductive layer 117 from the etching process. Therefore, the second selection line 117S2 can be retained between the slit 189 and the sidewall SW of the unit post CP, thus as referenced Figure 3A The aforementioned can define a selection transistor having a gate-all-around (GAA) structure.

[0100] refer to Figure 5J It can remove Figure 5I The protective layer 181 and mask pattern 185 shown make it possible to expose the unit pillar CP. Subsequently, an upper insulating layer 191 can be formed. The upper insulating layer 191 can extend to fill the slit 189 between the second selection lines 117S2 and cover the second portion CP of each unit pillar CP [2]. The surface of the upper insulating layer 191 can be planarized by a process such as chemical mechanical polishing (CMP).

[0101] refer to Figure 5K A bit line contact 197 can be formed, which contacts the channel layer 123 of the cell post CP. The process of forming the bit line contact 197 may include: forming a contact hole 190 that penetrates the upper insulating layer 191 and the storage layer 121; and filling the contact hole 190 with a conductive material.

[0102] The conductive material constituting the bit line contact 197 can be varied. In one embodiment, the bit line contact 197 may include a metal barrier layer 193 and a metal layer 195. The metal barrier layer 193 may extend along the surface of the contact hole 190 and may contact the channel layer 123. The metal layer 195 may be disposed on the metal barrier layer 193.

[0103] refer to Figure 5L A bit line 205, which contacts the bit line contact 197, can be formed on the upper insulating layer 191. The bit line 205 can overlap with the peripheral circuit structure 170, with the stacked structure ST inserted therebetween. The conductive material of the bit line 205 can be varied. In one embodiment, the bit line 205 may include a metal barrier layer 201 and a metal layer 203. The metal barrier layer 201 may extend to contact the bit line contact 197 and overlap with the upper insulating layer 191. The metal layer 203 may be disposed on the metal barrier layer 201.

[0104] Figure 5K and Figure 5LThe unit post CP shown may include: a unit post connected to bit line 205 shown in the figure; and a unit post connected to another line not shown in the figure. Some unit posts CP not connected to bit line 205 may be connected to another line not shown in the figure via bit line contacts not shown in the figure.

[0105] Figures 6A to 6C It is shown Figure 5F A cross-sectional view of one embodiment of the process for forming the impurity injection region shown. Figures 6A to 6C yes Figure 5F An enlarged cross-sectional view of region A shown in the diagram.

[0106] refer to Figure 6A When removed Figure 5E When the support structure 101 shown is in place, the barrier insulating layer 121A of the storage layer 121 can be exposed. The barrier insulating layer 121A, the data storage layer 121B, and the tunnel insulating layer 121C of the storage layer 121 can be formed by a reference... Figure 3A The barrier insulation layer 63, data storage layer 65, and tunnel insulation layer 67 described are made of the same material.

[0107] The portion of the barrier insulation layer 121A surrounded by the stacked structure ST can be protected by the stacked structure ST without being exposed.

[0108] refer to Figure 6B The exposed areas of the barrier insulating layer 121A can be selectively removed. In one embodiment, the exposed areas of the barrier insulating layer 121A can be removed by wet etching. Therefore, a portion of the data storage layer 121B can be exposed.

[0109] refer to Figure 6C At least one of n-type and p-type impurities can be implanted into a portion of the channel layer 123 surrounded by the unblocked insulating layer 121A and the stacked structure ST. Therefore, an impurity implantation region 123N can be formed in a portion of the channel layer 123. In one embodiment, the impurity implantation region 123N can be formed by implanting an n-type impurity 122 into a portion of the channel layer 123.

[0110] Figures 7A to 7H This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0111] refer to Figure 7A ,pass Figure 4 The preliminary memory cell array 310 formed by process ST1 shown can be supported by support structure 305. The preliminary memory cell array 310 may include a stacked structure ST' and cell pillars CP'.

[0112] The support structure 305 may include: a silicon substrate 301 overlapping the stacked structure ST'; and an etch stop layer 303 disposed between the stacked structure ST' and the silicon substrate 301. The etch stop layer 303 may include a material having etch selectivity relative to the silicon substrate 301. In one embodiment, the etch stop layer 303 may include a nitride layer.

[0113] The stacked structure ST' can be arranged between the vertical insulating layers 333. The stacked structure ST' may include conductive layers 309, 317, and 317S1 and an interlayer insulating layer 311, which are alternately stacked on the support structure 305. The conductive layers 309, 317, and 317S1 and the interlayer insulating layer 311 may extend along a first direction D1 and a second direction D2. The conductive layers 309, 317, and 317S1 and the interlayer insulating layer 311 may be arranged at different heights from the support structure 305.

[0114] Each of the conductive layers 309, 317, and 317S1 may comprise various conductive materials, such as metal layers, metal silicide layers, and doped silicon layers. In one embodiment, conductive layers 309, 317, and 317S1 may comprise: a first conductive layer 309 adjacent to the support structure 305; and second conductive layers 317 and 317S1 stacked on the first conductive layer 309 and spaced apart from each other. In one embodiment, the first conductive layer 309 may comprise doped silicon. Each of the second conductive layers 317 and 317S1 is similar to Figure 5A The conductive layer 117 shown may include a metal barrier layer 313 and a metal layer 315.

[0115] Each of the unit pillars CP' may include: a first portion CP'[1] that penetrates the stacked structure ST'; and a second portion CP'[2] that extends along a third direction D3 from the first portion CP'[1] toward the support structure 305. The second portion CP'[2] may be inserted into a trench 300 formed in the etch stop layer 303.

[0116] Each of the cell pillars CP' may include a memory layer 321, a channel layer 323, a core insulating layer 325, and a doped semiconductor pattern 327. A first portion CP'[1] of the cell pillar CP' may include a central region filled with the core insulating layer 325 and the doped semiconductor pattern 327. The core insulating layer 325 may extend to the central region of a second portion CP'[2]. The doped semiconductor pattern 327 may overlap with the core insulating layer 325. The doped semiconductor pattern 327 may include at least one of n-type and p-type impurities. In one embodiment, the doped semiconductor pattern 327 may include an n-type doped silicon layer.

[0117] The channel layer 323 may extend to surround the sidewalls of the core insulating layer 325 and the sidewalls of the doped semiconductor pattern 327. The channel layer 323 may extend along the bottom surface of the core insulating layer 325 facing third direction D3. The storage layer 321 may extend along the outer wall of the channel layer 323 facing the support structure 305 and the stacked structure ST'.

[0118] The channel layer 323 may include a semiconductor layer. The memory layer 321 may include... Figure 3A The barrier insulation layer 53, data storage layer 65, and tunnel insulation layer 67 are shown.

[0119] The initial memory cell array 310 can be formed using different processes. Reference [reference / reference] can be used. Figure 5A The described implementation method forms a preliminary storage cell array 310.

[0120] Subsequently, at least one of the conductive layers 317 and 317S1 can form a first selection line 317S1, which is spaced apart from each other by means of an insulating layer 335, as shown in the reference. Figure 5B The first selection line 317S1 can constitute a drain selection line or a source selection line. In the following description, the implementation of a drain selection line based on the first selection line 317S1 will be referred to... Figures 7B to 7H The subsequent processes are described. However, this disclosure is not limited thereto.

[0121] refer to Figure 7B This can form a bit line contact 345, which is connected to the channel layer 323 of the unit post CP'.

[0122] In one embodiment, the process of forming bit line contact 345 may include: forming a first insulating layer 337 that extends to cover cell pillar CP' and battery structure ST'; forming a contact hole 340 that penetrates the first insulating layer 337 and opens a doped semiconductor pattern 327; and filling the contact hole 340 with a conductive material.

[0123] In one embodiment, the conductive material constituting the bit line contact 345 may include a metal barrier layer 341 and a metal layer 343. The metal barrier layer 341 may extend along the surface of the contact hole 340 and may contact the doped semiconductor pattern 327. The metal layer 343 may be disposed on the metal barrier layer 341.

[0124] Subsequently, a bit line 351 can be formed, which contacts the bit line contact 345. The bit line 351 can extend onto the first insulating layer 337. The conductive material of the bit line 351 can be varied. In one embodiment, the bit line 351 may include a metal barrier layer 347 and a metal layer 349. The metal barrier layer 347 can contact the bit line contact 345 and can extend to overlap the first insulating layer 337. The metal layer 349 can be disposed on the metal barrier layer 347.

[0125] Figure 7B The unit post CP' shown may include: a unit post connected to bit line 351 shown in the figure; and a unit post connected to another line not shown in the figure. Some unit posts CP' not connected to bit line 351 may be connected to another line not shown in the figure via bit line contacts not shown in the figure.

[0126] Subsequently, a first insulating structure 353 can be formed on the bit line 351. A first interconnect structure 355 can be embedded in the first insulating structure 353. The first insulating structure 353 may include two or more insulating layers. The first interconnect structure 355 may include various shapes and types of conductive materials. The first interconnect structure 355 may include a first bonding metal pattern 355B. The first interconnect structure 355 may overlap with the stacked structure ST', with the bit line 351 interposed therebetween.

[0127] refer to Figure 7C The peripheral circuit structure 370 can be arranged facing the first bonding metal pattern 355B. Similar to the already referenced... Figure 5E As described, the peripheral circuit structure 370 may include: a substrate 361 having an active region separated by an isolation layer 363 and a transistor 360 formed in the active region; a second insulating structure 365 covering the substrate 361; and a second interconnect structure 367.

[0128] The second interconnect structure 367 may include various shapes and types of conductive materials. The second interconnect structure 367 may include a second bonding metal pattern 367B.

[0129] The peripheral circuit structure 370 can be bonded to the first interconnect structure 355. In one embodiment, the second insulating structure 365 of the peripheral circuit structure 370 can be bonded to the first insulating structure 353, and the second bonding metal pattern 367B of the peripheral circuit structure 370 can be bonded to the first bonding metal pattern 355B.

[0130] refer to Figure 7D It can remove Figure 7C The support structure 305 shown. When removed... Figure 7C When the silicon substrate 301 shown is used, the stacked structure ST' can be Figure 7CThe etch stop layer 303 shown provides protection. When... Figure 7C When the etch stop layer 303 of the support structure 305 shown is removed, the first conductive layer 309 can serve as an etch stop layer.

[0131] When the support structure 305 is removed, the second part CP'[2] of the unit column CP' can be exposed. Furthermore, refer to... Figure 4 The non-uniform structure described in process ST5 shown can be defined by the exposed second part CP'[2] of unit column CP'.

[0132] refer to Figure 7E This can form a protective layer 381. Similar to the referenced... Figure 5G As described, the protective layer 381 may have a suspended structure that covers the second part of each unit post CP'[2] and defines the first opening 383.

[0133] Subsequently, similar to what has already been referenced Figure 5H As described, a mask pattern 385 with a second opening 387 can be formed.

[0134] Subsequently, similar to what has already been referenced Figure 5I As described, etching can be performed through the second opening 387 and the first opening 383. Figure 7D A portion of the stacked structure ST' shown forms a slit 389.

[0135] Slit 389 can be formed as a penetration Figure 7D The first conductive layer 309 shown is illustrated. Figure 7D The first conductive layer 309 shown can be isolated by the slit 389 to form a second select line 309S2. In one embodiment, the second select line 309S2 can constitute a source select line. The conductive layer between the second select line 309S2 and the first select line 317S1 can constitute a word line 317W. The word line 317W can extend to overlap with the insulating layer 335 and the slit 389.

[0136] refer to Figure 7F It can remove Figure 7E The protective layer 381 and mask pattern 385 shown make it possible to expose the unit post CP'. Subsequently, an upper insulating layer 391 can be formed. The upper insulating layer 391 can extend to fill the slit 389 between the second selection lines 309S2 and cover the second portion of each unit post CP'[2].

[0137] refer to Figure 7G A portion of the upper insulating layer 391 and a portion of the storage layer 321 can be removed by an etching process such as a back etching process, so that the channel layer 323 of each unit pillar CP' can be exposed.

[0138] refer to Figure 7H A source layer 399 can be formed. The source layer 399 can be connected to the channel layer 323 of each unit pillar CP'. In one embodiment, the source layer 399 may include a doped semiconductor layer 393 and a conductive layer having metal. The conductive layer having metal may include a metal barrier layer 395 and a metal layer 397.

[0139] The doped semiconductor layer 393 may be in contact with the channel layer 323. The doped semiconductor layer 393 may include at least one of n-type and p-type impurities. In one embodiment, the doped semiconductor layer 393 may include an n-type doped silicon layer.

[0140] The metal barrier layer 395 can be formed between the doped semiconductor layer 393 and the metal layer 309.

[0141] Figure 8 This is a block diagram illustrating the construction of a storage system 1100 according to one embodiment of the present disclosure.

[0142] refer to Figure 8 The storage system 1100 includes a storage device 1120 and a storage controller 1110.

[0143] The storage device 1120 may include an array of memory cells and peripheral circuitry interconnected by bonding, and may include select transistors adjacent to the peripheral circuitry. The select transistors may be connected to select lines isolated by slits. Each select transistor may have a gate-all-around (GAA) structure.

[0144] Storage device 1120 may be a multi-chip package configured to have multiple flash memory chips.

[0145] The storage controller 1110 controls the storage device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a storage interface 1115. The SRAM 1111 can be used as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 may include a data exchange protocol for a host connected to the storage system 1100. The error correction block 1114 can detect and correct errors in data read from the storage device 1120. The storage interface 1115 can interface with the storage device 1120. The storage controller 1110 may also include a read-only memory (ROM) for storing code data that interfaces with the host.

[0146] Figure 9 This is a block diagram illustrating the construction of a computing system 1200 according to one embodiment of the present disclosure.

[0147] refer to Figure 9 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a storage system 1210, which are electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0148] The storage system 1210 may be configured with a storage device 1212 and a storage controller 1211. The storage device 1212 may include an array of storage cells and peripheral circuitry interconnected by bonding, and may include select transistors adjacent to the peripheral circuitry. The select transistors may be connected as select lines isolated by slits. Each select transistor may have a gate-all-around (GAA) structure.

[0149] According to this disclosure, the selection transistor, which is located at the intersection of the selection line and the cell pillar, can be formed as a gate all around (GAA) structure, thereby improving the operating characteristics of the semiconductor memory device.

[0150] Cross-references to related applications

[0151] This application claims priority to Korean Patent Application No. 10-2020-0129527, filed on October 7, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A preliminary memory cell array is formed on a support structure, the preliminary memory cell array having a stacked structure and cell pillars, wherein the stacked structure includes an interlayer insulating layer and a conductive layer alternately stacked on the support structure, and wherein each cell pillar has a first portion penetrating the stacked structure and a second portion extending from the first portion into the support structure; Remove the support structure to expose the second portion of each unit column; A protective layer is formed covering the second portion of each of the unit columns, wherein the protective layer has a first inclined surface and a second inclined surface facing each other, wherein a first opening is inserted between the first inclined surface and the second inclined surface, wherein the first inclined surface and the second inclined surface are arranged between the unit columns, and wherein the width of the first opening narrows as the first opening moves away from the second portion; A mask pattern exposing the first opening is formed on the protective layer; as well as At least one conductive layer adjacent to the first opening is etched into the conductive layer, thereby isolating the at least one conductive layer into a select line.

2. The method according to claim 1, wherein, The protective layer comprises a material that is etch-selective relative to the interlayer insulating layer and the conductive layer.

3. The method according to claim 1, wherein, The protective layer includes an amorphous carbon layer.

4. The method according to claim 1, wherein, The protective layer includes: A shielding pattern surrounding the sidewall of the second portion; and A protruding pattern is arranged on the surface of the second portion, the protruding pattern extending from the shielding pattern, and The width of the protruding pattern increases as it moves away from the second portion.

5. The method according to claim 4, wherein, The protective layer also includes a horizontal pattern overlapping the laminated structure between the first inclined surface and the second inclined surface, and The thickness of the protruding pattern is greater than the thickness of the horizontal pattern.

6. The method according to claim 4, wherein, The mask pattern includes a second opening that overlaps with the first opening, and The sidewall of the second opening overlaps with the protruding pattern.

7. The method according to claim 1, wherein, The mask pattern includes a second opening that overlaps with the first opening, and The width of the second opening is wider than the width of the first opening.

8. The method according to claim 1, wherein, The support structure includes a silicon substrate with trenches, and the second portion is inserted into the trenches.

9. The method according to claim 1, wherein, The support structure includes: A silicon substrate overlapping the stacked structure; and An etch stop layer is disposed between the stacked structure and the silicon substrate, the etch stop layer having trenches into which the second portion is inserted.

10. The method according to claim 9, wherein, The etch stop layer comprises a material that has etch selectivity relative to the silicon substrate.

11. The method according to claim 9, wherein, The etch stop layer includes a nitride layer.

12. The method according to claim 1, wherein, Each of the aforementioned unit columns includes: A core insulating layer, wherein the core insulating layer is disposed in the central region of the first portion and extends to the central region of the second portion; A channel layer, the channel layer surrounding the sidewalls of the core insulation layer, the channel layer extending along the bottom surface of the core insulation layer; and A storage layer extending along the outer wall of the channel layer, the storage layer facing the support structure and the stacked structure.

13. The method of claim 12, further comprising the step of removing the support structure prior to the following step: A portion of the core insulation layer is removed to define the recessed area; A doped semiconductor layer is formed to fill the recessed region, the doped semiconductor layer extending to cover the stacked structure; A metal layer is formed on the doped semiconductor layer; A first insulating layer is formed covering the metal layer; as well as The peripheral circuit structure is bonded to the first insulating layer.

14. The method of claim 13, further comprising the step of: Remove the protective layer and the mask pattern; An upper insulating layer is formed to fill the space between the selection lines, the upper insulating layer extending to cover the second portion of each of the unit posts; A bit line contact is formed that penetrates the upper insulating layer and the storage layer, and the bit line contact is in contact with the channel layer; as well as Bit lines that overlap with the peripheral circuit structure are formed on the upper insulating layer, and the stacked structure is inserted between the bit lines and the peripheral circuit structure.

15. The method according to claim 12, wherein, Each of the unit pillars further includes a doped semiconductor pattern overlapping the core insulating layer, and The channel layer extends to form sidewalls covering the doped semiconductor pattern.

16. The method of claim 15, further comprising the step of removing the support structure prior to the following step: A first insulating layer is formed, the first insulating layer extending to cover the unit pillar and the stacked structure; A bit line contact is formed that penetrates the first insulating layer, and the bit line contact is in contact with the doped semiconductor pattern; A bit line is formed that contacts the bit line contact member, and the bit line extends onto the first insulating layer; An interconnect structure is formed that overlaps with the stacked structure, and the bit line is inserted between the interconnect structure and the stacked structure; as well as The peripheral circuit structure is joined to the interconnect structure.

17. The method of claim 16, further comprising the step of: Remove the protective layer and the mask pattern; An upper insulating layer is formed to fill the space between the selection lines, the upper insulating layer extending to cover the second portion of each of the unit posts and the stacked structure; A portion of the upper insulating layer and a portion of the storage layer are removed to expose the channel layer; as well as A source layer is formed that is connected to the channel layer, the source layer overlapping the peripheral circuit structure, the stack-up structure and the bit line, wherein the stack-up structure and the bit line are interposed between the source layer and the peripheral circuit structure.

Images