Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. Provided is a semiconductor device stable in electrical characteristics even when a crystal defect that becomes a lifetime suppression element is formed within a semiconductor substrate. Having: a first semiconductor layer (2) provided between a first main surface (1a) and an n ‑ type drift layer (1); a first buffer layer (5) provided between the second main surface (1b) and the n ‑ type drift layer, having a hydrogen-induced donor; a second semiconductor layer (3) provided between the second main surface (1b) and the first buffer layer (5), the first buffer layer 5 having a complex defect between interstitial carbon and interstitial oxygen that decreases in density from the second main surface (1b) toward the first main surface (1a) side.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] In semiconductor devices such as diodes and IGBTs (Insulated Gate Bipolar Transistors), protons are injected into the back side of a thinned semiconductor substrate through grinding to form a buffer layer with hydrogen-induced donors, preventing the depletion layer extending from the front side of the semiconductor substrate from reaching the back side. Additionally, irradiating the semiconductor substrate with charged particles such as electrons, protons, or helium creates crystal defects within the substrate that act as lifetime killers, shortening the recombination lifetime of charge carriers and improving switching performance.

[0003] In conventional semiconductor device manufacturing methods, after crystal defects are formed by irradiating the front side of a semiconductor substrate with an electron beam, a heat treatment is performed at a temperature of 300°C or higher and 500°C for 1 hour to 10 hours to adjust the amount of crystal defects. Then, after protons are implanted from the back side of the semiconductor substrate, which has been thinned by grinding, a heat treatment is performed at a temperature of 350°C or higher and 550°C for 1 hour to 10 hours to donor the implanted protons and form a buffer layer with hydrogen-induced donors. In conventional semiconductor devices, crystal defects formed by electron beam irradiation are used as lifetime suppression factors and to improve the donor generation rate based on proton implantation (for example, see Patent Document 1).

[0004] Patent Document 1: Japanese Patent Application Publication No. 2015-130524

[0005] However, conventional semiconductor devices have crystal defects that increase the donor generation rate based on proton injection and become a factor in lifetime suppression. As a result, the following problem exists: the changes in electrical characteristics such as switching characteristics caused by changes in crystal defects due to heat generation under actual use of semiconductor devices have not been taken into account. Summary of the Invention

[0006] The present invention was proposed to solve the above-mentioned problems, and its purpose is to provide a semiconductor device and a method for manufacturing a semiconductor device with stable electrical characteristics even when crystal defects that become lifetime suppression factors are formed in the semiconductor substrate.

[0007] The semiconductor device of the present invention comprises: a drift layer of a first conductivity type disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first semiconductor layer of a second conductivity type disposed between the first main surface of the semiconductor substrate and the drift layer, having a higher impurity concentration than the drift layer; a first buffer layer of a first conductivity type disposed between the second main surface of the semiconductor substrate and the drift layer, having hydrogen donors having a higher impurity concentration than the drift layer; and a second semiconductor layer of either a first conductivity type or a second conductivity type disposed between the second main surface of the semiconductor substrate and the first buffer layer, having a higher impurity concentration than the drift layer, wherein the first buffer layer has interstitial carbon and interstitial oxygen recombination defects whose density decreases from the second main surface side toward the first main surface side.

[0008] Furthermore, the semiconductor device manufacturing method of the present invention includes the following steps: preparing a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and comprising carbon and oxygen; forming a first semiconductor layer of a second conductivity type with a higher impurity concentration than the semiconductor substrate on the first main surface side of the semiconductor substrate; after the step of forming the first semiconductor layer, grinding the semiconductor substrate from the second main surface side; after the step of grinding the semiconductor substrate, forming a second semiconductor layer of either the first conductivity type or the second conductivity type with a higher impurity concentration than the semiconductor substrate on the second main surface side of the semiconductor substrate; and grinding the semiconductor substrate... After the first heat treatment process, protons are injected from the second main surface side; in the first heat treatment process, the semiconductor substrate is heated at a first temperature to hydrogen-induced donor oxidation of the protons injected into the semiconductor substrate, forming a first buffer layer with a first conductivity type and a higher impurity concentration than the semiconductor substrate; in the charged particle irradiation process, after the first heat treatment process, the semiconductor substrate is irradiated with charged particles to form composite defects between interstitial carbon and interstitial oxygen, as well as composite defects between interstitial carbon and lattice carbon; and in the second heat treatment process, after the charged particle irradiation process, the semiconductor substrate is heated at a second temperature lower than the first temperature to eliminate the composite defects between interstitial carbon and lattice carbon.

[0009] The effects of the invention

[0010] The semiconductor device according to the present invention can provide a semiconductor device with stable electrical characteristics even when crystal defects that become lifetime-inhibiting factors are formed in the semiconductor substrate.

[0011] Furthermore, the semiconductor device manufacturing method according to the present invention can provide a method for manufacturing a semiconductor device with stable electrical characteristics even when crystal defects that become lifetime suppression factors are formed in the semiconductor substrate. Attached Figure Description

[0012] Figure 1This is a cross-sectional view showing the semiconductor device of Embodiment 1.

[0013] Figure 2 This is a diagram showing the impurity concentration distribution of the first and second buffer layers of the semiconductor device of Embodiment 1 and the semiconductor device of the comparative example.

[0014] Figure 3 This is a diagram showing an example of the spectral distribution of photoluminescence of the semiconductor device of Embodiment 1.

[0015] Figure 4 This is a graph showing the change in the amount of crystal defects relative to the depth measured from the second main surface in the semiconductor device of Embodiment 1 and the semiconductor device of the comparative example.

[0016] Figure 5 This is a graph showing the change in the amount of crystal defects relative to the depth measured from the second main surface in the semiconductor device of Embodiment 1 and the semiconductor device of the comparative example.

[0017] Figure 6 This is a graph showing the change in the amount of crystal defects relative to the depth measured from the second main surface in the semiconductor device of Embodiment 1 and the semiconductor device of the comparative example.

[0018] Figure 7 This is a graph showing the change in the amount of crystal defects relative to the depth measured from the second main surface in the semiconductor device of Embodiment 1 and the semiconductor device of the comparative example.

[0019] Figure 8 This is a flowchart illustrating a method for manufacturing a semiconductor device according to Embodiment 1.

[0020] Figure 9 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 10 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0022] Figure 11 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0023] Figure 12 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0024] Figure 13 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0025] Figure 14 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0026] Figure 15 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0027] Figure 16 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0028] Figure 17 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0029] Figure 18 This is a top view showing the structure of the semiconductor device in Embodiment 2.

[0030] Figure 19 yes Figure 18 A cross-sectional view of the semiconductor device 200 shown at the dashed line AA.

[0031] Figure 20 yes Figure 18 A cross-sectional view of the semiconductor device 200 shown at the dashed line BB.

[0032] Figure 21 This is a cross-sectional view showing the semiconductor device of Embodiment 3. Detailed Implementation

[0033] Implementation method 1.

[0034] First, the structure of the semiconductor device in Embodiment 1 will be described. Figure 1 This is a cross-sectional view showing the semiconductor device of Embodiment 1.

[0035] In the following description, n and p represent the conductivity type of the semiconductor. In this invention, the first conductivity type is defined as n-type and the second conductivity type as p-type. Furthermore, n - This indicates that the impurity concentration is lower than n, where n + This indicates that the impurity concentration is higher than n. Similarly, p - This indicates that the impurity concentration is lower than p, p + This indicates that the impurity concentration is higher than p.

[0036] exist Figure 1 In this context, the semiconductor device 100 is a diode, for example, an n-type diode grown using the FZ (Floating Zone) method or the MCZ (Magnetic Field Applied Czochralski) method. -The semiconductor device 100 is formed from a silicon semiconductor substrate. It has a first main surface 1a of the semiconductor substrate and a second main surface 1b opposite to the first main surface 1a. Each semiconductor layer is formed by introducing n-type or p-type impurities between the first main surface 1a and the second main surface 1b of the semiconductor substrate. The remaining portion of the semiconductor substrate becomes an n-type semiconductor layer. - Type 1 drift layer. - The n-type drift layer 1 is a semiconductor layer with an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 15 / cm 3 .

[0037] On the first principal surface 1a and n of the semiconductor substrate - A p-type anode layer 2 is disposed between the p-type drift layers 1. The p-type anode layer 2 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 p-type anode layer 2 is related to n - The drift layer 1 has a higher impurity concentration than the first semiconductor layer.

[0038] A first electrode, namely an anode electrode 6, is disposed on the first main surface 1a of the semiconductor substrate. The anode electrode 6 is in contact with and electrically connected to the p-type anode layer 2. Furthermore, in Figure 1 Although not illustrated, it can also be structured as follows: a p-type anode layer 2 with a higher concentration of p-type impurities than the p-type anode layer 2 is placed between the p-type anode layer 2 and the first main surface 1a. + Type-p contact layer, p-type anode layer 2 and anode electrode 6 are connected via p + Electrical connection is achieved through a type of contact layer.

[0039] The anode electrode 6 can be formed of an aluminum alloy, such as an aluminum-silicon alloy (Al-Si type alloy), or it can be an electrode composed of a multilayer metal film on which a coating has been formed by chemical plating or electrolytic plating. The coating formed by chemical plating or electrolytic plating can be, for example, a nickel coating or a copper coating. In addition, to prevent oxidation of nickel or copper, a gold coating can also be formed on the nickel coating or copper coating. Furthermore, a barrier metal made of a conductor containing titanium can be provided between the anode electrode 6 and the first main surface 1a of the semiconductor substrate, and the barrier metal can also be included and referred to as the anode electrode 6.

[0040] The semiconductor device 100 has a diode trench gate 11 on the first main surface 1a side of the semiconductor substrate. The diode trench gate 11 has a diode trench electrode 11a disposed in the trench through an oxide film 11b, the oxide film 11b being disposed from the first main surface 1a of the semiconductor substrate through the p-type anode layer 2 to the n-type anode layer 2. - The inner wall of the trench extends up to the drift layer 1. The diode trench electrode 11a contacts the anode electrode 6 on the first main surface 1a side and is electrically connected to the anode electrode 6. By providing the diode trench gate 11 in the diode, i.e., semiconductor device 100, the breakdown voltage of the semiconductor device 100 can be improved. However, the semiconductor device 100 functions as a diode even without the diode trench gate 11, so the diode trench gate 11 may not be provided.

[0041] On the second principal surface 1b and n of the semiconductor substrate - Between the drift layers 1, n are sequentially arranged starting from the second main surface 1b. + The structure consists of three layers: a first-type cathode layer (3), a second-type buffer layer (4), and a first-type buffer layer (5). The first buffer layer is an n-type buffer layer with hydrogen-induced donors formed through proton injection, and the concentration of n-type impurities is higher than that of n-type impurities. - Type drift layer 1. Additionally, the second buffer layer 4 is an n-type buffer layer containing phosphorus as an n-type impurity, with a higher n-type impurity concentration than the first buffer layer 5. + The cathode layer 3 is an n-type semiconductor layer with phosphorus and arsenic as n-type impurities, and the concentration of n-type impurities is higher than that of n-type semiconductors. - The p-type drift layer 1 is a second semiconductor layer higher than the first buffer layer 5 or the second buffer layer 4. Furthermore, although not shown, it can also be configured to introduce p-type impurities into the n-type layer in a discrete distribution. + Type 3 cathode layer, p-type semiconductor layers are discretely distributed on n + The structure of the cathode layer 3.

[0042] In addition, Figure 1 The image shows a semiconductor device 100 in n + The semiconductor device 100 has a structure with a second buffer layer 4 between the cathode layer 3 and the first buffer layer 5, but it can also have a structure without the second buffer layer 4. That is, the semiconductor device 100 only needs to have a second buffer layer 4 between the second main surface 1b and n of the semiconductor substrate. - A first buffer layer 5 is disposed between the drift layers 1 and the first buffer layer 5, and a second semiconductor layer, i.e., n, is disposed between the second main surface 1b of the semiconductor substrate and the first buffer layer 5. + Type 3 cathode layer is sufficient.

[0043] A second electrode, namely a cathode electrode 7, is disposed on the second main surface 1b of the semiconductor substrate. The cathode electrode 7 and n + Type 3 cathode layer contact, with n +The cathode layer 3 is electrically connected. Regarding the cathode electrode 7, it can be located in the second semiconductor layer, i.e., n... + A metal film containing at least one of Al, Ti, Ni, Au, Ag, and Cu is formed on the cathode layer 3 by sputtering or evaporation. Similarly to the anode electrode 6, the cathode electrode 7 may also have a structure in which a nickel or copper plating film is formed on the metal film formed by sputtering or evaporation by electroless plating or field plating. Furthermore, a gold plating film may also be formed on the nickel or copper plating film.

[0044] The semiconductor device 100 has crystal defects 9 formed within the semiconductor substrate, which are lifetime suppression factors that shorten the recombination lifetime of charge carriers. Figure 1 In the first buffer layer 5, crystal defects 9 that serve as lifetime inhibition factors are shown. However, crystal defects 9 that serve as lifetime inhibition factors only need to be formed at least in the first buffer layer 5, and can be formed in n - Type drift layer 1 can also be formed in the second buffer layer 4.

[0045] Crystal defects 9 that become lifetime suppression factors can be classified into several types according to their structure. In the case of fabricating a semiconductor device 100 using a silicon semiconductor substrate, crystal defects 9 that may become lifetime suppression factors include, for example, voids (V), interstitial silicon (ISi), interstitial carbon (Ci), lattice-position carbon (Cs), recombination defects of voids (V2, V4, or V6), recombination defects of interstitial silicon (ISi3 or ISi4), recombination defects between interstitial carbon and interstitial oxygen (CiOi), or recombination defects between interstitial carbon and lattice-position carbon (CiCs). Here, I or i represents the state (interstitial) of silicon (Si), carbon (C), or oxygen (O) atoms located between the lattice elements of the Si crystal. Furthermore, s represents the state (substitutional) of Si atoms at lattice positions of the Si crystal being replaced by other atoms.

[0046] Recombination defects between interstitial carbon and interstitial oxygen (CiOi), also known as C centers, emit 0.790 eV through photoluminescence. Recombination defects between interstitial carbon and lattice-position carbon (CiCs), also known as G centers, emit 0.969 eV through photoluminescence. Recombination defects in interstitial silicon (ISi3), also known as W centers, emit 1.019 eV through photoluminescence. Additionally, recombination defects in interstitial silicon (ISi4), also known as X centers, emit 1.040 eV through photoluminescence. The emission from C centers, G centers, W centers, and X centers through photoluminescence is referred to as C-line, G-line, W-line, and X-line, respectively. Hereinafter, the recombination defects between interstitial carbon and interstitial oxygen are sometimes referred to as CiOi, the recombination defects between interstitial carbon and lattice-position carbon as CiCs, and the recombination defects in interstitial silicon as ISi3 or ISi4.

[0047] Semiconductor device 100 has interstitial carbon-oxygen composite defects (CiOi) within its semiconductor substrate, and at least the first buffer layer 5 has interstitial carbon-oxygen composite defects (CiOi). If the temperature of the semiconductor substrate increases, the crystal defects gradually disappear, but CiOi disappears at a higher temperature compared to other crystal defects. For example, CsCs disappears at approximately 300°C, but CiOi disappears at approximately 400°C. In the case of semiconductor device 100, the density of CiOi contained within the semiconductor substrate is greater than the density of CiCs, and at least the density of CiOi contained in the first buffer layer 5 is greater than the density of CiCs.

[0048] Figure 2 This is a graph showing the impurity concentration distribution of the first and second buffer layers in the semiconductor device of Embodiment 1 and the comparative example semiconductor device. Figure 2 In the diagram, the "Example" shown by the solid line represents the impurity concentration distribution of the semiconductor device 100 of Embodiment 1, while the "Comparative Example 1" shown by the dashed line and the "Comparative Example 2" shown by the dotted line represent the impurity concentration distributions of comparative semiconductor devices. The impurity concentration was determined using the Spreading Resistance (SR) method. Figure 2 In the diagram, the horizontal axis represents the depth measured from the second principal surface, and the vertical axis represents the impurity concentration determined by the extended resistance method.

[0049] The semiconductor device 100 of Embodiment 1, i.e., the semiconductor device of the "Example," is manufactured differently from the semiconductor devices of "Comparative Example 1" and "Comparative Example 2." The processes for forming the crystal defect 9, which becomes a lifetime suppression factor, differ from those in the "Example," "Comparative Example 1," and "Comparative Example 2." The semiconductor device 100 of Embodiment 1, i.e., the semiconductor device of the "Example," is manufactured by the following process: after protons are implanted from the second main surface 1b side of the semiconductor substrate, a heat treatment is performed at a first temperature of 400°C for 2 hours; then, after irradiating the semiconductor substrate with an electron beam, a heat treatment is performed at a second temperature of 345°C for 0.5 hours. The semiconductor device of "Comparative Example 1" is manufactured by implanting protons from the second main surface 1b side of the semiconductor substrate after irradiating the semiconductor substrate with an electron beam, and then heating at 400°C for 2 hours. The semiconductor device of "Comparative Example 2" is manufactured by implanting protons from the second main surface 1b side of the semiconductor substrate and then heating at 400°C for 2 hours. The semiconductor device in "Comparative Example 2" is not irradiated with an electron beam. Furthermore, details regarding the manufacturing method of the semiconductor device 100 in Embodiment 1 will be described later.

[0050] like Figure 2 As shown, the semiconductor device 100 includes: a second buffer layer 4 having a concentration peak at a depth of 0.5 μm from the second main surface 1b of the semiconductor substrate, extending to a depth of 2 μm from the second main surface 1b; and a first buffer layer 5 extending from the second buffer layer 4 toward the first main surface 1a, extending to a depth of approximately 34 μm from the second main surface 1b. More located on the first main surface 1a side than the first buffer layer 5 is n. - Type drift layer 1. The second buffer layer 4 is a phosphorus-containing buffer layer, and the first buffer layer 5 is a hydrogen-containing donor buffer layer. The semiconductor devices of Comparative Example 1 and Comparative Example 2 also have the same second buffer layer 4 and first buffer layer 5 as the semiconductor device 100 of the embodiment, and have the same impurity concentration distribution.

[0051] like Figure 2 As shown, the first buffer layer 5 has four concentration peaks 5a, 5b, 5c, and 5d. However, the number of concentration peaks in the first buffer layer 5 can be greater than or equal to four or less than or equal to four, as long as at least one concentration peak with a hydrogen-induced donor is present. Figure 2 The concentration peaks of the first buffer layer 5, measured from the second principal surface 1b, are as follows: peak concentration 5a is 28.0 μm, peak concentration 5b is 20.0 μm, peak concentration 5c is 10.5 μm, and peak concentration 5d is 3.5 μm. The maximum impurity concentration of the first buffer layer 5 is less than 1.0 × 10⁻⁶. 15 / cm 3 ,For example, Figure 2The maximum impurity concentration of the first buffer layer 5 of the semiconductor device 100 in the illustrated embodiment is a peak concentration of 7.0 × 10⁻⁶ d⁻¹. 14 / cm 3 .

[0052] Next, we will describe the crystal defects 9 in the semiconductor substrate of the semiconductor device 100 that serve as lifetime inhibition factors. As mentioned above, there are several types of crystal defects that serve as lifetime inhibition factors, but the crystal defects in the semiconductor device 100 present in the semiconductor substrate can be evaluated, for example, by irradiating the semiconductor substrate with a laser and measuring the photoluminescence from the semiconductor substrate.

[0053] Figure 3 This is a diagram showing an example of the spectral distribution of photoluminescence from the semiconductor device of Embodiment 1. Figure 3 In the diagram, the horizontal axis represents the photon energy of photoluminescence, and the vertical axis represents the intensity of photoluminescence. Photon energy is calculated using the relationship E = h·v = h·c / λ. Here, E is the photon energy, h is Planck's constant, v is the frequency, c is the speed of light, and λ is the wavelength. Figure 3 The photoluminescence was obtained by cooling the semiconductor device 100 to 30K, irradiating a cross-section of the semiconductor device 100 with a He-Ne laser with a wavelength of 633nm, and detecting the light emission from the cross-section of the semiconductor device 100 using a spectrometer. The diameter of the irradiated He-Ne laser beam was 1.3μm, and the irradiation energy on the cross-section of the semiconductor device 100 was 4.5mW. Figure 3 It represents the spectral distribution of photoluminescence at a position 4 μm from the second main surface 1b of the semiconductor device 100.

[0054] like Figure 3 As shown, in the photoluminescence spectral distribution of the semiconductor device 100, C-lines caused by CiOi, G-lines caused by CiCs, W-lines caused by ISi3, and X-lines caused by ISi4 are visible. Additionally, in... Figure 3 In the image, the spectrum shown by the band-end is the band-end emission of silicon.

[0055] Figures 4-7 This is a graph showing the change in the amount of crystal defects in the semiconductor device of Embodiment 1 and the comparative semiconductor device relative to the depth measured from the second main surface. Figures 4-7 The “Example,” “Comparative Example 1,” and “Comparative Example 2” shown correspond to the examples provided by… Figure 2 The example shown is an illustration of the impurity concentration distribution. Figures 4-7In the diagram, the horizontal axis represents the depth measured from the second principal surface 1b, showing the illumination of He-Ne laser beams with a diameter of 1.3 μm at various depths. Figures 4-7 In the diagram, the vertical axis represents the photoluminescence intensity caused by crystal defects in a cross-section of the semiconductor device 100, normalized to a value equal to 1, based on the intensity of silicon band-end emission at each depth. Figures 4-7 In the figures, the measurement results of the semiconductor device in the “Example” are indicated by black dots, the measurement results of the semiconductor device in Comparative Example 1 are indicated by white triangles, and the measurement results of the semiconductor device in Comparative Example 2 are indicated by white boxes.

[0056] At once Figure 3 Regarding the photoluminescence spectrum shown, if the depth measured from the second principal plane changes, the intensity of the photoluminescence along the vertical axis (i.e., the intensity of the photoluminescence) changes even for factors other than the amount of crystal defects. However, due to... Figure 3 The band-end luminescence of silicon, as represented by the band end, differs from that of crystal defects and should not vary with depth measured from the second principal plane. Therefore, by standardizing multiple measurement data at different depths from the second principal plane in a manner that keeps the intensity of silicon band-end luminescence constant, variations other than the amount of crystal defects can be removed from the intensity variations of photoluminescence caused by each crystal defect, enabling the measurement of the amount of crystal defects corresponding to the depth measured from the second principal plane.

[0057] In addition, by Figures 4-7 The magnitude of the intensity / BE intensity, represented by the vertical axis, can be used as a relative value to represent the amount of crystal defects at the same photon energy. However, for example, it is not possible to compare the magnitude of the intensity / BE intensity between different photon energies such as C-line and X-line to evaluate the amount of crystal defects.

[0058] like Figure 4 As shown, in the semiconductor device 100 of Embodiment 1, i.e., the semiconductor device of the "Example", CiOi photoluminescence, i.e., C-line, appears at all measurement depths from the black dot mark 9a, which is closest to the second main surface 1b at a measurement depth of 1 μm, to the black dot mark 9d, which is furthest from the second main surface 1b at a measurement depth of 40 μm. On the other hand, in the semiconductor devices of "Comparative Example 1" and "Comparative Example 2", no C-line of effective size appears. That is, the semiconductor devices of "Comparative Example 1" and "Comparative Example 2" do not have an effective density of CiOi in the first buffer layer 5.

[0059] like Figure 2As shown, in the "Example", the first buffer layer 5 of the semiconductor device 100 is formed to a depth of approximately 34 μm from the second main surface 1b, and is further from the first main surface 1a than the depth of 34 μm from the second main surface 1b. - Type 1 drift layer. (e.g., ...) Figure 4 As shown, regarding the semiconductor device 100 of the "Embodiment", as in the case where a C-line is also observed at a depth of 40 μm from the second main surface 1b, the first buffer layer 5 has a crystal defect 9, CiOi, which is a lifetime suppression factor, and the second buffer layer 4 and n - Type-1 drift layer also has CiOi. Additionally, as... Figure 2 As shown, the concentration peak 5a closest to the first principal surface 1a among the multiple concentration peaks of the first buffer layer 5 has a depth of 28.0 μm from the second principal surface 1b. Therefore, CiOi exists on the side closer to the first principal surface 1a than the concentration peak 5a closest to the first principal surface 1a among the concentration peaks of the first buffer layer 5.

[0060] Additionally, the semiconductor device 100 in the "Example" has within the first buffer layer 5 Figure 4 The CiOi density shown at the observation points from black dot mark 9b to black dot mark 9c indicates that the density of CiOi within the first buffer layer 5 decreases from the second main surface 1b side towards the first main surface 1a side. The density of CiOi in the first buffer layer 5 of the semiconductor device 100 decreases with increasing depth from the second main surface 1b, but the percentage decrease in CiOi density is smaller at shallower depths from the second main surface 1b and increases with increasing depth from the second main surface 1b.

[0061] Furthermore, the second buffer layer 4 of the semiconductor device 100 in the "embodiment" also has a depth of 2 μm from the second main surface 1b. Figure 4 CiOi is represented by the observation point marked 9a with a black dot. Figure 4 The vertical axis of the black dot mark 9a is smaller than that of the black dot mark 9b. That is, with respect to the semiconductor device 100 of the "Embodiment", the density of CiOi in the second buffer layer 4 is less than the maximum density of CiOi in the first buffer layer 5.

[0062] Next, as Figure 5 As shown, regardless of the distance measured from the second principal surface 1b, the observed G-line values ​​of the semiconductor device 100 of Embodiment 1 (i.e., the semiconductor device of "Example 1", the semiconductor device of "Comparative Example 1", and the semiconductor device of "Comparative Example 2") all show values ​​of 0.3 to 0.4. However, from... Figure 3The spectral distribution of photoluminescence shows that a broad spectral distribution of emission is observed near the G-line, where the G-line represents the extent to which this broad emission overlaps and is only observable. That is, in... Figure 5 In the study, observations of 0.3–0.4 were obtained, but most of these observations were due to the broad luminescence. Figure 5 The contribution of the G-line in the image is minimal, and no effective size of G-line is observed. Therefore, the first buffer layer 5 of the semiconductor device 100 in the "Example" does not have an effective density of CiCs. Similarly, the first buffer layer of the semiconductor device in "Comparative Example 1" and the first buffer layer of the semiconductor device in "Comparative Example 2" also do not have an effective density of CiCs. Furthermore, from... Figure 4 and Figure 5 The measurement results show that the density of CiOi in the first buffer layer 5 of the semiconductor device 100 in the "Example" is greater than the density of CiCs present in the first buffer layer 5.

[0063] like Figure 6 As shown, regarding the W-line, at a depth of 2μm to 34μm from the second main surface where the first buffer layer is located, the semiconductor device 100 of "Example" is the largest, followed by the semiconductor device of "Comparative Example 2," and the semiconductor device of "Comparative Example 1" is the smallest. Furthermore, regardless of the semiconductor device, at a depth of 2μm to 34μm from n... - At a depth of 34 μm or deeper from the second principal plane where the type-drift layer is located, the W-line cannot be effectively observed. That is, regardless of the semiconductor device, ISi3 does not exist at an effective density in n... - Type drift layer.

[0064] like Figure 6 As shown, the semiconductor device 100 of the "Embodiment" has ISi3 in the first buffer layer 5 and the second buffer layer 4. The density of ISi3 in the first buffer layer 5 of the semiconductor device 100 decreases with increasing depth from the second main surface 1b, but the rate of decrease in ISi3 density is greater at shallower depths from the second main surface 1b and decreases with increasing depth. This tendency of defect density variation is similar to... Figure 4 The CiOi shown is different. That is, the first buffer layer 5 of the semiconductor device 100 has a region with the following characteristics: from the second main surface 1b side toward the first main surface 1a side, the density of CiOi decreases by a larger percentage, and the density of ISi3 decreases by a smaller percentage.

[0065] like Figure 7As shown, regarding X-rays, at a depth of 2 μm to 34 μm from the second principal plane where the first buffer layer is located, the semiconductor device in "Comparative Example 1" is the largest, followed by the semiconductor device 100 in "Example," and the semiconductor device in "Comparative Example 2" is the smallest. Furthermore, regardless of the semiconductor device, at a depth of 2 μm to 34 μm from n... - At a depth of 34 μm or deeper from the second principal plane where the drift layer is located, the observed values ​​on the vertical axis are very small. Regardless of the semiconductor device, n - The density of the ISi4 drift layer is less than or equal to 1 / 10 to 2 / 10 of the maximum density in the first buffer layer 5 or the second buffer layer 4.

[0066] In addition, such as Figure 7 As shown, the semiconductor device 100 of the "embodiment" has ISi4 in the first buffer layer 5 and the second buffer layer 4. The density of ISi4 in the first buffer layer 5 of the semiconductor device 100 is similar to... Figure 6 Similarly, the density of ISi3 decreases with increasing depth from the second principal surface 1b, but the proportion of density decrease in ISi4 is greater at shallower depths from the second principal surface 1b and decreases with increasing depth. This tendency of defect density variation is similar to... Figure 4 The CiOi shown is different. That is, the first buffer layer 5 of the semiconductor device 100 has a region with the following characteristics: from the second main surface 1b side toward the first main surface 1a side, the density decrease of CiOi increases and the density decrease of ISi4 decreases.

[0067] The semiconductor device 100 of Embodiment 1 is configured as described above.

[0068] Next, the manufacturing method of the semiconductor device according to Embodiment 1 will be described. Figure 8 This is a flowchart illustrating a method for manufacturing a semiconductor device according to Embodiment 1. Additionally, Figures 9-17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Embodiment 1. Figures 9-17 The diagram shows the state of the semiconductor device 100 during the manufacturing process.

[0069] First of all, Figure 8 In step S01, the process of preparing the semiconductor substrate, such as Figure 9As shown, a semiconductor substrate 1c is prepared having a first main surface 1a and a second main surface 1b opposite to the first main surface 1a. The semiconductor substrate 1c is a semiconductor substrate containing carbon and oxygen as impurities, and may be, for example, a silicon semiconductor substrate grown by the FZ method or MCZ method. In a silicon semiconductor substrate grown by the FZ method or MCZ method, oxygen and carbon are contained as impurities due to the bulk growth process. The silicon semiconductor substrate grown by the FZ method or MCZ method has a thickness of 1.0 × 10⁻⁶. 15 ~2.0×10 18 / cm 3 The oxygen concentration is 3.0 × 10⁻⁶. 13 ~2.0×10 15 / cm 3 The carbon concentration is relatively high. Silicon semiconductor substrates grown using the MCZ method have a higher oxygen concentration compared to silicon semiconductor substrates grown using the FZ method. In the case where semiconductor substrate 1c is not a silicon semiconductor substrate grown using the FZ or MCZ method, but rather a semiconductor substrate with a low concentration of carbon or oxygen contained as impurities, it can be a semiconductor substrate in which carbon or oxygen has been implanted and then thermally diffused within the semiconductor substrate. Alternatively, oxygen can be introduced into the semiconductor substrate from the atmosphere or an oxidizing atmosphere through heat treatment processes such as oxide film formation and annealing during semiconductor device manufacturing.

[0070] Next, in Figure 8 In the surface structure formation process of step S02, a first semiconductor layer, namely a p-type anode layer 2, is formed on the first main surface 1a side of the semiconductor substrate 1c. Furthermore, if the semiconductor device 100 has a diode trench gate 11, the diode trench gate 11 is formed on the first main surface 1a side of the semiconductor substrate 1c. Figure 10 A cross-sectional view showing a state in which a first semiconductor layer, namely a p-type anode layer 2 and a diode trench gate 11 are formed on the first main surface 1a side of the semiconductor substrate 1c.

[0071] First, after implanting p-type impurities such as boron (B) from the first main surface 1a side of the semiconductor substrate 1c, the semiconductor substrate 1c is heated at a temperature greater than or equal to 1000°C for 1 to 8 hours, thereby causing impurity ions to diffuse and forming a p-type anode layer 2. Next, as follows... Figure 10 As shown, a p-type anode layer 2 is formed that extends from the first main surface 1a side of the semiconductor substrate 1c to the n-type anode layer 2. -After the trench of the drift layer 1 is formed, the semiconductor substrate 1c is heated in an oxygen-containing atmosphere to form an oxide film 11b on the inner wall of the trench. Next, polysilicon doped with n-type or p-type impurities is deposited in the trench with the oxide film 11b formed on the inner wall by CVD (chemical vapor deposition) or the like to form a diode trench electrode 11a and a diode trench gate 11.

[0072] Next, as Figure 11 As shown, a first electrode, namely an anode electrode 6, is formed on the first main surface 1a of the semiconductor substrate 1c. The anode electrode 6 is formed by sintering the semiconductor substrate 1c after aluminum (Al) has been formed on the first main surface 1a of the semiconductor substrate 1c by sputtering or vapor deposition. The anode electrode 6 is formed in contact with the p-type anode layer 2. The anode electrode 6 can also be formed such that, after aluminum has been formed by sputtering or vapor deposition, a nickel or copper plating film is further formed on the aluminum film by chemical plating or electrolytic plating. Furthermore, the anode electrode 6 does not necessarily have to be formed before the back-side grinding process of the semiconductor substrate 1c described below; it can also be formed after the process described below. That is, the process of forming the anode electrode 6 may not be included in the... Figure 8 The surface structure formation process in step S02.

[0073] Next, in Figure 8 In the back-side grinding process of step S03, the second main surface 1b of the semiconductor substrate 1c is ground, such as... Figure 12 As shown, the semiconductor substrate 1c is thinned to a predetermined thickness. The thickness of the semiconductor substrate 1c after grinding can be, for example, 80 μm to 200 μm. Furthermore, strictly speaking, the second principal surface 1b of the semiconductor substrate 1c before the back-side grinding process disappears after the back-side grinding process; however, in this invention, the surface of the semiconductor substrate 1c opposite to the first principal surface 1a is defined as the second principal surface 1b. That is, with the thinning achieved by the back-side grinding of the semiconductor substrate 1c, the second principal surface 1b exists near the first principal surface 1a.

[0074] Next, in Figure 8 In the proton implantation process of step S04, such as Figure 13 As shown, protons 10 are implanted into the semiconductor substrate 1c from the second main surface 1b side. The protons 10 are implanted into the region 51 where the first buffer layer 5 is formed. By changing the proton implantation energy, the depth of the implanted protons, measured from the second main surface 1b, can be adjusted. Figure 2 For the semiconductor device 100 of the "Embodiment", the semiconductor device of "Comparative Example 1", and the semiconductor device of "Comparative Example 2", the proton acceleration energy and injection rate are set to 400 keV and 3.0 × 10⁻⁶ keV, respectively.13 / cm 2 800keV, 1.5×10 13 / cm 2 1200keV, 8.0×10 12 / cm 2 1500keV, 4.0×10 12 / cm 2 The first buffer layer 5 is formed through four proton injections.

[0075] In addition, Figure 2 In the semiconductor device of "Comparative Example 1" shown, prior to proton implantation, electron beam irradiation is performed from the first main surface 1a side of the semiconductor substrate at an accelerating energy of 750 keV as charged particle irradiation. The semiconductor device 100 of "Example" and the semiconductor device of "Comparative Example 2" do not undergo electron beam irradiation prior to proton implantation. However, in the semiconductor device 100 of Embodiment 1, charged particle irradiation may also be performed prior to proton implantation.

[0076] Next, in Figure 8 In the first heat treatment step of step S05, such as Figure 14 As shown, proton donors implanted into the semiconductor substrate 1c are proton-donated to form an n-type first buffer layer 5 with hydrogen-induced donors. Furthermore, in Figure 14 The illustration of the protons after donor conversion is omitted. In the first heat treatment step, the semiconductor substrate 1c is heated for 0.5 hours and 4 hours at a first temperature greater than or equal to 380°C and less than or equal to 525°C. If the first temperature is less than 380°C, the donor conversion of the injected protons is insufficient; if it exceeds 525°C, defects are generated in the semiconductor substrate 1c during heating, which is therefore not preferred. The first heat treatment step can be performed in a nitrogen atmosphere. Figure 2 The semiconductor device 100 of the “Example”, the semiconductor device of “Comparative Example 1”, and the semiconductor device of “Comparative Example 2” set the first temperature to 400°C and heated in a nitrogen atmosphere for 2 hours to donate the injected protons.

[0077] Next, in Figure 8 In the back-side structure formation process of step S06, such as Figure 15 As shown, a second buffer layer 4 is formed by implanting phosphorus from the second main surface 1b side of the semiconductor substrate 1c, and then arsenic or phosphorus is implanted from the second main surface 1b side of the semiconductor substrate 1c to form n. + Type 3 cathode layer. For example, it can be a second buffer layer 4 to accelerate to an energy of 990 keV and an injection volume of 2.0 × 10⁻⁶. 13 / cm 2 And to inject phosphorus, n +Type 3 cathode layer with an acceleration energy of 50 keV and an injection rate of 2.0 × 10⁻⁶ 15 / cm 2 Phosphorus implantation is then performed. Next, laser annealing is performed by irradiating the second main surface 1b of the semiconductor substrate 1c with a laser, thereby removing the phosphorus implanted into the second buffer layer 4 and the phosphorus implanted into the n... + Arsenic or phosphorus is used to activate the cathode layer 3. Furthermore, laser annealing involves placing the semiconductor substrate 1c in the atmosphere and irradiating the second main surface 1b with a laser. At this time, nitrogen can also be sprayed onto the irradiated second main surface 1b to adjust the amount of oxygen introduced into the semiconductor substrate 1c.

[0078] also, Figure 8 The back-side structure formation process in step S06 can be performed before the charged particle irradiation process in step S07, or it can be performed between the proton irradiation process in step S04 and the first heat treatment process in step S05, or between the back-side grinding process in step S03 and the proton implantation process in step S04. By performing the back-side structure formation in step S06 before the charged particle irradiation process in step S07, the CiOi formed in the charged particle irradiation process in step S07 can also remain within the second buffer layer 4 formed in the back-side structure formation process in step S06.

[0079] Next, in Figure 8 In step S07, the charged particle irradiation process involves irradiating charged particles from either the first main surface 1a side or the second main surface 1b side of the semiconductor substrate 1c. Figure 16 As shown, a crystal defect 9, which becomes a lifetime suppression factor, is formed in the semiconductor substrate 1c. At this time, in the first buffer layer 5, the second buffer layer 4, and the n... - Type-drift layer 1 forms crystal defects 9 that become lifetime-inhibiting factors. The irradiated charged particles can be electrons or protons.

[0080] When the charged particle is a proton, an irradiation device with high acceleration energy, such as a cyclotron, can be used to irradiate the proton at an acceleration energy of 5 to 10 MeV. Alternatively, an aluminum absorber can be disposed on the first main surface 1a or the second main surface 1b of the semiconductor substrate 1c to decelerate the protons accelerated by the irradiation device before irradiating the semiconductor substrate 1c. By irradiating the protons with a high acceleration energy of 5 to 10 MeV, the distribution of crystal defects formed in the semiconductor substrate 1c can be broadened. Furthermore, by decelerating the protons by the aluminum absorber, the peak depth of the crystal defect density formed in the semiconductor substrate 1c can be controlled.

[0081] When the charged particle is an electron, due to the electron's long range, even if an electron beam is irradiated from either the first principal surface 1a or the second principal surface 1b of the semiconductor substrate 1c, crystal defects can still form in the region from the first principal surface 1a to the second principal surface 1b of the semiconductor substrate 1c. The accelerating energy of the irradiated electrons can be, for example, 500–1000 keV. Figure 2 In the semiconductor device 100 of the illustrated "Embodiment", in the charged particle irradiation step S07 after the first heat treatment step, as charged particle irradiation, electron beam irradiation is performed from the first main surface 1a side of the semiconductor substrate 1c with an acceleration energy of 750 keV. The semiconductor devices of "Comparative Example 1" and "Comparative Example 2" do not undergo electron beam irradiation after the first heat treatment step in step S05.

[0082] Next, in Figure 8 In the second heat treatment step of step S08, crystal defects that disappear at a temperature lower than the second temperature, formed in the charged particle irradiation step of step S07, are eliminated, while crystal defects that do not disappear at the second temperature remain. Crystal defects that disappear at a temperature lower than the second temperature are, for example, CiCs, while crystal defects that do not disappear at the second temperature are, for example, CiOi. In the proton implantation step of step S04, protons implanted into the semiconductor substrate 1c are activated and hydrogen-induced donors at a temperature greater than or equal to 360°C, but the second temperature is preferably a temperature less than 360°C that does not contribute to the activation of protons. In the second heat treatment step, the semiconductor substrate 1c is heated at a second temperature greater than or equal to 250°C and less than or equal to 350°C for greater than or equal to 10 minutes and less than or equal to 2 hours. Figure 2 The semiconductor device 100 of the "Example" shown sets the second temperature to 345°C and heats it in a nitrogen atmosphere for 30 minutes to make CiCs disappear.

[0083] As mentioned above, CsCs disappears at approximately 300°C, but CiOi disappears at approximately 400°C. Therefore, by setting the second temperature of the second heat treatment process in step S08 to be greater than or equal to 250°C and less than or equal to 350°C, CiCS can disappear at a greater proportion than CiOi.

[0084] Next, as Figure 17 As shown, a second electrode, namely a cathode electrode 7, is formed on the second main surface 1b of the semiconductor substrate 1c, and the semiconductor substrate 1c is cut into a specified size, thereby completing the semiconductor device 100.

[0085] The second electrode, namely the cathode electrode 7, is formed through a film-forming process followed by a sintering process involving heating. This film-forming process is performed on the second semiconductor layer, i.e., n, formed on the second main surface 1b side of the semiconductor substrate 1c. + A metal film comprising at least one of Al, Ti, Ni, Au, Ag, and Cu is formed on the cathode layer 3 by sputtering or vapor deposition. The heating temperature in the sintering process can be equal to the second temperature of the second heat treatment process, for example, it can be greater than or equal to 250°C and less than or equal to 350°C. Therefore, the second heat treatment process in step S08 can also be performed after the film formation process for forming the cathode electrode 7, and the second heat treatment process can also be used as a sintering process. By using the second heat treatment process as a sintering process, the manufacturing process of the semiconductor device 100 can be simplified, and the cost of the semiconductor device 100 can be reduced.

[0086] Furthermore, the film-forming process for forming the second electrode, i.e., the cathode electrode 7, and the sintering process can also be performed before the charged particle irradiation process in step S07. In this case, the heating temperature of the sintering process can be higher than the second temperature of the second heat treatment process, or the heating temperature of the sintering process can be lower than the first temperature of the first heat treatment process and higher than the second temperature of the second heat treatment process. On the other hand, if the sintering process is performed after the second heat treatment process in step S08, the heating temperature of the sintering process can be lower than the second temperature of the second heat treatment process. By making the heating temperature of the sintering process performed after the second heat treatment process lower than the second temperature, it is possible to prevent the CiOi remaining in the second heat treatment process from disappearing in the sintering process.

[0087] The semiconductor device 100 of Embodiment 1 is manufactured through the above processes.

[0088] As described above, the semiconductor device 100 of Embodiment 1 has more CiOi (crystal defects 9) within the semiconductor substrate compared to CiCs, which are considered lifetime suppression factors. The semiconductor device 100 in n - The drift layer 1 has more CiOi than CiCs, and the first buffer layer 5 and the second buffer layer 4 also have more CiOi than CiCs.

[0089] The semiconductor device 100 is formed using a silicon semiconductor substrate; therefore, the maximum operating temperature in actual use is approximately 175°C. Crystal defects formed within the semiconductor substrate, which are factors affecting lifetime suppression, can be continuously used for extended periods even at temperatures as low as 175°C for crystal defect recovery. Consequently, the crystal defects gradually disappear, and electrical characteristics such as switching speed change. That is, in Figure 8In the manufacturing method of the semiconductor device 100 shown, without performing the second heat treatment step S08, CiOi and CiCs remain in the semiconductor substrate as crystal defects 9, which are factors that inhibit lifetime. However, if it is used continuously at 175°C for a long time, CiOi and CiCs gradually disappear together. Therefore, the variation in electrical characteristics becomes larger, and long-term quality assurance becomes difficult. In particular, CiCs disappear at a lower temperature than CiOi. Therefore, even with long-term use, the proportion of CiCs disappearing is greater than the proportion of CiOi disappearing, and CiCs remain, thus making long-term quality assurance difficult.

[0090] On the other hand, the semiconductor device 100 in Embodiment 1 Figure 8 In the second heat treatment step of step S08, CiCs disappears more than CiOi, thus... Figure 4 and Figure 5 As shown, in the first buffer layer 5, the second buffer layer 4, and n - The drift layer 1 has more CiOi compared to CiCs. Compared to CiCs, CiOi disappears at a higher temperature through the recovery of crystal defects. Therefore, the semiconductor device 100 of Embodiment 1, which has less residual CiCs and more residual CiOi, exhibits minimal variation in electrical characteristics such as switching speed even when used continuously for a long time at 175°C. This enables stable electrical characteristics and facilitates long-term quality assurance.

[0091] Implementation method 2.

[0092] Figure 18 This is a top view showing the structure of the semiconductor device according to Embodiment 2. Additionally, Figure 19 and Figure 20 This is a cross-sectional view showing the structure of the semiconductor device in Embodiment 2. Figure 19 yes Figure 18 The cross-sectional view of the semiconductor device 200 shown at the dashed line AA. Figure 20 yes Figure 18 A cross-sectional view of the semiconductor device 200 shown at the dashed line BB. Figure 18 In the middle, it is marked with Figure 1 Structures with the same reference numerals indicate the same or corresponding structures, and their descriptions are omitted. The semiconductor device 200 in Embodiment 2 is an IGBT (Insulated Gate Bipolar Transistor).

[0093] like Figure 18As shown, in the semiconductor device 200, the active trench gate 12 and the dumb trench gate 13 are arranged in a strip shape. The active trench gate 12 is configured to have a gate trench electrode 12a disposed in a trench formed in the semiconductor substrate, separated by a gate trench insulating film 12b. The dumb trench gate 13 is configured to have a dumb trench electrode 13a disposed in a trench formed in the semiconductor substrate, separated by a dumb trench insulating film 13b. The gate trench electrode 12a of the active trench gate 12 is electrically connected to a gate pad (not shown). The dumb trench electrode 13a of the dumb trench gate 13 is electrically connected to a first electrode, namely an emitter electrode 26, disposed on the first main surface 1a of the semiconductor device 200.

[0094] n + The source layer 25 is disposed in contact with the gate trench insulating film 12b on both sides of the active trench gate 12 in the width direction. + The source layer 25 is a semiconductor layer with n-type impurities such as arsenic or phosphorus, and the concentration of the n-type impurities is 1.0 × 10⁻⁶. 17 / cm 3 ~1.0×10 20 / cm 3 n + The source layer 25 extends along the extension direction of the active trench gate 12 and is adjacent to the p + Type contact layers 32 are alternately arranged. p + The contact layer 32 is also disposed between two adjacent dumb trench gates 13. + The p-type contact layer 14 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0 × 10⁻⁶. 15 / cm 3 ~1.0×10 20 / cm 3 .

[0095] like Figure 18 As shown, the semiconductor device 200 is configured such that three dumb trench gates 13 are arranged adjacent to three side-by-side active trench gates 12, and three active trench gates 12 are arranged adjacent to three side-by-side dumb trench gates 13. The semiconductor device 200 is configured in this way such that groups of active trench gates 12 and groups of dumb trench gates 13 are alternately arranged side-by-side. Figure 18 In this configuration, the number of active trench gates 12 in a group of active trench gates 12 is set to 3, but it can be greater than or equal to 1. Similarly, the number of dumb trench gates 13 in a group of dumb trench gates 13 can be greater than or equal to 1, or the number of dumb trench gates 13 can be 0. That is, all trenches provided in the semiconductor device 200 can also be designated as active trench gates 12.

[0096] Figure 19It is a semiconductor device 200 Figure 18 The sectional view at the dashed line AA in the diagram. (See example...) Figure 19 As shown, semiconductor device 200 in n - The first main surface 1a of the drift layer 1 is provided with a surface that is similar to n. - The n-type carrier accumulation layer 15 has a higher concentration of n-type impurities compared to the n-type drift layer 1. The n-type carrier accumulation layer 15 is a semiconductor layer containing, for example, arsenic or phosphorus as n-type impurities, with a concentration of 1.0 × 10⁻⁶. 13 / cm 3 ~1.0×10 17 / cm 3 Furthermore, the semiconductor device 200 may also omit the n-type carrier accumulation layer 15, while... Figure 19 The region of the n-type carrier accumulation layer 15 shown also has n - The structure of the n-type drift layer 1. By providing the n-type carrier accumulation layer 15, the current loss when current flows through the semiconductor device 200 can be reduced. Alternatively, the n-type carrier accumulation layer 15 and n... - The drift layers 1 are collectively referred to as drift layers.

[0097] A p-type base layer 22 is provided as a first semiconductor layer on the first main surface 1a side of the n-type carrier accumulation layer 15. The p-type base layer 22 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 22 is in contact with the gate trench insulating film 12b of the active trench gate 12. An n-type base layer 22 is disposed on the first main surface 1a side of the p-type base layer 22 in contact with the gate trench insulating film 12b of the active trench gate 12. + Type source layer 25, with p in the remaining region + Type contact layer 32. n + Type source layer 25 and p + The contact layer 32 forms the first main surface 1a of the semiconductor substrate. Furthermore, p... + The p-type contact layer 32 is a region with a higher concentration of p-type impurities compared to the p-type base layer 22, where it is necessary to control p-type impurities. + When distinguishing between the p-type contact layer 32 and the p-type base layer 22, they can be referred to separately, or the p-type base layer 22 can be referred to as... + The p-type contact layer 32 and the p-type base layer 22 are collectively referred to as the p-type base layer. In the case of the semiconductor device 200 of Embodiment 2, the first semiconductor layer refers to the layer in which the p-type contact layer 32 is formed. + The p-type base layer is referred to as the p-type base layer, which is a combination of the p-type contact layer 32 and the p-type base layer 22.

[0098] Furthermore, semiconductor device 200, like semiconductor device 100 in Embodiment 1, has n - A first buffer layer 5 and a second buffer layer 4 are provided on the second main surface 1b side of the drift layer 1. The structure and formation method of the first buffer layer 5 and the second buffer layer 4 are the same as those described in Embodiment 1. The first buffer layer 5 has crystal defects 9 that serve as lifetime inhibition elements. Although not shown in the figure, the second buffer layer 4 also has crystal defects 9 that serve as lifetime inhibition elements. - The drift layer 1 also has crystal defects 9 that become lifetime suppression factors. As explained in Embodiment 1, the crystal defects 9 that become lifetime suppression factors in the semiconductor device 200 are CiOi, CiCs, ISi3, or ISi4, and the first buffer layer 5, the second buffer layer 4, and n - The density of CiOi in drift layer 1 is greater than the density of CiCs.

[0099] The semiconductor device 200 has a p-type collector layer 23 disposed as a second semiconductor layer on the second main surface 1b side of the second buffer layer 4. That is, the p-type collector layer 23 is disposed between the first buffer layer 5 and the second main surface 1b. The p-type collector layer 23 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 23 constitutes the second main surface 1b of the semiconductor substrate.

[0100] like Figure 19 As shown, the semiconductor device 200 has a p-type base layer 22 extending from the first main surface 1a of the semiconductor substrate to the n-type base layer 22. - The trench of the drift layer 1. An active trench gate 12 is formed by providing a gate trench electrode 12a within the trench, separated by a gate trench insulating film 12b. The gate trench electrode 12a is connected to the n-type drift layer 1 through the gate trench insulating film 12b. - The drift layer 1 is opposite to the type. Furthermore, a dumb trench gate 13 is formed by providing a dumb trench electrode 13a within the trench, separated by a dumb trench insulating film 13b. The dumb trench electrode 13a is separated from the n-type drift layer by the dumb trench insulating film 13b. - The drift layer 1 is opposite to the active trench gate 12. The gate trench insulating film 12b of the active trench gate 12 is opposite to the p-type base layer 22 and the n-type base layer 22. + The p-type source layer 25 is in contact. If a gate drive voltage is applied to the gate trench electrode 12a, a channel is formed in the p-type base layer 22 that is in contact with the gate trench insulating film 12b of the active trench gate 12.

[0101] like Figure 19As shown, an interlayer insulating film 28 is disposed on the gate trench electrode 12a of the active trench gate 12. A barrier metal 29 is formed on the region of the first main surface 1a of the semiconductor substrate where the interlayer insulating film 28 is not disposed, and also on the interlayer insulating film 28. The barrier metal 29 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi alloyed with titanium and silicon (Si). Figure 19 As shown, blocking metal 29 and n + Type source layer 25, p + Type contact layer 32 and dummy trench electrode 13a ohmic contact, with n + Type source layer 25, p + The contact layer 32 and the dumb groove electrode 13a are electrically connected.

[0102] An emitter electrode 26 is disposed on top of the barrier metal 29. The emitter electrode 26 may have the same structure as the anode electrode 6 of the semiconductor device 100 described in Embodiment 1. Alternatively, when there are small areas, such as between adjacent interlayer insulating films 28, where good filling cannot be achieved by the emitter electrode 26, tungsten, which has better filling properties than the emitter electrode 26, may be disposed in the small areas, and the emitter electrode 26 may be disposed on top of the tungsten. Furthermore, the barrier metal 29 may be omitted, and the emitter electrode 26 may be disposed on top of the tungsten. + Type source layer 25, p + An emitter electrode 26 is disposed on the contact layer 32 and the dummy trench electrode 13a. Alternatively, an emitter electrode 26 may be disposed only on n. + A barrier metal 29 is disposed on an n-type semiconductor layer such as the source layer 25. The barrier metal 29 and the emitter electrode 26 can be collectively referred to as the first electrode, i.e., the emitter electrode.

[0103] In addition, Figure 19 The diagram shows a configuration where the interlayer insulating film 28 is not provided on the dumb trench electrode 13a of the dumb trench gate 13, but the interlayer insulating film 28 can also be formed on the dumb trench electrode 13a of the dumb trench gate 13. When the interlayer insulating film 28 is formed on the dumb trench electrode 13a of the dumb trench gate 13, it is sufficient to electrically connect the emitter electrode 26 to the dumb trench electrode 13a in other cross-sections.

[0104] A second electrode, namely a collector electrode 27, is provided on the second main surface 1b side of the p-type collector layer 23. The collector electrode 27 may have the same structure as the cathode electrode 7 of the semiconductor device 100 described in Embodiment 1. The collector electrode 27 is in ohmic contact with the p-type collector layer 23 and is electrically connected to the p-type collector layer 23.

[0105] Figure 20 It is a semiconductor device 200 Figure 18 The cross-sectional view at the dashed line BB in the diagram. (And...) Figure 19 The difference in the sectional view shown at the dashed line AA is that, Figure 20 The cross-section at the dashed line BB does not show n, which is disposed on the first main surface 1a side of the semiconductor substrate in contact with the active trench gate 12. + Type source electrode layer 25. That is, as... Figure 18 As shown, n + The p-type source layer 25 is selectively disposed on the first main surface 1a side of the p-type base layer. Furthermore, the p-type base layer referred to here means a p-type base layer 22 and a p-type base layer 25. + The p-type base layer is referred to as the contact layer 32.

[0106] Regarding the semiconductor device 200, photoluminescence caused by the C-line induced by CiOi can also be obtained from... Figure 4 The same measurement results were obtained for the density change of CiOi relative to the depth measured from the second main surface 1b of the semiconductor device. Furthermore, the photoluminescence of the G-line induced by CiCs was obtained... Figure 5 The same measurement results represent the density variation of CiCs relative to the depth measured from the second main surface 1b of the semiconductor device.

[0107] Furthermore, like the semiconductor device 100 of Embodiment 1, the semiconductor device 200 has interstitial silicon recombination defects, i.e., ISi3 or ISi4, within the semiconductor substrate. Moreover, in the case of the semiconductor device 200, photoluminescence from the W-line caused by ISi3 can also be obtained... Figure 6 The same measurement results were obtained for the density change of ISi3 relative to the depth measured from the second main surface 1b of the semiconductor device. Additionally, X-ray photoluminescence induced by ISi4 was obtained... Figure 7 The same measurement results show the density change of ISi4 of the semiconductor device relative to the depth measured from the second main surface 1b.

[0108] Like the semiconductor device 100 of Embodiment 1, semiconductor device 200 has more CiOi in the semiconductor substrate compared to CiCs, which are crystal defects 9 that constitute lifetime suppression factors. Semiconductor device 200 has more CiOi in n - The drift layer 1 has more CiOi than CiCs, and the first buffer layer 5 and the second buffer layer 4 also have more CiOi than CiCs. As a result, the semiconductor device 200 of Embodiment 2 achieves the same effect as the semiconductor device 100 of Embodiment 1.

[0109] Implementation method 3.

[0110] Figure 21 This is a cross-sectional view showing the semiconductor device in Embodiment 3. Figure 21 In the middle, it is marked with Figure 1 , Figure 19 or Figure 20 Structures with the same reference numerals indicate the same or corresponding structures, and their descriptions are omitted. The cases where the semiconductor device 100 is a diode in Embodiment 1 and the semiconductor device 200 is an IGBT in Embodiment 2 have been described, but the semiconductor device 300 in Embodiment 3 is an RC-IGBT (Reverse Conducting IGBT) in which an IGBT region 40 and a diode region 41 are provided in a single semiconductor substrate.

[0111] The semiconductor device 300 has one or more IGBT regions 40 and diode regions 41 within a semiconductor substrate (semiconductor chip). The semiconductor device 300 is configured such that the IGBT regions 40 and diode regions 41 are alternately arranged in a strip shape, or the IGBT regions 40 are arranged in a manner that surrounds the diode regions 41 which are arranged in an island-like distribution, or the diode regions 41 are arranged in a manner that surrounds the IGBT regions 40 which are arranged in an island-like distribution.

[0112] The IGBT region 40 and the diode region 41 constitute a cell region, and an end region is provided between the cell region and the outer periphery of the semiconductor substrate (semiconductor chip) in a manner that surrounds the cell region. The first buffer layer 5, the second buffer layer 4, and n - Type-a type drift layer 1 is also provided in the end region, and the first buffer layer 5, the second buffer layer 4, or n in the end region are also provided. - Type-shifted drift layers can also have crystal defects that can become lifetime-inhibiting factors.

[0113] like Figure 21 As shown, the structure of the IGBT region 40 of the semiconductor device 300 is the same as that of the IGBT, i.e., semiconductor device 200, described in Embodiment 2. Furthermore, the structure of the diode region 41 of the semiconductor device 300 is the same as that of the diode, i.e., semiconductor device 100, described in Embodiment 1, but the difference lies in the fact that the structure of the diode region 41 between the p-type anode layer 2 and the n-type anode layer 400 is different. - There is an n-type carrier accumulation layer 15 between the n-type drift layers 1, and a p-type anode layer 2 between the p-type anode layer 2 and the first main surface 1a. + Type contact layer 32. Additionally, the difference lies in that a p-type collector layer 23 is provided across a distance U1 from the boundary between the IGBT region 40 and the diode region 41 toward the diode region 41, without an n-type collector layer. +Type 3 cathode layer. Furthermore, diode region 41 may also be provided without an n-type carrier storage layer 15, as in the semiconductor device 100 described in Embodiment 1. + Type contact layer 32, and n is also provided in a range of distance U1 from the boundary between IGBT region 40 and diode region 41 toward diode region 41. + The structure of the cathode layer 3.

[0114] Regarding the semiconductor device 300 in Embodiment 3, in the IGBT region 40, the first semiconductor layer is composed of a p-type base layer 22 and a p-type base layer 22. + The p-type base layer, which is formed by combining the p-type contact layer 32, is located in diode region 41. The first semiconductor layer is formed by combining the p-type anode layer 2 and the p-type base layer 32. + The anode layer is formed by merging the contact layers 32. Additionally, the second semiconductor layer is a p-type collector layer 23 in the IGBT region 40 and an n-type collector layer 23 in the diode region 41. + Type 3 cathode layer.

[0115] The first electrode of the diode region 41 of the semiconductor device 300, namely the anode electrode, is integrally formed with the emitter electrode 26 of the IGBT region 40, and the second electrode of the diode region 41, namely the cathode electrode, is integrally formed with the collector electrode 27 of the IGBT region 40.

[0116] like Figure 21 As shown, the semiconductor device 300 has crystal defects 9 in the first buffer layer 5 of the IGBT region 40 and the first buffer layer 5 of the diode region 41, which are factors that inhibit lifetime. Additionally, although not shown in the figure, crystal defects 9, which are factors that inhibit lifetime, also exist in the second buffer layer 4 of the IGBT region 40 and the first buffer layer 5 of the diode region 41. - n-type drift layer 1 and diode region 41 - The drift layer 1 also has crystal defects 9 that become lifetime suppression factors. As described in Embodiment 1, the crystal defects 9 that become lifetime suppression factors in the semiconductor device 300 are CiOi, CiCs, ISi3, or ISi4, and the first buffer layer 5, the second buffer layer 4, and n - The density of CiOi in drift layer 1 is greater than the density of CiCs.

[0117] Regarding the semiconductor device 300, photoluminescence induced by CiOi along the C-line is also obtained. Figure 4 The same measurement results were obtained for the density change of CiOi relative to the depth measured from the second main surface 1b of the semiconductor device. Furthermore, the photoluminescence of the G-line induced by CiCs was obtained... Figure 5The same measurement results represent the density variation of CiCs relative to the depth measured from the second main surface 1b of the semiconductor device.

[0118] Furthermore, like the semiconductor device 100 of Embodiment 1, the semiconductor device 300 has interstitial silicon recombination defects, i.e., ISi3 or ISi4, within the semiconductor substrate. Moreover, in the semiconductor device 300, photoluminescence is also obtained from the W-line photoluminescence caused by ISi3. Figure 6 The same measurement results were obtained for the density change of ISi3 relative to the depth measured from the second main surface 1b of the semiconductor device. Additionally, X-ray photoluminescence induced by ISi4 was obtained... Figure 7 The same measurement results show the density change of ISi4 of the semiconductor device relative to the depth measured from the second main surface 1b.

[0119] Like the semiconductor device 100 of Embodiment 1, semiconductor device 300 has more CiOi in the semiconductor substrate than CiCs, which are crystal defects 9 that constitute lifetime suppression factors. Semiconductor device 300 has more CiOi in n - The drift layer 1 has more CiOi than CiCs, and the first buffer layer 5 and the second buffer layer 4 also have more CiOi than CiCs. As a result, the semiconductor device 300 of Embodiment 3 achieves the same effect as the semiconductor device 100 of Embodiment 1.

[0120] Explanation of the label

[0121] 1 n - Type-shifting layer, 1a First main surface, 1b Second main surface, 1c Semiconductor substrate

[0122] 2 p-type anode layer (first semiconductor layer)

[0123] 3 n + Type-2 cathode layer (second semiconductor layer)

[0124] 4. Second Buffer Layer

[0125] 5. Buffer Layer 1

[0126] 6. Anode electrode

[0127] 7. Cathode electrode

[0128] 9. Crystal defects

[0129] 10 protons

[0130] 11 Diode trench gate

[0131] 12 Active Trench Gate

[0132] 13. Dumb Trench Gate

[0133] 15 n-type carrier accumulation layer

[0134] 22 p-type base layer (first semiconductor layer)

[0135] 23 p-type collector layer (second semiconductor layer)

[0136] 25 n + Source layer

[0137] 27 Collector electrode

[0138] 28-layer interlayer insulation film

[0139] 29. Blocking metal

[0140] 32 p + Type-contact layer (first semiconductor layer)

[0141] 40 IGBT areas

[0142] 41 Diode Region

[0143] 100, 200, 300 semiconductor devices

Claims

1. A semiconductor device, comprising: a drift layer of a first conductivity type provided in a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first semiconductor layer of a second conductivity type provided between the first main surface of the semiconductor substrate and the drift layer, having a higher impurity concentration than the drift layer; a first buffer layer of the first conductivity type provided between the second main surface of the semiconductor substrate and the drift layer, having a hydrogen-induced donor having a higher impurity concentration than the drift layer; and a second semiconductor layer of the first conductivity type or the second conductivity type provided between the second main surface of the semiconductor substrate and the first buffer layer, having a higher impurity concentration than the drift layer, the first buffer layer having a density of a complex defect between interstitial carbon and interstitial oxygen decreasing from the second main surface side toward the first main surface side, the density of the complex defect between the interstitial carbon and the interstitial oxygen of the first buffer layer being greater than a density of a complex defect between interstitial carbon and lattice position carbon present in the first buffer layer.

2. The semiconductor device according to claim 1, wherein the complex defect between the interstitial carbon and the interstitial oxygen is a lifetime inhibiting element that shortens a carrier recombination lifetime.

3. The semiconductor device according to claim 1 or 2, wherein the first buffer layer further has a complex defect of interstitial silicon decreasing in density from the second main surface side toward the first main surface side, the first buffer layer having a region in which, from the second main surface side toward the first main surface side, a proportion of a decrease in the density of the complex defect between the interstitial carbon and the interstitial oxygen increases, and a proportion of a decrease in the density of a complex defect caused by the interstitial silicon decreases.

4. The semiconductor device according to claim 1 or 2, wherein the first buffer layer has at least one concentration peak of the hydrogen-induced donor, the complex defect between the interstitial carbon and the interstitial oxygen being present at a position closer to the first main surface than a concentration peak closest to the first main surface among the concentration peaks of the hydrogen-induced donor.

5. The semiconductor device according to claim 1 or 2, further comprising a second buffer layer of the first conductivity type provided between the second semiconductor layer and the first buffer layer, containing phosphorus as an impurity, having a higher impurity concentration than the first buffer layer, the second buffer layer having a complex defect between the interstitial carbon and the interstitial oxygen, the density of the complex defect between the interstitial carbon and the interstitial oxygen within the second buffer layer being smaller than a maximum density of the complex defect between the interstitial carbon and the interstitial oxygen within the first buffer layer.

6. The semiconductor device according to claim 1 or 2, wherein the second semiconductor layer is a collector layer of the second conductivity type.

7. The semiconductor device according to claim 1 or 2, wherein the second semiconductor layer is a cathode layer of the first conductivity type.

8. The semiconductor device according to claim 1 or 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The semiconductor substrate has an IGBT region in which the second semiconductor layer is a collector layer of a second conductivity type and a diode region in which the second semiconductor layer is a cathode layer of a first conductivity type.

9. A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, containing carbon and oxygen; forming a first semiconductor layer of a second conductivity type having a higher impurity concentration than the semiconductor substrate on the first main surface side of the semiconductor substrate; grinding the semiconductor substrate from the second main surface side after the step of forming the first semiconductor layer; forming a second semiconductor layer of the first conductivity type or the second conductivity type having a higher impurity concentration than the semiconductor substrate on the second main surface side of the semiconductor substrate after the step of grinding the semiconductor substrate; injecting protons from the second main surface side after the step of grinding the semiconductor substrate; a first heat treatment step of heating the semiconductor substrate at a first temperature to hydrogenate the protons injected into the semiconductor substrate to form a first buffer layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate; a charged particle irradiation step of irradiating the semiconductor substrate with charged particles to form complex defects between interstitial carbon and interstitial oxygen and complex defects between interstitial carbon and lattice position carbon after the first heat treatment step; and a second heat treatment step of heating the semiconductor substrate at a second temperature lower than the first temperature to eliminate the complex defects between interstitial carbon and lattice position carbon and to leave the complex defects between interstitial carbon and interstitial oxygen after the charged particle irradiation step.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the second heat treatment step eliminates the complex defects between interstitial carbon and lattice position carbon at a larger proportion than the complex defects between interstitial carbon and interstitial oxygen.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the charged particles are electrons or protons.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the charged particles are electrons or protons.

13. The method for manufacturing a semiconductor device according to any one of claims 9 to 12, wherein the complex defects between interstitial carbon and interstitial oxygen are lifetime inhibiting elements that shorten a carrier recombination lifetime.

14. The method for manufacturing a semiconductor device according to any one of claims 9 to 12, wherein the complex defects between interstitial carbon and interstitial oxygen are formed in the first buffer layer.

15. The method for manufacturing a semiconductor device according to any one of claims 9 to 12, wherein the first temperature is greater than or equal to 380°C and less than or equal to 525°C, the second temperature is greater than or equal to 250°C and less than or equal to 350°C.

16. The method for manufacturing a semiconductor device according to any one of claims 9 to 12, wherein The step of forming the second semiconductor layer includes a step of irradiating laser light on the second main surface of the semiconductor substrate in the atmosphere after injecting impurities of the first conductivity type or impurities of the second conductivity type from the second main surface side of the semiconductor substrate, The charged particle irradiation step is performed after the step of forming the second semiconductor layer.

17. The method for manufacturing a semiconductor device according to any one of Claims 9 to 12, wherein a step of forming a second buffer layer of the first conductivity type between the second semiconductor layer and the first buffer layer is further included, the second buffer layer of the first conductivity type contains phosphorus as an impurity, and the impurity concentration is higher than that of the first buffer layer, The charged particle irradiation step is performed after the step of forming the second buffer layer.

18. The method for manufacturing a semiconductor device according to any one of Claims 9 to 12, wherein a film formation step of forming a metal film on the second semiconductor layer and a sintering treatment step of heating the metal film are included, the film formation step is performed between the first heat treatment step and the second heat treatment step, the sintering treatment step is performed by the second heat treatment step.

19. The method for manufacturing a semiconductor device according to Claim 18, wherein the film formation step includes a step of forming a metal film containing at least one of Al, Ti, Ni, Au, Ag, and Cu by sputtering or evaporation on the second semiconductor layer.

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