Positive and negative three-value SR trigger circuit based on binary memristor

Abstract

The invention discloses a positive and negative three-value SR trigger circuit based on a binary memristor. The invention comprises a signal trigger circuit and a signal latch circuit. The signal latch circuit comprises three identical basic logic gates and a composite logic gate, and a corresponding pair of basic logic gates and the composite logic gate constitute a group of logic units. Each basic logic gate comprises two memristors, the negative poles of which are used as unit input terminals, and the positive poles are connected as the output terminals of the basic logic gates. The composite logic gate comprises four memristors and two MOS tubes, the positive pole of a memristor is connected to the output terminal of the basic logic gate, the negative pole is connected to the negative pole of another memristor and then connected to the gates of the two MOS tubes, the drain of one MOS tube is connected to the power supply through the memristor, and the source is connected to the drain of another MOS tube. The trigger circuit comprises three composite logic gates of the same structure, which are respectively connected to the three unit input terminals of the signal latch circuit. The circuit structure of the invention is clear and simple, easy to implement, and can be universal for positive and negative.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, relates to a three-value digital logic circuit structure, and specifically relates to a positive and negative three-value SR trigger circuit based on a binary memristor. Background Art

[0002] In 1971, Professor Shao-Tang Tsai of the University of California, Berkeley, predicted from the perspective of circuit theory completeness that in addition to resistors, capacitors, and inductors, there is a fourth missing passive basic circuit element that characterizes the relationship between charge and magnetic flux, and named it memristor. In the more than 30 years since the concept of memristor was proposed, there has been almost no progress in research on memristors due to the inability to obtain physical memristor devices. It was not until 2008 that HP Labs linked the theoretical concept of memristor with the phenomenon of bipolar transition of resistance in TiO2 devices and proposed the HP model of memristor. As a nonlinear nanoelement, HP memristor has unique nanometer size, memory characteristics, non-volatile characteristics, hard switching characteristics, etc., and can be applied to medicine, biological sciences, neural networks, chaotic systems, microelectronics and other related fields.

[0003] At present, most of the research is to apply memristors to binary digital logic circuit systems. Compared with binary signals, multi-value signals carry more information, which can improve the information density of transmission signal lines and integrated circuits and the time and space utilization of information processing. In three-valued logic circuits, there is an intermediate level between low level and high level, which plays a great role in reducing power consumption and circuit integration. Therefore, the three-valued logic system has gradually become a substitute for the binary logic system. In terms of realizing high-density logic systems, it has higher operating speed, smaller computing level and smaller chip area, and is widely used in the design of various algorithms and logic applications. Summary of the invention

[0004] The invention aims to provide a positive and negative three-value SR trigger circuit based on a binary memristor, which is suitable for positive three-value and negative three-value universal SR trigger circuits.

[0005] The positive and negative three-value SR trigger circuit of the present invention comprises a signal trigger circuit and a signal latch circuit.

[0006] The signal trigger circuit comprises three identical composite logic gates, each composite logic gate comprises four memristors and two MOS tubes; the negative electrode of the first memristor is connected to the negative electrode of the second memristor and then connected to the gate of the first MOS tube and the gate of the second MOS tube, the drain of the first MOS tube is connected to the negative electrode of the third memristor, the positive electrode of the third memristor is connected to the power supply, the source of the first MOS tube is connected to the drain of the second MOS tube and the positive electrode of the fourth memristor, and the source of the second MOS tube and the negative electrode of the fourth memristor are grounded. The positive electrodes of the three first memristors in the three composite logic gates are respectively used as the high-order, second-order and low-order signal input terminals of the signal trigger circuit, the corresponding drain electrodes of the first MOS tube are respectively used as the high-order, second-order and low-order signal output terminals of the signal trigger circuit, and the positive electrodes of the three second memristors are connected as the trigger signal input terminals.

[0007] The signal latch circuit comprises three identical basic logic gates and three identical compound logic gates, and a corresponding pair of basic logic gates and compound logic gates constitute a group of logic units.

[0008] In each logic unit, the basic logic gate includes two memristors, wherein the negative electrode of the fifth memristor and the negative electrode of the sixth memristor are respectively used as input terminals of the basic logic gate, and the positive electrode of the fifth memristor and the positive electrode of the sixth memristor are connected as output terminals of the basic logic gate;

[0009] The composite logic gate includes four memristors and two MOS tubes, the positive electrode of the seventh memristor is connected to the output end of the basic logic gate, the negative electrode of the seventh memristor and the negative electrode of the eighth memristor are connected and then connected to the gate of the third MOS tube and the gate of the fourth MOS tube, the drain of the third MOS tube is connected to the negative electrode of the ninth memristor, the positive electrode of the ninth memristor is connected to the power supply, the source of the third MOS tube is connected to the drain of the fourth MOS tube and the positive electrode of the tenth memristor, and the negative electrode of the tenth memristor and the source of the fourth MOS tube are grounded;

[0010] The positive pole of the eighth memristor of the first group of logic units is connected to the high-order signal output end of the signal trigger circuit, the positive pole of the eighth memristor of the second group of logic units is connected to the secondary-order signal output end of the signal trigger circuit, and the positive pole of the eighth memristor of the third group of logic units is connected to the low-order signal output end of the signal trigger circuit; the negative pole of the ninth memristor of the first group of logic units and the negative pole of the fifth memristor of the second and third groups of logic units are connected as the high-order output end of the SR trigger circuit; the negative pole of the fifth memristor of the first group of logic units, the negative pole of the ninth memristor of the second group of logic units, and the negative pole of the sixth memristor of the third group of logic units are connected as the secondary-order output end of the SR trigger circuit; the negative pole of the sixth memristor of the first and second groups of logic units and the negative pole of the ninth memristor of the third group of logic units are connected as the low-order output end of the SR trigger circuit.

[0011] If the SR trigger circuit is a positive three-value SR trigger, all MOS tubes are NMOS tubes, and the power supply is a positive voltage +Vdd; if the SR trigger circuit is a negative three-value SR trigger, all MOS tubes are PMOS tubes, and the power supply is a negative voltage -Vdd.

[0012] The three-value SR trigger circuit structure of the present invention is clear and simple, easy to implement, and can be used for both positive and negative signals. Only when the trigger signal becomes a valid level, the three-value SR trigger will set the output to a corresponding state according to the input signal. The application research of this circuit model in many fields such as multi-value digital sequential logic circuit operation is of great significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a circuit block diagram of a negative three-value SR trigger based on a binary memristor according to the present invention.

[0014] Figure 2 It is a schematic diagram of a negative three-value SR trigger circuit based on a binary memristor according to the present invention. DETAILED DESCRIPTION

[0015] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0016] Among them, the voltage -Vdd is defined as -3.3V, corresponding to logic -2, the voltage -Vdd / 2 is defined as -1.65V, corresponding to logic -1, and GND is defined as 0V, corresponding to logic 0.

[0017] The positive and negative three-value SR trigger circuit model based on the binary memristor of the present invention has a circuit block diagram as shown in FIG. Figure 1 As shown, it consists of six three-value compound logic gates and three three-value basic logic gates, and is implemented using the switching characteristics and memory characteristics of the memristor. Taking the negative three-value SR trigger circuit as an example, the logic state in the circuit is the voltage value, and the truth table corresponding to the negative three-value SR trigger is shown in the following table:

[0018]

[0019] According to the truth table of the negative three-valued SR trigger, it can be seen that when CP=-2, the negative three-valued SR trigger can accept the input signal and set the output of the circuit to the corresponding state according to the input signal. When CP=0, the negative three-valued SR trigger saves the instantaneous state before the trigger signal is 0.

[0020] When the trigger signal CP=0, or when the trigger signal CP=-2, the input signal (S2, S1, S0)=(0, 0, 0), the corresponding Figure 1The outputs of the three three-value NOR gates NOR1, NOR2 and NOR3 connected to the trigger signal are all -2, and the outputs of the other three three-value NOR gates NOR4, NOR5 and NOR6 depend on the outputs of the three three-value AND gates AND1, AND2 and AND3 connected to their inputs, and the inputs of the three AND gates in the circuit are all controlled by the output terminals. For example, if the output of the last circuit is Q2Q1Q0=00-2, the output of the three-value AND gate AND3 connected to Q2 and Q1 in the circuit is 0, and the outputs of the other two are both -2. After the input signal is connected to the three-value NOR gates NOR4, NOR5 and NOR6, the output of the circuit is Q2Q1Q0=00-2, and the output of the negative three-value SR trigger circuit remains unchanged.

[0021] When the trigger signal CP = -2, the input signal (S2, S1, S0) = (-2, 0, 0), it can be seen that the corresponding Figure 1 The outputs of the first three three-value NOR gates NOR1, NOR2 and NOR3 are (0, -2, -2), so the output of NOR4 Q2 = -2. Under the influence of Q2, the outputs of the two three-value AND gates AND2 and AND3 are both -2, and then connected to the three-value NOR gates NOR5 and NOR6 together with the input signals S1 and S0, and Q1Q0 = 00 is obtained.

[0022] When the trigger signal CP = -2, the input signal (S2, S1, S0) = (0, -2, 0), it can be seen that the corresponding Figure 1 The outputs of the first three three-value NOR gates NOR1, NOR2 and NOR3 are (-2, 0, -2), so the output of NOR5 Q1 = -2. Under the influence of Q1, the outputs of the two three-value AND gates AND1 and AND3 are both -2, and then connected to the three-value NOR gates NOR4 and NOR6 together with the input signals S2 and S0, Q2Q0 = 00 is obtained.

[0023] When the trigger signal CP = -2, the input signal (S2, S1, S0) = (0, 0, -2), it can be seen that the corresponding Figure 1 The outputs of the first three three-value NOR gates NOR1, NOR2 and NOR3 are (-2, -2, 0), so the output of NOR6 Q0 = -2. Under the influence of Q0, the outputs of the two three-value AND gates AND1 and AND2 are both -2, and then connected to the three-value NOR gates NOR4 and NOR5 together with the input signals S2 and S1, and Q2Q1 = 00 is obtained.

[0024] The above circuit conditions correspond to the first, sixth, fourth, third and second conditions in the truth table of the negative three-valued SR trigger respectively. The three-bit output signals of the negative three-valued SR trigger corresponding to the combinations of the remaining input signals cannot represent the three-value signals -2, -1 and 0.

[0025] According to the input and output relationship of the above truth table, construct Figure 1 The negative three-value SR trigger circuit block diagram is shown in the figure. The detailed circuit structure is as follows Figure 2 shown.

[0026] For the negative three-value SR trigger circuit, the high input terminal S2 is connected to the positive electrode of the first memristor M1. The negative electrode of the first memristor M1, the negative electrode of the second memristor M2, the gate of the first PMOS tube P1 and the gate of the second PMOS tube P2 are connected. The drain of the first PMOS tube P1 is connected to the negative electrode of the third memristor M3 and the positive electrode of the eighth memristor M8, and the source of the first PMOS tube P1 is connected to the positive electrode of the fourth memristor M4 and the drain of the second PMOS tube P2. The source of the second PMOS tube P2 is connected to the negative electrode of the fourth memristor M4 and then grounded. The positive electrode of the third memristor M3 is connected to the DC voltage source -V DD The positive electrodes of the fifth memristor M5, the sixth memristor M6 and the seventh memristor M7 are connected. The negative electrode of the fifth memristor M5 is connected to the output terminal Q1, and the negative electrode of the sixth memristor M6 is connected to the output terminal Q0. The negative electrode of the seventh memristor M7, the negative electrode of the eighth memristor M8, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4 are connected. The drain of the third PMOS tube P3 is connected to the negative electrode of the ninth memristor M9 and the output terminal Q2, and the source of the third PMOS tube P3 is connected to the tenth memristor M 10 The source of the fourth PMOS tube P4 is connected to the positive electrode of the tenth memristor M 10 The positive electrode of the ninth memristor M9 is connected to the DC voltage source -V DD connected.

[0027] The secondary input terminal S1 and the eleventh memristor M 11 The eleventh memristor M 11 The negative electrode of the twelfth memristor M 12 The drain of the fifth PMOS tube P5 is connected to the negative electrode of the thirteenth memristor M 13 The negative electrode of the eighteenth memristor M 18 The source of the fifth PMOS tube P5 is connected to the positive electrode of the fourteenth memristor M 14 The source of the fifth PMOS tube P5 and the fourteenth memristor M 14 The negative electrode of is connected to the ground. The thirteenth memristor M 13 The positive terminal of the DC voltage source is -V DD The fifteenth memristor M 15 、16th memristor M 16and the seventeenth memristor M 17 The fifteenth memristor M 15 The negative electrode of the sixteenth memristor M is connected to the output terminal Q2. 16 The negative electrode of is connected to the output terminal Q0. 17 The negative electrode of the eighteenth memristor M 18 The drain of the seventh PMOS tube P7 is connected to the negative electrode of the nineteenth memristor M 19 The source of the seventh PMOS tube P7 is connected to the negative electrode of the twentieth memristor M 20 The source of the eighth PMOS tube P8 is connected to the positive electrode of the twentieth memristor M 20 The negative electrode of is connected to the ground. 19 The positive terminal of the DC voltage source is -V DD connected.

[0028] The low input terminal S0 and the twenty-first memristor M 21 The twenty-first memristor M 21 The negative electrode of the twenty-second memristor M 22 The negative electrode, the gate of the ninth PMOS tube P9 and the tenth PMOS tube P 10 The drain of the ninth PMOS tube P9 is connected to the gate of the twenty-third memristor M 23 The negative electrode of the twenty-eighth memristor M 28 The source of the ninth PMOS tube P9 is connected to the positive electrode of the twenty-fourth memristor M 24 The positive electrode of the tenth PMOS tube P 10 The source of the ninth PMOS tube P9 is connected to the drain of the twenty-fourth memristor M 24 The negative electrode is connected to the ground. 23 The positive terminal of the DC voltage source is -V DD The twenty-fifth memristor M 25 、Twenty-sixth memristor M 26 and the twenty-seventh memristor M 27 The twenty-fifth memristor M 25 The negative electrode of the twenty-sixth memristor M is connected to the output terminal Q2. 26 The negative electrode of is connected to the output terminal Q1. 27 The negative electrode of the twenty-eighth memristor M 28 The negative electrode of the eleventh PMOS tube P 11 The gate and the twelfth PMOS tube P 12 The gate of the eleventh PMOS tube P11 The drain of the twenty-ninth memristor M 29 The cathode of the eleventh PMOS tube P is connected to the output terminal Q0. 11 The source of the 30th memristor M 30 The positive electrode of the twelfth PMOS tube P 12 The twelfth PMOS tube P 12 The source of the 30th memristor M 30 The negative electrode is connected to the ground. 29 The positive terminal of the DC voltage source is -V DD connected.

[0029] The trigger signal input terminal CP is connected to the positive electrode of the second memristor M2 and the twelfth memristor M 12 The positive electrode of the 22nd memristor M 22 The positive electrode is connected.

[0030] If the SR trigger circuit is a positive three-valued SR trigger, all PMOS tubes are changed to NMOS tubes, and the power supply is a positive voltage +Vdd.

Claims

1. A positive and negative three-value SR trigger circuit based on a binary memristor, comprising a signal trigger circuit and a signal latch circuit, characterized in that: The signal trigger circuit comprises three identical composite logic gates, each composite logic gate comprises four memristors and two MOS tubes; the negative electrode of the first memristor is connected to the gate of the first MOS tube and the gate of the second MOS tube, the drain of the first MOS tube is connected to the negative electrode of the third memristor, the positive electrode of the third memristor is connected to the power supply, the source of the first MOS tube is connected to the drain of the second MOS tube and the positive electrode of the fourth memristor, and the source of the second MOS tube and the negative electrode of the fourth memristor are grounded; the positive electrodes of the three first memristors in the three composite logic gates are respectively used as the high, second and low signal input terminals of the signal trigger circuit, the corresponding drain electrodes of the first MOS tubes are respectively used as the high, second and low signal output terminals of the signal trigger circuit, and the positive electrodes of the three second memristors are connected as the trigger signal input terminals; The signal latch circuit comprises three identical basic logic gates and three identical compound logic gates, and a corresponding pair of basic logic gates and compound logic gates constitute a group of logic units; In each logic unit, the basic logic gate includes two memristors, wherein the negative electrode of the fifth memristor and the negative electrode of the sixth memristor are respectively used as input terminals of the basic logic gate, and the positive electrode of the fifth memristor and the positive electrode of the sixth memristor are connected as output terminals of the basic logic gate; The composite logic gate includes four memristors and two MOS tubes, the positive electrode of the seventh memristor is connected to the output end of the basic logic gate, the negative electrode of the seventh memristor and the negative electrode of the eighth memristor are connected and then connected to the gate of the third MOS tube and the gate of the fourth MOS tube, the drain of the third MOS tube is connected to the negative electrode of the ninth memristor, the positive electrode of the ninth memristor is connected to the power supply, the source of the third MOS tube is connected to the drain of the fourth MOS tube and the positive electrode of the tenth memristor, and the negative electrode of the tenth memristor and the source of the fourth MOS tube are grounded; The positive pole of the eighth memristor of the first group of logic units is connected to the high-order signal output end of the signal trigger circuit, the positive pole of the eighth memristor of the second group of logic units is connected to the secondary-order signal output end of the signal trigger circuit, and the positive pole of the eighth memristor of the third group of logic units is connected to the low-order signal output end of the signal trigger circuit; the negative pole of the ninth memristor of the first group of logic units and the negative pole of the fifth memristor of the second and third groups of logic units are connected as the high-order output end of the SR trigger circuit; the negative pole of the fifth memristor of the first group of logic units, the negative pole of the ninth memristor of the second group of logic units, and the negative pole of the sixth memristor of the third group of logic units are connected as the secondary-order output end of the SR trigger circuit; the negative pole of the sixth memristor of the first and second groups of logic units and the negative pole of the ninth memristor of the third group of logic units are connected as the low-order output end of the SR trigger circuit.

2. The positive and negative three-value SR trigger circuit based on a binary memristor as claimed in claim 1, characterized in that: If the SR trigger circuit is a positive three-valued SR trigger, all MOS tubes are NMOS tubes, and the power supply is a positive voltage +Vdd.

3. The positive and negative three-value SR trigger circuit based on a binary memristor as claimed in claim 1, characterized in that: If the SR trigger circuit is a negative three-valued SR trigger, all MOS tubes are PMOS tubes, and the power supply is a negative voltage -Vdd.

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