Positive and negative three-value D flip-flop circuit based on binary memristor

Abstract

The invention discloses a positive and negative three-value D flip-flop circuit based on a binary memristor. The invention comprises a signal trigger circuit and a signal latch circuit. The signal trigger circuit comprises thirteen memristors and six MOS tubes, and has a trigger signal input terminal and high-order, secondary-order and low-order signal output terminals. The signal latch circuit comprises three identical basic logic gates and a composite logic gate, and a corresponding pair of basic logic gates and composite logic gates constitute a group of logic units. Each basic logic gate comprises two memristors, the negative pole is used as the unit input terminal, and the positive pole is connected as the basic logic gate output terminal. The composite logic gate comprises four memristors and two MOS tubes, the positive pole of a memristor is connected to the basic logic gate output terminal, the negative pole is connected to the negative pole of another memristor and then connected to the gates of two MOS tubes, the drain of one MOS tube is connected to a power supply through a memristor, and the source is connected to the drain of another MOS tube. The circuit structure of the invention is clear and simple, easy to implement, and can be used for both positive and negative terminals.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, relates to a three-value digital logic circuit structure, and specifically relates to a positive and negative three-value D flip-flop circuit based on a binary memristor. Background Art

[0002] In 1971, Professor Shao-Tang Tsai of the University of California, Berkeley, predicted from the perspective of circuit theory completeness that in addition to resistance, capacitance, and inductance, there is a fourth missing passive basic circuit element that characterizes the relationship between charge and magnetic flux, and named it memristor. For more than 30 years after the concept of memristor was proposed, there was almost no progress in the research on memristor due to the inability to obtain physical memristor devices. It was not until 2008 that HP Labs combined the theoretical concept of memristor with TiO 2 The HP model of memristor is proposed by linking the bipolar transition phenomenon of resistance in the device. As a nonlinear nano-element, HP memristor has unique nano-size, memory characteristics, non-volatile characteristics, hard switching characteristics, etc., and can be applied to medicine, biological sciences, neural networks, chaotic systems, microelectronics and other related fields.

[0003] At present, most of the research is to apply memristors to binary digital logic circuit systems. Compared with binary signals, multi-value signals carry more information, which can improve the information density of transmission signal lines and integrated circuits and the time and space utilization of information processing. In three-valued logic circuits, there is an intermediate level between low level and high level, which plays a great role in reducing power consumption and circuit integration. Therefore, the three-valued logic system has gradually become a substitute for the binary logic system. In terms of realizing high-density logic systems, it has higher operating speed, smaller computing level and smaller chip area, and is widely used in the design of various algorithms and logic applications. Summary of the invention

[0004] The invention aims to provide a positive and negative three-value D flip-flop circuit based on a binary memristor, which is suitable for positive three-value and negative three-value universal D flip-flop circuits.

[0005] The positive and negative three-value D trigger circuit of the present invention comprises a signal trigger circuit and a signal latch circuit.

[0006] The signal trigger circuit includes thirteen memristors and six MOS tubes. The gates of the first, second and third MOS tubes are connected as the signal input end of the D trigger circuit. The drain of the first MOS tube is connected to the negative electrode of the first memristor and the gate of the fourth MOS tube, the source of the first MOS tube is connected to the positive electrode of the second memristor and the drain of the second MOS tube, the positive electrode of the first memristor is connected to the power supply, and the source of the second MOS tube and the negative electrode of the second memristor are grounded. The drain of the fourth MOS tube is connected to the negative electrode of the third memristor and the positive electrode of the fourth memristor, the positive electrode of the third memristor is connected to the power supply, and the source of the fourth MOS tube is grounded. The drain of the third MOS tube is connected to the negative electrode of the fifth memristor and the positive electrode of the sixth memristor, the positive electrode of the fifth memristor is connected to the power supply, and the source of the third MOS tube is grounded. The negative electrodes of the fourth and seventh memristors are connected to the gate of the fifth MOS tube, the drain of the fifth MOS tube is connected to the negative electrode of the eighth memristor and the positive electrode of the ninth memristor, as the high-order signal output end of the trigger circuit, the positive electrode of the eighth memristor is connected to the power supply, and the source of the fifth MOS tube is grounded. The negative electrodes of the sixth and tenth memristors are connected to the gate of the sixth MOS tube, the drain of the sixth MOS tube is connected to the negative electrode of the eleventh memristor and the positive electrode of the twelfth memristor, as the low-order signal output terminal of the trigger circuit, the positive electrode of the eleventh memristor is connected to the power supply, and the source of the sixth MOS tube is grounded. The positive electrodes of the seventh, tenth, and thirteenth memristors are connected as the trigger signal input terminal; the negative electrodes of the ninth, twelfth, and thirteenth memristors are connected as the secondary signal output terminal of the trigger circuit.

[0007] The signal latch circuit comprises three identical basic logic gates and three identical compound logic gates, and a corresponding pair of basic logic gates and compound logic gates constitute a group of logic units.

[0008] In each logic unit, the basic logic gate includes two memristors, wherein the negative electrode of the fourteenth memristor and the negative electrode of the fifteenth memristor are respectively used as input terminals of the basic logic gate, and the positive electrodes of the fourteenth and fifteenth memristors are connected as output terminals of the basic logic gate.

[0009] The composite logic gate includes four memristors and two MOS tubes, the positive electrode of the sixteenth memristor is connected to the output end of the basic logic gate, the negative electrodes of the sixteenth and seventeenth memristors are connected and then connected to the gate of the seventh MOS tube and the gate of the eighth MOS tube, the drain of the seventh MOS tube is connected to the negative electrode of the eighteenth memristor, the positive electrode of the eighteenth memristor is connected to the power supply, the source of the seventh MOS tube is connected to the drain of the eighth MOS tube and the positive electrode of the nineteenth memristor, and the negative electrode of the nineteenth memristor and the source of the eighth MOS tube are grounded.

[0010] The positive electrode of the seventeenth memristor of the first group of logic units is connected to the high-order signal output end of the signal trigger circuit, the positive electrode of the seventeenth memristor of the second group of logic units is connected to the secondary-order signal output end of the signal trigger circuit, and the positive electrode of the seventeenth memristor of the third group of logic units is connected to the low-order signal output end of the signal trigger circuit. The negative electrode of the eighteenth memristor of the first group of logic units and the negative electrode of the fourteenth memristor of the second and third groups of logic units are connected as the high-order output end of the D trigger circuit. The negative electrode of the fourteenth memristor of the first group of logic units, the negative electrode of the eighteenth memristor of the second group of logic units, and the negative electrode of the fifteenth memristor of the third group of logic units are connected as the secondary-order output end of the D trigger circuit. The negative electrode of the fifteenth memristor of the first and second groups of logic units and the negative electrode of the eighteenth memristor of the third group of logic units are connected as the low-order output end of the D trigger circuit.

[0011] If the D flip-flop circuit is a positive three-valued D flip-flop, all MOS tubes are NMOS tubes, and the power supply is a positive voltage +Vdd; if the D flip-flop circuit is a negative three-valued D flip-flop, all MOS tubes are PMOS tubes, and the power supply is a negative voltage -Vdd.

[0012] The three-value SR flip-flop circuit structure of the present invention is clear and simple, easy to implement, and can be used for both positive and negative signals. Only when the trigger signal becomes a valid level, the three-value D flip-flop will set the output to a corresponding state according to the input signal. The application research of this circuit model in many fields such as multi-value digital sequential logic circuit operation is of great significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a block diagram of a negative three-value D flip-flop circuit based on a binary memristor.

[0014] Figure 2 It is a schematic diagram of a negative three-value D flip-flop circuit based on a binary memristor according to the present invention. DETAILED DESCRIPTION

[0015] The present invention is described in detail below by taking a negative three-value D flip-flop circuit based on a binary memristor as an example.

[0016] Among them, the voltage -Vdd is defined as -3.3V, corresponding to logic -2, the voltage -Vdd / 2 is defined as -1.65V, corresponding to logic -1, and GND is defined as 0V, corresponding to logic 0.

[0017] The circuit block diagram of the negative three-value D flip-flop based on binary memristor of the present invention is as follows: Figure 1 As shown, it is composed of a three-value decoder, a three-value three-input maximum value, three positive polarity three-value inverters PTI, two three-value OR gates, three three-value AND gates and three three-value NOR gates, and is implemented by using the switching characteristics and memory characteristics of the memristor.

[0018] The truth table corresponding to the negative three-valued D flip-flop is shown in the following table:

[0019]

[0020] According to the truth table of the negative three-valued D flip-flop, it can be seen that when CP=-2, the negative three-valued D flip-flop can accept the input signal and set the output of the circuit to the corresponding state according to the input signal. When CP=0, the negative three-valued D flip-flop saves the instantaneous state before the trigger signal is 0.

[0021] When the trigger signal CP=0, the corresponding Figure 1 The outputs of the three three-value NOT gates PTI1, PTI2 and PTI3 are all -2, then the outputs of the three three-value NOR gates NOR1, NOR2 and NOR3 depend on the outputs of the three three-value AND gates AND1, AND2 and AND3 connected to their inputs, and the inputs of the three AND gates in the circuit are all controlled by the output terminals. For example, if the output Q of the previous circuit is 2 Q 1 Q 0 =00-2, then the circuit is connected with Q 2 and Q 1 The output of the connected three-value AND gate AND3 is 0, and the outputs of the other two are -2. Then, the output Q of the circuit is obtained by connecting the input signal to the three-value NOR gates NOR4, NOR5 and NOR6 respectively. 2 Q 1 Q 0 =00-2, the output of the negative three-valued D flip-flop circuit remains unchanged.

[0022] When the trigger signal CP = -2 and the input signal D = 0, the output D of the three-value decoder 2 D 1 D 0 =00-2, corresponding to Figure 1 The outputs of the three three-value NOT gates PTI1, PTI2 and PTI3 are -2, -2 and 0 respectively. Then the output Q of NOR3 is 0 = -2. 0 Under the influence of, the outputs of the two three-value AND gates AND1 and AND2 are both -2, and then connected to the three-value NOR gates NOR1 and NOR2 together with the outputs of PTI1 and PTI2, and Q is obtained. 2 Q 1 =00.

[0023] When the trigger signal CP = -2 and the input signal D = -1, the output D of the three-value decoder 2 D 1 D 0 =0-20, corresponding to Figure 1The outputs of the three three-value NOT gates PTI1, PTI2 and PTI3 are -2, 0 and -2 respectively. Then the output Q of NOR2 is 1 = -2. 1 Under the influence of, the outputs of the two three-value AND gates AND1 and AND3 are both -2, and then connected to the three-value NOR gates NOR1 and NOR3 together with the outputs of PTI1 and PTI3, and Q is obtained. 2 Q 0 =00.

[0024] When the trigger signal CP = -2 and the input signal D = -2, the output D of the three-value decoder 2 D 1 D 0 =-200, corresponding to Figure 1 The outputs of the three three-value NOT gates PTI1, PTI2 and PTI3 are 0, -2 and -2 respectively. Then the output Q of NOR1 is 2 = -2. 2 Under the influence of, the outputs of the two three-value AND gates AND2 and AND3 are both -2, and then connected to the three-value NOR gates NOR2 and NOR3 together with the outputs of PTI2 and PTI3, and Q is obtained. 1 Q 0 =00.

[0025] According to the input and output relationship of the above truth table, we can construct Figure 1 The negative three-value D flip-flop circuit block diagram is shown in the figure. The detailed circuit structure is as follows Figure 2 shown.

[0026] For the negative three-value D flip-flop circuit, the input terminal D is connected to the first PMOS tube P 1 The gate of the second PMOS tube P 2 The gate of the third PMOS tube P 3 The gate of the first PMOS tube P 1 The drain of the first memristor M 1 The negative electrode of the fourth PMOS tube P 4 The gate of the first PMOS tube P 1 The source of the second memristor M 2 The positive electrode of the second PMOS tube P 2 The second PMOS tube P 2 The source of the second memristor M 2 The fourth PMOS tube P 4 The drain of the third memristor M 3 The negative electrode of the fourth memristor M 4 The positive electrode of the fourth PMOS tube P 4 The source of the first memristor M is grounded.1 The positive electrode of the third memristor M 3 The positive electrode of the fifth memristor M 5 The positive electrode of the third PMOS tube P is connected to the DC voltage source -Vdd. 3 The drain of the fifth memristor M 5 The negative electrode of the sixth memristor M 6 The positive electrode of the third PMOS tube P 3 The source of the fourth memristor M is grounded. 4 、The seventh memristor M 7 The negative electrode and the fifth PMOS tube P 5 The seventh memristor M 7 The positive electrode of the thirteenth memristor M 13 The positive electrode of the tenth memristor M 10 The positive electrode of the fifth PMOS tube P is connected to the trigger signal CP. 5 The drain of the eighth memristor M 12 The negative electrode of the ninth memristor M 9 The positive electrode of the seventeenth memristor M 17 The ninth memristor M 9 The negative electrode of the thirteenth memristor M 13 The negative electrode of the twelfth memristor M 12 The negative electrode of the twenty-third memristor M 23 The twelfth memristor M 12 The positive electrode of the sixth PMOS tube P 6 The drain of the eleventh memristor M 11 The negative electrode of the twenty-ninth memristor M 29 The fifth PMOS tube P 5 The source of the sixth PMOS tube P 6 The source of the eighth memristor M is grounded. 8 The positive electrode of the eleventh memristor M 11 The positive electrode of the tenth memristor M is connected to the DC voltage source -Vdd. 10 The negative electrode of the sixth memristor M 6 The negative electrode of the sixth PMOS tube P 6 The gate of the fourteenth memristor M 14 、15th memristor M 15 and the twentieth memristor M 20 The fourteenth memristor M 14 The negative pole and output terminal Q 1 The fifteenth memristor M 15 The negative pole and output terminal Q 0 The sixteenth memristor M 16 The negative electrode of the seventeenth memristor M17 The negative electrode of the eighth PMOS tube P 8 The gate and the seventh PMOS tube P 7 The seventh PMOS tube P 7 The drain of the eighteenth memristor M 18 The negative pole and the output terminal Q 2 connected, the seventh PMOS tube P 7 The source of the nineteenth memristor M 19 The positive electrode of the eighth PMOS tube P 8 The drain of the eighth PMOS tube P 8 The source of the nineteenth memristor M 19 The negative electrode of the eighteenth memristor M is connected to the ground. 18 The positive electrode is connected to the DC voltage source -Vdd. 20 、The twenty-first memristor M 21 and the twenty-second memristor M 22 The twentieth memristor M 20 The negative pole and output terminal Q 2 The twenty-first memristor M 21 The negative pole and output terminal Q 0 The twenty-second memristor M 22 The negative electrode of the twenty-third memristor M 23 The negative electrode of the ninth PMOS tube P 9 The gate and the tenth PMOS tube P 10 The ninth PMOS tube P 9 The drain of the twenty-fourth memristor M 24 The negative pole and the output terminal Q 1 connected, the ninth PMOS tube P 9 The source of the twenty-fifth memristor M 25 The positive electrode of the tenth PMOS tube P 10 The tenth PMOS tube P 10 The source of the twenty-fifth memristor M 25 The negative electrode is connected to the ground. 24 The positive electrode is connected to the DC voltage source -Vdd. 18 、Nineteenth memristor M 19 and the twenty-fourth memristor M 24 The twenty-sixth memristor M 26 The negative pole and output terminal Q 2 The twenty-seventh memristor M 27 The negative pole and output terminal Q 1 The twenty-sixth memristor M 26The negative electrode of the twenty-seventh memristor M 27 The negative electrode of the eleventh PMOS tube P 11 The gate and the twelfth PMOS tube P 12 The gate of the eleventh PMOS tube P 11 The drain of the 30th memristor M 30 The negative pole and the output terminal Q 0 connected, the eleventh PMOS tube P 11 The source of the thirty-first memristor M 31 The positive electrode of the twelfth PMOS tube P 12 The twelfth PMOS tube P 12 The source of the thirty-first memristor M 31 The negative electrode of is connected to the ground. 30 The positive pole is connected to the DC voltage source -Vdd.

[0027] If the D flip-flop circuit is a positive three-valued D flip-flop, all PMOS tubes are changed to NMOS tubes, and the power supply is a positive voltage +Vdd.

Claims

1. A positive and negative three-value D flip-flop circuit based on a binary memristor, comprising a signal trigger circuit and a signal latch circuit, characterized in that: The signal trigger circuit comprises thirteen memristors and six MOS tubes; the gates of the first, second and third MOS tubes are connected as the signal input end of the D trigger circuit; the drain of the first MOS tube is connected to the negative electrode of the first memristor and the gate of the fourth MOS tube, the source of the first MOS tube is connected to the positive electrode of the second memristor and the drain of the second MOS tube, the positive electrode of the first memristor is connected to the power supply, the source of the second MOS tube and the negative electrode of the second memristor are grounded; the drain of the fourth MOS tube is connected to the negative electrode of the third memristor and the positive electrode of the fourth memristor, the positive electrode of the third memristor is connected to the power supply, and the source of the fourth MOS tube is grounded; the drain of the third MOS tube is connected to the negative electrode of the fifth memristor and the positive electrode of the sixth memristor, the positive electrode of the fifth memristor is connected to the power supply, and the positive electrode of the third MOS tube is grounded. The source is grounded; the negative electrodes of the fourth and seventh memristors are connected to the gate of the fifth MOS tube, the drain of the fifth MOS tube is connected to the negative electrode of the eighth memristor and the positive electrode of the ninth memristor, as the high-order signal output end of the trigger circuit, the positive electrode of the eighth memristor is connected to the power supply, and the source of the fifth MOS tube is grounded; the negative electrodes of the sixth and tenth memristors are connected to the gate of the sixth MOS tube, the drain of the sixth MOS tube is connected to the negative electrode of the eleventh memristor and the positive electrode of the twelfth memristor, as the low-order signal output end of the trigger circuit, the positive electrode of the eleventh memristor is connected to the power supply, and the source of the sixth MOS tube is grounded; the positive electrodes of the seventh, tenth and thirteenth memristors are connected as the trigger signal input end; the negative electrodes of the ninth, twelfth and thirteenth memristors are connected as the secondary signal output end of the trigger circuit; The signal latch circuit comprises three identical basic logic gates and three identical compound logic gates, and a corresponding pair of basic logic gates and compound logic gates constitute a group of logic units; In each logic unit, the basic logic gate includes two memristors, wherein the negative electrode of the fourteenth memristor and the negative electrode of the fifteenth memristor are respectively used as the input end of the basic logic gate, and the positive electrodes of the fourteenth and fifteenth memristors are connected as the output end of the basic logic gate; the composite logic gate includes four memristors and two MOS tubes, the positive electrode of the sixteenth memristor is connected to the output end of the basic logic gate, the negative electrodes of the sixteenth and seventeenth memristors are connected and then connected to the gate of the seventh MOS tube and the gate of the eighth MOS tube, the drain of the seventh MOS tube is connected to the negative electrode of the eighteenth memristor, the positive electrode of the eighteenth memristor is connected to the power supply, the source of the seventh MOS tube is connected to the drain of the eighth MOS tube and the positive electrode of the nineteenth memristor, and the negative electrode of the nineteenth memristor and the source of the eighth MOS tube are grounded; The positive pole of the seventeenth memristor of the first group of logic units is connected to the high signal output end of the signal trigger circuit, the positive pole of the seventeenth memristor of the second group of logic units is connected to the secondary signal output end of the signal trigger circuit, and the positive pole of the seventeenth memristor of the third group of logic units is connected to the low signal output end of the signal trigger circuit; the negative pole of the eighteenth memristor of the first group of logic units and the negative pole of the fourteenth memristor of the second and third groups of logic units are connected as the high output end of the D trigger circuit; the negative pole of the fourteenth memristor of the first group of logic units, the negative pole of the eighteenth memristor of the second group of logic units, and the negative pole of the fifteenth memristor of the third group of logic units are connected as the secondary output end of the D trigger circuit; the negative pole of the fifteenth memristor of the first and second groups of logic units and the negative pole of the eighteenth memristor of the third group of logic units are connected as the low output end of the D trigger circuit.

2. The positive and negative three-value D flip-flop circuit based on a binary memristor as claimed in claim 1, characterized in that: If the D flip-flop circuit is a positive three-valued SR flip-flop, all MOS tubes are NMOS tubes, and the power supply is a positive voltage +Vdd.

3. The positive and negative three-value D flip-flop circuit based on a binary memristor as claimed in claim 1, characterized in that: If the D flip-flop circuit is a negative three-value SR flip-flop, all MOS tubes are PMOS tubes, and the power supply is a negative voltage -Vdd.

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