Fractional divider, numerically controlled oscillator and phase locked loop circuit

Abstract

A fractional divider, a digitally controlled oscillator, a phase-locked loop circuit are provided. The fractional divider includes a multi-modulus divider configured to generate a first divided clock based on an input clock and a sequence of division coefficients; a first flip-flop configured to generate a second divided clock based on the first divided clock; a second flip-flop configured to generate a third divided clock based on the first divided clock; a first multiplexer configured to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer configured to select one of the second divided clock and the third divided clock as a second output divided clock.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and in particular to a fractional frequency divider, a numerically controlled oscillator, and a phase-locked loop circuit. Background Technology

[0002] In modern electronic system design, frequency divider circuits are a crucial component. Frequency divider circuits divide higher-frequency signals to obtain the desired lower-frequency signals, and depending on the division factor, they can be categorized as integer dividers or fractional dividers. Frequency divider circuits have a wide range of applications, including numerically controlled oscillator circuits and phase-locked loop circuits. Summary of the Invention

[0003] According to one aspect of this disclosure, a fractional frequency divider is provided, comprising: a multi-mode frequency divider for generating a first divided clock based on an input clock and a division coefficient sequence; a first flip-flop for generating a second divided clock based on the first divided clock; a second flip-flop for generating a third divided clock based on the first divided clock; a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock.

[0004] According to another aspect of this disclosure, a numerically controlled oscillator is provided, comprising: a fractional frequency divider, the fractional frequency divider comprising: a multi-mode frequency divider, the multi-mode frequency divider being configured to generate a first frequency-divided clock based on an input clock and a frequency division coefficient sequence; a first flip-flop, the first flip-flop being configured to generate a second frequency-divided clock based on the first frequency-divided clock; a second flip-flop, the second flip-flop being configured to generate a third frequency-divided clock based on the first frequency-divided clock; a first multiplexer, the first multiplexer being configured to select one of the first frequency-divided clock and the second frequency-divided clock as a first output frequency-divided clock; and a second multiplexer, the second multiplexer being configured to select one of the second frequency-divided clock and the third frequency-divided clock as a second output frequency-divided clock; a digital time converter, the digital time converter being configured to generate an output clock based on the first output frequency-divided clock and the second output frequency-divided clock, and being configured to perform phase error correction on the output clock according to a phase error signal; a modulator, the modulator being configured to generate the frequency division coefficient sequence and the frequency error signal; and an accumulator, the accumulator being configured to accumulate the frequency error signal to obtain the phase error signal.

[0005] According to another aspect of this disclosure, a phase-locked loop circuit is provided, comprising: a phase comparator for outputting an error signal based on a reference clock and a feedback clock, the error signal indicating a phase difference between the reference clock and the feedback clock; a loop filter for loop filtering the error signal; a voltage-controlled oscillator for generating a voltage-controlled oscillation signal based on the loop-filtered error signal; and a numerically controlled oscillator according to an embodiment of this disclosure, the numerically controlled oscillator for receiving the voltage-controlled oscillation signal as the input clock and for generating the output clock as the feedback clock.

[0006] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0007] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1A A schematic circuit diagram of a numerically controlled oscillator in the related art is shown.

[0009] Figures 1B to 1D A schematic diagram of a digital time converter in the related art is shown.

[0010] Figure 2A An example fractional frequency divider according to an embodiment of the present disclosure is shown.

[0011] Figure 2B An example timing diagram of a frequency divider clock in a fractional frequency divider according to an embodiment of the present disclosure is shown.

[0012] Figure 3 An example numerically controlled oscillator according to an embodiment of the present disclosure is shown.

[0013] Figure 4 An example phase-locked loop circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0014] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0015] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items, and the phrase “at least one of A and B” includes only A, only B, and both A and B.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0017] Figure 1A A schematic circuit diagram of a digitally controlled oscillator 100 in the related art is shown. A digitally controlled oscillator (DCO), also known as a digitally controlled oscillator, is capable of generating controllable oscillation waveforms, such as sine or cosine waves. Figure 1AAs shown, the numerically controlled oscillator 100 may include a fractional frequency divider 101, a digital time converter 102, a modulator 103, and an accumulator 104. The numerically controlled oscillator can be used to generate an output clock 106 based on an input clock 105. The modulator 103 may be a Sigma-Delta modulator. The inputs to the numerically controlled oscillator 100 may include an input clock (ckin) 105 and a frequency division coefficient (Div_ratio) 107. In the case where the numerically controlled oscillator is a fractional frequency divider, the frequency division coefficient Div_ratio may be an integer plus a decimal, such as 1.3, 4.4, 5.7, etc., and this disclosure is not limited thereto. The modulator 103 may convert the frequency division coefficient 107 into an integer frequency division coefficient sequence 107' whose average value is equal to the frequency division coefficient 107. For example, in the example where the division factor is 4.25, the sequence of integer division factors could be [4,4,4,5,4…], such that the sequence of integer division factors is equal to or approximately equal to 4.25 during a predetermined period or desired time. In such an example, the average frequency of the output of the fractional divider 101, or the divided clock (ckdiv) 110, could be Fckin / Div_ratio, where Fckin is the frequency of the input clock ckin 105, and Div_ratio is the desired division factor that can contain a decimal. The accumulator 104 can accumulate the frequency error 108 in the fractional divider 101 into a phase error 108' and input it to the digital time converter 102. Thus, the digital time converter 102 can correct the phase error in the period based on the phase error 108' to reduce the jitter of the final output clock 106.

[0018] Figures 1B to 1D Examples of digital time converters, or digital time dividers 112, 122, and 132, in the related art are given, wherein digital time converters 112, 122, and 132 can be used as... Figure 1A The digital time converter 102 in the numerically controlled oscillator 100.

[0019] like Figure 1B As shown, the digital time converter 112 includes a capacitor array 113 and a Schmitt trigger 114 to convert the input divided clock ckdiv into an output clock ckout. It is understood that, when applied to... Figure 1AIn the numerically controlled oscillator shown, the input divided clock ckdiv can correspond to divided clock 110. In other cases, the input clock can correspond to input clock 105, etc. The phase can be adjusted by adjusting the capacitor array 113 to adjust the rise time of the inverter. The digital time converter 112 can include a Schmitt trigger 114 to ensure that metastability does not occur during switching. The Schmitt trigger compares the input voltage Vs with the threshold voltage Vt and switches whenever the input voltage reaches the threshold voltage. Since the phase adjustment is generated by the delay of the RC constant, this structure naturally introduces an undesirable integral nonlinearity (INL).

[0020] like Figure 1C As shown, the digital-to-time converter 122 may include a capacitor array 123, a digital-to-analog converter (DAC) 125, and a Schmitt trigger 124. The DAC 125 can be used to obtain the voltage V before the arrival of the input clock ckdiv of the digital-to-time converter 122. DAC Then, the capacitor is charged through a current mirror to reach the threshold voltage, which causes the Schmitt trigger 124 to flip.

[0021] In this case, the time delay td can be expressed as the following formula:

[0022]

[0023] Where C is the capacitance and I is the current value. The resulting time delay td has relatively good linearity, but in this case, the resolution of the digital time converter 122 needs to be guaranteed by the numerical-to-analog converter (DAC) 125, so it is more difficult to achieve a larger dynamic range.

[0024] refer to Figure 1D The digital time converter 132 may include a capacitor array 133 and a Schmitt trigger 134. The digital time converter 132 may have two clocks, clock A (ckdiv_A) and clock B (ckdiv_B), as inputs. The rising edges of clock A and clock B define the full-scale amplitude of the digital time converter. Typically, clock A and clock B can be separated by one input clock cycle (T). ckin That is, clock A and clock B can be spaced 1*T apart. ckin .

[0025] return Figure 1A In the related art, the full-scale amplitude of the digital time converter 102 is one input clock cycle 1*T of the numerically controlled oscillator 100. ckinThe jitter of the output clock of the numerically controlled oscillator 100 is determined by the minimum resolution (LSB) of the digital time converter 102. That is, jitter can be expressed as...

[0026]

[0027] Here, N represents the number of bits in the digital time converter 102. Therefore, to achieve lower jitter, a larger number of bits N is needed. However, increasing the number of bits N in the digital time converter 102 by one bit often means doubling the area of ​​the capacitor array or current mirror array and doubling the wiring complexity, thus significantly increasing the design complexity. Furthermore, if 1*T... ckin Reduced to 1 / 2*T ckin This will more effectively reduce shaking.

[0028] Exemplary embodiments of this disclosure will now be described in detail, which can be used for many reasons, such as alleviating or reducing these undesirable side effects.

[0029] Reference Figure 2A A fractional frequency divider 201 according to an embodiment of the present disclosure is described. The fractional frequency divider 201 includes a multi-mode frequency divider 211, a first flip-flop 212, a second flip-flop 213, a first multiplexer 214, and a second multiplexer 215.

[0030] The multi-mode frequency divider 211 is used to generate a first divided clock ckdiv1 based on the input clock ckin and the division coefficient sequence 207'. The division coefficient sequence 207' can be similar to the previously mentioned integer division coefficient sequence 107', for example, an integer signal sequence used to characterize the desired fractional division coefficient by means of an average value. The multi-mode frequency divider 211 can be implemented using counter chips, programmable logic device designs, etc., including but not limited to implementations that can be conceived by those skilled in the art, and this disclosure is not limited thereto.

[0031] The first flip-flop 212 is used to generate the second divided clock ckdiv2 based on the first divided clock ckdiv1. The flip-flop receives the input signal and the clock pulse, and is sensitive to the pulse edge. Its state changes only at the rising or falling edge of the clock pulse. The flip-flop can be a D flip-flop, where the clock signal is valid after the data signal is valid. This means that the data signal is established first, and the clock signal is established later, and the corresponding flip-flop is engaged at the valid edge of the CP pulse.

[0032] The second flip-flop 213 is used to generate a third divided clock ckdiv3 based on the first divided clock ckdiv1. Similarly, the second flip-flop 213 may also be a D flip-flop, or other types of flip-flops that can be selected by those skilled in the art, and this disclosure is not limited thereto.

[0033] The first multiplexer 214 is used to select one of the first divided clock ckdiv1 and the second divided clock ckdiv2 as the first output divided clock ckdiv-A. A multiplexer (or mux), also known as a data selector, can select a signal from multiple analog or digital input signals and forward it, thus outputting different selected signals to the same output line. The first multiplexer 214 can be a dual multiplexer, that is, selecting one of the two clock signals, namely the first divided clock ckdiv1 and the second divided clock ckdiv2, as the output ckdiv-A. The second multiplexer 215 is used to select one of the second divided clock ckdiv2 and the third divided clock ckdiv3 as the second output divided clock ckdiv-B. Similarly, the second multiplexer 215 can be a dual multiplexer. For example, 1 / 2*T can be generated using these three divided clocks. ckin It can effectively help, such as Figure 1D The digital time converter shown reduces the full-scale range, thereby improving accuracy.

[0034] According to some optional embodiments, the first multiplexer 214 and the second multiplexer 215 can be used for clock selection based on the same clock selection signal 209. For example, as Figure 2A As shown, the clock selection signal can come from modulator 203, such as a modulator similar to the Sigma-Delta modulator 103 described above, or other types of modulators that those skilled in the art would recognize. Alternatively, the clock selection signal can come from another unit used to generate the clock selection signal.

[0035] According to some alternative embodiments, the first flip-flop 212 and the second flip-flop 213 can be triggered by a pair of clocks with opposite phases. Figure 2B An example timing diagram of the first divided clock ckdiv1, the second divided clock ckdiv2, and the third divided clock ckdiv3 in such an embodiment is shown. Figure 2B It can be seen that the rising edges of the two clock pairs (ckdiv1 and ckdiv2, ckdiv2 and ckdiv3) differ by 0.5T. ckin T ckin This refers to the period of the input clock signal ckin. By controlling the multiplexer to trigger clock signals ckdiv1 and ckdiv2, or clock signals ckdiv2 and ckdiv3 respectively, a 0.5T clock can be achieved. ckin A higher resolution.

[0036] According to some alternative embodiments, the first flip-flop 212 can be used to receive the inverted signal of the input clock ckin. As a clock control signal, the second flip-flop 213 can be used to receive the input clock ckin as a clock control signal.

[0037] It is understood that the fractional frequency divider 201 according to one or more embodiments of this disclosure can be used with... Figure 1D The digital time converter 132 is used in conjunction with it, and this disclosure is not limited thereto.

[0038] The following is for reference. Figure 3 A numerically controlled oscillator 300 according to some embodiments of the present disclosure is described. For example... Figure 3 As shown, the numerically controlled oscillator 300 may include a fractional frequency divider 301, a digital time converter 302, a modulator 303, and an accumulator 304. The numerically controlled oscillator 300 can generate an output clock (ckout) 306 based on an input clock (ckin) 305 and a frequency division coefficient (Div_ratio) 307. The frequency division coefficient Div_ratio can be a non-integer value, such as the sum of an integer and a fractional number.

[0039] The fractional divider 301 can be a fractional divider as described with reference to embodiments of this disclosure. For example, the fractional divider 301 can be similar to that described with reference to... Figure 2B The fractional frequency divider 201 or a variant thereof is described. The fractional frequency divider 301 may include a multi-mode frequency divider 311, a first flip-flop 312, a second flip-flop 313, a first multiplexer 314, and a second multiplexer 315. The multi-mode frequency divider 311 can be used to generate a first divided clock based on an input clock 305 (ckin) and a division coefficient sequence 307'. The first flip-flop 312 can be used to generate a second divided clock ckdiv2 based on the first divided clock ckdiv1. The second flip-flop 313 can be used to generate a third divided clock ckdiv3 based on the first divided clock ckdiv1. The first multiplexer 314 can be used to select one of the first divided clock ckdiv1 and the second divided clock ckdiv2 as a first output divided clock ckdiv-A. The second multiplexer 315 can be used to select one of the second divided clock ckdiv2 and the third divided clock ckdiv3 as a second output divided clock ckdiv-B. Figure 3 As shown, the first output divided clock ckdiv-A and the second output divided clock ckdiv-B are then output to the digital time converter 302.

[0040] The digital time converter 302 can be used to generate an output clock 306 (ckout) based on a first output divided clock ckdiv-A and a second output divided clock ckdiv-B. The digital time converter 302 can also be used to perform phase error correction on the output clock 306 based on a phase error signal 308' from the accumulator 304.

[0041] Modulator 303 can be used to generate a frequency division coefficient sequence 307' and a frequency error signal. Specifically, modulator 303 can convert the frequency division coefficient 307 into an integer frequency division coefficient sequence 307', where each division value in the sequence is an integer to control the frequency division operation of the multimode frequency divider, and the average value of these integers is equal to the frequency division coefficient 307 over a period of time. Modulator 303 can be a first-order Sigma Delta modulator, or can be or can include any other modulator or modulation circuit that can be conceived by those skilled in the art.

[0042] Accumulator 304 can be used to accumulate frequency error signal 308 to obtain phase error signal 308'. Accumulator 304 can employ any accumulator circuit that can be conceived by those skilled in the art, and this disclosure is not limited thereto.

[0043] According to some alternative embodiments, modulator 303 is also used to generate clock selection signal 309. In such embodiments, first multiplexer 314 and second multiplexer 315 can be configured to perform clock selection based on clock selection signal 309. For example, first multiplexer 314 and second multiplexer 315 can be selected based on the same or identical clock signal, such that the outputs of the two multiplexers are coordinated. For instance, when first multiplexer 314 selects the output first divided clock ckdiv1 as the first output divided clock ckdiv-A, second multiplexer 315 selects the output second divided clock ckdiv2 as the second output divided clock ckdiv-B; and when first multiplexer 314 selects the output second divided clock ckdiv2 as the first output divided clock ckdiv-A, second multiplexer 315 can select the output third divided clock ckdiv3 as the second output divided clock ckdiv-B. It is understood that the above are merely examples, and this disclosure is not limited thereto.

[0044] According to some alternative embodiments, the digital time converter 302 can be as follows: Figure 1D The digital time converter shown is based on a phase interpolator.

[0045] According to some embodiments, the first flip-flop 312 is used to receive the inverted signal of the input clock as a clock control signal, and the second flip-flop 313 is used to receive the input clock as a clock control signal.

[0046] According to one or more embodiments of this disclosure, the numerically controlled oscillator 300 can achieve a full-amplitude of 0.5*T. ckin T ckinThis refers to the period of the input clock clock (ckin). In other words, the output clock can have a resolution of 0.5 times the input clock period. This allows for lower jitter without increasing circuit complexity.

[0047] The following is for reference. Figure 4 To describe other aspects according to this disclosure.

[0048] A phase-locked loop (PLL) circuit can be used to calibrate a fractional frequency divider. A PLL circuit is a feedback control circuit that controls the frequency and phase of the internal oscillation signal by using an externally input reference signal. Figure 4 A phase-locked loop circuit 400 according to an embodiment of the present disclosure is shown. For example... Figure 4 As shown, the phase-locked loop circuit 400 may include: a phase comparator 401, a loop filter 402, a voltage-controlled oscillator 403, and a digitally controlled oscillator 404.

[0049] The numerically controlled oscillator 404 can be an oscillator according to embodiments of the present disclosure, and specifically can be similar to that described in reference to [reference needed]. Figure 3 The configuration of the numerically controlled oscillator 300 described herein will not be repeated here. The numerically controlled oscillator 404 may include a fractional frequency divider, a digital time converter, a modulator, and an accumulator.

[0050] Phase comparator 401, also known as phase detector or phase discriminator, can be used to output an error signal 413 based on a reference clock 411 and a feedback clock 412. The error signal 413 can be in the form of charge, voltage, digital signal, etc., and this disclosure is not limited thereto. The error signal 413 is used to indicate the phase difference between the reference clock 411 and the feedback clock 412. The error signal 413 can then be output to a loop filter 402, and used to loop-filter the error signal 413 to generate a loop-filtered error signal 414. Voltage-controlled oscillator 403 can be used to generate a voltage-controlled oscillation signal 415 based on the loop-filtered error signal 414. Numerically controlled oscillator 404 can be used to receive the voltage-controlled oscillation signal 415 as an input clock, such as the input clock ckin described in embodiments of this disclosure, and to generate an output clock, for example, referring to the aforementioned ckout as the feedback clock 412. Understandably, based on such a phase-locked loop circuit 400, the fractional frequency divider in the numerically controlled oscillator 404 can be calibrated to achieve an accurate 0.5*T. ckin Output.

[0051] According to some alternative embodiments, the phase-locked loop circuit 400 may further include a calibration circuit 410. The calibration circuit 410 may include a first error estimation circuit 405, a first multiplier 406, a second error estimation circuit 407, a first adder 408, and a second multiplier 409. The calibration circuit 410 can be used to calibrate errors caused by transistor errors and circuit asymmetry to obtain a more accurate circuit resolution (e.g., 0.5*T). ckin (resolution). In such an embodiment, the phase comparator 401 can also be used to output a late signal 416 based on the reference clock 411 and the feedback clock 412. The late signal 416 indicates the time order of the reference clock 411 and the feedback clock 412 relative to each other. In such an embodiment, the modulator of the numerically controlled oscillator 404 can also be used to generate a clock selection signal 417, which may be, for example, a clock selection signal as described above, for selecting the output of the multiplexer in the numerically controlled oscillator.

[0052] The first error estimation circuit 405 can be used to determine the clock phase error 418 based on the late signal 416 and the clock selection signal 417. The first multiplier 406 can be used to multiply the clock phase error 418 with the clock selection signal 417 to obtain the clock error signal 419. The second error estimation circuit 407 can be used to determine the gain error 421 based on the late signal 416 and the phase error signal 420. As mentioned above, the phase error signal 420 can come from the numerically controlled oscillator 404, for example, it can be obtained by the accumulator of the numerically controlled oscillator 404 by accumulating the frequency error signal, and can be similarly combined with Figure 3 The phase error signal 308' is mentioned above. The first adder 408 can be used to add the clock error signal 419 to the phase error signal 420 to obtain an added error signal 422. For example, the clock phase error can be added to the phase error in open-loop operation. The second multiplier 409 can be used to multiply the gain error 421 with the added error signal 422 to obtain a full-amplitude error correction signal 423. The full-amplitude error correction signal 423 can be output to the numerically controlled oscillator 404 (specifically, to a digital time converter within the numerically controlled oscillator 404, not shown) for full-amplitude error correction by the digital time converter.

[0053] According to this alternative embodiment, gain calibration and 1 / 2*T can also be performed via a digital time converter. ckin The calibration enables the calibration of the output clock ckout of the numerically controlled oscillator 404, and can also reduce the output clock error caused by transistor errors and circuit asymmetry.

[0054] The first multiplier 406, the first adder 408, and the second multiplier 409 according to embodiments of the present disclosure can be implemented in any manner that can be conceived by those skilled in the art, including but not limited to common adder and multiplier circuits. Similarly, the first error estimation circuit 405 and the second error estimation circuit 407 according to embodiments of the present disclosure can be implemented in any manner that can be conceived by those skilled in the art, including but not limited to using circuits capable of achieving minimum mean square error (LMS) estimation, or other circuits that can be conceived by those skilled in the art.

[0055] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, and the words "a" or "an" do not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

Claims

1. A fractional frequency divider, comprising: A multi-mode frequency divider, wherein the multi-mode frequency divider is used to generate a first frequency-divided clock based on an input clock and a frequency division coefficient sequence; A first flip-flop, which is used to generate a second frequency-divided clock based on the first frequency-divided clock; The second flip-flop is used to generate a third frequency-divided clock based on the first frequency-divided clock. A first multiplexer is configured to select one of the first divided clock and the second divided clock as the first output divided clock. as well as The second multiplexer is used to select one of the second divided clock and the third divided clock as the second output divided clock, wherein the first multiplexer and the second multiplexer are used to perform clock selection based on the same clock selection signal.

2. The fractional frequency divider according to claim 1, wherein, The first flip-flop is used to receive the inverted signal of the input clock as a clock control signal, and the second flip-flop is used to receive the input clock as a clock control signal.

3. A numerically controlled oscillator, comprising: A fractional frequency divider, the fractional frequency divider comprising: A multi-mode frequency divider, wherein the multi-mode frequency divider is used to generate a first frequency-divided clock based on an input clock and a frequency division coefficient sequence; A first flip-flop, which is used to generate a second frequency-divided clock based on the first frequency-divided clock; The second flip-flop is used to generate a third frequency-divided clock based on the first frequency-divided clock. A first multiplexer, configured to select one of the first divided clock and the second divided clock as the first output divided clock; and The second multiplexer is used to select one of the second divided clock and the third divided clock as the second output divided clock, wherein the first multiplexer and the second multiplexer are used to perform clock selection based on the same clock selection signal; A digital time converter, wherein the digital time converter is used to generate an output clock based on a first output divided clock and a second output divided clock, and is used to perform phase error correction on the output clock according to a phase error signal; A modulator, the modulator being used to generate the frequency division coefficient sequence and the frequency error signal; and An accumulator is used to accumulate the frequency error signal to obtain the phase error signal.

4. The numerically controlled oscillator according to claim 3, wherein, The modulator is also used to generate the clock selection signal.

5. The numerically controlled oscillator according to claim 3, wherein, The digital time converter is a digital time converter based on a phase interpolator.

6. The numerically controlled oscillator according to any one of claims 3-5, wherein, The first flip-flop is used to receive the inverted signal of the input clock as a clock control signal, and the second flip-flop is used to receive the input clock as a clock control signal.

7. The numerically controlled oscillator according to any one of claims 3-5, wherein, The output clock has a period resolution that is 0.5 times that of the input clock.

8. A phase-locked loop circuit, comprising: A phase comparator, the phase comparator being configured to output an error signal based on a reference clock and a feedback clock, the error signal indicating the phase difference between the reference clock and the feedback clock; A loop filter, wherein the loop filter is used to perform loop filtering on the error signal; A voltage-controlled oscillator, the voltage-controlled oscillator being used to generate a voltage-controlled oscillation signal based on the error signal that has been loop-filtered; as well as The numerically controlled oscillator according to any one of claims 4-7 is configured to receive the voltage-controlled oscillation signal as the input clock and to generate the output clock as the feedback clock.

9. The phase-locked loop circuit according to claim 8, wherein, The phase comparator is further configured to output a delayed signal based on the reference clock and the feedback clock, the delayed signal indicating the time order of the reference clock and the feedback clock relative to each other, wherein the modulator is further configured to generate a clock selection signal, and wherein the phase-locked loop circuit further includes: A first error estimation circuit is used to determine a clock phase error based on the late signal and the clock selection signal. A first multiplier is used to multiply the clock phase error by the clock selection signal to obtain a clock error signal; A second error estimation circuit is used to determine the gain error based on the late signal and the phase error signal; A first adder, configured to add the clock error signal to the phase error signal to obtain an added error signal; and A second multiplier is used to multiply the gain error by the summed error signal and output it to the digital time converter for full-amplitude error correction.

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