XOR engine on RAM

Abstract

The present invention provides methods and apparatus for an exclusive-OR (XOR) engine in a random access memory (RAM) device for accelerating cryptographic operations in a processor. For example, an integrated circuit memory device enclosed within a single integrated circuit package may include an XOR engine coupled to memory cells in the RAM device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., a system on a chip (SoC) or a central processing unit (CPU)) may have cryptographic logic that performs cryptographic operations using an XOR operation, which is performed by the XOR engine in the RAM device using data in the RAM device.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application No. 16 / 582,871, filed on September 25, 2019, and entitled “EXCLUSIVE OR ENGINE ON RANDOMACCESS MEMORY,” the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, an XOR engine in a memory system configured to facilitate cryptographic operations of a processor. Background Art

[0004] A memory subsystem may include one or more memory components that store data. The memory subsystem may be a data storage system, such as a solid-state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small-outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). Memory components may be, for example, non-volatile memory components and volatile memory components. Examples of memory components include memory integrated circuits. Some memory integrated circuits are volatile and require power to maintain stored data. Some memory integrated circuits are non-volatile and can retain stored data even when power is not supplied. Examples of non-volatile memory include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM), among others. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM). Generally speaking, a host system may utilize a memory subsystem to store data at and retrieve data from the memory components.

[0005] For example, a computer may include a host system and one or more memory subsystems attached to the host system. The host system may have a central processing unit (CPU) that communicates with the one or more memory subsystems to store and / or retrieve data and instructions. Instructions for the computer may include an operating system, device drivers, and application programs. The operating system manages resources in the computer and provides common services to application programs, such as memory allocation and time-sharing of resources. Device drivers operate or control specific types of devices in the computer; and the operating system uses these device drivers to provide resources and / or services provided by these types of devices. The computer system's central processing unit (CPU) may run the operating system and device drivers to provide services and / or resources to application programs. The CPU may run application programs that use the services and / or resources. For example, an application program implementing a type of application program of the computer system may instruct the CPU to store data in and retrieve data from the memory components of the memory subsystem.

[0006] The host system can communicate with the memory subsystem according to a predefined communication protocol, such as the Non-Volatile Memory Host Controller Interface Specification (NVMHCI), also known as NVM Express (NVMe), which specifies a logical device interface protocol for accessing non-volatile memory devices via a Peripheral Component Interconnect Express (PCI Express or PCIe) bus. Depending on the communication protocol, the host system can send different types of commands to the memory subsystem, and the memory subsystem can execute the commands and provide responses to the commands. Some commands, such as read and write commands, instruct the memory subsystem to store or retrieve data items at or from addresses specified in the command. Some commands manage infrastructure and / or system management tasks in the memory subsystem, such as commands for managing namespaces, attaching namespaces, creating input / output submission or completion queues, deleting input / output submission or completion queues, and commands for firmware management. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0008] Figure 1 A system with an exclusive-OR (XOR) engine configured on a random access memory is shown.

[0009] Figure 2 A method for performing cryptographic operations using an exclusive-OR (XOR) engine on random access memory is presented.

[0010] Figure 3 Another method of performing cryptographic operations using an exclusive-OR (XOR) engine on random access memory is presented.

[0011] Figure 4 Another method using an exclusive-OR (XOR) engine on random access memory is shown.

[0012] Figure 5 An example computing system is shown that can use the (XOR) engine technique. DETAILED DESCRIPTION

[0013] At least some aspects of the present disclosure relate to an exclusive-OR (XOR) engine in a memory system. For example, an integrated circuit (IC) memory device (e.g., one having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)) can be configured to include an XOR engine and provide random memory access, thereby accelerating encryption / decryption operations in a processor connected to the memory device. A processor (e.g., a system-on-chip or a central processing unit (CPU) for a mobile device) can include encryption logic that utilizes the services provided by an XOR engine in a device configured with random access memory (RAM). In some embodiments, at least some XOR operations encountered in encryption / decryption are performed using data in the random access memory and an XOR engine in the random access memory to accelerate the encryption / decryption process.

[0014] Figure 1 A system is shown with an exclusive OR (XOR) engine configured on a random access memory. For example, a single memory device enclosed within an integrated circuit (IC) package may include an XOR engine 111 and a random access memory device 110 (e.g., DRAM or NVRAM). The XOR engine 111 can be used to accelerate encryption / decryption operations using data in the random access memory device 110. For example, Figure 1 The system may include a processor such as a system on a chip (SoC) 100. The SoC may include cryptographic logic 101, which may be implemented via software instructions, hardware logic, and / or a combination of software instructions and hardware logic. The cryptographic logic 101 in the SoC 100 may be configured to perform cryptographic operations (e.g., encryption and / or decryption) using an XOR operation performed by an XOR engine 111 on data stored in a random access memory device 110.

[0015] Figure 2 A method for performing cryptographic operations using an exclusive-OR (XOR) engine on random access memory is presented. For example, Figure 2 The method can be found in Figure 1 Generally speaking, Figure 2The method may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0016] At block 201 , a processor 100 having multiple execution units executes instructions programmed for the processor 100 .

[0017] At block 203 , a logic unit (eg, 111 ) of a random access memory device 110 coupled to the processor 100 to provide random access memory to the processor 100 performs an exclusive OR (XOR) 111 operation on data stored in the random access memory device 110 .

[0018] At block 205 , the processor 100 encrypts data for storage in the random access memory device 110 using the result of the XOR operation performed by the logic unit of the random access memory device 110 .

[0019] At block 207 , the processor 100 decrypts the data retrieved from the random access memory device 110 using the result of the XOR operation performed by the logic unit of the random access memory device 110 .

[0020] Figure 3 Another method of performing cryptographic operations using an exclusive-OR (XOR) engine on random access memory is shown. For example, Figure 3 The method can be found in Figure 1 The present invention is performed in a system, or generally, by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the described embodiments should be understood as examples only, and the described processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0021] At block 301 , a processor 100 , having a plurality of execution units configured to execute instructions programmed for the processor 100 , randomly accesses a plurality of memory cells in a random access memory device 110 .

[0022] At block 303 , a logic unit coupled to the memory cells in the random access memory device 110 performs an exclusive OR (XOR) 111 operation on the data stored in the random access memory device 110 .

[0023] At block 305 , the processor 100 encrypts data for storage in the random access memory device 110 using an XOR operation performed by a logic unit in the random access memory device 110 .

[0024] At block 307 , the processor 100 decrypts the data retrieved from the random access memory device 110 using an XOR operation performed by a logic unit in the random access memory device 110 .

[0025] Figure 4 Another method using the XOR engine on random access memory is shown. For example, Figure 4 The method can be found in Figure 1 The present invention is performed in a system, or generally, by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the described embodiments should be understood as examples only, and the described processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0026] At box 401, a first logic unit performs an exclusive OR (XOR) operation on data stored in memory cells of a random access memory device 110 coupled to a processor 100, the processor having a plurality of execution units configured to execute instructions programmed for the processor 100 and capable of randomly accessing memory cells provided in the random access memory device 110.

[0027] At block 403 , the second logic unit configured in the processor 100 encrypts data for storage in the random access memory device 110 using the XOR operation performed by the first logic unit of the random access memory device 110 .

[0028] At block 405 , the second logic unit configured in the processor 100 decrypts the data retrieved from the random access memory device 110 using the XOR operation performed by the first logic unit of the random access memory device 110 .

[0029] Figure 5 An example computing system is shown that can use the (XOR) engine technique. Figure 5 The system includes a memory subsystem 510 and a host system 520. For example, Figure 1 The XOR engine 111 may be implemented in the processing device 517 and / or the controller 515 of the memory subsystem 510; and Figure 1 The encryption logic 101 may be implemented in or via the processing device (518) and / or the controller 516 of the host system 520.

[0030] Generally speaking, a memory subsystem may also be referred to as a "memory device." An example of a memory subsystem is a memory module connected to a central processing unit (CPU) via a memory bus. Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual inline memory modules (NVDIMMs), and the like.

[0031] Another example of a memory subsystem is a data storage device / system connected to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs).

[0032] In some embodiments, the memory subsystem is a hybrid memory / storage subsystem that provides both memory and storage functions. Generally speaking, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0033] The memory subsystem 510 may include media, such as media units / memory components 509A through 509N. Generally speaking, media units / memory components 509A through 509N may be volatile memory components, non-volatile memory components, or a combination of these components. Each of the media units / memory components 509A through 509N can perform operations to store, record, program, write, or submit new data independently of the operations of the other media units / memory components 509A through 509N. Therefore, the media units / memory components 509A through 509N can be used in parallel when executing write commands. In some embodiments, the memory subsystem is a storage system. An example of a storage system is a solid-state drive (SSD). In some embodiments, the memory subsystem 510 is a memory module. Examples of memory modules include DIMMs, NVDIMMs, and NVDIMM-Ps. In some embodiments, the memory subsystem 510 is a hybrid memory / storage subsystem. Generally speaking, the computing environment may include a host system 520 that utilizes the memory subsystem 510. For example, the host system 520 can write data to and read data from the memory subsystem 510 .

[0034] Host system 520 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or any other computing device that includes memory and processing devices. Host system 520 may include or be coupled to memory subsystem 510, such that host system 520 can read data from or write data to memory subsystem 510. Host system 520 may be coupled to memory subsystem 510 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, etc. The physical host interface may be used to transfer data between host system 520 and memory subsystem 510. When the memory subsystem 510 is coupled to the host system 520 via a PCIe interface, the host system 520 may further utilize an NVM Express (NVMe) interface to access the memory components 509A to 509N. The physical host interface may provide an interface for passing control, addresses, data, and other signals between the memory subsystem 510 and the host system 520. Figure 5Memory subsystem 510 is depicted as an example. In general, host system 520 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] The host system 520 includes a processing device 518 and a controller 516. The processing device 518 of the host system 520 can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 516 can be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 516 controls communication via a bus coupled between the host system 520 and the memory subsystem 510.

[0036] In general, the controller 516 may send commands or requests to the memory subsystem 510 for desired access to the memory components 509A to 509N. The controller 516 may further include interface circuitry to communicate with the memory subsystem 510. The interface circuitry may convert responses received from the memory subsystem 510 into information for the host system 520.

[0037] The controller 516 of the host system 520 can communicate with the controller 515 of the memory subsystem 510 to perform operations, such as reading, writing, or erasing data at the memory components 509A-509N, as well as other such operations. In some cases, the controller 516 is integrated into the same package as the processing device 518. In other cases, the controller 516 is separate from the package of the processing device 518. The controller 516 and / or the processing device 518 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 516 and / or the processing device 518 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0038] In general, media units / memory components 509A-509N may include any combination of different types of nonvolatile memory components and / or volatile memory components. An example of a nonvolatile memory component includes NAND-type flash memory. Each of memory components 509A-509N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC), such as triple-level cells (TLC) or quad-level cells (QLC). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., a data block) used by the host system 520. Although nonvolatile memory components such as NAND-type flash memory are described, memory components 509A-509N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 509A-509N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, ferroelectric random access memory (FeTRAM), ferroelectric RAM (FeRAM), conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), nanowire-based nonvolatile memory, memory incorporating memristor technology, and cross-point arrays of nonvolatile memory cells. The cross-point array of the nonvolatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable crossbar grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. Furthermore, the memory cells of memory components 509A-509N can be grouped into memory pages or data blocks, which can refer to the units of the memory component used to store data.

[0039] The controller 515 of the memory subsystem 510 can communicate with the memory components 509A-509N to perform operations such as reading, writing, or erasing data at the memory components 509A-509N, as well as other such operations (e.g., in response to commands dispatched by the controller 516 on a command bus). The controller 515 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 515 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The controller 515 may include a processing device 517 (processor) configured to execute instructions stored in the local memory 519. In the illustrated example, the local memory 519 of the controller 515 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 510, including handling communications between the memory subsystem 510 and the host system 520. In some embodiments, local memory 519 may include memory registers that store memory pointers, fetched data, etc. Local memory 519 may also include read-only memory (ROM) for storing microcode. Figure 5 The example memory subsystem 510 in FIG. 5 is illustrated as including a controller 515, but in another embodiment of the present disclosure, the memory subsystem 510 may not include a controller 515 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0040] In general, the controller 515 may receive commands or operations from the host system 520 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 509A-509N. The controller 515 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 509A-509N. The controller 515 may further include host interface circuitry to communicate with the host system 520 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions for accessing the memory components 509A-509N, and convert responses associated with the memory components 509A-509N into information for the host system 520.

[0041] The memory subsystem 510 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 510 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 515 and decode the addresses to access the memory components 509A-509N.

[0042] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations serve as a means for those skilled in the data processing arts to effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0043] It should be borne in mind, however, that all of these terms and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms it into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0044] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0045] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures for various such systems will be described below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0046] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0047] In this specification, various functions and operations are described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that such representations mean that the functions are generated by one or more controllers or processors, such as microprocessors, executing computer instructions. Alternatively, or in combination, functions and operations may be implemented using dedicated circuitry, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), with or without software instructions. Embodiments may be implemented using hard-wired circuitry without software instructions, or in combination with software instructions. Thus, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source of instructions executed by the data processing system.

[0048] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A computing device comprising: a processor having a plurality of execution units configured to execute instructions programmed for the processor; and a random access memory device coupled to the processor to provide random access memory to the processor, the random access memory device having a logic unit configured to perform an exclusive OR (XOR) operation on data stored in the random access memory device; wherein the processor is configured to encrypt data for storage in the random access memory device and to decrypt data retrieved from the random access memory device; and Wherein the logic unit of the random access memory device is configured to perform at least a portion of an XOR operation for encrypting data for storage in the random access memory device and decrypting data retrieved from the random access memory device.

2. The computing apparatus of claim 1, wherein the random access memory device is enclosed in an integrated circuit package.

3. The computing apparatus of claim 2, wherein the random access memory device comprises a plurality of memory cells and the logic cell configured on a same substrate. The computing device of claim 3 , wherein the processor comprises a system on a chip.

5. The computing apparatus of claim 3, wherein the processor includes a logic unit configured to encrypt data for storage in the random access memory device using an XOR operation performed by the logic unit in the random access memory device.

6. The computing apparatus of claim 3, wherein the processor includes a logic unit configured to decrypt data retrieved from the random access memory device using an XOR operation performed by the logic unit in the random access memory device.

7. The computing device of claim 1, wherein the at least a portion of the XOR operation is performed in response to a read command from the processor.

8. A random access memory device comprising: a plurality of memory units configured to be randomly accessed by a processor, wherein the processor has a plurality of execution units configured to execute instructions programmed for the processor; and a logic unit coupled to the memory unit, the logic unit configured to perform an exclusive OR (XOR) operation on data stored in the random access memory device; wherein the processor is configured to encrypt data for storage in the random access memory device and to decrypt data retrieved from the random access memory device; and Wherein the logic unit of the random access memory device is configured to perform at least a portion of an XOR operation for encrypting data for storage in the random access memory device and decrypting data retrieved from the random access memory device.

9. The random access memory device of claim 8, wherein the random access memory device is enclosed in an integrated circuit package.

10. The random access memory device according to claim 9, wherein the random access memory device comprises a plurality of memory cells and the logic unit arranged on a same substrate.

11. The random access memory device of claim 10, wherein the processor comprises a system on a chip.

12. The random access memory device of claim 10, wherein the processor includes a logic unit configured to encrypt data for storage in the random access memory device using an XOR operation performed by the logic unit in the random access memory device.

13. The random access memory device of claim 10, wherein the processor includes a logic unit configured to decrypt data retrieved from the random access memory device using an XOR operation performed by the logic unit in the random access memory device.

14. The random access memory device of claim 8, wherein the at least a portion of the XOR operation is performed in response to a write command from the processor.

15. A processor comprising: a plurality of execution units configured to execute instructions programmed for the processor, wherein the processor is configured to be coupled to a random access memory device to randomly access memory cells provided in the random access memory device, the random access memory device having a first logic unit configured to perform an exclusive OR (XOR) operation on data stored in the random access memory device; and A second logic unit is configured to encrypt data for storage in the random access memory device and decrypt data retrieved from the random access memory device using the XOR operation performed by the first logic unit of the random access memory device.

16. The processor of claim 15, wherein the random access memory device is enclosed in an integrated circuit package.

17. The processor of claim 16, wherein the random access memory device comprises a plurality of memory cells and the logic unit configured on a same substrate.

18. The processor of claim 17, wherein the processor comprises a system on a chip.

19. The processor of claim 17, wherein the processor includes a logic unit configured to encrypt data for storage in the random access memory device using an XOR operation performed by the logic unit in the random access memory device.

20. The processor of claim 15, wherein at least a portion of an XOR operation is performed in response to read and write commands from the processor.

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