Video prediction using one or more neural networks

Abstract

Apparatuses, systems, and techniques for enhancing video are disclosed. In at least one embodiment, one or more neural networks are used to create a second video having one or more additional video frames from a first video.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training neural networks according to the various novel techniques described herein. Background Technology

[0002] As video content is consumed in ever-growing ways, on a wide range of devices, and from diverse sources, instances of video content that are not optimal for a particular use or application may exist. For example, the video may be running at a lower frame rate or resolution than expected on a particular viewing device. There may also be one or more dropped frames, or errors in one or more data frames. Furthermore, the video content in the file may be less than expected. Attached Figure Description

[0003] Various embodiments according to this disclosure will now be described with reference to the accompanying drawings, in which:

[0004] Figure 1A , 1B 1C, 1D, 1E and 1F illustrate image data that can be analyzed according to at least one embodiment;

[0005] Figure 2 Components of a video frame analysis system according to at least one embodiment are shown;

[0006] Figure 3A and 3B Video frame prediction according to at least one embodiment is shown;

[0007] Figure 4 A video frame inference system according to at least one embodiment is shown.

[0008] Figure 5A and 5B A portion of a process for reasoning about one or more video frames, according to at least one embodiment, is shown;

[0009] Figure 6 A system for training and inference using one or more neural networks, according to at least one embodiment, is shown;

[0010] Figure 7 A system for training one or more neural networks according to at least one embodiment is shown;

[0011] Figure 8 The structure of a neural network according to at least one embodiment is shown;

[0012] Figure 9A The inference and / or training logic according to at least one embodiment is illustrated;

[0013] Figure 9B The inference and / or training logic according to at least one embodiment is illustrated;

[0014] Figure 10 An example data center system according to at least one embodiment is shown;

[0015] Figure 11 A computer system according to at least one embodiment is shown;

[0016] Figure 12 A computer system according to at least one embodiment is shown;

[0017] Figure 13 A computer system according to at least one embodiment is shown;

[0018] Figure 14 A computer system according to at least one embodiment is shown;

[0019] Figure 15A A computer system according to at least one embodiment is shown;

[0020] Figure 15B A computer system according to at least one embodiment is shown;

[0021] Figure 15C A computer system according to at least one embodiment is shown;

[0022] Figure 15D A computer system according to at least one embodiment is shown;

[0023] Figure 15E and Figure 15F A shared programming model according to at least one embodiment is shown;

[0024] Figure 16 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0025] Figures 17A-17B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0026] Figures 18A-18B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0027] Figure 19 A computer system according to at least one embodiment is shown;

[0028] Figure 20A A parallel processor according to at least one embodiment is shown;

[0029] Figure 20B A partitioning unit according to at least one embodiment is shown;

[0030] Figure 20C A processing cluster according to at least one embodiment is shown;

[0031] Figure 20D A graphics multiprocessor according to at least one embodiment is shown;

[0032] Figure 21 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0033] Figure 22 A graphics processor according to at least one embodiment is shown;

[0034] Figure 23 A processor microarchitecture according to at least one embodiment is shown;

[0035] Figure 24 A deep learning application processor according to at least one embodiment is shown;

[0036] Figure 25 An example neuromorphic processor according to at least one embodiment is shown;

[0037] Figure 26 and 27 At least a portion of a graphics processor according to at least one embodiment is shown;

[0038] Figure 28 At least a portion of a graphics processor core according to at least one embodiment is shown;

[0039] Figures 29A-29B At least a portion of a graphics processor core according to at least one embodiment is shown;

[0040] Figure 30 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0041] Figure 31 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0042] Figure 32 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; and

[0043] Figure 33 A streaming multiprocessor according to at least one embodiment is shown. Detailed Implementation

[0044] In at least one embodiment, it can be as follows: Figure 1AThe video stream shown receives a sequence of video frames 100. In at least one embodiment, consecutive video frames may include variations from earlier video frames. In at least one embodiment, the frame rate at which the video is captured or created determines not only how frequently the video refreshes the image, but also how much variation occurs between frames. In at least one embodiment, it may be desirable to improve the frame rate or frames per second in this video stream or associated video files or clips. In at least one embodiment, increasing the frame rate may improve the viewer's experience of the video stream, or may improve the perceived quality of the video stream. In at least one embodiment, one or more of these video frames may be dropped from the video stream due to errors, such as... Figure 1B The video stream sequence 120 is shown. In at least one embodiment, Figure 1A and Figure 1B Both scenarios can benefit from the addition of video frames used to improve the frame rate of the video or to replace one or more dropped frames. In at least one embodiment, this method can produce results such as... Figure 1C The video stream sequence 140 shown in the figure includes a method where any dropped frames are replaced, resulting in an increased overall frame rate. In at least one embodiment, it may be desirable to correct either one, both, or neither, but to improve the resolution of the video stream.

[0045] In at least one embodiment, video frame prediction can be performed using the current video frame 160, such as Figure 1D The video frames shown are illustrated. In at least one embodiment, such a sequence of frames can be analyzed to model a long-term video sequence. In at least one embodiment, a machine learning-based approach can be used, which utilizes a latent representation to attempt to map the video frames to a low-dimensional, compact space. In at least one embodiment, one or more neural networks can be trained to model how the latent representation changes over time to find the mapping that returns to the original video frames. In at least one embodiment, one or more constraints are placed on this latent space to make the latent space interpretable. In at least one embodiment, the constraints involve modeling a set of coordinates that move over time, where those moving coordinates can be used to adjust the appearance of one or more objects in the corresponding video file.

[0046] In at least one embodiment, given one or more video frames from past time points, one or more neural networks can be trained to predict or infer video frames from one or more future time points, at least relative to the playback time of the video. In at least one embodiment, features such as unsupervised landmarks can be used to represent various features of an object for modeling movement or other changes over time and between adjacent frames in the video data. In at least one embodiment, features such as landmarks can be used to model the motion of an object, such as a person, over a sequence of video frames. In at least one embodiment, a pose detector can be used to determine feature points, such as those corresponding to the limbs and joints of a person represented in the video, and to infer the motion of the person by those feature points that move between frames. In at least one embodiment, the trained model can map the feature points and their inferred motion back to the image data of this video frame to infer subsequent video frames, including a representation of the person at future time points, based on previously observed motion or behavior. In at least one embodiment, features such as unsupervised landmarks can be used to approximate keypoints of an object without manually annotating large amounts of training data. In at least one embodiment, a pose detector can be used to analyze video frames, such as Figure 1D The frame 160 includes a representation of person 162, and generates as follows: Figure 1E The pose information 182 is shown in frame 180 of the image. In at least one embodiment, frame 180 includes a region corresponding to the moving portion of this person 182, the intensity or other values ​​of which are capable of determining feature points or unsupervised landmarks in this image data. In at least one embodiment, the intensity value must satisfy at least a minimum feature threshold before being considered or selected as an image feature. In at least one embodiment, centroid calculation or absolute maximum value methods can be used to determine the coordinates of a particular feature point, which can be selected from a set of coordinate selection algorithms. In at least one embodiment, these feature points can be considered unsupervised landmarks because none of these feature points are annotated, so that the pose detector can determine the coordinates of an elbow joint but does not know that this point corresponds to an elbow joint. In at least one embodiment, some annotation can be performed using image reconstruction or other similar processes, where some type of knowledge of points can be taken into account when modeling the motion of an object over time. In at least one embodiment, this processing can be used for long-term video prediction, for example, for Figure 1F The video stream contains a sequence of frames 190, in which multiple frames 192 are predicted using information from one or more previous frames.

[0047] In at least one embodiment, the system 200 for analyzing input video frames may include, for example: Figure 2The components are shown. In at least one embodiment, system 200 includes three main components: an image encoder 222, an image decoder 216, and a temporal dynamic encoder 214. In at least one embodiment, a video frame 202 is received as input to the image encoder 222. In at least one embodiment, the image encoder 222 is configured to project the video frame 202 into a factorized pose-appearance space. In at least one embodiment, the image encoder 222 includes a pose encoder 204 for determining pose information of the input frame 202 and an appearance encoder 206 for determining appearance information of the input frame 202. In at least one embodiment, pose data 208 may be determined by the pose encoder 204, which may be used in conjunction with a pose analyzer 212 to generate pose information at time point t of the input video frame 202 that can be passed to the temporal encoder 214. In at least one embodiment, the appearance information determined from the appearance encoder 206 may be directly passed to the image decoder 216. In at least one embodiment, the image decoder 216 may acquire the appearance information and use it together with the predicted pose data (as data in the pose appearance space) to (re)construct the video frame 220 that should correspond to the input frame 202 in order to learn for landmark modeling of motion.

[0048] In at least one embodiment, pose data from pose encoder 204 is passed to temporal encoder 214 to attempt to determine how the pose representation changes or differs at one or more future time points (e.g., t+2). In at least one embodiment, time refers to the playback time of the video, which can be viewed at various time points as stored video time. In at least one embodiment, for video prediction and interpolation, it can be assumed that the appearance information in this video is constant over at least a defined time period and that changes can be captured by the pose representation. In at least one embodiment, if a frame is decomposed into pose and appearance, temporal dynamic encoder 214 can predict how the pose representation changes over time. In at least one embodiment, at each moment, image decoder 216 can subsequently construct a new frame 220 using the constant appearance information and the updated pose representation.

[0049] In at least one embodiment, such a method can be used to predict video frames based on one or more input frames. In at least one embodiment, such as... Figure 3A and 3BAs shown, video streams 300 and 350 can be generated using this method to predict data but without ground reality data. In at least one embodiment, the inference frames correspond well to the corresponding ground reality data for a short period of time, but as time increases, significant differences may appear and become more pronounced in the absence of another reference frame. In at least one embodiment, even with fine-tuning, the video stream can only be amplified to a certain amount in terms of resolution or frame rate without potentially noticeable artifacts.

[0050] In at least one embodiment, this method can be used for prediction and interpolation of long-range video data. In at least one embodiment, video prediction and interpolation are modeled as unsupervised latent structural reasoning, followed by temporal prediction in a latent space. In at least one embodiment, the latent representation can capture foreground semantics under explicit supervision, such as by leveraging keypoints or annotated pose data. In at least one embodiment, each landmark can be mapped to a coordinate indicating where the semantic portion is located, allowing reliable interpolation within a coordinate domain to achieve predictable motion interpolation. In at least one embodiment, the image decoder can map these landmarks back to the image domain, achieving high-quality long-range video interpolation and extrapolation by operating on the landmark representation space. In at least one embodiment, a self-supervised pipeline is used to model long-term video dynamics in a latent, explicit pose representation. In at least one embodiment, coarse object-level bounding boxes are used for training purposes.

[0051] In at least one embodiment, a latent representation of K landmark "keypoints" can be learned, each describing the spatial local appearance and 2D coordinates of a single rigid component. In at least one embodiment, this representation is interpretable and naturally follows when dynamically modeling associated or highly correlated rigid objects in a scene. In at least one embodiment, an unsupervised landmark recognition process can be utilized, which learns local landmarks that are consistently activated at the same semantic location without relying on a class of typical transformations. In at least one embodiment, this can be extended to using unsupervised landmarks for long-range video frame prediction and interpolation. In at least one embodiment, the constrained and parameterized representation is both sufficiently expressive and stable for long-range quality estimation of video prediction, while also providing intuitive results in interpolation tasks. In at least one embodiment, in the prediction and interpolation settings, the pose representation can be manipulated at least in part based on a two-dimensional (2D) Gaussian heatmap.

[0052] In at least one embodiment, the pose and appearance decompositions are learned using unsupervised labeling by splitting the input image into an appearance-invariant pose representation and a pose-invariant appearance representation, and then an attempt is made to reconstruct the original input image to learn landmarks. In at least one embodiment, three models can be used to build the network: an image-to-pose encoder, an image-to-appearance encoder, and an image decoder that attempts to reconstruct the input image from the decomposed pose and appearance representations.

[0053] In at least one embodiment, the attitude encoder Φ pose =Enc pose (x) can acquire an input image x and output a set of consistent partial activation maps. In at least one embodiment, these partial activation maps are invariant to changes in local appearance and are consistent across deformations. In at least one embodiment, the heatmap activated on a person's right hand should be invariant across changing skin color and lighting conditions, and track the position of this right hand across changing deformations and translations. In at least one embodiment, the appearance encoder Φ is conditional on the activation maps of the pose encoder. app =Enc app (x;Enc pose (x) Extracting local appearance information. In at least one embodiment, given an input image x, the pose encoder will first provide a KxHxW partial activation map Φ pose In at least one embodiment, in order to extract local appearance vectors, the appearance encoder projects the image onto a CxHxW appearance feature map M. app In at least one embodiment, the appearance vector for the k-th pose activation mapping can be calculated using the following formula:

[0054]

[0055] Given K C-dimensional appearance vectors. In at least one embodiment, Φ pose Each activation map in the array is normalized by the softmax function.

[0056] In at least one embodiment, the image decoder attempts to reconstruct the original input image by combining pose information from K activation maps with a set appearance vector of each of the K parts. In at least one embodiment, 2D Gaussian functions are adapted to each activation of these K activation maps by estimating their respective mean and covariance matrices, rather than conditioned on the activation pose maps normalized by the original softmax function. In at least one embodiment, each part is represented as... in and In at least one embodiment, the 2D Gaussian approximation is able to manipulate the pose representation because it forces each part activation map to become a unimodal representation with simple parameterization. In at least one embodiment, the pose encoder, shape encoder, and image decoder are jointly trained in a fully self-supervised manner using the final image reconstruction task as the sole source of supervision.

[0057] In at least one embodiment, color jitter and thin-plate spline (TPS) warpage are incorporated into the training pipeline to enhance the appearance invariance and localization properties of the attitude encoder, respectively. In at least one embodiment, let T... cj (x) and T tps (x) represent the color jitter and thin-plate spline deformation operations on the input image x, respectively. In at least one embodiment, the training process can be expressed as follows:

[0058]

[0059] Φ app =Enc app (T tps (x); Enc pos e(T tps (x))

[0060]

[0061] Among them, the original input x and the reconstructed x can be minimized. The reconstruction losses between them.

[0062] In at least one embodiment, neither the shape encoder nor the appearance encoder can access the undisturbed target x. In at least one embodiment, the pose information fed into the image decoder Dec(·,·) is based on a color-dithered input image, where only local appearance information is perturbed. In at least one embodiment, the appearance information is calculated from a plate-spline warped version of the input image, where the pose information is perturbed. In at least one embodiment, since the shape encoder also operates on the TPS-warped input image, it can locate the corresponding position in the new warped coordinates to capture the correct appearance information. In at least one embodiment, existing motion is also used as a source of pose perturbation in the input video data. In at least one embodiment, in addition to In addition to pairing, other pairings can be included, where T is replaced by sampling a random video frame between 3 and 60 frames away from the current frame x. tps .

[0063] In at least one embodiment, the source The 2D Gaussian parameters are projected onto a heatmap of the target output width and height for use as a semantic map. In at least one embodiment, the formula to be used is given by the following:

[0064]

[0065] Where s(k,l) is the heatmap value of part of graph k at coordinate position l.

[0066] In at least one embodiment, for the loss, the VGG-perceptual loss can be combined with pre-trained ImageNet weights and combined with adversarial loss to improve realism and standard pixel-level mean squared error loss. In at least one embodiment, the reconstruction loss can be expressed as follows:

[0067]

[0068] In at least one embodiment, since the unsupervised landmark-based pose representation can be explicitly interpreted as localized partial markers, it can be naturally manipulated and interpolated within that space. However, in at least one embodiment, care can be taken to ensure that the covariance matrix of each landmark remains positive definite during any operation. In at least one embodiment, this can be done in many parameterizations, such as directly in the covariance parameters, indirectly in the Chollisky decomposition parameters or the angles and magnitudes of the principal components, or even along the optimal transport along the Wasserstein Barycenter. In at least one embodiment, due to the wide variety of possible projection distortions, none of these methods dominates under all conditions.

[0069] In at least one embodiment, the parameters of the Cholesky decomposition are used because they are directly computed and guarantee covariance validity in both interpolation and extrapolation paradigms. In at least one embodiment, the Cholesky decomposition of each covariance matrix is ​​a unique matrix with a positive diagonal. Make Where L k It is a lower triangle. In at least one embodiment, the two-dimensional keypoints, as described herein, can generate three scalars (e.g., two positive and one unconstrained) that uniquely parameterize the covariance of each keypoint. In at least one embodiment, when these five parameters are coupled with a two-dimensional mean μ_k, the state vector of keypoint k at time step t is formed. In at least one embodiment, interpolation is performed linearly, as can be given by:

[0070]

[0071] In at least one embodiment, Long Short-Term Memory (LSTM) can be used to model the nonlinear temporal dynamics of the attitude representation. In at least one embodiment, with regard to interpolation, care must be taken to maintain the positive definite covariance matrix during prediction. In at least one embodiment, the parameters of the Cholesky decomposition of the covariance matrix are used as the prediction target. In at least one embodiment, the LSTM can produce an estimate of L, which is not an efficient Cholesky factor, but when calculating LL... T Even in this situation, an effective covariance matrix will still be produced.

[0072] In at least one embodiment, a pair of LSTMs is used to predict the Gaussian mean of the covariance and the perturbation of the Cholesky parameter. In at least one embodiment, predicting the residuals during extrapolation, rather than directly predicting the state, in addition to Cholesky parameterization, helps ensure robust long-term predictions. In at least one embodiment, this state residual, or error state, can be used to improve estimation performance in various nonlinear dynamic tasks. In at least one embodiment, besides keeping the unconstrained gradient path extended far back, the error state can also induce the model to learn local deformations of the state, which can be learned more easily because it is small and nearly linear. In at least one embodiment, this can help improve training performance and generalization. In at least one embodiment, at each time step, the LSTM uses a concatenation of the previous state and the state residuals to predict the next state residual.

[0073] In at least one embodiment, the self-supervised paradigm for long-range video prediction and interpolation preserves image structure over long frames. In at least one embodiment, this is achieved by decomposing image data into pose information and time-invariant appearance information. In at least one embodiment, since the pose information will undergo many perturbations throughout the long-range video prediction, a set of unsupervised 2D Gaussian landmarks can be used as the pose state. In at least one embodiment, each 2D Gaussian function can be safely perturbed in the Gaussian parameter space (μ, Σ) before being projected onto a 2D heatmap to be fed into the image decoder, thereby ensuring that the image decoder will see a set of unimodal Gaussian heatmaps. In at least one embodiment, the pose representation is a set of 2D anisotropic Gaussian heatmaps. In at least one embodiment, the strict Gaussian representation enables operation in the Gaussian parameter space while still guaranteeing the Gaussian function at each time step. In at least one embodiment, each Gaussian function can be interpreted as the localization of an object “part,” such as a wrist or leg, where the covariance roughly captures the spatial support of said part. In at least one embodiment, Gaussian landmarks are learned without any manual part annotation. In at least one embodiment, the learned portion is fully determined during training.

[0074] In at least one embodiment, the Gaussian functions can be time-operated in a Gaussian parameter space (e.g., values ​​of mean and covariance), thereby ensuring that the pose representation is a set of strictly Gaussian heatmaps at each time step. In at least one embodiment, a deterministic transformation can then be applied to these Gaussian functions. In at least one embodiment, the covariance can be tricky because it may need to be invertible and positive definite after any predicted perturbation. In at least one embodiment, a Cholesky decomposition of the lower triangular matrix L can be performed. In at least one embodiment, the matrix L can be perturbed and LL can be utilized. T Reconstruct a new covariance, thereby ensuring a positive definite covariance matrix at each step.

[0075] In at least one embodiment, the unsupervised landmarks or other features obtained for the video frames can then be smoothed in free space. In at least one embodiment, each unsupervised landmark is represented by a Gaussian heatmap, which can be parameterized as a mean and covariance, the mean being the center coordinates of the corresponding feature. In at least one embodiment, given these coordinate sequences, a time-dynamic model (e.g., an LSTM for prediction) can be trained to determine how these coordinates move over time. In at least one embodiment, a new layout of these color distributions can be predicted over time. In at least one embodiment, this layout can be fed into another network, whether as... Figure 4 The image decoder 216 shown is also part of a separate video generator 402, which maps it back to image space to create inference video. In at least one embodiment, linear interpolation can be used to capture determined motion in the inference video frame sequence. In at least one embodiment, one or more physics simulators can be used to infer how these Gaussian coordinates may move over time. In at least one embodiment, the inferred video includes one or more additional video frames, whether adding new content, filling in missing content, or improving the quality of existing content, such as increasing the frame rate or resolution of an existing video file or stream.

[0076] In at least one embodiment, Figure 5AThe process 500 shown can be used to train a model to infer video frames for purposes such as augmenting video data. In at least one embodiment, one or more video frames 502 are received or otherwise obtained, for example, as part of a video file or stream. In at least one embodiment, frames from the video are provided as input training data to a training system for training one or more neural networks. In at least one embodiment, the current video frame is analyzed to determine the pose and appearance representation of the current video frame 504. In at least one embodiment, an unsupervised landmarking method can be used, wherein features in the pose representation are represented as Gaussian heatmaps, each Gaussian heatmap being parameterized as mean and covariance. In at least one embodiment, these heatmaps can be used to predict one or more pose representations 506, such as corresponding to one or more future time points or time periods. In at least one embodiment, the pose representation information can be used together with appearance representation information 508 to reconstruct the current video frame being analyzed. In at least one embodiment, the input and reconstructed versions of the current video frame are compared to determine a current loss value 510 using an appropriate loss function. In at least one embodiment, one or more network parameters can be adjusted to attempt to minimize this loss 512. It can be determined whether more frames 514 should be analyzed. In at least one embodiment, the determining factors include whether additional frames exist in the video file or stream, and whether the model convergence or training completion criteria are met. In at least one embodiment, if more frames are to be analyzed, the process can continue with another input video frame. In at least one embodiment, if no more frames are analyzed, an enhanced video stream or file 516 comprising at least some inference frames can be provided, wherein the video may have a higher resolution, a higher frame rate, a new frame sequence, or a fewer number of dropped or lost frames than the original input video or set of video frames.

[0077] In at least one embodiment, during inference, the following can be used: Figure 5B The process 550 shown is used to infer video frames for purposes such as enhancing video data. In at least one embodiment, one or more video frames 552 of a video file or stream are received into a trained model. In at least one embodiment, input frames from this video can be used to infer additional video frames 554 using the trained model. In at least one embodiment, these inferred video frames can be used to generate an enhanced video stream or file 566.

[0078] Neural network training and development

[0079] A growing number of industries and applications are leveraging machine learning. In at least one embodiment, deep neural networks (DNNs) developed on processors have been used in a variety of use cases, from self-driving cars to faster drug development, from automated image analysis in security systems to intelligent real-time language translation in video chat applications. In at least one embodiment, deep learning is a technique that can model the neural learning processes of the human brain, continuously learn, become increasingly intelligent, and deliver more accurate results faster over time. Adults initially teach children to correctly identify and classify various shapes, eventually enabling them to recognize shapes without any guidance. Similarly, in at least one embodiment, deep learning or neural learning systems designed to perform similar tasks will need to be trained to become more intelligent and efficient in recognizing basic objects, occluded objects, etc., while also assigning context to those objects.

[0080] In at least one embodiment, neurons in the human brain examine the received inputs, assign a importance level to each of these inputs, and pass the outputs to other neurons for action. Artificial neurons, or perceptrons, are the most basic model of neural networks. In at least one embodiment, a perceptron may receive one or more inputs representing various features of an object that the perceptron is trained to recognize and classify, and assign a specific weight to each of these features based on their importance in defining the shape of the object.

[0081] A deep neural network (DNN) model comprises multiple layers of numerous connected perceptrons (e.g., nodes) that can be trained with large amounts of input data to solve complex problems quickly and with high accuracy. In one example, the first layer of the DNN model breaks down an input image of a car into different segments and looks for basic patterns such as lines and angles. The second layer assembles the lines to look for higher-level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle, and the final few layers produce labels for the input image that identify a specific car brand. Once trained, the DNN can be deployed and used to identify and classify objects or patterns in a process known as inference. Examples of inference (the process by which a DNN extracts useful information from a given input) include recognizing handwritten digits on checks deposited into an ATM, recognizing images of friends in photos, delivering movie recommendations, identifying and classifying different types of cars, pedestrians, and road hazards in self-driving cars, or translating human speech in near real-time.

[0082] During training, data flows through the DNN in the forward propagation phase until predictions are generated to indicate the labels corresponding to the inputs. If the neural network does not correctly label the input, the error between the correct label and the predicted label is analyzed, and the weights are adjusted for each feature during the backpropagation phase until the DNN correctly labels the inputs and other inputs in the training dataset. Training complex neural networks requires significant parallel computational power, including support for floating-point multiplication and addition. Inference is less computationally intensive than training and is a latency-sensitive process where the trained neural network is applied to new inputs it has not previously seen to classify images, translate speech, and infer new information.

[0083] Neural networks heavily rely on matrix mathematical operations, and complex multi-layered networks require significant floating-point performance and bandwidth to balance efficiency and speed. With thousands of processing cores, optimized matrix mathematical operations, and performance ranging from tens to hundreds of TFLOPS, a single computing platform can provide the performance required for deep neural network-based artificial intelligence and machine learning applications.

[0084] Figure 6 Components of a system 600, which can be used to train and utilize machine learning, are illustrated in at least one embodiment. As discussed below, the various components may be provided by various combinations of computing devices and resources or a single computing system, which may be under the control of a single entity or multiple entities. Furthermore, aspects may be triggered, initiated, or requested by different entities. In at least one embodiment, the training of the neural network may be instructed by a provider associated with provider environment 606, while in at least one embodiment, a customer or other user accessing the provider environment via client device 602 or other such resources may request training. In at least one embodiment, training data (or data to be analyzed by the trained neural network) may be provided by a provider, user, or third-party content provider 624. In at least one embodiment, client device 602 may be a vehicle or object navigating on behalf of a user, for example, the vehicle or object may submit a request for assistance in navigating the device and / or receive instructions.

[0085] In at least one embodiment, a request can be submitted to a provider environment 606 across at least one network 604. In at least one embodiment, the client device can be any suitable electronic and / or computing device that enables a user to generate and send such requests, such as a desktop computer, laptop computer, computer server, smartphone, tablet computer, game console (portable or otherwise), computer processor, computing logic, and set-top box. One or more networks 604 can include any suitable network for sending requests or other such data, such as the Internet, intranet, Ethernet, cellular network, local area network (LAN), a network with direct wireless connections between nodes, etc.

[0086] In at least one embodiment, a request may be received by interface layer 608, which in this example may forward data to training and inference manager 610. This manager may be a system or service, including hardware and software systems or services for managing data or content associated with requests and services. In at least one embodiment, the manager may receive requests to train a neural network and may provide data to training manager 612 in response to such requests. In at least one embodiment, training manager 612 may select an appropriate model or network to use, and may also use relevant training data to train the model if not specified in a request. In at least one embodiment, the training data may be a batch of data stored in training data repository 614, received from client device 602, or obtained from third-party provider 624. In at least one embodiment, training manager 612 may be responsible for training the data, for example, by using a LARC-based method as discussed herein. The network may be any suitable network, such as a recurrent neural network (RNN) or convolutional neural network (CNN). Once the network is trained and successfully evaluated, the trained network may be stored in model repository 616, such as a model repository 616 that may store different models or networks for users, applications, or services. In at least one embodiment, there may be multiple models for a single application or entity, which may be utilized based on multiple different factors.

[0087] In at least one embodiment, at a subsequent point in time, a request may be received from client device 602 (or another such device), the content of which (e.g., path determination) or is at least partially determined or influenced by a trained neural network. This request may include, for example, processing input data using a neural network to obtain one or more inference or other output values, classifications, or predictions. In at least one embodiment, input data may be received by interface layer 608 and directed to inference module 618, although different systems or services may also be used. In at least one embodiment, if not already locally stored in inference module 618, inference module 618 may obtain a suitable trained network, such as a trained deep neural network (DNN) discussed herein, from model repository 616. Inference module 618 may provide data as input to the trained network, which may then generate one or more inferences as outputs. This may include, for example, classification of instances of the input data. In at least one embodiment, the inference may then be transmitted to client device 602 for display to a user or other communication. In at least one embodiment, user context data may also be stored in a user context data store 622, which may include data about the user that is useful as input to the network when generating inference, or data determined to be returned to the user after an instance is obtained. In at least one embodiment, related data may include at least some input or inference data, and may also be stored in a local database 620 for processing future requests. In at least one embodiment, a user may use an account or other information to access resources or functions of the provider environment. In at least one embodiment, user data may also be collected and used to further train the model to provide more accurate inference for future requests, if permitted and available. In at least one embodiment, requests may be received through a user interface of the machine learning application 626 executed via a client device 602, and results may be displayed through the same interface. The client device may include resources for generating requests and processing results or responses, such as a processor 628 and memory 630, and at least one data storage element 632 for storing data for the machine learning application 626.

[0088] In at least one embodiment, processor 628 (or the processor of training manager 612 or inference module 618) will be a central processing unit (CPU). However, as mentioned, resources in such an environment can utilize GPUs to process at least some types of requested data. Utilizing thousands of cores, GPUs are designed to handle large amounts of parallel workloads and have thus become popular in deep learning for training neural networks and generating predictions. While using GPUs for offline building has made it possible to train larger and more complex models faster, offline prediction generation means either not being able to use the input features at request time, or having to generate predictions for all permutations of features and store them in a lookup table to serve real-time requests. If the deep learning framework supports CPU mode and the model is small and simple enough to perform feedforward on the CPU with a reasonable latency, a service on a CPU instance can host the model. In this case, training can be done offline on the GPU, and inference can be done in real time on the CPU. If the CPU approach is not feasible, the service can run on a GPU instance. However, because GPUs have different performance and cost characteristics than CPUs, running a service that offloads runtime algorithms to the GPU may require it to be designed differently from a CPU-based service.

[0089] In at least one embodiment, video data may be provided by client device 602 for enhancement in provider environment 606. In at least one embodiment, video data may be processed for enhancement on client device 602. In at least one embodiment, video data may originate from third-party content provider 624 and be enhanced by or by third-party provider 624, provider environment 606, or client device 602.

[0090] Figure 7A system 700 for classifying data or generating inference is illustrated in at least one embodiment. In at least one embodiment, both supervised and self-supervised training can be used, as discussed below. In at least one embodiment, a set of training datasets 702 (e.g., classified or labeled data) is provided as input to serve as training data. In at least one embodiment, the training data may include instances of at least one class of objects for a neural network to be trained, as well as information identifying that class of objects. In at least one embodiment, the training data may include a set of images, each image including a representation of a class of objects, wherein each image also includes or is associated with a label, metadata, and other information classifying or identifying the class of objects represented in the respective images. Various other types of data may also be used as training data and may include text data, audio data, video data, etc. In at least one embodiment, the training data 702 is provided as training input to a training manager 704. In at least one embodiment, the training manager 704 may be a system or service including hardware and software, such as one or more computing devices executing a training application for training a neural network (or other model or algorithm, etc.). In at least one embodiment, the training manager 704 receives instructions or requests instructing a class of models for training. In at least one embodiment, the model can be any suitable statistical model, network, or algorithm that can be used for these purposes, such as artificial neural networks, deep learning algorithms, learned classifiers, Bayesian networks, etc. In at least one embodiment, the training manager 704 can select an initial model or other untrained model from a suitable repository 706 and train the model using training data 702 to generate a trained model 708 (e.g., a trained deep neural network) that can be used to classify similar types of data, or to generate other such inference. In at least one embodiment where training data is not used, a suitable initial model can still be selected for training for each training manager 704's input data.

[0091] In at least one embodiment, the model can be trained in several different ways, possibly depending to some extent on the type of model chosen. In at least one embodiment, a set of training datasets can be provided to the machine learning algorithm, wherein the model is a model artifact created by the training process. In at least one embodiment, each instance of the training data contains a correct answer (e.g., a classification), which may be referred to as the target or target attribute. In at least one embodiment, the learning algorithm finds patterns in the training data, maps the input data attributes to the target, an answer to be predicted, and outputs a machine learning model that captures these patterns. In at least one embodiment, the machine learning model can then be used to obtain predictions for new data without a specified target.

[0092] In at least one embodiment, the training manager 704 can select from a set of machine learning models, including a collection of binary classification, multi-class classification, and regression models. In at least one embodiment, the type of model to be used can depend at least partially on the type of the target to be predicted. In at least one embodiment, a machine learning model for a binary classification problem predicts binary results, such as one of two possible categories. In at least one embodiment, a learning algorithm such as logistic regression can be used to train a binary classification model. In at least one embodiment, a machine learning model for a multi-class classification problem allows generating predictions for multiple categories, such as predicting one of more than two results. Multinomial logistic regression can be used to train a multi-class model. A machine learning model for a regression problem predicts numerical values. Linear regression can be used to train a regression model.

[0093] In at least one embodiment, in order to train a machine learning model according to one embodiment, the training manager must determine the input training data source, as well as other information such as the name of the data attribute containing the target to be predicted, the required data transformation instructions, and the training parameters controlling the learning algorithm. In at least one embodiment, during training, the training manager 704 may automatically select a suitable learning algorithm based on the target type specified in the training data source. In at least one embodiment, the machine learning algorithm may accept parameters for controlling certain characteristics of the training process and the resulting machine learning model. These are referred to herein as training parameters. In at least one embodiment, if no training parameters are specified, the training manager may utilize default values ​​known to work well in a wide range of machine learning tasks. Examples of training parameters for which values ​​can be specified include maximum model size, maximum number of passes for training data, shuffling type, regularization type, learning rate, and regularization amount. Default settings can be specified, with options to adjust values ​​to fine-tune performance.

[0094] In at least one embodiment, the maximum model size is the total size, in bytes, of the patterns created during the model's training. In at least one embodiment, a model of a specified size, such as 100MB, can be created by default. If the training manager cannot determine enough patterns to fill a model's size, a smaller model can be created. If the training manager finds more patterns than fit within a specified size, the maximum cutoff can be enforced by trimming the patterns that have the least impact on the quality of the learned model. Choosing a model size provides control over the trade-off between the model's predictive quality and its cost of use. In at least one embodiment, a smaller model may cause the training manager to remove many patterns to fit within the maximum size limit, thus affecting the quality of predictions. In at least one embodiment, a larger model may incur more cost in querying real-time predictions. In at least one embodiment, a larger input dataset does not necessarily result in a larger model because the model stores patterns, not input data. In at least one embodiment, if the patterns are few and simple, the resulting model will be small. Input data with a large number of original attributes (input columns) or derived features (outputs of data transformations) may result in more patterns being discovered and stored during a training process.

[0095] In at least one embodiment, the training manager 704 may perform multiple passes or iterations on the training data to attempt to discover patterns. In at least one embodiment, a default number of passes may exist, such as ten passes, while in at least one embodiment, a maximum number of passes may be set, such as one hundred passes. In at least one embodiment, a maximum set may not exist, or there may be a convergence criterion or other set of factors that triggers the termination of the training process. In at least one embodiment, the training manager 704 may monitor the quality of patterns during training (e.g., for model convergence) and may automatically stop training when no more data points or patterns need to be discovered. In at least one embodiment, a dataset with only a few observations may require more data passes to achieve sufficiently high model quality. Larger datasets may contain many similar data points, which can reduce the need for a large number of passes. A potential impact of choosing to pass more data is that model training may take longer and be more costly in terms of resource and system utilization.

[0096] In at least one embodiment, training data is shuffled before training or between training deliveries. In at least one embodiment, shuffling is random or pseudo-random to generate a truly random ordering, although there may be appropriate constraints to ensure that certain types of data are not grouped, or if such grouping exists, the shuffled data can be reshuffled, etc. In at least one embodiment, shuffling changes the order or arrangement in which data is used for training, such that the training algorithm does not encounter groupings of similar types of data, or does not encounter a single type of data for too many consecutive observations. In at least one embodiment, a model can be trained to predict objects. In at least one embodiment, data can be categorized by object type before uploading. In at least one embodiment, the algorithm can then process the data alphabetically by object type, initially encountering only data of a certain object type. In at least one embodiment, the model will begin to learn patterns for objects of that type. In at least one embodiment, the model will then encounter only data of a second object type and will attempt to adjust the model to fit that object type, which may degrade the fit to the patterns of the first object type. This abrupt switching from object types can produce a model that does not need to learn how to accurately predict object types. In at least one embodiment, shuffling may be performed before the training dataset is split into training and evaluation subsets to facilitate a relatively uniform distribution of data types in both stages. In at least one embodiment, the training manager 704 may use techniques such as pseudo-random shuffling to automatically shuffle the data.

[0097] In at least one embodiment, when creating a machine learning model, the training manager 704 allows the user to specify settings or apply custom options. In at least one embodiment, the user can specify one or more evaluation settings indicating a portion of the input data to be retained for evaluating the predictive quality of the machine learning model. In at least one embodiment, the user can specify strategies for indicating which attributes and attribute transformations can be used for model training. In at least one embodiment, the user can also specify different training parameters for controlling the training process and certain characteristics of the resulting model.

[0098] In at least one embodiment, once the training manager has determined that the model training is complete, the trained model 708 can be used by the classifier 714 to classify the validation data 712 (or otherwise generate inference) by using at least one final criterion discussed herein. In at least one embodiment, this involves a logical transition between the model's training mode and its inference mode. However, in at least one embodiment, the trained model 708 will first be delivered to an evaluator 710, which may include an application, process, or service executing on at least one computing resource (e.g., the CPU or GPU of at least one server) for evaluating the quality (or another such aspect) of the trained model. In at least one embodiment, the model is evaluated to determine whether the model provides at least a minimum acceptable or threshold level of performance when predicting targets on new and future data. If not, the training manager 704 may continue training the model. In at least one embodiment, since future data instances often have unknown target values, it may be desirable to examine machine learning accuracy metrics on data with known target answers and use that evaluation as a proxy for the accuracy of predictions on future data.

[0099] In at least one embodiment, a subset of the training data 702 provided for training is used to evaluate the model. This subset can be determined using shuffling and splitting methods as discussed above. In at least one embodiment, this evaluation data subset is labeled as a target and thus can serve as a source of ground truth for evaluation. Using the same data used for training to evaluate the predictive accuracy of a machine learning model is not useful, as it might produce a positive evaluation for a model that memorizes the training data rather than generalizes from it. In at least one embodiment, once training is complete, the evaluation data subset is processed using the trained model 708, and the evaluator 710 can determine the model's accuracy by comparing the ground truth data with the model's corresponding output (or prediction / observation). In at least one embodiment, the evaluator 710 can provide an overview or performance metric indicating how well the predicted values ​​match the true values. In at least one embodiment, if the trained model does not meet at least a minimum performance criterion or other such accuracy threshold, the training manager 704 can be instructed to perform further training, or in some examples, to attempt to train a new or different model. In at least one embodiment, if the trained model 708 meets the relevant criteria, the trained model can be provided for use by the classifier 714.

[0100] In at least one embodiment, when creating and training a machine learning model, it is desirable to specify model settings or training parameters to produce a model capable of making accurate predictions. In at least one embodiment, parameters include the number of deliveries to be performed (forward and / or backward), regularization or refinement, model size, and shuffling type. In at least one embodiment, selecting model parameter settings that produce the best predictive performance on evaluation data may lead to overfitting of the model. In at least one embodiment, overfitting occurs when the model has memorized patterns occurring in the training and evaluation data sources but fails to generalize patterns in the data. Overfitting often occurs when the training data includes all the data used in the evaluation. In at least one embodiment, an overfitted model may perform well during evaluation but may not make accurate predictions on new or other validation data. In at least one embodiment, to avoid selecting an overfitted model as the best model, the training manager may retain additional data to validate the model's performance. For example, the training dataset may be divided into 60% for training and 40% for evaluation or validation, which may be divided into two or more phases. In at least one embodiment, after selecting model parameters that work well on the evaluation data, resulting in convergence on a subset of validation data, such as half of the validation data, a second validation can be performed using the remaining portion of the validation data to ensure the model's performance. If the model meets expectations on the validation data, then the model is not overfitting the data. In at least one embodiment, a test set or hold set can be used to test the parameters. In at least one embodiment, a second validation or testing step is used to help select appropriate model parameters to prevent overfitting. However, retaining more data from the training process for validation results in less data available for training. This can be problematic for smaller datasets, as there may not be enough data for training. In at least one embodiment, one approach in this case is to perform cross-validation, as described elsewhere in this document.

[0101] In at least one embodiment, numerous metrics or insights can be used to review and evaluate the predictive accuracy of a given model. In at least one embodiment, the evaluation results include a predictive accuracy metric to report the overall success of the model, and visualizations to help explore the model's accuracy beyond the predictive accuracy metric. The results may also provide the ability to review the impact of setting score thresholds, such as for binary classification, and to generate reminders of criteria to check the validity of the evaluation. The choice of metrics and visualizations may depend at least in part on the type of model being evaluated.

[0102] In at least one embodiment, once satisfactorily trained and evaluated, the trained machine learning model can be used to build or support machine learning applications. In one embodiment, building a machine learning application is an iterative process involving a sequence of steps. In at least one embodiment, a core machine learning problem can be framed based on observed things and the answer the model wants to predict. In at least one embodiment, data can then be collected, cleaned, and prepared to suit the machine learning model training algorithm for consumption. This data can be visualized and analyzed to run sanity checks to verify the quality of the data and to understand the data. It is possible that the raw data (e.g., input variables) and answer data (e.g., the target) are not represented in a way that can be used to train a highly predictive model. Therefore, it may be desirable to construct more predictive input representations or features from the raw variables. The resulting features can be fed into the learning algorithm to build a model and evaluate the quality of the model based on the data retained from the built model. The model can then be used to generate predictions of the target answer for new data instances.

[0103] In at least one embodiment, Figure 7 In the illustrated system 700, an evaluated, trained model 710 is provided to or made available to a classifier 714, which is capable of using the trained model to process validation data. In at least one embodiment, this may include, for example, data received by a user or third party that has never been classified, such as query images seeking information about what is represented in those images. In at least one embodiment, validation data may be processed by the classifier using the trained model, and the resulting outcome 716 (such as classification or prediction) may be sent back to the appropriate source or otherwise processed or stored. In at least one embodiment, where such use is permitted, these now-classified data instances may be stored in a training data repository, which may be used by a training manager to further train the trained model 708. In at least one embodiment, the model will be continuously trained as new data becomes available, but in at least one embodiment, these models will be retrained periodically, such as once a day or once a week, depending on factors such as the size of the dataset or the complexity of the model.

[0104] In at least one embodiment, the classifier 714 may include appropriate hardware and software for processing validation data 712 using a trained model. In at least one embodiment, the classifier will include one or more computer servers, each with one or more graphics processing units (GPUs) capable of processing data. In at least one embodiment, the GPUs are configured and designed to be more suitable than CPUs or other such components for processing machine learning data. In at least one embodiment, the trained model may be loaded into GPU memory, and received data instances are provided to the GPU for processing. GPUs may have a much larger number of cores than CPUs, and GPU cores may also have lower complexity. In at least one embodiment, a given GPU may be able to process thousands of data instances simultaneously through different hardware threads. In at least one embodiment, the GPU may also be configured to maximize floating-point throughput, which can provide significant additional processing advantages for large datasets.

[0105] In at least one embodiment, even when using GPUs, accelerators, and other such hardware to accelerate tasks such as training models or classifying data using such models, such tasks may still require significant time, resource allocation, and cost. In at least one embodiment, if a machine learning model is to be trained using 700 deliveries, and the dataset includes 1,000,000 data instances to be used for training, then all millions of instances need to be processed in each delivery. Different parts of the architecture can also be supported by different types of devices. In at least one embodiment, a set of servers can be used in a logically centralized location to perform training, such as if it were offered as a service, while the classification of the raw data can be performed by such a service or on client devices, among other such options. These devices can also be owned, operated, or controlled by the same entity or multiple entities.

[0106] In at least one embodiment, Figure 8The example neural network 800 shown can be trained or otherwise used in at least one embodiment. In at least one embodiment, the statistical model is an artificial neural network (ANN) comprising multiple layers of nodes, including an input layer 802, an output layer 806, and multiple layers 804 of intermediate nodes, often referred to as “hidden” layers because inner layers and nodes are typically invisible or inaccessible in a neural network. In at least one embodiment, although only a few intermediate layers are shown for illustrative purposes, it should be understood that there is no limitation on the number of intermediate layers that can be used, and any limitation on the number of layers tends to be a factor in the resources or time required to process the model. In at least one embodiment, additional types of models, networks, algorithms, or processes may also be used, and other numbers or options of nodes and layers, as well as other such options, may be included. In at least one embodiment, validation data may be processed by layers of the network to produce a set of inference or inference scores, which may then be fed to a loss function 808.

[0107] In at least one embodiment, all nodes in a given layer are interconnected to all nodes in adjacent layers. In at least one embodiment, nodes in intermediate layers are then each connected to nodes in two adjacent layers. In at least one embodiment, in some models, nodes are also referred to as neurons or connection units, and the connections between nodes are referred to as edges. Each node can perform a function on the received input, such as by using a specified function. In at least one embodiment, nodes and edges can be given different weights during training, and individual layers of nodes can perform specific types of transformations on the received input, wherein those transformations can also be learned or adjusted during training. In at least one embodiment, learning can be supervised or self-supervised learning, as can be at least in part dependent on the type of information contained in the training dataset. In at least one embodiment, different types of neural networks can be utilized, such as including convolutional neural networks (CNNs), which include multiple convolutional layers and a set of pooling layers, and have proven beneficial for applications such as image recognition. CNNs are also easier to train than other networks due to the relatively small number of parameters to be determined.

[0108] In at least one embodiment, different tuning parameters can be used to train such a complex machine learning model. Selecting parameters, fitting the model, and evaluating the model are part of the model tuning process, often referred to as hyperparameter optimization. In at least one embodiment, this tuning may involve introspection of the underlying model or data. A robust workflow is important in training or production settings to avoid overfitting of hyperparameters, as discussed elsewhere in this document. Cross-validation and adding Gaussian noise to the training dataset are techniques that can be used to avoid overfitting to either dataset. For hyperparameter optimization, it may be desirable to keep the training and validation sets fixed. In at least one embodiment, hyperparameters can be tuned in several categories, such as including data preprocessing (e.g., converting words into vectors), CNN architecture definitions (e.g., filter size, number of filters), stochastic gradient descent (SGD) parameters (e.g., learning rate), and regularization or refinement (e.g., exit probability), among other such options.

[0109] In at least one embodiment, instances of the dataset can be embedded into a lower-dimensional space of a specific size during preprocessing. In at least one embodiment, the size of this space is a parameter to be tuned. In at least one embodiment, the CNN architecture incorporates many tunable parameters. The parameter of the filter size can represent the interpretation of information corresponding to the size of the instances to be analyzed. In computational linguistics, this is called the n-gram size. The example CNN uses three different filter sizes, which represent potentially different n-gram sizes. Several filters of each filter size can correspond to the depth of a filter. Each filter attempts to learn something different from the structure of the instances, such as the sentence structure used for text data. In the convolutional layer, the activation function can be a rectified linear unit, and the pooling type is set to max pooling. The results can then be concatenated into a single-dimensional vector, and the last layer is fully connected to the two-dimensional output. This corresponds to binary classification to which the optimization function can be applied. One such function is an implementation of the root mean square (RMS) propagation method of gradient descent, where example hyperparameters can include learning rate, batch size, maximum gradient normal, and epoch. With neural networks, regularization can be an extremely important consideration. In at least one embodiment, the input data can be relatively sparse. In this case, the primary hyperparameter could be dropout at the penultimate layer, representing the proportion of nodes that will not be "triggered" in each training epoch. An example training process can suggest different hyperparameter configurations based on performance feedback from previously configured settings. The model can then be trained with the proposed configurations, evaluated on a specified validation set, and its performance reported. This process can be repeated, for example, by balancing exploration (learning more about different configurations) and development (leveraging prior knowledge to achieve better results).

[0110] Because CNN training can be parallelized and can leverage GPU-enabled computational resources, multiple optimization strategies can be tried for different scenarios. Complex scenarios allow for tuning of the model architecture, as well as preprocessing and stochastic gradient descent parameters. This expands the model configuration space. In basic scenarios, only preprocessing and stochastic gradient descent parameters are tuned. In complex scenarios, there can be a much larger number of configuration parameters than in basic scenarios. Tuning in the joint space can be performed using linear or exponential steps, iterating the model through optimization loops. The cost of this tuning process can be significantly lower than tuning processes such as random search and grid search, without any significant performance loss.

[0111] In at least one embodiment, backpropagation can be used to compute gradients for determining the weights of the neural network. Backpropagation is a form of differentiation and can be used by gradient descent optimization algorithms to adjust the weights applied to individual nodes or neurons, as described above. The gradients of the relevant loss function can be used to determine the weights. Backpropagation can utilize the derivative of the loss function with respect to the output produced by the statistical model. As previously mentioned, each node can have an associated activation function to define the output of the respective node. Various activation functions can be appropriately used, such as radial basis functions (RBF) and sigmoid functions, which can be used by various support vector machines (SVMs) to transform the data. The activation functions of the intermediate layers of a node are referred to herein as the internal product kernel. These functions can include, for example, identity functions, step functions, sigmoid functions, ramp functions, etc. Among other such options, the activation functions can also be linear or non-linear.

[0112] In at least one embodiment, a training dataset is used to train an untrained neural network. In at least one embodiment, the training framework is a PyTorch framework, Tensorflow, Boost, Caffe, Microsoft CognitiveToolkit / CNTK, MXNet, Chainer, Keras, Deechiming4j, or other training framework. In at least one embodiment, the training framework trains the untrained neural network and enables it to be trained using the processing resources described herein to generate a trained neural network. In at least one embodiment, weights may be selected randomly or by using pre-training of a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or self-supervised manner.

[0113] In at least one embodiment, supervised learning is used to train an untrained neural network, wherein the training dataset comprises inputs paired with desired outputs of the inputs, or wherein the training dataset comprises inputs with known outputs, and the outputs of the neural network are manually rated. In at least one embodiment, the untrained neural network is trained in a supervised manner, processing inputs from the training dataset and comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network. In at least one embodiment, the training framework adjusts the weights controlling the untrained neural network. In at least one embodiment, the training framework includes tools for monitoring how well the untrained neural network converges to a model, such as a trained neural network, which is adapted to generate correct answers, such as results, based on known input data (e.g., new data). In at least one embodiment, the training framework repeatedly trains the untrained neural network while using a loss function and tuning algorithms, such as stochastic gradient descent, to refine the outputs of the untrained neural network. In at least one embodiment, the training framework trains the untrained neural network until the untrained neural network reaches the desired accuracy. In at least one embodiment, the trained neural network can then be deployed to implement any number of machine learning operations.

[0114] In at least one embodiment, self-supervised learning is used to train an untrained neural network, wherein the untrained neural network attempts to train itself using unlabeled data. In at least one embodiment, the self-supervised learning training dataset will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network can learn groupings within the training dataset and can determine relationships between individual inputs and the untrained dataset. In at least one embodiment, self-supervised training can be used to generate self-organizing maps, which are trained neural networks capable of performing operations useful for dimensionality reduction on new data. In at least one embodiment, self-supervised training can also be used to perform anomaly detection, which allows the identification of data points in a new dataset that deviate from the normal patterns of the new dataset.

[0115] In at least one embodiment, semi-supervised learning can be used, which is a technique that includes a mixture of labeled and unlabeled data in the training dataset. In at least one embodiment, the training framework can be used to perform incremental learning, such as learning techniques via transfer. In at least one embodiment, incremental learning enables the trained neural network to adapt to new data without forgetting the knowledge instilled in the network during initial training.

[0116] Reasoning and training logic

[0117] Figure 9AInference and / or training logic 915 is shown for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Provide details about reasoning and / or training logic 915.

[0118] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, a code and / or data storage device 901, which is used to forward store and / or output weights and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inference in multiple aspects of one or more embodiments. In at least one embodiment, the training logic 915 may include or be coupled to the code and / or data storage device 901, which is used to store graphical code or other software for controlling timing and / or sequence, wherein weight and / or other parameter information is loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as Arithmetic Logic Units (ALUs)). In at least one embodiment, based on the architecture of the neural network corresponding to this code, the code, such as graphical code, loads weight or other parameter information into the processor ALU. In at least one embodiment, the code and / or data memory 901 stores the weight parameters and / or input / output data of each layer of a neural network trained or used with one or more embodiments during training and / or inference, during the forward propagation of input / output data and / or weight parameters, using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage device 901 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0119] In at least one embodiment, any portion of the code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, whether the code and / or data storage 901 is internal or external to the processor, for example, or constitutes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip and off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0120] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, code and / or data memory 905 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more aspects of the embodiments. In at least one embodiment, during training and / or inference using one or more aspects of the embodiments, during backpropagation of input / output data and / or weight parameters, the code and / or data memory 905 stores weight parameters and / or input / output data for each layer of the neural network trained or used with one or more embodiments. In at least one embodiment, the training logic 915 may include or be coupled to the code and / or data memory 905 for storing graphical code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, an arithmetic logic unit (ALU)). In at least one embodiment, code, such as graphical code, loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 905 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 905 may be on or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, the choice between the code and / or data storage 905 being internal to the processor, for example, consisting of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip and off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0121] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially identical and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0122] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910, including integer and / or floating-point units, performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, in response to execution instructions or other code, activations stored in activation storage 920 are generated according to linear algebraic and / or matrix-based mathematical operations performed by one or more ALUs 910, wherein weight values ​​stored in code and / or data storage 905 and / or code and / or data storage 901 are used together with other values, such as bias values, gradient information, momentum values ​​or other parameters or hyperparameters, as operands, any or all of which may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip memory.

[0123] In at least one embodiment, one or more ALUs 910 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processor or other hardware logic devices or circuits using them (e.g., coprocessors). In at least one embodiment, ALUs 910 may be included within the execution unit of the processor or otherwise included within an ALU bank accessible by the execution unit of the processor, or located within the same processor or distributed among different types of processors (e.g., central processing unit, graphics processing unit, fixed-function unit, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be extracted and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0124] In at least one embodiment, the active memory 920 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage device. In at least one embodiment, the active memory 920 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the selection of whether the active memory 920 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip and off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors. In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU) or from Intel (e.g., a "LakeCrest" processor). In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”)

[0125] Figure 9B An inference and / or training logic 915 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise exclusively used in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 9B The inference and / or training logic 915 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU) or from Intel (For example, a "Lake Crest" processor. In at least one embodiment, Figure 9BThe inference and / or training logic 915 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field-programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graphical code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown, each of code and / or data storage 901 and code and / or data storage 905 is associated with dedicated computing resources, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, each of computing hardware 902 and computing hardware 906 includes one or more ALUs that perform mathematical functions, such as linear algebra functions, on the information stored in code and / or data storage 901 and code and / or data storage 905, and the results of the mathematical functions are stored in activation memory 920.

[0126] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of the neural network, such that activations generated from a “store / compute pair 901 / 902” of the code and / or data storage 901 and computing hardware 902 are provided as inputs to a “store / compute pair 905 / 906” of the code and / or data storage 905 and computing hardware 906 to reflect the conceptual organization of the neural network. In at least one embodiment, each of the store / compute pairs 901 / 902 and 905 / 906 may correspond to more than one neural network layer. In at least one embodiment, additional store / compute pairs (not shown) following or paralleling the store / compute pairs 901 / 902 and 905 / 906 may be included in the inference and / or training logic 915.

[0127] Data Center

[0128] Figure 10 An example data center 1000 that can be used in at least one embodiment is shown. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0129] In at least one embodiment, such as Figure 10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, packet computing resources 1014, and node computing resources (“nodes CR”) 1016(1)-1016(N), where “N” represents any positive integer. In at least one embodiment, nodes CR 1016(1)-1016(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NWI / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1016(1)-1016(N) may be servers having one or more of the aforementioned computing resources.

[0130] In at least one embodiment, the grouped computing resource 1014 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographical locations. The individual groups of node CRs within the grouped computing resource 1014 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0131] In at least one embodiment, resource coordinator 1012 may be configured or otherwise control one or more nodes CR1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may include a Software Design Infrastructure (“SDI”) management entity for data center 1000. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0132] In at least one embodiment, such as Figure 10As shown, framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, framework layer 1020 may include a framework of software 1032 supporting software layer 1030 and / or one or more applications 1042 supporting application layer 1040. In at least one embodiment, software 1032 or application 1042 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1028 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1032 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be able to configure different layers, such as the software layer 1030 and the framework layer 1020, which includes Spark and a distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the cluster or group computing resources may include group computing resources 1014 on the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0133] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least a portion of the nodes CR1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0134] In at least one embodiment, the application layer 1040 may include one or more applications 1042 that can be used by at least a portion of nodes CR1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0135] In at least one embodiment, any of the configuration manager 1024, resource manager 1026, and resource coordinator 1012 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1000 and can prevent underutilization and / or poor performance of the data center.

[0136] In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1000, by using weight parameters calculated through one or more training techniques described herein.

[0137] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0138] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 10 Used in this context for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0139] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0140] Computer System

[0141] Figure 11 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1100 may include, but is not limited to, components such as processor 1102, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1100 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0142] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0143] In at least one embodiment, computer system 1100 may include, but is not limited to, processor 1102, which may include, but is not limited to, one or more execution units 1108, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to processor bus 1110, which can transmit data signals between processor 1102 and other components in computer system 1100.

[0144] In at least one embodiment, processor 1102 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0145] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1102. In at least one embodiment, the processor 1102 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of the general-purpose processor 1102, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1102 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0146] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that can be executed by processor 1102.

[0147] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may initiate data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0148] In at least one embodiment, computer system 1100 may use system I / O 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, audio controller 1129, firmware hub (“Flash BIOS”) 1128, wireless transceiver 1126, data storage 1124, a conventional I / O controller 1123 including user input and keyboard interfaces, serial expansion port 1127 (e.g., Universal Serial Bus (USB)), and network controller 1134. Data storage 1124 may include hard disk drives, floppy disk drives, CD-ROM devices, flash memory devices, or other mass storage devices.

[0149] In at least one embodiment, Figure 11 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 11An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, the device may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1100 are interconnected using a compute fast link (CXL) interconnect.

[0150] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can... Figure 11 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0151] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0152] Figure 12 This is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0153] In at least one embodiment, system 1200 may include, but is not limited to, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 uses a bus or interface coupling, such as an I2C bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high-definition audio (“HDA”) bus, a serial advanced technology accessory (“SATA”) bus, a universal serial bus (“USB”) (versions 1, 2, and 3), or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 12 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 12 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 12 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0154] In at least one embodiment, Figure 12 It may include a display 1224, a touch screen 1225, a touchpad 1230, a near field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) 1255, a camera (“USB 3.0 camera”) 1254 (e.g., a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0155] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1246, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1264 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 can be implemented as next-generation form factor (NGFF).

[0156] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 12 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0157] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0158] Figure 13 A computer system 1300 according to at least one embodiment is shown. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described throughout this disclosure.

[0159] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Device Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1304 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1322 provides an interface to other computing devices and networks for receiving data from the computer system 1300 and transferring data to other systems.

[0160] In at least one embodiment, the computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the above modules may reside on a single semiconductor platform to form the processing system.

[0161] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 13 It is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0162] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0163] Figure 14 A computer system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1400 includes, but is not limited to, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0164] In at least one embodiment, the USB flash drive 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing core 1430 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1430 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1430 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0165] In at least one embodiment, the USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic enabling the processing unit 1430 to connect to a device (e.g., computer 1410) via the USB connector 1440.

[0166] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 14 In use, at least in part, the operation is based on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein to infer or predict operations.

[0167] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0168] Figure 15A An exemplary architecture is illustrated, in which multiple GPUs 1510-1513 are communicatively coupled to multiple multi-core processors 1505-1506 via high-speed links 1540-1543 (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1540-1543 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0169] Furthermore, in one embodiment, two or more GPUs 1510-1513 are interconnected via high-speed links 1529-1530, which may use the same or different protocols / links as those used for high-speed links 1540-1543. Similarly, two or more multi-core processors 1505-1506 may be connected via high-speed link 1528, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) may be used. Figure 15A This shows all communication between the various system components.

[0170] In one embodiment, each multi-core processor 1505-1506 is communicatively coupled to processor memories 1501-1502 via memory interconnects 1526-1527, and each GPU 1510-1513 is communicatively coupled to GPU memories 1520-1523 via GPU memory interconnects 1550-1553. Memory interconnects 1526-1527 and 1550-1553 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1501-1502 and GPU memories 1520-1523 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3DXPoint or Nano-RAM. In one embodiment, some portions of the processor memories 1501-1502 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0171] As described below, although the various processors 1505-1506 and GPUs 1510-1513 can be physically coupled to specific memories 1501-1502 and 1520-1523 respectively, a unified memory architecture can be implemented, in which the virtual system address space (also known as the "effective address" space) is distributed among the various physical memories. For example, processor memories 1501-1502 can each include 64GB of system memory address space, and GPU memories 1520-1523 can each include 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0172] Figure 15B Additional details are shown regarding the interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 according to an exemplary embodiment. The graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed link 1540. Alternatively, the graphics acceleration module 1546 may be integrated on the same package or chip as the processor 1507.

[0173] In at least one embodiment, the processor 1507 shown includes multiple cores 1560A-1560D, each core having a translation back buffer 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components (not shown) for executing instructions and processing data. Caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by the respective groups of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. Processor 1507 and graphics acceleration module 1546 are connected to system memory 1514, which may include Figure 15A The processor memory 1501-1502 in the memory.

[0174] Consistency of data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 is maintained via inter-core communication through the consistency bus 1564. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1564 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 1564 to snoop on cache accesses.

[0175] In one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. Specifically, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540 (e.g., PCIe bus, NVlink, etc.), and interface 1537 connects graphics acceleration module 1546 to link 1540.

[0176] In one implementation, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 1531, 1532, and N of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1531, 1532, and N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1531, 1532, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531-1532, and N, or the graphics processing engines 1531-1532, and N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0177] In one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. MMU 1539 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1538 stores commands and data for effective access by graphics processing engines 1531-1532, N. In one embodiment, data stored in cache 1538 and graphics memories 1533-1534, M is kept consistent with core caches 1562A-1562D, 1556 and system memory 1514. As described above, this task can be accomplished via proxy circuitry 1525 representing cache 1538 and graphics memory 1533-1534, M (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0178] A set of registers 1545 stores the context data of the threads executed by graphics processing engines 1531-1532, N, and context management circuitry 1548 manages the thread context. For example, context management circuitry 1548 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1548 can store the current register value into a designated area in memory (e.g., identified by the context pointer). The register value can then be restored when returning to the context. In one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0179] In one implementation, MMU 1539 translates virtual / effective addresses from graphics processing engine 1531 into real / physical addresses in system memory 1514. One embodiment of accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. Graphics accelerator module 1546 may be dedicated to a single application executing on processor 1507, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, wherein the resources of graphics processing engines 1531-1532, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0180] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system of the graphics acceleration module 1546, providing address translation and system memory caching services. Additionally, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1531-1532, N.

[0181] Because the hardware resources of graphics processing engines 1531-1532, N are explicitly mapped to the actual address space seen by the host processor 1507, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1536 is to physically separate the graphics processing engines 1531-1532, N, so that they appear as independent units to the system.

[0182] In at least one embodiment, one or more graphics memories 1533-1534, M are coupled to each graphics processing engine 1531-1532, N, respectively. Graphics memories 1533-1534, M store instructions and data, which are processed by each graphics processing engine 1531-1532, N. Graphics memories 1533-1534, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0183] In one embodiment, to reduce data traffic on link 1540, a biasing technique is used to ensure that the data stored in graphics memories 1533-1534, M is the data most frequently used by graphics processing engines 1531-1532, N, and preferably not used (or at least infrequently used) by cores 1560A-1560D. Similarly, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1531-1532, N) in the core caches 1562A-1562D, 1556 and system memory 1514.

[0184] Figure 15C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1536 is integrated within the processor 1507. In at least this embodiment, the graphics processing engines 1531-1532, N communicate directly with the accelerator integrated circuit 1536 via a high-speed link 1540 through interfaces 1537 and 1535 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 1536 can perform operations related to... Figure 15B The operations described are the same. However, due to its close proximity to the coherence bus 1564 and caches 1562A-1562D, 1556, it may have higher throughput. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1536 and a programming model controlled by graphics acceleration module 1546.

[0185] In at least one embodiment, graphics processing engines 1531-1532, N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1531-1532, N, thereby providing virtualization within a VM / partition.

[0186] In at least one embodiment, graphics processing engines 1531-1532, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1531-1532, N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1531-1532, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1531-1532, N to provide access to each process or application.

[0187] In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engines 1531-1532, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1531-1532, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0188] Figure 15D An exemplary accelerator integration slice 1590 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1536. The application is an effective address space 1582 in system memory 1514, which stores process element 1583. In one embodiment, process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. Process element 1583 contains the process state of the corresponding application 1580. A job descriptor (WD) 1584 contained in process element 1583 may be a single job requested by the application, or it may contain pointers to job queues. In at least one embodiment, WD 1584 is a pointer to a job request queue in the application's address space 1582.

[0189] The graphics acceleration module 1546 and / or the various graphics processing engines 1531-1532, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1584 to the graphics acceleration module 1546 to begin operations in a virtualized environment.

[0190] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 1546 or an individual graphics processing engine 1531. Because the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0191] In operation, the WD fetch unit 1591 in the accelerator integrated slice 1590 fetches the next WD 1584, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. Data from the WD 1584 can be stored in register 1545 and used by the MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of the MMU 1539 includes segment / page roaming circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. The interrupt management circuitry 1547 can handle interrupt events 1592 received from the graphics acceleration module 1546. When performing graphics operations, the effective address 1593 generated by the graphics processing engines 1531-1532, N is translated into a real address by the MMU 1539.

[0192] In one embodiment, register 1545 is copied for each graphics processing engine 1531-1532, N, and / or graphics acceleration module 1546, and the same group of registers 1545 can be initialized by a hypervisor or the operating system. Each of these copied registers can be included in the accelerator integration slice 1590. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0193] Table 1 – Registers for Supervisor Initialization

[0194]

[0195] Table 2 shows exemplary registers that can be initialized by the operating system.

[0196] Table 2 – Operating System Initialization Registers

[0197] 1 Process and thread identification 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) memory segment table pointer 5 Access Control 6 Job descriptor

[0198] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531-1532, N. It contains all the information required for the graphics processing engine 1531-1532, N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0199] Figure 15E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598, in which a list of process elements 1599 is stored. The hypervisor real address space 1598 can be accessed via a hypervisor 1596, which virtualizes the graphics acceleration module engine for operating system 1595.

[0200] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. Two programming models exist, in which the graphics acceleration module 1546 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0201] In this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. For the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 may adhere to the following provisions: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1546 must provide context saving and restoration mechanisms; 2) The graphics acceleration module 1546 guarantees that application job requests are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1546 provides the ability to preempt job processing; 3) When operating in a directed shared programming model, fairness among the processes of the graphics acceleration module 1546 must be ensured.

[0202] In at least one embodiment, application 1580 needs to make a system call to operating system 1595 using graphics acceleration module 1546 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1546 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1546 and can take the form of graphics acceleration module 1546 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1546. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. If the implementation of accelerator integrated circuit 1536 and graphics acceleration module 1546 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1596 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1583. In at least one embodiment, CSRP is one of registers 1545 containing the effective address of a region in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0203] Upon receiving a system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 uses the information shown in Table 3 to invoke the hypervisor 1596.

[0204] Table 3 – Operating System to Hypervisor Call Parameters

[0205] 1 Working Descriptor (WD) 2 Access Control Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Log Pointer (AURP) 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0206] Upon receiving a hypervisor call, hypervisor 1596 verifies that operating system 1595 has been registered and granted permission to use graphics acceleration module 1546. Then, hypervisor 1596 adds process element 1583 to the linked list of process elements of the corresponding graphics acceleration module 1546 type. The process element may include the information shown in Table 4.

[0207] Table 4 – Process Element Information

[0208]

[0209]

[0210] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1590 registers 1545.

[0211] like Figure 15F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1501-1502 and GPU memories 1520-1523. In this implementation, operations performed on GPUs 1510-1513 utilize the same virtual / effective memory address space to access processor memories 1501-1502 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501, a second portion to second processor memory 1502, a third portion to GPU memory 1520, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1501-1502 and GPU memories 1520-1523, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0212] In one embodiment, the bias / coherence management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherence between the caches of one or more host processors (e.g., 1505) and the GPUs 1510-1513, and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. While in Figure 15F Several instances of bias / coherence management circuitry 1594A-1594E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1505 and / or within the accelerator integrated circuit 1536.

[0213] One embodiment allows GPU-attached memories 1520-1523 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memories 1520-1523 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1505 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memories 1520-1523 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1510. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0214] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (i.e., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1510-1513, the bias table can be implemented across one or more stolen memory ranges of GPU-attached memory 1520-1523. Alternatively, the entire bias table can be maintained within the GPU.

[0215] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1520-1523 is performed, resulting in the following operations: First, a local request from GPUs 1510-1513 to locate its page in the GPU bias is directly forwarded to the corresponding GPU memory 1520-1523. A local request from the GPU to locate its page in the host bias is forwarded to processor 1505 (e.g., via the high-speed link described above). In one embodiment, a request from processor 1505 to locate the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1510-1513. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, in limited cases, purely hardware-based mechanisms.

[0216] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrations from the host processor 1505 bias to the GPU bias, but not for the reverse migration.

[0217] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1505 cannot cache. To access these pages, the processor 1505 may request access from the GPU 1510, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that the GPU bias pages are those required by the GPU, not those required by the host processor 1505, and vice versa.

[0218] The inference and / or training logic 915 is used to execute one or more implementations. The following is in conjunction with... Figure 9A and / or Figure 9B Provide details about reasoning and / or training logic 915.

[0219] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0220] Figure 16 Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0221] Figure 16 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPU), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic, which includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I... 2 S / I 2 C controller 1640. In at least one embodiment, integrated circuit 1600 may include display device 1645 coupled to one or more of high-definition multimedia interface (HDMI) controller 1650 and mobile industrial processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by flash memory subsystem 1660, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1670.

[0222] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in integrated circuit 1600 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0223] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0224] Figures 17A-17BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0225] Figures 17A-17B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 17B Further exemplary graphics processor 1740 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 17A The graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 may be... Figure 16 A variant of the 1610 graphics processor.

[0226] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0227] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mappings for the graphics processor 1710, including for vertex processors 1705 and / or fragment processors 1715A-1715N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B can be synchronized with other MMUs within the system, including with... Figure 16 One or more application processors 1605, graphics processors 1615, and / or video processors 1620 are associated with one or more MMUs, enabling each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0228] In at least one embodiment, the graphics processor 1740 includes Figure 17A The graphics processor 1710 includes one or more MMUs 1720A-1720B, one or more caches 1725A-1725B, and one or more interconnects 1730A-1730B. In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N-1 and 1755N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1755A-1755N and a tile unit 1758 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0229] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 may be integrated into an integrated circuit. Figure 17A and / or Figure 17B The above is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0230] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0231] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 18A It shows that it can be included in Figure 16 The graphics core 1800 within the graphics processor 1610, and in at least one embodiment, may be as follows: Figure 17B The unified shader cores shown are 1755A-1755N. Figure 18B A highly parallel general-purpose graphics processing unit 1830 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0232] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1817, which are common to the execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1800. Slices 1801A-1801N may include supporting logic, including local instruction caches 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFU1812A-1812N), floating-point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double-precision floating-point units (DPFPU 1815A-1815N), and matrix processing units (MPU1817A-1817N).

[0233] In at least one embodiment, the FPU 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1815A-1815N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1812A-1812N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0234] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the graphics core 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0235] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0236] Figure 18BA general-purpose processing unit (GPGPU) 1830 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 to allocate execution threads associated with those commands to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 can be used as a higher-level cache within the cache memory of computing clusters 1836A-1836H.

[0237] In at least one embodiment, the GPGPU 1830 includes memories 1844A-1844B, which are coupled to the computing cluster 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memories 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0238] In at least one embodiment, each of the computing clusters 1836A-1836H includes a set of graphics cores, for example... Figure 18A The graphics core 1800 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0239] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 1836A-1836H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840, enabling direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1830 reside in a separate data processing system and communicate via network devices accessible through the host interface 1832. In at least one embodiment, GPU link 1840 may be configured to enable connection to a host processor other than or as a replacement for host interface 1832.

[0240] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, where the GPGPU 1830 is used for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H compared to when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0241] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in the GPGPU 1830 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0242] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0243] Figure 19 A block diagram of a computer system 1900 according to at least one embodiment is shown. In at least one embodiment, the computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset assembly or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that enables the computer system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 enables a display controller to provide output to one or more display devices 1910A, the display controller being included in one or more processors 1902. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0244] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to a memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1912 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1912 form a graphics processing subsystem that can output pixels to one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, the one or more parallel processors 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B.

[0245] In at least one embodiment, system storage unit 1914 may be connected to I / O hub 1907 to provide a storage mechanism for computer system 1900. In at least one embodiment, I / O switch 1916 may be used to provide an interface mechanism to enable connectivity between I / O hub 1907 and other components, such as network adapter 1918 and / or wireless network adapter 1919 which may be integrated into the platform, and various other devices that can be added via one or more attachment devices 1920. In at least one embodiment, network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0246] In at least one embodiment, the computer system 1900 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1907. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 19 The communication paths of various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0247] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, memory hub 1905, processor 1902, and I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1900 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0248] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can... Figure 19 The system 1900 is used for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0249] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0250] processor

[0251] Figure 20A A parallel processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is according to an exemplary embodiment. Figure 19 The variant of the 1912, which includes one or more parallel processors, is shown.

[0252] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices using a hub or switch interface (e.g., a memory hub 1905). In at least one embodiment, the connection between the memory hub 1905 and the I / O unit 2004 forms a communication link 1913. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0253] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to assign commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is correctly configured and in an active state before assigning tasks to processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2012. In at least one embodiment, host software can demonstrate workloads for scheduling on processing array 2012 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0254] In at least one embodiment, the processing cluster array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A-2014N of the processing cluster array 2012, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of the processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0255] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0256] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0257] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0258] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0259] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing cluster array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0260] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0261] In at least one embodiment, any of clusters 2014A-2014N of the processing cluster array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, and clusters 2014A-2014N can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to a memory interface 2018 for communication with I / O unit 2004, and a connection to a local instance of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0262] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0263] Figure 20B This is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is... Figure 20AThis is an example of one of the partitioning units 2020A-2020N. In at least one embodiment, the partitioning unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a raster operation unit (“ROP”) 2026. The L2 cache 2021 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2025. In at least one embodiment, the frame buffer interface 2025 communicates with memory cells in the parallel processor memory (such as…). Figure 20A The memory cells 2024A-2024N (e.g., within the parallel processor memory 2022) interact with one of them.

[0264] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. The compression logic performed by ROP 2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0265] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A Clusters 2014A-2014N are used instead of partition units 2020. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2016 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 22 Displayed by one or more display devices 2210, routed by processor 2202 for further processing, or by... Figure 20A One of the processing entities within the parallel processor 2000 is routed for further processing.

[0266] Figure 20C This is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 20AAn instance of one of the processing clusters 2014A-2014N. In at least one embodiment, one or more processing clusters 2014 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0267] In at least one embodiment, the operation of the processing cluster 2014 can be controlled by a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20A The scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2014 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2014 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossover switch 2040 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2040.

[0268] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0269] In at least one embodiment, instructions transmitted to the processing cluster 2014 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2034.

[0270] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use a cache memory within the processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20A The L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0271] In at least one embodiment, each processing cluster 2014 may include a memory management unit (“MMU”) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20AThe memory interface 2018 is located within the MMU 2045. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation lookup buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034, the L1 cache, or the processing cluster 2014. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0272] In at least one embodiment, the processing cluster 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs a processed task to a data crossbar switch 2040 to provide the processed task to another processing cluster 2014 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2016. In at least one embodiment, a PROP 2042 (raster pre-operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which can be coupled with a partitioning unit as described herein (e.g., Figure 20A The partition units 2020A-2020N are located together. In at least one embodiment, the PROP 2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0273] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in a graphics processing cluster 2014 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0274] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0275] Figure 20D A graphics multiprocessor 2034 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2034 is coupled to a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066. The one or more GPGPU cores 2062 and one or more load / store units 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068.

[0276] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched to instruction unit 2054 for execution. In one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2066.

[0277] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2034 (e.g., GPGPU core 2062, load / store unit 2066). In at least one embodiment, register file 2058 is partitioned among each functional unit, such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is partitioned among different thread bundles being executed by graphics multiprocessor 2034.

[0278] In at least one embodiment, each of the GPGPU cores 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be architecturally similar or may differ in architecture. A first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0279] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0280] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a cross-switch interconnect that allows the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2072, the thread executing on GPGPU core 2062 can also programmatically store data in shared memory.

[0281] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0282] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in a graphics multiprocessor 2034 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0283] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0284] Figure 21 A multi-GPU computing system 11100 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 11100 may include a processor 11102 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 11106A-D via a host interface switch 11104. In at least one embodiment, the host interface switch 11104 is a PCI Express switch device that couples the processor 11102 to a PCI Express bus, through which the processor 11102 can communicate with the GPGPUs 11106A-D. The GPGPUs 11106A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 11116. In at least one embodiment, the GPU-to-GPU links 11116 are connected to each of the GPGPUs 11106A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 11116 enable direct communication between each of the GPGPUs 11106A-D without communication via the host interface bus 11104 to which the processor 11102 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 11116, the host interface bus 11104 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 11100 via one or more network devices. While in at least one embodiment, the GPGPUs 11106A-D are connected to the processor 11102 via the host interface switch 11104, in at least one embodiment, the processor 11102 includes direct support for the P2P GPU link 11116 and can be directly connected to the GPGPUs 11106A-D.

[0285] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in a multi-GPU computing system 11100 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0286] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0287] Figure 22 This is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated within a multi-core processing system.

[0288] In at least one embodiment, graphics processor 2200 receives multiple batches of commands via ring interconnect 2202. In at least one embodiment, the input commands are interpreted by command streamer 2203 in pipeline front-end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, command streamer 2203 provides commands to geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, command streamer 2203 provides commands to video front-end 2234, which is coupled to media engine 2237. In at least one embodiment, media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2233 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate an execution thread for the thread execution resources provided by at least one graphics core 2280A.

[0289] In at least one embodiment, the graphics processor 2200 includes scalable thread execution resources featuring modular cores 2280A-2280N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2200 may have any number of graphics cores 2280A-2280N. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, the graphics processor 2200 is a low-power processor with a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A-2280N, each graphics core including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0290] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0291] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0292] Figure 23This is a block diagram illustrating a microarchitecture for a processor 2300 according to at least one embodiment, the processor 2300 including logic circuitry for executing instructions. In at least one embodiment, the processor 2300 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2300 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled MMX technology microprocessors. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2300 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0293] In at least one embodiment, processor 2300 includes an ordered front end (“front end”) 2301 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2301 may include several units. In at least one embodiment, instruction prefetcher 2323 fetches instructions from memory and provides the instructions to instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2328 decodes the received instructions into one or more machine-executable so-called “microinstructions” or “microoperations” (also referred to as “microoperations” or “microinstructions”). In at least one embodiment, instruction decoder 2328 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2330 may assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2334 for execution. In at least one embodiment, when the trace cache 2330 encounters complex instructions, the microcode ROM 2332 provides the microinstructions required to complete the operation.

[0294] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2332. In at least one embodiment, the trace cache 2330 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2332 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 has completed the micro-operation ordering of the instructions, the machine front end 2301 may resume fetching micro-operations from the trace cache 2330.

[0295] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2303 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2303 includes, but is not limited to, an allocator / register renamer 2340, a memory microinstruction queue 2342, an integer / floating-point microinstruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2304, and a simple floating-point scheduler (“simple FP scheduler”) 2306. In at least one embodiment, the fast scheduler 2302, the slow / general-purpose floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to as “microinstruction schedulers 2302, 2304, 2306”. In at least one embodiment, the allocator / register renamer 2340 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2340 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2340 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2342 for memory operations and an integer / floating-point microinstruction queue 2344 for non-memory operations, preceding the memory scheduler 2346 and microinstruction schedulers 2302, 2304, and 2306. In at least one embodiment, the microinstruction schedulers 2302, 2304, and 2306 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2302 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2304 and the simple floating-point scheduler 2306 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2302, 2304, and 2306 arbitrate the scheduling port to schedule microinstructions for execution.

[0296] In at least one embodiment, execution block 2311 includes, but is not limited to, integer register file / tribute network 2308, floating-point register file / tribute network (“FP register file / tribute network”) 2310, address generation units (“AGU”) 2312 and 2314, fast arithmetic logic units (“fast ALU”) 2316 and 2318, slow arithmetic logic unit (“slow ALU”) 2320, floating-point ALU (“FP”) 2322, and floating-point move unit (“FP move”) 2324. In at least one embodiment, integer register file / tribute network 2308 and floating-point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310”. In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating-point ALU 2322, and floating-point movement unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324". In at least one embodiment, execution block 2311 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0297] In at least one embodiment, register files 2308 and 2310 may be arranged between microinstruction schedulers 2302, 2304, and 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / tribute network 2308 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2310 performs floating-point operations. In at least one embodiment, each of register files 2308 and 2310 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2308 and 2310 can communicate data with each other. In at least one embodiment, integer register file / tribute network 2308 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2310 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0298] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324 can execute instructions. In at least one embodiment, register files 2308 and 2310 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2300 can be, but is not limited to, any number of execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324, and combinations thereof. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2322 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2316 and 2318. In at least one embodiment, fast ALUs 2316 and 2318 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2320, because slow ALU 2320 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by ALUs 2312 and 2314. In at least one embodiment, fast ALUs 2316, 2318, and slow ALU 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALUs 2316, 2318, and slow ALU 2320 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2322 and the floating-point movement unit 2324 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2322 and the floating-point movement unit 2324 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0299] In at least one embodiment, microinstruction schedulers 2302, 2304, and 2306 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2300, processor 2300 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0300] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0301] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into execution block 2311 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2311. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2311 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0302] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0303] Figure 24 A deep learning application processor 2400 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2400 uses instructions, which, if executed by the deep learning application processor 2400, cause the deep learning application processor 2400 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2400 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2400 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2400 includes, but is not limited to, processing clusters 2410(1)-2410(12), inter-chip links (“ICL”) 2420(1)-2420(12), inter-chip controllers (“ICC”) 2430(1)-2430(2), memory controllers (“MemCtrlr”) 2442(1)-2442(4), high-bandwidth memory physical layers (“HBM PHY”) 2444(1)-2444(4), management controller central processing unit (“management controller CPU”) 2450, serial peripheral interface, internal integrated circuits and general-purpose input / output blocks (“SPI, I2C, GPIO”), peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2470, and sixteen-channel peripheral component interconnect fast port (“PCI Express x 16”) 2480.

[0304] In at least one embodiment, processing cluster 2410 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2400 can include any number and type of processing cluster 2400. In at least one embodiment, the inter-chip link 2420 is bidirectional. In at least one embodiment, the inter-chip link 2420 and the inter-chip controller 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2400 can include any number (including zero) and type of ICL 2420 and ICC 2430.

[0305] In at least one embodiment, the HBM2 2440 provides a total of 32GB of memory. The HBM2 2440(i) is associated with both the memory controller 2442(i) and the HBM PHY 2444(i). In at least one embodiment, any number of HBM2 2440s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2442 and HBM PHY 2444. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO3360, PCIe controller 2460, and DMA2470 and / or PCIe2480 to implement any number and type of communication standards in any technically feasible manner.

[0306] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor 2400 is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2400. In at least one embodiment, the deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2400. In at least one embodiment, the processor 2400 may be used to perform one or more neural network use cases described herein.

[0307] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0308] Figure 25 This is a block diagram of a neuromorphic processor 2500 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2500 may receive one or more inputs from a source external to the neuromorphic processor 2500. In at least one embodiment, these inputs may be transmitted to one or more neurons 2502 within the neuromorphic processor 2500. In at least one embodiment, the neurons 2502 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, thousands upon thousands of instances of neurons 2502, but any suitable number of neurons 2502 may be used. In at least one embodiment, each instance of a neuron 2502 may include a neuron input 2504 and a neuron output 2506. In at least one embodiment, a neuron 2502 may generate an output that can be transmitted to the inputs of other instances of the neuron 2502. In at least one embodiment, the neuron input 2504 and the neuron output 2506 may be interconnected via synapses 2508.

[0309] In at least one embodiment, neuron 2502 and synapse 2508 may be interconnected, causing neuromorphic processor 2500 to operate to process or analyze information received by neuromorphic processor 2500. In at least one embodiment, neuron 2502 may send an output pulse (or “trigger” or “peak”) when the input received through neuron input 2504 exceeds a threshold. In at least one embodiment, neuron 2502 may sum or integrate the signal received at neuron input 2504. For example, in at least one embodiment, neuron 2502 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as “membrane potential”) exceeds a threshold, neuron 2502 may use a transfer function such as a sigmoid or threshold function to generate an output (or “trigger”). In at least one embodiment, the leaky integral-triggered neuron may sum the signal received at neuron input 2504 to a membrane potential and may apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaking integral-triggered neuron may trigger if multiple input signals are received at neuron input 2504 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2502 may be implemented using circuitry or logic that receives input, integrates the input to the membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2502 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2506 when the result of applying the transfer function to neuron input 2504 exceeds a threshold. In at least one embodiment, once neuron 2502 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2502 may resume normal operation after a suitable period of time (or recovery period).

[0310] In at least one embodiment, neurons 2502 can be interconnected via synapses 2508. In at least one embodiment, synapses 2508 are operable to transmit signals from the output of a first neuron 2502 to the input of a second neuron 2502. In at least one embodiment, neurons 2502 can transmit information on more than one instance of synapses 2508. In at least one embodiment, one or more instances of neuron outputs 2506 can be connected via instances of synapses 2508 to instances of neuron inputs 2504 within the same neuron 2502. In at least one embodiment, an instance of neuron 2502 that produces an output to be transmitted on the instance of synapse 2508 may be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2502 that receives input transmitted via an instance of synapse 2508 may be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2508, since an instance of neuron 2502 can receive input from one or more instances of synapse 2508 and can also transmit output through one or more instances of synapse 2508, a single instance of neuron 2502 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0311] In at least one embodiment, neurons 2502 may be organized into one or more layers. Each instance of neuron 2502 may have a neuron output 2506, which can fan out to one or more neuron inputs 2504 via one or more synapses 2508. In at least one embodiment, the neuron output 2506 of neuron 2502 in the first layer 2510 may be connected to the neuron input 2504 of neuron 2502 in the second layer 2512. In at least one embodiment, layer 2510 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2502 in an instance of the first layer 2510 may fan out to each instance of neuron 2502 in the second layer 2512. In at least one embodiment, the first layer 2510 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2502 in an instance of the second layer 2512 fan out to fewer than all instances of neuron 2502 in the third layer 2514. In at least one embodiment, the second layer 2512 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2502 in the second layer 2512 may fan out to neurons 2502 in multiple other layers, including neurons 2502 fan out to (the same) second layer 2512. In at least one embodiment, the second layer 2512 may be referred to as a “periodic layer”. In at least one embodiment, the neuromorphic processor 2500 may be any suitable combination of, but not limited to, periodic layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0312] In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect synapses 2508 to neurons 2502. In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2502 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2508 may be connected to neurons 2502 using interconnect structures (such as on-chip networks) or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0313] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0314] Figure 26A processing system according to at least one embodiment is illustrated. In at least one embodiment, system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2602 or processor cores 2607. In at least one embodiment, system 2600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0315] In at least one embodiment, system 2600 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2600 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0316] In at least one embodiment, each of the one or more processors 2602 includes one or more processor cores 2607 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a particular instruction set 2609. In at least one embodiment, the instruction set 2609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2607 may process a different instruction set 2609, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor core 2607 may also include other processing devices, such as a digital signal processor (DSP).

[0317] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherence techniques. In at least one embodiment, processor 2602 further includes a register file 2606, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2606 may include general-purpose registers or other registers.

[0318] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transmit communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2610 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a platform controller hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between memory devices and other components of the processing system 2600, while the platform controller hub (PCH) 2630 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0319] In at least one embodiment, memory device 2620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2620 may be used as system memory of processing system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute an application or process. In at least one embodiment, memory controller 2616 is also coupled to an optional external graphics processor 2612, which may communicate with one or more graphics processors 2608 of processor 2602 to perform graphics and media operations. In at least one embodiment, display device 2611 may be connected to processor 2602. In at least one embodiment, display device 2611 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2611 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0320] In at least one embodiment, the platform controller hub 2630 enables peripheral devices to connect to the storage device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, a touch sensor 2625, and a data storage device 2624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2624 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2625 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2628 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2634 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2610. In at least one embodiment, audio controller 2646 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system 2600. In at least one embodiment, platform controller hub 2630 may also be connected to one or more Universal Serial Bus (USB) controllers 2642 that connect input devices, such as a keyboard and mouse combination 2643, a camera 2644, or other USB input devices.

[0321] In at least one embodiment, instances of the memory controller 2616 and platform controller hub 2630 may be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, the platform controller hub 2630 and / or the memory controller 2616 may be external to one or more processors 2602. For example, in at least one embodiment, system 2600 may include an external memory controller 2616 and platform controller hub 2630, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with processor 2602.

[0322] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into graphics processor 2600. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in graphics processor 2612. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, in addition to Figure 9A or Figure 9B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0323] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0324] Figure 27 This is a block diagram of a processor 2700 having one or more processor cores 2702A-2702N, an integrated memory controller 2714, and an integrated graphics processor 2708 according to at least one embodiment. In at least one embodiment, the processor 2700 may include additional cores, up to and including additional cores 2702N indicated by dashed boxes. In at least one embodiment, each processor core 2702A-2702N includes one or more internal cache units 2704A-2704N. In at least one embodiment, each processor core may also access one or more shared cache units 2706.

[0325] In at least one embodiment, internal cache units 2704A-2704N and shared cache unit 2706 represent a cache memory hierarchy within processor 2700. In at least one embodiment, cache memory units 2704A-2704N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2706 and 2704A-2704N.

[0326] In at least one embodiment, the processor 2700 may further include a set of one or more bus controller units 2716 and a system agent core 2710. In at least one embodiment, one or more bus controller units 2716 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2710 provides management functions for various processor components. In at least one embodiment, the system agent core 2710 includes one or more integrated memory controllers 2714 to manage access to various external memory devices (not shown).

[0327] In at least one embodiment, one or more processor cores 2702A-2702N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2710 includes components for coordinating and operating cores 2702A-2702N during multi-threaded processing. In at least one embodiment, system agent core 2710 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2702A-2702N and graphics processor 2708.

[0328] In at least one embodiment, processor 2700 further includes a graphics processor 2708 for performing graph processing operations. In at least one embodiment, graphics processor 2708 is coupled to a shared cache unit 2706 and a system proxy core 2710 including one or more integrated memory controllers 2714. In at least one embodiment, system proxy core 2710 further includes a display controller 2711 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2711 may also be a separate module coupled to graphics processor 2708 via at least one interconnect, or it may be integrated within graphics processor 2708.

[0329] In at least one embodiment, ring-based interconnect unit 2712 is used to couple internal components of processor 2700. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2708 is coupled to ring interconnect 2712 via I / O link 2713.

[0330] In at least one embodiment, I / O link 2713 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2718 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2702A-2702N and graphics processor 2708 uses embedded memory module 2718 as a shared last-level cache.

[0331] In at least one embodiment, processor cores 2702A-2702N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2702A-2702N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2702A-2702N executing a common instruction set, while one or more other processor cores 2702A-2702N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2702A-2702N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2700 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0332] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the processor 2700. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in... Figure 27 The graphics processor 2612, graphics core 2702A-2702N, or other components are used. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, except... Figure 9A or Figure 9B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2700 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0333] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0334] Figure 28 This is a block diagram of the hardware logic of a graphics processor core 2800 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2800 is included within a graphics core array. In at least one embodiment, the graphics processor core 2800 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2800 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2800 may include a fixed-function block 2830, also referred to as a sub-slice, coupled to a plurality of sub-cores 2801A-2801F, which includes modules of general-purpose and fixed-function logic.

[0335] In at least one embodiment, the fixed-function block 2830 includes a geometry / fixed-function pipeline 2836, which, for example, may be shared by all sub-cores of the graphics processor 2800 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry and fixed-function pipeline 2836 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0336] In at least one fixed embodiment, the fixed functional block 2830 further includes a graphics SoC interface 2837, a graphics microcontroller 2838, and a media pipeline 2839. In at least one embodiment, the fixed graphics SoC interface 2837 provides an interface between the graphics core 2800 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 2838 is a programmable subprocessor configurable to manage various functions of the graphics processor 2800, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2839 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2839 implements media operations via requests for computation or sampling logic within subcores 2801-2801F.

[0337] In at least one embodiment, the SoC interface 2837 enables the graphics core 2800 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2837 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2800 and the CPU within the SoC. In at least one embodiment, the SoC interface 2837 also implements power management control for the graphics core 2800 and enables interfacing between the clock domain of the graphics core 2800 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2837 enables the reception of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 2839, or when a graphics processing operation is to be performed, they can be assigned to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipelines 2836 and 2814).

[0338] In at least one embodiment, the graphics microcontroller 2838 can be configured to perform various scheduling and management tasks on the graphics core 2800. In at least one embodiment, the graphics microcontroller 2838 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2802A-2802F, 2804A-2804F in the subcores 2801A-2801F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2800 can submit a workload to one of multiple graphics processor paths, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2838 may also facilitate a low-power or idle state of the graphics core 2800, thereby providing the graphics core 2800 with the ability to save and restore registers across low-power state transitions within the graphics core 2800, independent of the operating system and / or the graphics driver software on the system.

[0339] In at least one embodiment, the graphics core 2800 may have up to N more or fewer modular sub-cores than the illustrated sub-cores 2801A-2801F. For each group of N sub-cores, in at least one embodiment, the graphics core 2800 may further include shared functional logic 2810, shared and / or cache memory 2812, geometry / fixed-function pipeline 2814, and additional fixed-function logic 2816 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2810 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 2800. In at least one embodiment, the shared and / or cache memory 2812 may be the last-level cache of the N sub-cores 2801A-2801F within the graphics core 2800, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry / fixed function pipeline 2814 may be included to replace the geometry / fixed function pipeline 2836 within the fixed function block 2830, and may include the same or similar logic units.

[0340] In at least one embodiment, the graphics core 2800 includes additional fixed-function logic 2816, which may include various fixed-function acceleration logics for use by the graphics core 2800. In at least one embodiment, the additional fixed-function logic 2816 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2816, 2836, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2816. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2816 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0341] In at least one embodiment, the additional fixed-function logic 2816 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementing optimizations for machine learning training or inference.

[0342] In at least one embodiment, each graphics subcore 2801A-2801F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2801A-2801F includes multiple EU arrays 2802A-2802F, 2804A-2804F, thread dispatch and inter-thread communication (TD / IC) logic 2803A-2803F, 3D (e.g., texture) samplers 2805A-2805F, media samplers 2806A-2806F, shader processors 2807A-2807F, and shared local memory (SLM) 2808A-2808F. Each of the EU arrays 2802A-2802F and 2804A-2804F contains multiple execution units, which are general-purpose graphics processing units capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2803A-2803F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2805A-2805F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2806A-2806F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2801A-2801F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2801A-2801F may utilize shared local memory 2808A-2808F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0343] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into graphics processor 2810. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in graphics processor 2612, graphics microcontroller 2838, geometry & fixed-function pipelines 2814 and 2836, or... Figure 27 One or more ALUs embodied in other logic within the [the document]. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use [other methods besides...]. Figure 9A or Figure 9B The logic other than that shown is used to perform the task. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2800 to execute one or more machine learning algorithms, neural network architectures, use cases or training techniques described herein.

[0344] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0345] Figures 29A-29B The diagram illustrates thread execution logic 2900 of an array of processing elements including a graphics processor core, according to at least one embodiment. Figure 29A At least one embodiment is shown in which thread execution logic 2900 is used. Figure 29B Exemplary internal details of an execution unit according to at least one embodiment are shown.

[0346] like Figure 29AAs shown, in at least one embodiment, thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable execution unit array including multiple execution units 2908A-2908N, a sampler 2910, a data cache 2912, and a data port 2914. In at least one embodiment, the scalable execution unit array can be dynamically scaled, for example, based on the computational requirements of the workload, by enabling or disabling one or more execution units (e.g., any one of execution units 2908A, 2908B, 2908C, 2908D to 2908N-1 and 2908N). In at least one embodiment, the scalable execution units are interconnected via an interconnect structure linking to each execution unit. In at least one embodiment, the thread execution logic 2900 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 2906, data port 2914, sampler 2910, and execution units 2908A-2908N. In at least one embodiment, each execution unit (e.g., 2907A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2908A-2908N is scalable to include any number of individual execution units.

[0347] In at least one embodiment, execution units 2908A-2908N are primarily used to execute shader programs. In at least one embodiment, shader processor 2902 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2904. In at least one embodiment, thread dispatcher 2904 includes logic for arbitrating thread initialization celebrations from the graphics and media pipeline and for instantiating requested threads on one or more execution units 2908A-2908N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2904 can also handle runtime thread generation requests from executing shader programs.

[0348] In at least one embodiment, execution units 2908A-2908N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs in graphics libraries (e.g., Direct3D and OpenGL) to execute with minimal conversion. In at least one embodiment, the execution unit supports vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders). In at least one embodiment, each execution unit 2908A-2908N includes one or more arithmetic logic units (ALUs) capable of performing multiple-issue single-instruction multiple-data (SIMD) operations, and multithreaded operation enables an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. In at least one embodiment, execution is multiple issues per clock cycle to a pipeline capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, a priori operations, and other operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within execution units 2908A-2908N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the latency associated with vertex shader operations, the execution unit can perform operations on the pixel shader, fragment shader, or another type of shader program (including different vertex shaders).

[0349] In at least one embodiment, each of the execution units 2908A-2908N operates on an array of data elements. In at least one embodiment, the plurality of data elements is an "execution size" or the number of instruction channels. In at least one embodiment, an execution channel is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the plurality of channels may be independent of the plurality of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 2908A-2908N support integer and floating-point data types.

[0350] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as encapsulated data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit encapsulated data elements (quad-word (QW) size data elements), eight separate 32-bit encapsulated data elements (double-word (DW) size data elements), sixteen separate 16-bit encapsulated data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0351] In at least one embodiment, one or more execution units may be combined into a fused execution unit 2909A-2909N having thread control logic (2907A-2907N) for executing fused EUs. In at least one embodiment, multiple EUs may be merged into an EU group. In at least one embodiment, the number of EUs in a fused EU group may be configured to execute separate SIMD hardware threads, and the number of EUs in a fused EU group may vary depending on the embodiment. In at least one embodiment, each EU may execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2909A-2909N includes at least two execution units. For example, in at least one embodiment, a fused execution unit 2909A includes a first EU 2908A, a second EU 2908B, and thread control logic 2907A shared by the first EU 2908A and the second EU 2908B. In at least one embodiment, thread control logic 2907A controls the threads executing on the fused graphics execution unit 2909A, thereby allowing each EU within the fused execution units 2909A-2909N to execute using a common instruction pointer register.

[0352] In at least one embodiment, one or more internal instruction caches (e.g., 2906) are included in the thread execution logic 2900 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2910 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0353] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 2900 via thread creation and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2902 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated on the rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 2902 then executes a pixel or fragment shader program provided by an application programming interface (API). In at least one embodiment, to execute the shader program, shader processor 2902 dispatches threads to execution units (e.g., 2908A) via thread dispatcher 2904. In at least one embodiment, shader processor 2902 uses texture sampling logic in sampler 2910 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data are performed to calculate pixel color data for each geometric segment, or one or more pixels are discarded for further processing.

[0354] In at least one embodiment, data port 2914 provides a memory access mechanism for thread execution logic 2900 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2914 includes or is coupled to one or more cache memories (e.g., data cache 2912) to cache data for memory access via the data port.

[0355] like Figure 29BAs shown, in at least one embodiment, the graphics execution unit 2908 may include an instruction fetch unit 2937, a general-purpose register file array (GRF) 2924, an architecture register file array (ARF) 2926, a thread arbiter 2922, a send unit 2930, a branch unit 2932, a set of SIMD floating-point units (FPUs) 2931, and in at least one embodiment, a set of dedicated integer SIMD ALUs 2935. The GRF 2924 and ARF 2926 include a set of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 2908. In at least one embodiment, the architecture state of each thread is maintained in the ARF 2926, while data used during thread execution is stored in the GRF 2924. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in the ARF 2926.

[0356] In at least one embodiment, the graphics execution unit 2908 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and the number of registers per execution unit, wherein execution unit resources are logically allocated for executing multiple simultaneous threads.

[0357] In at least one embodiment, the graphics execution unit 2908 can jointly issue multiple instructions, each of which can be a different instruction. In at least one embodiment, the thread arbiter 2922 of the graphics execution unit thread 2908 can dispatch instructions to one of the sending unit 2930, the branching unit 2942, or the SIMD FPU 2934 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers in the GRF 2924, where each register can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4KB of the GRF 2924, although the embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, a maximum of seven threads can be executed simultaneously. In at least one embodiment where seven threads can access 4KB, the GRF 2924 can store a total of 28KB. In at least one embodiment, the flexible addressing mode can allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0358] In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are scheduled via a “send” instruction executed by message sending unit 2930. In at least one embodiment, branch instructions are dispatched to dedicated branch unit 2932 to facilitate SIMD divergence and eventual convergence.

[0359] In at least one embodiment, the graphics execution unit 2908 includes one or more SIMD floating-point units (FPUs) 2934 to perform floating-point operations. In at least one embodiment, the one or more FPUs 2934 also support integer computation. In at least one embodiment, the one or more FPUs 2934 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In at least one embodiment, at least one FPU provides extended mathematical capabilities to support high-throughput a priori mathematical functions and double-precision 64-bit floating-point operations. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2935 is also present and can be specifically optimized to perform operations related to machine learning computations.

[0360] In at least one embodiment, an array of multiple instances of the graphics execution unit 2908 may be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, the execution unit 2908 may execute instructions across multiple execution channels. In at least one embodiment, each thread executed on the graphics execution unit 2908 executes on a different channel.

[0361] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the thread execution logic 2900. Furthermore, in at least one embodiment, additional... Figure 9A or Figure 9B The logic other than that shown is used to perform the inference and / or training operations described herein. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of execution logic 2900 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0362] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0363] Figure 30 A parallel processing unit (“PPU”) 3000 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 3000 is configured with machine-readable code that, if executed by the PPU 3000, causes the PPU 3000 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 3000 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of an instruction set configured to be executed by the PPU 3000. In at least one embodiment, the PPU 3000 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as a liquid crystal display (“LCD”) device. In at least one embodiment, the PPU 3000 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 30 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture contemplated within the scope of this disclosure, which may be supplemented and / or replaced by any suitable processor.

[0364] In at least one embodiment, one or more PPU 3000s are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, the PPU 3000 is configured to accelerate deep learning systems and applications, including, but not limited to, the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analytics, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language conversion, online search optimization, and personalized user recommendations, etc.

[0365] In at least one embodiment, the PPU 3000 includes, but is not limited to, an input / output (“I / O”) unit 3006, a front-end unit 3010, a scheduler unit 3012, a job allocation unit 3014, a hub 3016, a crossbar (“Xbar”) 3020, one or more general-purpose processing clusters (“GPCs”) 3018, and one or more partitioning units (“memory partitioning units”) 3022. In at least one embodiment, the PPU 3000 is connected to a host processor or other PPU 3000 via one or more high-speed GPU interconnects (“GPU interconnects”) 3008. In at least one embodiment, the PPU 3000 is connected to a host processor or other peripheral device via a system bus 3002. In one embodiment, the PPU 3000 is connected to local memory including one or more memory devices (“memory”) 3004. In at least one embodiment, the memory device 3004 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high-bandwidth memory (“HBM”) subsystem, and multiple DRAM dies are stacked within each device.

[0366] In at least one embodiment, the high-speed GPU interconnect 3008 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 3000s (“CPUs”) combined with one or more central processing units, supporting cache coherency between the PPUs 3000s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 3008 transmits data and / or commands to other units of the PPU 3000, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 3016. Figure 30 Other components that may not be explicitly shown.

[0367] In at least one embodiment, the I / O unit 3006 is configured to access the host processor via the system bus 3002. Figure 30(Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 3006 communicates directly with the host processor via system bus 3002 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 3006 may communicate with one or more other processors (e.g., one or more PPUs 3000) via system bus 3002. In at least one embodiment, I / O unit 3006 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communication via the PCIe bus. In at least one embodiment, I / O unit 3006 implements an interface for communicating with external devices.

[0368] In at least one embodiment, I / O unit 3006 decodes packets received via system bus 3002. In at least one embodiment, at least some packets represent commands configured to cause PPU 3000 to perform various operations. In at least one embodiment, I / O unit 3006 sends the decoded commands to various other units of PPU 3000 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 3010 and / or to hub 3016 or other units of PPU 3000, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 30 (Not explicitly shown in the text). In at least one embodiment, I / O unit 3006 is configured to route communication between various logical units of PPU 3000.

[0369] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 3000 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 3000—the host interface unit can be configured to access a buffer in system memory connected to the system bus 3002 via memory requests transmitted through the system bus 3002 via the I / O unit 3006. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 3000, causing the front-end unit 3010 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 3000.

[0370] In at least one embodiment, a front-end unit 3010 is coupled to a scheduler unit 3012, which configures various GPCs 3018 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 3012 is configured to track status information related to the various tasks managed by the scheduler unit 3012, wherein the status information may indicate which GPC 3018 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, the scheduler unit 3012 manages multiple tasks executed on one or more GPCs 3018.

[0371] In at least one embodiment, a scheduler unit 3012 is coupled to a job allocation unit 3014 configured to dispatch tasks for execution on a GPC 3018. In at least one embodiment, the job allocation unit 3014 tracks multiple scheduled tasks received from the scheduler unit 3012 and manages a pool of pending tasks and an active task pool for each GPC 3018. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 30 time slots) containing tasks assigned to a specific GPC 3018; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by the GPC 3018, such that as one of the GPCs 3018 completes its execution, that task is evicted from the active task pool of the GPC 3018, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 3018. In at least one embodiment, if an active task is idle on GPC 3018, for example while waiting for data dependency resolution, the active task is evicted from GPC 3018 and returned to the task pool, while another task in the task pool is selected and scheduled to be executed on GPC 3018.

[0372] In at least one embodiment, the work allocation unit 3014 communicates with one or more GPCs 3018 via an XBar 3020. In at least one embodiment, the XBar 3020 is an interconnect network that couples a plurality of units of the PPU 3000 to other units of the PPU 3000, and can be configured to couple the work allocation unit 3014 to a specific GPC 3018. In at least one embodiment, other units of one or more PPUs 3000 can also be connected to the XBar 3020 via a hub 3016.

[0373] In at least one embodiment, tasks are managed by scheduler unit 3012 and assigned to one of GPCs 3018 by job allocation unit 3014. GPCs 3018 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 3018, routed to different GPCs 3018 via XBar 3020, or stored in memory 3004. In at least one embodiment, results may be written to memory 3004 via partitioning unit 3022, which implements a memory interface for writing data to or reading data from memory 3004. In at least one embodiment, results may be transferred to another PPU 3004 or CPU via high-speed GPU interconnect 3008. In at least one embodiment, PPU 3000 includes, but is not limited to, U partitioning units 3022, which are equal to the number of separate and different memory devices 3004 coupled to PPU 3000, as described below. Figure 32 To describe in more detail.

[0374] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 3000. In one embodiment, multiple computing applications are executed concurrently by the PPU 3000, and the PPU 3000 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 3000, and the driver core outputs the tasks to one or more streams processed by the PPU 3000. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 30 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory, in combination with... Figure 32 Threads and cooperative threads are described in more detail according to at least one embodiment.

[0375] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 3000. In at least one embodiment, the PPU 3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 3000. In at least one embodiment, the PPU 3000 can be used to perform one or more neural network use cases described herein.

[0376] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0377] Figure 31 A general-purpose processing cluster (“GPC”) 3100 according to at least one embodiment is illustrated. In at least one embodiment, the GPC 3100 is Figure 30 The GPC 3018. In at least one embodiment, each GPC 3100 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3100 includes, but is not limited to, a pipeline manager 3102, a pre-raster operation unit (“PROP”) 3104, a raster engine 3108, a work assignment crossbar switch (“WDX”) 3116, a memory management unit (“MMU”) 3118, one or more data processing clusters (“DPC”) 3106, and any suitable combination of components.

[0378] In at least one embodiment, the operation of GPC 3100 is controlled by pipeline manager 3102. In at least one embodiment, pipeline manager 3102 manages the configuration of one or more DPCs 3106 to handle tasks assigned to GPC 3100. In at least one embodiment, pipeline manager 3102 configures at least one of one or more DPCs 3106 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 3106 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 3114. In at least one embodiment, pipeline manager 3102 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 3100, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 3104 and / or raster engine 3108, while other packets may be routed to DPC 3106 for processing by raw engine 3112 or SM 3114. In at least one embodiment, pipeline manager 3102 configures at least one of DPCs 3106 to implement a neural network model and / or computation pipeline.

[0379] In at least one embodiment, the PROP unit 3104 is configured to route data generated by the raster engine 3108 and DPC 3106 to the raster operation (“ROP”) unit in the partition unit 3022, in conjunction with the above. Figure 30 More detailed description. In at least one embodiment, the PROP unit 3104 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, the raster engine 3108 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 3108 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is passed to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and passed to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to the fine raster engine to generate properties of pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 3108 includes fragments that will be processed by any suitable entity (e.g., by the fragment shader implemented within the DPC 3106).

[0380] In at least one embodiment, each DPC 3106 included in GPC 3100 includes, but is not limited to, an M-pipeline controller (“MPC”) 3110; a primitive engine 3112; one or more SMs 3114; and any suitable combination thereof. In at least one embodiment, the MPC 3110 controls the operation of the DPC 3106, routing packets received from the pipeline manager 3102 to the appropriate units within the DPC 3106. In at least one embodiment, packets associated with vertices are routed to the primitive engine 3112, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SM 3114.

[0381] In at least one embodiment, the SM 3114 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 3114 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process different datasets based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 3114 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process different datasets based on the same instructions, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. At least one embodiment of SM 3114 is described in more detail below.

[0382] In at least one embodiment, the MMU 3118 is integrated with the GPC 3100 and the memory partitioning unit (e.g., Figure 30 The MMU 3118 provides an interface between partition units 3022 and provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 3118 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0383] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 3100. In at least one embodiment, the GPC 3100 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 3100. In at least one embodiment, the GPC 3100 can be used to perform one or more neural network use cases described herein.

[0384] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of a lower frame rate video.

[0385] Figure 32 A memory partitioning unit 3200 of a parallel processing unit (“PPU”) according to at least one embodiment is illustrated. In at least one embodiment, the memory partitioning unit 3200 includes, but is not limited to, a raster operation (“ROP”) unit 3202; a secondary (“L2”) cache 3204; a memory interface 3206; and any suitable combination thereof. In at least one embodiment, the memory interface 3206 is coupled to memory. In at least one embodiment, the memory interface 3206 may implement a 32, 64, 128, or 1024-bit data bus, or a similar implementation for high-speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 3206, one memory interface 3206 per pair of partitioning units 3200, wherein each pair of partitioning units 3200 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high-bandwidth memory stack or graphics dual data rate version 5 synchronous dynamic random access memory (“GDDR5 SDRAM”).

[0386] In at least one embodiment, memory interface 3206 implements a high-bandwidth second-generation (“HBM2”) memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack resides on the same physical package as the PPU, providing significant power savings and area savings compared to conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y equals 4, with each HBM2 stack including two 128-bit channels per die for a total of eight channels and a 1024-bit data bus width. In at least one embodiment, the memory supports Single Error Corrected Double Error Detection (“SECDED”) error correction code (“ECC”) to protect data. In at least one embodiment, ECC can provide higher reliability for data corruption-sensitive computing applications.

[0387] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partitioning unit 3200 supports unified memory to provide a single unified virtual address space for the central processing unit (“CPU”) and the PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses pages more frequently. In at least one embodiment, the high-speed GPU interconnect 3008 supports address translation services, which allow the PPU to directly access the CPU's page tables and provide full access to the CPU's memory through the PPU.

[0388] In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the replication engine can generate page faults for addresses not mapped to page tables, and memory partitioning unit 3200 then servicees the page faults, mapping the addresses to page tables, after which the replication engine performs the transfer. In at least one embodiment, multiple replication engines operating on fixed (i.e., non-pageable) memory across multiple processors substantially reduce available memory. In at least one embodiment, in the event of a hardware page fault, an address can be passed to the replication engine regardless of whether a memory page resides, and the replication process is transparent.

[0389] According to at least one embodiment, from Figure 30 Data from memory 3004 or other system memory is retrieved by memory partitioning unit 3200 and stored in L2 cache 3204, which is located on-chip and shared among various GPCs. In at least one embodiment, each memory partitioning unit 3200 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in various units within a GPC. In at least one embodiment, each SM 3114 may implement a Level 1 (“L1”) cache, wherein the L1 cache is a private memory dedicated to a specific SM 3114, and data is retrieved from L2 cache 3204 and stored in each L1 cache for processing within the functional units of the SM 3114. In at least one embodiment, L2 cache 3204 is coupled to memory interface 3206 and XBar 3020.

[0390] In at least one embodiment, ROP unit 3202 performs graphic raster operations related to pixel color, such as color compression, pixel blending, etc. In at least one embodiment, ROP unit 3202 performs depth testing in conjunction with raster engine 3108, receiving depth from the culling engine of raster engine 3108 for sample locations associated with pixel fragments. In at least one embodiment, depth is tested for the corresponding depth in the depth buffer at the sample location associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 3202 updates the depth buffer and sends the result of the depth test to raster engine 3108. It will be appreciated that the number of partition units 3200 may differ from the number of GPCs; therefore, each ROP unit 3202 may be coupled to each of the GPCs in at least one embodiment. In at least one embodiment, ROP unit 3202 tracks packets received from different GPCs and determines whether the result generated by ROP unit 3202 should be routed through XBar 3020.

[0391] Figure 33 A streaming multiprocessor (“SM”) 3300 according to at least one embodiment is illustrated. In at least one embodiment, the SM 3300 is Figure 31SM 3114. In at least one embodiment, SM 3300 includes, but is not limited to, instruction cache 3302; one or more scheduler units 3304; register file 3308; one or more processing cores (“cores”) 3310; one or more special function units (“SFUs”) 3312; one or more load / store units (“LSUs”) 3314; interconnect network 3316; shared memory / Level 1 (“L1”) cache 3318; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 3300. In at least one embodiment, scheduler unit 3304 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks allocated to SM 3300. In at least one embodiment, scheduler unit 3304 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 3304 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 3310, SFU 3312, and LSU 3314) in each clock cycle.

[0392] In at least one embodiment, a cooperative group can refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, a cooperative startup API supports synchronization between blocks of threads to execute parallel algorithms. In at least one embodiment, applications using a conventional programming model provide a single, simple construct for synchronizing cooperative threads: a barrier (e.g., the `syncthreads()` function) across all threads in a block of threads. However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block (i.e., as small as a single thread) and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, this programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their native environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0393] In at least one embodiment, scheduling unit 3306 is configured to send instructions to one or more functional units, and scheduler unit 3304 includes, but is not limited to, two sc...

Claims

1. A processor, comprising: One or more arithmetic logic units (ALUs) are configured to reason about frames of a video using one or more neural networks, said neural networks being trained using a series of video frames, wherein said series of video frames are used to generate a series of temporal pose representations and one or more time-invariant appearance representations. The series of temporal pose representations includes features represented by Gaussian heatmaps, and represents the changes in pose at a series of time points. Specifically, the change of the pose at one or more future time points is determined by modeling the motion of the series of time pose representations over time using a time encoder, and the series of time pose representations and at least one time-invariant appearance representation are used to reconstruct the input video frame for the modeling.

2. The processor of claim 1, wherein color dithering and thin-plate spline TPS warping enhance the appearance invariance and localization properties of one or more of the series of time pose representations.

3. The processor of claim 1, wherein the feature is parameterized as mean and covariance.

4. The processor according to claim 1, wherein, By adjusting one or more network parameters of the one or more neural networks, the loss value generated by comparing the input video frame with the reconstructed video frame is minimized.

5. The processor of claim 1, wherein the time encoder comprises one or more Long Short-Term Memory (LSTM) networks.

6. The processor of claim 1, wherein the inferred frames are used to generate a video with a higher frame rate, fewer dropped frames, or additional content.

7. A system comprising: One or more processors are configured to infer frames of a video using one or more neural networks, said neural networks being trained using a series of video frames, wherein said series of video frames are used to generate a series of temporal pose representations and one or more time-invariant appearance representations; and One or more memories for storing the one or more neural networks. The series of temporal pose representations includes features represented by Gaussian heatmaps, and represents the changes in pose at a series of time points. Specifically, the change of the pose at one or more future time points is determined by modeling the motion of the series of time pose representations over time using a time encoder, and the series of time pose representations and at least one time-invariant appearance representation are used to reconstruct the input video frame for the modeling.

8. The system of claim 7, wherein color jitter and thin-plate spline TPS warping enhance the appearance invariance and localization properties of one or more of the series of time pose representations.

9. The system of claim 7, wherein the feature is parameterized as mean and covariance.

10. The system according to claim 7, wherein, By adjusting one or more network parameters of the one or more neural networks, the loss value generated by comparing the input video frame with the reconstructed video frame is minimized.

11. The system of claim 7, wherein the time encoder comprises one or more Long Short-Term Memory (LSTM) networks.

12. A machine-readable medium having an instruction set stored thereon, which, if executed by one or more processors, causes the one or more processors to at least: One or more neural networks are used to infer the frames of a video, said neural networks being trained on a series of video frames used to generate a series of temporal pose representations and one or more time-invariant appearance representations. in, The series of temporal pose representations includes features represented by Gaussian heatmaps, and represents the changes in pose at a series of time points. Specifically, the change of the pose at one or more future time points is determined by modeling the motion of the series of time pose representations over time using a time encoder, and the series of time pose representations and at least one time-invariant appearance representation are used to reconstruct the input video frame for the modeling.

13. The machine-readable medium of claim 12, wherein color dithering and thin-plate spline TPS warping enhance the appearance invariance and localization properties of one or more of the series of time-pose representations.

14. The machine-readable medium of claim 12, wherein the feature is parameterized as mean and covariance.

15. The machine-readable medium according to claim 12, wherein, By adjusting one or more network parameters of the one or more neural networks, the loss value generated by comparing the input video frame with the reconstructed video frame is minimized.

16. The machine-readable medium of claim 12, wherein the time encoder comprises one or more Long Short-Term Memory (LSTM) networks.

17. A processor, comprising: One or more arithmetic logic units (ALUs) are used to train one or more neural networks to at least partially reason about frames of a video, said neural networks being trained using a series of video frames used to generate a series of temporal pose representations and one or more time-invariant appearance representations. The series of temporal pose representations includes features represented by Gaussian heatmaps, and represents the changes in pose at a series of time points. Specifically, the change of the pose at one or more future time points is determined by modeling the motion of the series of time pose representations over time using a time encoder, and the series of time pose representations and at least one time-invariant appearance representation are used to reconstruct the input video frame for the modeling.

18. The processor of claim 17, wherein color dithering and thin-plate spline TPS warping enhance the appearance invariance and localization properties of one or more of the series of time pose representations.

19. The processor of claim 17, wherein the feature is parameterized as mean and covariance.

20. The processor of claim 17, wherein, By adjusting one or more network parameters of the one or more neural networks, the loss value generated by comparing the input video frame with the reconstructed video frame is minimized.

21. The processor of claim 17, wherein the time encoder comprises one or more Long Short-Term Memory (LSTM) networks.

22. A system comprising: One or more processors are used to compute parameters corresponding to one or more neural networks to infer at least partially frames of a video using a series of video frames, said series of video frames being used to generate a series of temporal pose representations and one or more time-invariant appearance representations; as well as One or more memories for storing the parameters. The series of temporal pose representations includes features represented by Gaussian heatmaps, and represents the changes in pose at a series of time points. Specifically, the change of the pose at one or more future time points is determined by modeling the motion of the series of time pose representations over time using a time encoder, and the series of time pose representations and at least one time-invariant appearance representation are used to reconstruct the input video frame for the modeling.

23. The system of claim 22, wherein color jitter and thin-plate spline TPS warping enhance the appearance invariance and localization properties of one or more of the series of time pose representations.

24. The system of claim 22, wherein the feature is parameterized as mean and covariance.

25. The system according to claim 22, wherein, By adjusting one or more network parameters of the one or more neural networks, the loss value generated by comparing the input video frame with the reconstructed video frame is minimized.

26. The system of claim 22, wherein the time encoder comprises one or more Long Short-Term Memory (LSTM) networks.

27. A machine-readable medium having an instruction set stored thereon, which, when executed by one or more processors, causes the one or more processors to at least: A neural network is trained using a series of video frames to at least partially infer the frames of the video, said series of video frames being used to generate a series of temporal pose representations and one or more time-invariant appearance representations; and One or more memories for storing parameters corresponding to the one or more neural networks. in, The series of temporal pose representations includes features represented by Gaussian heatmaps, and represents the changes in pose at a series of time points. Specifically, the change of the pose at one or more future time points is determined by modeling the motion of the series of time pose representations over time using a time encoder, and the series of time pose representations and at least one time-invariant appearance representation are used to reconstruct the input video frame for the modeling.

28. The machine-readable medium of claim 27, wherein color dithering and thin-plate spline TPS warping enhance the appearance invariance and localization properties of one or more of the series of time-pose representations.

29. The machine-readable medium of claim 27, wherein the feature is parameterized as mean and covariance.

30. The machine-readable medium of claim 27, wherein, By adjusting one or more network parameters of the one or more neural networks, the loss value generated by comparing the input video frame with the reconstructed video frame is minimized.

31. The machine-readable medium of claim 27, wherein the time encoder comprises one or more Long Short-Term Memory (LSTM) networks.

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