erasing memory

Abstract

Methods of operating a memory and memories configured to perform similar methods can include applying a positive first voltage level to a first node selectively connected to a series-connected string of memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the series-connected string of memory cells; and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, in one or more embodiments, to erasing memory cells. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic systems. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has become a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. Changes in the threshold voltage (Vt) of a memory cell determine the data state (e.g., data value) of each memory cell through programming (often referred to as writing) of the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization). Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0004] NAND flash memory is a common type of flash memory device in so-called logic form, in which a basic memory cell configuration is arranged. Typically, the memory cell array of a NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form access lines, such as word lines. Columns of the array contain strings of memory cells (often called NAND strings) connected together in series between a pair of select gates (e.g., source-select transistors and drain-select transistors). Each source-select transistor can be connected to the source, and each drain-select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0005] Memory cells are typically erased before they are programmed to the desired data state. For example, memory cells in a specific block of memory cells may be erased first, and then selectively programmed. For NAND arrays, memory cell blocks are typically erased by grounding all access lines (e.g., word lines) in the block and (e.g., connecting via data lines and source) applying an erase voltage to the channel region of the memory cell to remove charge that may be stored on the data storage structures (e.g., floating gates or charge traps) within the memory cell block. A typical erase voltage may be approximately 20V or higher before the erase operation is complete. Attached Figure Description

[0006] Figure 1 This is a simplified block diagram of a memory that communicates with a processor, which is part of an electronic system, according to an embodiment.

[0007] Figures 2A to 2B It can be used as a reference. Figure 1 A schematic diagram of the various parts of the memory cell array in the described type of memory.

[0008] Figure 3 It can be used as a reference. Figure 1 A cross-sectional view of a string of memory cells connected in series, describing the type of memory.

[0009] Figure 4A The waveform of the voltage level used to generate the GIDL current for the related technology is conceptually shown.

[0010] Figure 4B The waveform of the voltage level used to generate the GIDL current according to an embodiment is conceptually depicted.

[0011] Figure 5 This is a description of the ramp voltage levels used in various embodiments.

[0012] Figure 6 It is used in conjunction with various embodiments for generating Figure 5 The block diagram depicts a voltage generation system of the type of ramp voltage level.

[0013] Figure 7A A waveform of the voltage level used to generate GIDL current according to another embodiment is conceptually depicted.

[0014] Figure 7B A waveform of the voltage level used to generate the GIDL current is conceptually depicted according to a further embodiment.

[0015] Figure 8 This is a flowchart of a method for operating a memory according to an embodiment.

[0016] Figure 9 This is a flowchart of a method for operating a memory according to another embodiment.

[0017] Figure 10 This is a flowchart of a method for operating a memory according to a further embodiment.

[0018] Figure 11 This is a flowchart of a method for operating a memory according to yet another embodiment. Detailed Implementation

[0019] In the following detailed description, reference is made to the accompanying drawings, which form part of this description and illustrate specific embodiments therein by way of illustration. In the drawings, the same reference numerals describe substantially similar components in several views. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Unless explicitly defined, elements, waveforms, and / or other representations in the figures may not be drawn to scale. Therefore, the following detailed description should not be considered limiting.

[0020] The term "semiconductor" as described herein may refer to, for example, a material layer, a wafer, or a substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a basic semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when "semiconductor" is referred to in the following description, regions / junctions may have been formed in the basic semiconductor structure using prior process steps, and the term "semiconductor" may include an underlying layer containing such regions / junctions.

[0021] Unless the context otherwise requires, the term “conductive” as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless the context otherwise requires, the term “connection” as used herein, and its various related forms (e.g., connect, being connected, connection, etc.), refer to electrical connection.

[0022] Figure 1This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100 according to an embodiment, which communicates with a second device in the form of a processor 130, which is part of a third device in the form of an electronic system. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile phones, etc. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0023] Memory device 100 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (typically called a word line), while memory cells in logical columns are typically selectively connected to the same data line (typically called a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (not shown) can be programmed as one of at least two target data states.

[0024] Row decoding circuit 108 and column decoding circuit 110 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 100 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to the memory device 100, as well as the output of data and status information from the memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch the address signal before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch input commands.

[0025] A controller (e.g., control logic 116 within storage device 100) controls access to memory cell array 104 in response to commands and generates status information for external processor 130. Specifically, control logic 116 is configured to perform access operations on memory cell array 104 (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations), and may be configured to perform methods according to embodiments. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses.

[0026] Control logic 116 also communicates with cache register 118. Cache register 118 latches imported or exported data as instructed by control logic 116 to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 to be transferred to memory cell array 104; then new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to be output to external processor 130; then new data can be transferred from data register 120 back to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form part of it). The page buffer may also include sensing devices ( Figure 1 (Not shown) The data state of a memory cell can be sensed, for example, by sensing the state of the data lines connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and the control logic 116 to latch the status information for output to the processor 130.

[0027] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received further via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0028] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. For an 8-bit device, data can be received via input / output (I / O) pins [7:0], or for a 16-bit device, via input / output (I / O) pins [15:0] at I / O control circuitry 112 and then written to cache register 118. The data can then be written to data register 120 to program memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. For 8-bit devices, data can also be output via input / output (I / O) pins [7:0], or for 16-bit devices via input / output (I / O) pins [15:0]. Although references to I / O pins are possible, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connection to memory device 100 via an external device (e.g., processor 130).

[0029] Those skilled in the art will understand that additional circuitry and signals can be provided, and Figure 1 The memory device 100 has been simplified. It should be recognized that the reference... Figure 1 The functionality of the various block components described may not necessarily need to be separated into different parts or component portions of the integrated circuit device. For example, a single part or component portion of the integrated circuit device may be adapted to... Figure 1 More than one component performs the functionality. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform the functionality. Figure 1 Individual block components perform functionality.

[0030] In addition, although specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0031] Figure 2A This is a schematic diagram of a portion of a memory cell array 200A (such as a NAND memory array), which can be used in a reference. Figure 1 In the described type of memory, for example, as part of a memory cell array 104. The memory array 200A includes access lines (such as word lines 2020 to 202). N ) and data lines (such as bit lines 2040 to 204) MWord line 202 can be connected in a many-to-one relationship to... Figure 2A Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, for example, or to have a conductivity type such as n-type conductivity to form an n-well, for example.

[0032] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Some memory cells 208 may represent virtual memory cells, such as memory cells not intended to store user data. As is well known, virtual memory cells are generally not accessible to the user of the memory and are often incorporated into NAND string 206 for operational advantages.

[0033] The memory cells 208 of each NAND string 206 may be connected in series with select gates 210 (e.g., field-effect transistors) (such as select gates 2100 to 210). M One of them (e.g., typically a source-select transistor, collectively referred to as the select gate source) and select gate 212 (e.g., a field-effect transistor) (such as select gates 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, collectively referred to as the select gate drain). Select gates 2100 to 210 M They can be connected together to select line 214, such as the source select line (SGS), and select gates 2120 to 212. M They can be connected together to select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, each configured to receive the same or independent control signal. The control gate of each select gate 210 can be connected to select line 214. The control gate of each select gate 212 can be connected to select line 215.

[0034] Each NAND string 206's select gate 210 may be connected in series in its memory cell 208 with a GIDL (gate-induced drain leakage) generator gate 218 (e.g., a field-effect transistor) (such as GIDL generator (GG) gates 2180 to 218). M Between one of them. GG gates 2180 to 218 M This can be referred to as the Source Gate. Source Gate 2180 to 218 M Each can be individually connected (e.g., directly connected) to source 216, and selectively connected to its corresponding NAND strings 2060 to 206. M Alternatively, source select gate 210 and its GG gate 218 may represent, for example, a single gate connected (e.g., directly connected) to source 216 and connected (e.g., directly connected) to the corresponding NAND string 206. The select gate 212 of each NAND string 206 may be connected in series in its memory cell 208 with a GG gate 220 (e.g., a field-effect transistor) (such as GG gates 2200 to 220). M Between one of them. GG gates 2200 to 220 M This can be referred to as a drain GG gate. Drain GG gate 2200 to 220 M It can be connected (e.g., directly) to its corresponding data line 2040 to 204. M And selectively connected to its corresponding NAND strings 2060 to 206. M Alternatively, drain select gate 212 and its GG gate 220 may represent, for example, a single gate connected (e.g., directly connected) to the corresponding data line 204 and connected (e.g., directly connected) to the corresponding NAND string 206.

[0035] GG Gate 2180 to 218 M They can be connected together to control line 222, such as the SGS_GG control line, and GG gates 2200 to 220. MThey can be connected together to control line 224, such as the SGD_GG control line. Although depicted as conventional field-effect transistors, GG gates 218 and 220 can utilize a structure similar to (e.g., identical to) memory cell 208. GG gates 218 and 220 can represent multiple GG gates connected in series, each configured to receive the same or independent control signal. Generally, the threshold voltages of GG gates 218 and 220 can be different from (e.g., lower than) the threshold voltages of select gates 210 and 212. The threshold voltage of the source GG gate 218 can be different from (e.g., higher than) the threshold voltage of the drain GG gate 220. The threshold voltages of GG gates 218 and 220 can have the opposite polarity to the threshold voltages of select gates 210 and 212, and / or can be lower than the threshold voltages of select gates 210 and 212. For example, select gates 210 and 212 may have positive threshold voltages (e.g., 2V to 4V), while GG gates 218 and 220 may have negative threshold voltages (e.g., -1V to -4V). GG gates 218 and 220 may be provided to assist in generating GIDL current into the channel region of the corresponding NAND string 206 of the GG gate during, for example, an erase operation.

[0036] The source of each GG gate 218 can be connected to the common source 216. The drain of each GG gate 218 can be connected to the select gate 210 of the corresponding NAND string 206. For example, the drain of GG gate 2180 can be connected to the source of the select gate 2100 of the corresponding NAND string 2060. Therefore, each select gate 210 and GG gate 218 of the corresponding NAND string 206 can be configured to cooperatively selectively connect the NAND string 206 to the common source 216. The control gate of each GG gate 218 can be connected to the select line 222.

[0037] The drain of each GG gate 220 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of GG gate 2200 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each GG gate 220 can be connected to the select gate 212 of the corresponding NAND string 206. For example, the source of GG gate 2200 can be connected to the select gate 2120 of the corresponding NAND string 2060. Therefore, each select gate 212 and GG gate 220 of the corresponding NAND string 206 can be configured to cooperatively selectively connect the NAND string 206 to the corresponding bit line 204. The control gate of each GG gate 220 can be connected to the select line 224.

[0038] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, where the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2AThe memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the bit line 204, which can be substantially parallel to the plane containing the common source 216.

[0039] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, such as... Figure 2A As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The control gate 236 of the memory cell 208 is connected to (and in some forms forms) a word line 202.

[0040] A column of memory cells 208 can be a single NAND string 206 or multiple NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 can be memory cells 208 typically connected to a given word line 202. A row of memory cells 208 may, but does not necessarily, contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 typically connected to a given word line 202. For example, typically connected to word line 202... N Memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Memory cells 208 selectively connected to odd-numbered bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd-numbered memory cells). Although bit lines 2043 to 2045 are not in... Figure 2A While not explicitly described, it is clear from the diagram that bit line 204 of memory cell array 200A can extend from bit line 2040 to bit line 204. MSequential numbering. Other groups of memory cells 208 typically connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells typically connected to a given word line may be considered physical pages of the memory cells. A portion (in some embodiments, it may still be an entire line) of a physical page of a memory cell that is read during a single read operation or programmed during a single programmable operation (e.g., the previous or next page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 share a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell.

[0041] Although discussed in conjunction with NAND flash memory Figure 2A These are examples, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0042] Figure 2B This is another schematic diagram of a portion of a memory cell array 200B, which can be used in a reference. Figure 1 In the type of memory described, for example, as part of a memory cell array 104. Figure 2B Elements with the same number in the middle correspond to about Figure 2A The description provided. Figure 2B Additional details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, a portion of which may serve as the body and channel region of the memory cells of the NAND strings 206. The NAND strings 206 may each be selectively connected to bit lines 2040 to 204 via select transistors 212 (e.g., drain select transistors, commonly referred to as select gate drains). M And selectively connected to the common source 216 via a selection transistor 210 (e.g., a source-select transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via bias select lines 2150 to 215. KEach word line 202 is connected to its corresponding bit line 204 to selectively activate each specific selection transistor 212 between the NAND string 206 and the bit line 204. Selection transistor 210 can be activated by biasing selection line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells that are typically connected to each other via specific word lines 202 can be collectively referred to as a hierarchy.

[0043] A three-dimensional NAND memory array 200B may be formed above peripheral circuitry 226. Peripheral circuitry 226 may represent various circuits for accessing the memory array 200B. Peripheral circuitry 226 may include complementary circuit elements. For example, peripheral circuitry 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate (a process commonly referred to as CMOS) or on complementary metal-oxide-semiconductor (CMOS). Although CMOS typically no longer utilizes a rigid metal-oxide-semiconductor structure due to advancements in integrated circuit manufacturing and design, CMOS design remains convenient.

[0044] Figure 3 It can be used as a reference. Figure 1 A cross-sectional view of a string of memory cells connected in series, representing the type of memory described. Three-dimensional memory arrays are typically fabricated by forming alternating layers of conductors and dielectrics, forming vias in these layers, forming additional material on the sidewalls of the vias to define a stack of gates for the memory cells and other gates, and subsequently filling the vias with a semiconductor material to define pillars that act as the bodies (e.g., channel regions) of the memory cells and selection gates. To improve the conductivity of the pillars and, for example, the adjacent semiconductor material on which the pillars are formed, conductive (e.g., conductively doped) portions are typically formed in the vias at the interfaces with the adjacent semiconductor material. These conductive portions are typically formed of a different conductivity type than the pillars and the adjacent semiconductor material. For example, if the pillars are formed of a P-type semiconductor material, the conductive portions may have N-type conductivity. Figure 3 Describe the basic structure of a string of serially connected memory cells formed in this way. Figure 3 In the diagram, two strings of memory cells connected in series (e.g., NAND strings) are depicted in a cross-sectional view. Note that the spacing between the elements in the diagram may represent dielectric material.

[0045] refer to Figure 3The first NAND string includes a first pillar 3400. The first pillar 3400 may be formed of a semiconductor material of a first conductivity type (such as P-type polysilicon). A conductive portion 3420 may be formed at the bottom of the pillar 3400, wherein the conductive portion 3420 is electrically connected to the source 216. The conductive portion 3420 may be formed of a semiconductor material of a second conductivity type different from the first conductivity type. For the example where the first pillar 3400 may be formed of P-type polysilicon, the conductive portion 3420 may be formed of an N-type semiconductor material (such as N-type polysilicon). Additionally, the conductive portion 3420 may have a higher conductivity level than the pillar 3400. For example, the conductive portion 3420 may have N+ conductivity. Alternatively, the conductive portion 3420 may be formed of a conductor (e.g., a metal or metal silicide).

[0046] Pillar 3400 is electrically connected to data line 204 via conductive plug 3440. In this example, conductive plug 3440 may also be formed of a semiconductor material of a second conductivity type and may similarly have a higher conductivity level than pillar 3400. Alternatively, conductive plug 3440 may be formed of a conductor (e.g., metal or metal silicide). The first NAND string also includes a source GG gate at the intersection of control line 222 and pillar 3400 and a drain GG gate at the intersection of control line 2240 and pillar 3400. The first NAND string also includes a source select gate at the intersection of source select line 214 and pillar 3400 and a drain select gate at the intersection of drain select line 2150 and pillar 3400. The first NAND string also includes memory cells at each of the intersections of access lines 2020 to 2027 with pillar 3400. These memory cells also include data storage structure 234. 00 Up to 234 70 .although Figure 3 The structure is depicted as containing only eight access lines 202 in an effort to improve the readability of the diagram, but a typical NAND structure can have significantly more access lines 202.

[0047] Although not all are numbered, but for Figure 3 For clarity, data storage structures 234 are depicted on both sides of pillar 340. Each data storage structure 234 may completely surround its corresponding pillar 340, thus defining a data storage structure 234 for a single memory cell. Alternatively, structures are known to have segmented data storage structures 234, such that more than one (e.g., two) memory cells are defined at each intersection of access line 202 and pillar 340. The embodiments described herein are independent of the number of memory cells defined around pillar 340. However, examples of segmented data storage structures can be found in U.S. Patent No. 7,906,818 granted to Pekny.

[0048] Further reference Figure 3 The second NAND string includes a second pillar 3401. The second pillar 3401 may be formed of a semiconductor material of a first conductivity type (such as P-type polysilicon). A conductive portion 3421 may be formed at the bottom of the pillar 3401, wherein the conductive portion 3421 is electrically connected to the source 216. The conductive portion 3421 may be formed of a semiconductor material of a second conductivity type. For the example where the pillar 3401 may be formed of P-type polysilicon, the conductive portion 3421 may be formed of an N-type semiconductor material (such as N-type polysilicon). Additionally, the conductive portion 3421 may have a higher conductivity level than the pillar 3401. For example, the conductive portion 3421 may have N+ conductivity.

[0049] Pillar 3401 is electrically connected to data line 204 via conductive plug 3441. In this example, conductive plug 3441 may also be formed of a semiconductor material of a second conductivity type and may similarly have a higher conductivity level than pillar 3401. Alternatively, conductive plug 3441 may be formed of a conductor (e.g., metal or metal silicide). The second NAND string also includes a source GG gate located at the intersection of control line 222 and pillar 3401 and a drain GG gate located at the intersection of control line 2241 and pillar 3401. The second NAND string also includes a source select gate located at the intersection of source select line 214 and pillar 3401 and a drain select gate located at the intersection of drain select line 2151 and pillar 3401. The second NAND string also includes memory cells located at each intersection of access lines 2020 to 2027 with pillar 3401. These memory cells also include data storage structure 234. 01 Up to 234 71 .

[0050] Due to the nature of the removal processes commonly used in the semiconductor industry, forming vias through multiple layers typically results in vias with a decreasing diameter towards the bottom. To prevent the vias from becoming too narrow, a reference can be used... Figures 2A to 2B The segmented formation of the array of the described type allows for the formation of layers for forming a first portion of a NAND string, which can then be removed to define apertures, and the remaining structure can be formed within the apertures. After the first portion of the NAND string is formed, a second portion of the NAND string can be formed on top of the first portion in a similar manner. While the embodiments do not depend on the nature of the array structure, examples of segmented array structures can be found in U.S. Patent No. 10,049,750 to Sakui et al.

[0051] Typically, an erase operation on a memory cell of a NAND string involves a series of erase pulses (e.g., pulse 1, pulse 2, pulse 3...) applied to the NAND string via its respective data line 204 and source 216, while a voltage is applied to access line 202 having a polarity and magnitude intended to remove charge from the data storage structure of the memory cell when the erase pulses are applied to the NAND string. An erase verification operation can be performed between pulses to determine whether the memory cell has been sufficiently erased (e.g., with a threshold voltage at or below a certain target value). If the erase verification fails, another erase pulse, typically with a higher voltage level, can be applied.

[0052] Erasing operations typically utilize GIDL (Gate-Induced Drain Leakage) to provide sufficient current to pillar 340 (e.g., to the body of the memory cell) to sustain the erase operation. GIDL current can be generated by applying voltage levels to control lines 222 and / or 224, which are lower than the voltage levels applied to data lines 204 and source 216. Due to the different characteristics at opposite ends of the NAND string, the voltage level applied to control line 222 for the source GG gate can differ from the voltage level applied to control line 224 for the drain GG gate, even if data lines 204 and source 216 receive the same voltage level.

[0053] Although different voltages can be applied to control lines 222 and 224, the voltage differences from source 216 and data line 204, respectively, can be selected to be substantially equal (e.g., equal) to promote similar (e.g., equal) levels of GIDL current. For example, the voltage level applied to control line 222 can be 5V lower than the voltage level applied to source 216, and the voltage level applied to control line 224 can be 5V lower than the voltage level applied to data line 204. The voltage level applied to select lines 214 or 215 can be selected to reduce stress during erase operations, and therefore can have a value between the voltage level applied to the control lines (e.g., control lines 222 or 224) of the corresponding GG gates and the voltage levels applied to source 216 or data line 204, respectively. The selection of various voltage levels can generally depend on the array architecture, construction materials, and / or processing conditions, and is within the capabilities of a person skilled in the art of semiconductor manufacturing. Table 1 provides some exemplary voltage levels that can be used with the embodiments.

[0054] Table 1

[0055]

[0056]

[0057] Although the examples in Table 1 show the same voltage difference applied between source 216 and control line 222, and between data line 204 and control line 224 for each erase pulse, the voltage difference between opposite ends of the NAND string can be different due to different characteristics. For example, the voltage difference between the voltage level applied to control line 222 and the voltage level applied to source 216 can be different (e.g., greater) than the voltage difference between the voltage level applied to control line 224 and the voltage level applied to data line 204.

[0058] The GIDL current generated by the voltage difference between source 216 and control line 222 and / or data line 204 and control line 224 can depend exponentially on the magnitude of the voltage difference, which may be called offset. For example, a higher offset can produce a higher level of GIDL current. However, a higher level of offset may also lead to the degradation of the GG gate.

[0059] Figure 4A The waveform of the voltage level used to generate the GIDL current for related technologies is conceptually illustrated. Figure 4A In the waveform, waveform 460 may represent the voltage level applied to source 216 (or data line 204), waveform 462 may represent the voltage level applied to control line 222 (or control line 224), and waveform 464 may represent the voltage difference between waveform 462 and waveform 460. Waveform 460 may represent the erase pulse of the erase operation.

[0060] At time t0, the voltage level of waveform 460 can increase (e.g., ramp up) from an initial voltage level 463 (e.g., ground or 0V), while the voltage level of waveform 462 can remain at the initial voltage level. As a result, the voltage difference of waveform 464 can begin to increase by an amount. After time period 466, the voltage difference of waveform 464 can reach a target (e.g., desired) amount 461, and the voltage level of waveform 462 can increase from the initial voltage level at the same rate (e.g., the same ramp rate) as the voltage level of waveform 460 to maintain the amount 461 of the voltage difference of waveform 464.

[0061] After time period 468, the voltage level of waveform 460 can reach the target (e.g., desired) voltage level 467 to perform the erase operation. At this point, the voltage levels of waveforms 460 and 462 can be maintained, for example, by ceasing to increase their respective voltage levels. (Reference) Figure 4A The desired level of the GIDL current can only be generated after the time period 466 ends when the magnitude of the voltage difference 461 of waveform 464 reaches its target level.

[0062] During time period 466, the GG gate can generate a high longitudinal electric field to compensate for the displacement current, which is equal to the ramp rate of the voltage level of waveform 460 multiplied by the capacitance of its corresponding semiconductor pillar 340. To reduce the damage from these electric fields, the ramp rate can be reduced. Once the magnitude 461 of the voltage difference of waveform 464 reaches its target level, the desired level of the GIDL current with a lower longitudinal field can be generated, and the voltage level of the corresponding semiconductor pillar 340 can more easily follow the voltage level of the source 216 (or data line 204).

[0063] Figure 4B The waveform of the voltage level used to generate the GIDL current according to an embodiment is conceptually depicted. Figure 4B In the waveform, waveform 470 can represent the voltage level applied to source 216 (or data line 204), waveform 472 can represent the voltage level applied to control line 222 (or control line 224), and waveform 474 can represent the voltage difference between waveform 472 and waveform 470.

[0064] At time t0, the voltage level of waveform 470 may increase (e.g., ramp) from a first (e.g., initial) voltage level 473 (e.g., ground or 0V). The voltage level of waveform 472 may increase from a second (e.g., initial) voltage level 475 (e.g., negative voltage level) lower than the first voltage level 473 of waveform 470. The voltage difference between the second voltage level 475 and the first voltage level 473 may be selected to be substantially equal to (e.g., equal to) the desired offset level. As a result, the voltage difference of waveform 474 may reach its target (e.g., desired) magnitude 471 at or near time 0. The voltage level of waveform 472 may increase from the second voltage level 475 at the same rate (e.g., the same ramp rate) as the voltage level of waveform 470 to maintain the magnitude 471 of the voltage difference of waveform 474.

[0065] After time period 478, the voltage level of waveform 470 can reach the target (e.g., desired) voltage level 477 to perform the erase operation. At this time, the voltage levels of waveforms 470 and 472 can be maintained, for example, by ceasing to increase their respective voltage levels. (Reference) Figure 4B ,and Figure 4A Compared to the previous example, the desired level of GIDL current can be generated throughout the entire duration of the erase pulse or for a longer portion of the erase pulse duration. Therefore, exposure to high longitudinal electric fields can be mitigated. This can further promote higher ramp rates and / or higher offset levels for the erase pulse, thereby shortening the duration of the erase operation.

[0066] refer to Figure 4BThe voltage levels discussed are typically generated using a voltage generation system that utilizes digital-to-analog conversion. For example, a ramp voltage level can be generated in response to a counter. Figure 5 This is a depiction of a ramp voltage level 546 used in various embodiments. The ramp (e.g., increasing) voltage level has a voltage level that responds to a count (e.g., changing the voltage level). For example, as the count value increases, the voltage level of the ramp voltage level increases accordingly. The ramp voltage level 546 can approximate or more closely approximate a linear response by increasing the number of counts used to generate the same voltage level range.

[0067] Figure 6 It is used in conjunction with various embodiments for generating Figure 5 The block diagram depicts a voltage generation system of the type of ramp voltage level. Figure 6 The voltage generation system includes a counter 641 for generating counts. For example, counter 641 may have an output 643 for providing a bit pattern representing the count. Voltage generation circuitry 645 (e.g., a digital-to-analog converter (DAC)) may generate an analog voltage level in response to the output 643 of counter 641 (e.g., counting). DAC 645 may provide this voltage level at output 647. Output 647 of DAC 645 may be connected (e.g., selectively connected) to source 216 and / or data line 204.

[0068] Figure 7A A waveform of the voltage level used to generate GIDL current according to another embodiment is conceptually depicted. Figure 7A This can represent the voltage level applied during the erase operation. Figure 7A In the diagram, waveform 770 may represent the voltage level applied to source 216 (or data line 204), and waveform 772 may represent the voltage level applied to control line 222 (or control line 224). Waveform 770 may represent the erase pulse of an erase operation. Source 216 and data line 204 may each be referred to as nodes selectively connected to a series-connected string of memory cells, and the GG gates corresponding to control lines 222 and 224 respectively may be referred to as being connected between their respective nodes (e.g., source 216 or data line 204, respectively) and their corresponding series-connected strings of memory cells. This may include being connected (e.g., directly connected) to their respective nodes (e.g., source 216 or data line 204, respectively) and selectively connected to their corresponding series-connected strings of memory cells.

[0069] At time t0, waveforms 770 and 772 can each be at their initial voltage levels, for example, 0V. Also at time t0, for the time interval t0 to t1, the voltage level of waveform 770 can increase to a voltage level 7800 with a magnitude 782 higher than the initial voltage level, and the voltage level of waveform 772 can decrease to a voltage level 7840 with a magnitude 786 lower than the initial voltage level. The sum of magnitudes 782 and 786 can equal the desired offset of the erase operation.

[0070] At time t1, for the time interval t1 to t2, the voltage level of waveform 770 can increase to voltage level 7801, and the voltage level of waveform 772 can increase to voltage level 7841. The amount of increase in the voltage level of waveform 770 during the time interval t1 to t2 is equal to the difference between voltage level 7801 and voltage level 7800, while the amount of increase in the voltage level of waveform 772 during the time interval t1 to t2 is equal to the difference between voltage level 7841 and voltage level 7840. The amount of increase in the voltage level of waveform 770 during the time interval t1 to t2 is equal to the amount of increase in the voltage level of waveform 772 during the time interval t1 to t2, making the rate of increase assuming to be the same.

[0071] At time t2, for the time interval t2 to t3, the voltage level of waveform 770 can increase to voltage level 7802, and the voltage level of waveform 772 can increase to voltage level 7842. The increase in voltage level of waveform 770 during the time interval t2 to t3 is equal to the sum of voltage levels 7802 and 7802. \1 The difference between them, and the amount of increase in voltage level of waveform 772 during time period t2 to t3 can be equal to the difference between voltage level 7842 and voltage level 7841. The amount of increase in voltage level of waveform 770 during time period t2 to t3 can be equal to the amount of increase in voltage level of waveform 772 during time period t2 to t3, so that the rate of increase can be considered the same.

[0072] At time t3, for the time interval t3 to t4, the voltage level of waveform 770 can be increased to voltage level 780. X Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. X The increase in voltage level of waveform 770 during the time period t3 to t4 is equal to the increase in voltage level 780. X The difference between voltage level 7802 and voltage level 772, while the increase in voltage level of waveform 772 during time period t3 to t4 can be equal to voltage level 784. X With voltage level 784 XThe difference between them. The amount of increase in voltage level of waveform 770 during time period t3 to t4 can be equal to the amount of increase in voltage level of waveform 772 during time period t3 to t4, such that the rate of increase can be considered the same. The step size of waveforms 770 and 772 during time period t3 to t4 is depicted with dashed lines to indicate that more than one step of applied voltage level may occur between time t3 and time t4.

[0073] At time t4, for the time interval t4 to t5, the voltage level of waveform 770 can be increased to voltage level 780. N-2 Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. N-2 The increase in voltage level of waveform 770 during the time period t4 to t5 can be equal to the increase in voltage level 780. N-2 With voltage level 780 X The difference, and the increase in voltage level of waveform 772 during the time period t4 to t5 can be equal to the increase in voltage level 784. N-2 With voltage level 784 X The difference between them. The amount of increase in voltage level of waveform 770 during the time period t4 to t5 can be equal to the amount of increase in voltage level of waveform 772 during the time period t4 to t5, so that the rate of increase can be considered to be the same.

[0074] At time t5, for the time interval t5 to t6, the voltage level of waveform 770 can be increased to voltage level 780. N-1 Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. N-1 The increase in voltage level of waveform 770 during the time period t5 to t6 can be equal to the increase in voltage level 780. N-1 With voltage level 780 N-2 The difference between them, and the increase in voltage level of waveform 772 during the time period t5 to t6 can be equal to the increase in voltage level 784. N-1 With voltage level 784 N-2 The difference between them. The amount of increase in voltage level of waveform 770 during the time period t5 to t6 can be equal to the amount of increase in voltage level of waveform 772 during the time period t5 to t6, so that the rate of increase can be considered to be the same.

[0075] At time t6, for the time interval t6 to t7, the voltage level of waveform 770 can be increased to voltage level 780. N Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. N The increase in voltage level of waveform 770 during the time period t6 to t7 can be equal to the increase in voltage level 780. N With voltage level 780 N-1The difference between them, and the increase in voltage level of waveform 772 during the time period t6 to t7 can be equal to the increase in voltage level 784. N With voltage level 784 N-1 The difference between them. The amount of increase in voltage level of waveform 770 during the time period t6 to t7 can be equal to the amount of increase in voltage level of waveform 772 during the time period t6 to t7, so that the rate of increase can be considered to be the same.

[0076] At time t7, when waveform 770 has a voltage level of 780 N At this time, the voltage levels of waveforms 770 and 772 can stop increasing. During the time period t7 to t8, a voltage level can be applied to the control gate of memory cell 208, which is selectively connected to the source 216 (or data line 204) in series, and this voltage level can be expected (for example) in conjunction with the voltage level 780 applied to the source 216 (or data line 204). N The charge is removed from the data storage structure of the memory cell. At time t8, the voltage levels of waveforms 770 and 772 can be discharged to, for example, the initial voltage level. An erase verification operation can then be performed to determine whether the memory cell has been sufficiently erased or whether another (e.g., a higher) erase pulse can be applied.

[0077] The slope of the voltage level increase during a specific time period (e.g., t1 to t2, t2 to t3, t3 to t4, etc.) between time t1 and time t7 can be defined as the magnitude of the voltage level increase during that time period divided by the duration of that time period. For consecutive time periods t1 to t2, t2 to t3, t3 to t4, etc., the slope of the voltage level increase can be equal, making the rate of increase considered constant. In some embodiments, the magnitude and duration of these time periods can also be equal. Alternatively, for consecutive time periods t1 to t2, t2 to t3, t3 to t4, etc., the slope of the voltage level increase can include multiple different slope values, making the rate of increase considered variable.

[0078] Figure 7B A waveform of the voltage level used to generate the GIDL current is conceptually depicted according to a further embodiment. Figure 7B This can represent the voltage level applied during the erase operation. Figure 7BIn the diagram, waveform 770 may represent the voltage level applied to source 216 (or data line 204), and waveform 772 may represent the voltage level applied to control line 222 (or control line 224). Waveform 770 may represent the erase pulse of an erase operation. Source 216 and data line 204 may each be referred to as nodes selectively connected to a series-connected string of memory cells, and the GG gates corresponding to control lines 222 and 224, respectively, may be referred to as being connected (e.g., directly connected) to their corresponding nodes (e.g., source 216 or data line 204, respectively) and selectively connected to their corresponding series-connected strings of memory cells.

[0079] At time t i At this point, waveforms 770 and 772 can each be at their initial voltage level, for example, 0V. Similarly, at time t... i At this point, for the time period t i At t0, the voltage level of waveform 770 can be maintained at the initial voltage level, and the voltage level of waveform 772 can be reduced to a voltage level 784 that can have a value 771 lower than the initial voltage level. i The value 771 can be equal to the expected offset of the erase operation.

[0080] At time t0, for the time interval t0 to t1, the voltage level of waveform 770 can be increased to a voltage level 7800 that is higher than the initial voltage level 782, and the voltage level of waveform 772 can be increased to a voltage level 784 that is higher than the initial voltage level 7800. i The voltage level 7840 of the magnitude 782 makes the increase rate of waveforms 770 and 772 be considered to be the same for the time period t0 to t1.

[0081] At time t1, for the time interval t1 to t2, the voltage level of waveform 770 can increase to voltage level 7801, and the voltage level of waveform 772 can increase to voltage level 7841. The amount of increase in the voltage level of waveform 770 during the time interval t1 to t2 is equal to the difference between voltage level 7801 and voltage level 7800, while the amount of increase in the voltage level of waveform 772 during the time interval t1 to t2 is equal to the difference between voltage level 7841 and voltage level 7840. The amount of increase in the voltage level of waveform 770 during the time interval t1 to t2 is equal to the amount of increase in the voltage level of waveform 772 during the time interval t1 to t2, making the rate of increase assuming to be the same.

[0082] At time t2, for the time interval t2 to t3, the voltage level of waveform 770 can increase to voltage level 7802, and the voltage level of waveform 772 can increase to voltage level 7842. The increase in voltage level of waveform 770 during the time interval t2 to t3 is equal to the sum of voltage levels 7802 and 7802.\1 The difference between them, and the amount of increase in voltage level of waveform 772 during time period t2 to t3 can be equal to the difference between voltage level 7842 and voltage level 7841. The amount of increase in voltage level of waveform 770 during time period t2 to t3 can be equal to the amount of increase in voltage level of waveform 772 during time period t2 to t3, so that the rate of increase can be considered the same.

[0083] At time t3, for the time interval t3 to t4, the voltage level of waveform 770 can be increased to voltage level 780. X Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. X The increase in voltage level of waveform 770 during the time period t3 to t4 is equal to the increase in voltage level 780. X The difference between voltage level 7802 and voltage level 772, while the increase in voltage level of waveform 772 during time period t3 to t4 can be equal to voltage level 784. X With voltage level 784 X The difference between them. The amount of increase in voltage level of waveform 770 during time period t3 to t4 can be equal to the amount of increase in voltage level of waveform 772 during time period t3 to t4, such that the rate of increase can be considered the same. The step size of waveforms 770 and 772 during time period t3 to t4 is depicted with dashed lines to indicate that more than one step of applied voltage level may occur between time t3 and time t4.

[0084] At time t4, for the time interval t4 to t5, the voltage level of waveform 770 can be increased to voltage level 780. N-2 Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. N-2 The increase in voltage level of waveform 770 during the time period t4 to t5 can be equal to the increase in voltage level 780. N-2 With voltage level 780 X The difference, and the increase in voltage level of waveform 772 during the time period t4 to t5 can be equal to the increase in voltage level 784. N-2 With voltage level 784 X The difference between them. The amount of increase in voltage level of waveform 770 during the time period t4 to t5 can be equal to the amount of increase in voltage level of waveform 772 during the time period t4 to t5, so that the rate of increase can be considered to be the same.

[0085] At time t5, for the time interval t5 to t6, the voltage level of waveform 770 can be increased to voltage level 780. N-1 Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. N-1The increase in voltage level of waveform 770 during the time period t5 to t6 can be equal to the increase in voltage level 780. N-1 With voltage level 780 N-2 The difference between them, and the increase in voltage level of waveform 772 during the time period t5 to t6 can be equal to the increase in voltage level 784. N-1 With voltage level 784 N-2 The difference between them. The amount of increase in voltage level of waveform 770 during the time period t5 to t6 can be equal to the amount of increase in voltage level of waveform 772 during the time period t5 to t6, so that the rate of increase can be considered to be the same.

[0086] At time t6, for the time interval t6 to t7, the voltage level of waveform 770 can be increased to voltage level 780. N Furthermore, the voltage level of waveform 772 can be increased to voltage level 784. N The increase in voltage level of waveform 770 during the time period t6 to t7 can be equal to the increase in voltage level 780. N With voltage level 780 N-1 The difference between them, and the increase in voltage level of waveform 772 during the time period t6 to t7 can be equal to the increase in voltage level 784. N With voltage level 784 N-1 The difference between them. The amount of increase in voltage level of waveform 770 during the time period t6 to t7 can be equal to the amount of increase in voltage level of waveform 772 during the time period t6 to t7, so that the rate of increase can be considered to be the same.

[0087] At time t7, when waveform 770 has a voltage level of 780 N At this time, the voltage levels of waveforms 770 and 772 can stop increasing. During the time period t7 to t8, a voltage level can be applied to the control gate of memory cell 208, which is selectively connected to the source 216 (or data line 204) in series, and this voltage level can be expected (for example) in conjunction with the voltage level 780 applied to the source 216 (or data line 204). N The charge is removed from the data storage structure of the memory cell. At time t8, the voltage levels of waveforms 770 and 772 can be discharged to, for example, the initial voltage level. An erase verification operation can then be performed to determine whether the memory cell has been sufficiently erased or whether another (e.g., a higher) erase pulse can be applied.

[0088] The slope of the voltage level increase during a specific time period (e.g., t0 to t1, t1 to t2, t2 to t3, etc.) between time t0 and time t7 can be defined as the magnitude of the voltage level increase during that time period divided by the duration of that time period. For consecutive time periods t0 to t1, t1 to t2, t2 to t3, etc., the slope of the voltage level increase can be equal, making the rate of increase considered constant. Alternatively, for consecutive time periods t0 to t1, t1 to t2, t2 to t3, etc., the slope of the voltage level increase can include multiple different slope values, making the rate of increase considered variable. In some embodiments, the magnitude and duration of these time periods can vary. For example, the slope of the voltage level increase during the time period t0 to t1 (e.g., the first time period in a plurality of consecutive time periods) can be different from (e.g., greater than) the slope of the voltage level increase during the time period t1 to t2. In some embodiments, the slope of each of the plurality of consecutive time periods can be equal, except for the first time period in a plurality of consecutive time periods.

[0089] Figure 8 This is a flowchart of a method for operating a memory according to an embodiment. For example, Figure 8 The method can represent part of the erasure operation.

[0090] At 801, a positive first voltage level can be applied to a first node selectively connected to a series-connected string of memory cells, while a negative second voltage level is applied to the control gate of a transistor connected to the first node and selectively connected to the series-connected string of memory cells. For example, refer to... Figure 2A A first voltage level can be applied to source 216, while a second voltage level can be applied to control line 222. Alternatively, the first voltage level can be applied to data line 2040, and the second voltage level can be applied to control line 224. The voltage difference between the first and second voltage levels can be equal to the desired offset of the erase operation. For example, this action can correspond to... Figure 7A or Figure 7B The voltage level of waveform 770 at time t1, and corresponding to Figure 7A or Figure 7B The voltage level of waveform 772 at time t1.

[0091] Although it should be understood that this can be performed with respect to source 216 and control line 222 and / or with respect to data line 204 (e.g., one or more data lines 204) and control line 224. Figure 8 The method is described with reference to the source 216 corresponding to the first node of the series-connected memory cell string and the control line 222 corresponding to the voltage level applied to the control gate of the transistor 218 connected to the first node and selectively connected to the series-connected memory cell string. Figure 8The rest of the discussion.

[0092] At 803, the voltage level applied to the first node (e.g., applied to source 216) can be increased to a third voltage level (e.g., higher than the first voltage level), while the voltage level applied to the control gate of the transistor (e.g., applied to control line 222) can be increased to a fourth voltage level lower than the third voltage level and higher than the first voltage level. The voltage difference between the third and fourth voltage levels can be equal to the desired offset of the erase operation. For example, this action can correspond to... Figure 7A or Figure 7B The time period is from t1 to t7. Figure 7A or Figure 7B During the time period t1 to t7, the rate of increase of the voltage levels of waveforms 770 and 772 is equal. For some embodiments, in addition to being equal, the rate of increase of the voltage levels of waveforms 770 and 772 is... Figure 7A or Figure 7B The time period t1 to t7 can be constant or variable.

[0093] At 805, when the voltage level applied to the first node (e.g., applied to source 216) is at the third voltage level, a specific voltage level that can be expected to remove charge from the data storage structure of the memory cell can be applied to the control gate of the memory cell in the series-connected string of memory cells. For example, this action may correspond to Figure 7A or Figure 7B The time period t7 to t8. In some embodiments, this specific voltage level may be further applied before the voltage level applied to the first node is at the third voltage level (e.g., when the voltage level applied to the first node increases to the third voltage level). For example, it may be... Figure 7A or Figure 7B A specific voltage level is applied at time t0.

[0094] Figure 9 This is a flowchart of a method for operating a memory according to another embodiment. For example, Figure 9 The method can represent part of the erasure operation.

[0095] At 911, a negative first voltage level can be applied to the control gate of a transistor connected between the first node and the series-connected string of memory cells. This control gate can be directly connected to the first node and (e.g., selectively or directly) connected to the series-connected string of memory cells. As an example, refer to... Figure 2A A first voltage level may be applied to control line 222. Alternatively, a first voltage level may be applied to control line 224. The first voltage level may have an amount equal to the desired offset of the erase operation. For example, this action may correspond to... Figure 7AThe voltage level of waveform 772 at time t1, or corresponding to Figure 7B The voltage level of waveform 772 at time t0.

[0096] Although it should be understood that this can be performed with respect to source 216 and control line 222 and / or with respect to data line 204 (e.g., one or more data lines 204) and control line 224. Figure 9 The method is described with reference to the source 216 corresponding to the first node of the series-connected memory cell string and the control line 222 corresponding to the voltage level applied to the control gate of the transistor 218 connected to the first node and selectively connected to the series-connected memory cell string. Figure 9 The rest of the discussion.

[0097] At 913, the voltage level applied to the first node (e.g., applied to source 216) can increase at a specific rate, while the voltage level applied to the control gate of the transistor (e.g., applied to control line 222) can increase at that specific rate (e.g., simultaneously). The specific rate of increase can represent a constant rate of increase or a variable rate of increase. In this way, the voltage difference between the voltage level applied to the first node and the voltage level applied to the control gate of the transistor can be considered to remain constant, for example, equal to the desired offset of the erase operation. For example, this action could correspond to... Figure 7A The time period t1 to t7, or corresponding to Figure 7B The time period is from t0 to t7. As used herein, multiple actions performed simultaneously mean that each of these actions is executed for a corresponding time period, and each of these corresponding time periods partially or wholly overlaps with each of the remaining corresponding time periods. In other words, these actions are performed simultaneously for at least a period of time.

[0098] At point 915, when the voltage level applied to the first node (e.g., applied to source 216) reaches a specific voltage level, the increase in the voltage level applied to the first node and the increase in the voltage level applied to the control gate of the transistor (e.g., applied to control line 222) can be stopped. For example, this action may correspond to... Figure 7A or Figure 7B The time t7.

[0099] At 917, when the voltage level applied to the first node (e.g., applied to source 216) is at a specific voltage level, a voltage level that can be expected to remove charge from the data storage structure of the memory cell can be applied to the control gate of the memory cell in the series-connected string of memory cells. For example, this action may correspond to Figure 7A or Figure 7B The time period is from t7 to t8.

[0100] Figure 10 This is a flowchart of a method for operating a memory according to a further embodiment. For example, Figure 10 The method can represent part of the erasure operation.

[0101] At 1021, a first voltage level can be applied to a first node selectively connected to a series-connected string of memory cells, while simultaneously applying the first voltage level to the control gate of a transistor connected between the first node and the series-connected string of memory cells. This control gate can be directly connected to the first node and (e.g., selectively or directly) connected to the series-connected string of memory cells. As a reference... Figure 2A The first voltage level can be applied to source 216 and control line 222. Alternatively, the first voltage level can be applied to data line 2040 and control line 224. For example, this action could correspond to... Figure 7A The time t0. For example, the first voltage level may correspond to ground or 0V.

[0102] Although it should be understood that this can be performed with respect to source 216 and control line 222 and / or with respect to data line 204 (e.g., one or more data lines 204) and control line 224. Figure 10 The method is described with reference to the source 216 corresponding to the first node of the series-connected memory cell string and the control line 222 corresponding to the voltage level applied to the control gate of the transistor 218 connected to the first node and selectively connected to the series-connected memory cell string. Figure 10 The rest of the discussion.

[0103] At point 1023, the voltage level applied to the first node (e.g., to source 216) can be increased to a second voltage level, while the voltage level applied to the control gate of the transistor (e.g., to control line 222) can be decreased to a third voltage level. The voltage difference between the second and third voltage levels can be equal to the desired offset of the erase operation. For example, this action can correspond to... Figure 7A The voltage level of waveform 770 at time t0 increases, and corresponds to Figure 7A The voltage level of waveform 772 at time t0 decreases.

[0104] At 1025, for each of a plurality of consecutive time periods, the voltage level applied to the first node (e.g., applied to source 216) can be increased by a corresponding amount during that time period, and the voltage level applied to the control gate of the transistor (e.g., applied to control line 222) can be increased by a corresponding amount during that time period. This action can correspond to Figure 7ADuring consecutive time periods from t1 to t7 (e.g., t1 to t2, t2 to t3, t3 to t4, etc.), the voltage levels of waveforms 770 and 772 increase. For example, 7801 minus 7800 equals 7841 minus 7840, and 7802 minus 7801 equals 7842 minus 7841. X Subtracting 7802 equals 784 X Subtract 7842, etc.

[0105] At 1027, after the last time period of a series of consecutive time periods (e.g., time period t6 to t7), a voltage level that can be expected to remove charge from the data storage structure of the memory cell can be applied to the control gate of the memory cell in the series-connected string of memory cells. For example, this action may correspond to Figure 7A The time period is from t7 to t8.

[0106] Figure 11 This is a flowchart of a method for operating a memory according to yet another embodiment. For example, Figure 11 The method can represent part of the erasure operation.

[0107] At 1131, a first voltage level can be applied to a first node selectively connected to a series-connected string of memory cells, while simultaneously applying the first voltage level to the control gate of a transistor connected between the first node and the series-connected string of memory cells. This control gate can be directly connected to the first node and (e.g., selectively or directly) connected to the series-connected string of memory cells. As a reference... Figure 2A The first voltage level can be applied to source 216 and control line 222. Alternatively, the first voltage level can be applied to data line 2040 and control line 224. For example, this action could correspond to... Figure 7B Time t i For example, the first voltage level could correspond to ground or 0V.

[0108] Although it should be understood that this can be performed with respect to source 216 and control line 222 and / or with respect to data line 204 (e.g., one or more data lines 204) and control line 224. Figure 11 The method is described with reference to the source 216 corresponding to the first node of the series-connected memory cell string and the control line 222 corresponding to the voltage level applied to the control gate of the transistor 218 connected to the first node and selectively connected to the series-connected memory cell string. Figure 11 The rest of the discussion.

[0109] At 1133, the voltage level applied to the first node (e.g., to source 216) can be maintained at a first voltage level, while the voltage level applied to the control gate of the transistor (e.g., to control line 222) can be reduced to a second voltage level. The magnitude of the second voltage level can be equal to the desired offset of the erase operation. For example, this action can correspond to... Figure 7B Time period t i The voltage level of waveform 772 decreases at t0.

[0110] At 1135, for each of a plurality of consecutive time periods, the voltage level applied to the first node (e.g., applied to source 216) may increase by a corresponding amount during that time period, and the voltage level applied to the control gate of the transistor (e.g., applied to control line 222) may also increase by a corresponding amount during that time period. This action may correspond to Figure 7B The voltage levels of waveforms 770 and 772 increase during consecutive time periods from t0 to t7 (e.g., t0 to t1, t1 to t2, t2 to t3, etc.), for example, where 7800 can be equal to 7840 minus 784. i Where 7801 minus 7800 equals 7841 minus 7840, 7802 minus 7801 equals 7842 minus 7841, 780 X Subtracting 7802 equals 784 X Subtract 7842, etc.

[0111] At 1137, after the last time period of a series of consecutive time periods (e.g., time period t6 to t7), a voltage level that can be expected to remove charge from the data storage structure of the memory cell can be applied to the control gate of the memory cell in the series-connected string of memory cells. For example, this action could correspond to Figure 7B The time period is from t7 to t8.

[0112] in conclusion

[0113] Although specific embodiments have been shown and described herein, those skilled in the art will understand that any arrangement intended to achieve the same results can replace the specific embodiments shown. Many modifications to the embodiments will be known to those skilled in the art. Therefore, this application is intended to cover any modifications or variations of the embodiments.

Claims

1. A method for operating a memory, comprising: During the operation of erasing memory cells in a serially connected string of memory cells: A positive first voltage level is applied to a first node selectively connected to the series-connected string of memory cells, while a negative second voltage level is applied to the control gate of a transistor connected between the first node and the series-connected string of memory cells. as well as The voltage level applied to the first node is increased to a third voltage level, while the voltage level applied to the control gate of the transistor is increased to a fourth voltage level that is lower than the third voltage level and higher than the first voltage level.

2. The method according to claim 1, further comprising: When the voltage level applied to the first node is at the third voltage level, a voltage level intended to remove charge from the data storage structure of the memory cell is applied to the control gate of the memory cell in the series-connected string of memory cells.

3. The method of claim 2, further comprising applying the voltage level to the control gate of the memory cell before increasing the voltage level applied to the first node to the third voltage level.

4. The method according to claim 1, wherein the voltage difference between the first voltage level and the second voltage level is equal to the voltage difference between the third voltage level and the fourth voltage level.

5. The method of claim 4, wherein the voltage difference between the first voltage level and the second voltage level is equal to a voltage difference sufficient to generate a gate-drain leakage (GIDL) current through the transistor.

6. The method of claim 4, wherein increasing the voltage level applied to the first node to the third voltage level has a specific duration, and wherein increasing the voltage level applied to the control gate of the transistor to the fourth voltage level has the specific duration.

7. The method of claim 1, wherein increasing the voltage level applied to the first node and increasing the voltage level applied to the control gate of the transistor comprises increasing the voltage level applied to the first node at a specific rate and increasing the voltage level applied to the control gate of the transistor at the specific rate.

8. The method of claim 7, wherein increasing the voltage level applied to the first node at the specific rate and increasing the voltage level applied to the control gate of the transistor at the specific rate further comprises increasing the voltage level applied to the first node and increasing the voltage level applied to the control gate of the transistor at a variable rate.

9. The method of claim 1, wherein increasing the voltage level applied to the first node to the third voltage level comprises using a first plurality of voltage level step changes to increase the voltage level applied to the first node to the third voltage level, and wherein increasing the voltage level applied to the control gate of the transistor to the fourth voltage level comprises using a second plurality of voltage level step changes to increase the voltage level applied to the control gate of the transistor to the fourth voltage level.

10. The method of claim 1, further comprising: A positive fifth voltage level is applied to a second node selectively connected to the series-connected string of memory cells, while a negative sixth voltage level is applied to the control gate of the transistor connected between the second node and the series-connected string of memory cells. as well as The voltage level applied to the second node is increased to a seventh voltage level, while the voltage level applied to the control gate of the transistor connected to the second node is increased to an eighth voltage level that is lower than the seventh voltage level and higher than the fifth voltage level.

11. The method of claim 10, wherein the fifth voltage level is equal to the first voltage level, the sixth voltage level is equal to the second voltage level, the seventh voltage level is equal to the third voltage level, and the eighth voltage level is equal to the fourth voltage level.

12. A method of operating a memory, comprising: During the operation of erasing memory cells of a serially connected string of memory cells, a negative first voltage level is applied to the control gate of the transistor connected between the first node and the serially connected string of memory cells. The voltage level applied to the first node is increased at a specific rate, while the voltage level applied to the control gate of the transistor is increased at the same specific rate. as well as When the voltage level applied to the first node reaches a specific voltage level, the increase of the voltage level applied to the first node and the increase of the voltage level applied to the control gate of the transistor are stopped.

13. The method of claim 12, further comprising: When the voltage level applied to the first node is at the specific voltage level, a voltage level that is intended to remove charge from the data storage structure of the memory cell is applied to the control gate of the memory cell in the series-connected string of memory cells.

14. The method of claim 13, further comprising applying the voltage level to the control gate of the memory cell before the voltage level applied to the first node and increasing at the specific rate reaches the specific voltage level.

15. The method of claim 12, wherein applying the negative first voltage level to the control gate of the transistor connected between the first node and the series-connected memory cell string comprises applying the negative first voltage level to the control gate of the transistor connected between the series-connected memory cell string and a particular node selected from a group consisting of a source selectively connected to the series-connected memory cell string and data lines selectively connected to the series-connected memory cell string.

16. The method of claim 12, wherein applying the negative first voltage level to the control gate of the transistor comprises reducing the voltage level applied to the control gate of the transistor from an initial voltage level to the first voltage level, and wherein the method further comprises: The voltage level applied to the first node is increased from the initial voltage level to the second voltage level, while the voltage level applied to the control gate of the transistor is decreased from the initial voltage level to the first voltage level.

17. The method of claim 12, wherein applying the negative first voltage level to the control gate of the transistor comprises reducing the voltage level applied to the control gate of the transistor from an initial voltage level to the first voltage level, and wherein the method further comprises: The voltage level applied to the first node is maintained at the initial voltage level, while the voltage level applied to the control gate of the transistor is reduced from the initial voltage level to the first voltage level.

18. The method of claim 12, wherein increasing the voltage level applied to the first node at the specific rate includes increasing the voltage level applied to the first node at a variable rate.

19. The method of claim 12, further comprising: A negative second voltage level is applied to the control gate of the transistor connected between the second node and the series-connected string of memory cells; The voltage level applied to the second node is increased at the specified rate, and the voltage level applied to the control gate of the transistor connected between the second node and the series-connected string of memory cells is increased at the specified rate. as well as When the voltage level applied to the second node reaches the third voltage level, the increase in the voltage level applied to the second node stops, and the increase in the voltage level applied to the control gate of the transistor connected between the second node and the series-connected memory cell string also stops.

20. The method of claim 19, wherein the second voltage level is equal to the first voltage level, and wherein the third voltage level is equal to the specific voltage level.

21. The method of claim 19, wherein the first node is a data line selectively connected to the serially connected string of memory cells, and wherein the second node is selectively connected to the source of the serially connected string of memory cells.

22. The method of claim 12, wherein the transistor connected between the first node and the serially connected string of memory cells comprises a single transistor directly connected to the first node and directly connected to the serially connected string of memory cells.

23. A memory comprising: A memory cell array, the memory cell array comprising a plurality of serially connected memory cell strings; as well as A controller for accessing the memory cell array, wherein the controller is configured to cause the memory to, during the operation of erasing memory cells of the plurality of cascaded memory cell strings: A first voltage level is applied to a first node selectively connected to the series-connected string of memory cells, and the first voltage level is also applied to the control gate of a transistor connected between the first node and the series-connected string of memory cells. The voltage level applied to the first node is increased to a second voltage level, while the voltage level applied to the control gate of the transistor is decreased to a third voltage level; as well as For each of the multiple consecutive time periods: The voltage level applied to the first node will be increased by a corresponding amount during the time period; as well as During the time period, the voltage level applied to the control gate of the transistor is increased by the corresponding amount.

24. The memory of claim 23, wherein the controller is further configured to cause the memory to: After the last of the plurality of consecutive time periods, a voltage level intended to remove charge from the data storage structure of the memory cell is applied to the control gate of the memory cell in the series-connected string of memory cells.

25. The memory of claim 23, wherein the controller is configured to cause the memory to apply the first voltage level to the first node, comprising the controller being configured to cause the memory to apply the first voltage level to a node selected from a group consisting of sources selectively connected to the series-connected memory cell string and data lines selectively connected to the series-connected memory cell string.

26. The memory of claim 23, wherein the controller is configured to cause the memory to apply the first voltage level to the first node, further comprising the controller being configured to cause the memory to apply a ground voltage to the first node.

27. The memory of claim 23, wherein the voltage difference between the second voltage level and the third voltage level is configured to generate a gate-induced drain (GIDL) current from the first node through the transistor.

28. The memory of claim 23, wherein the corresponding value of a specific time period among the plurality of consecutive time periods is greater than the corresponding value of different time periods among the plurality of consecutive time periods.

29. The memory of claim 28, wherein the specific time period is a first time period among the plurality of consecutive time periods.

30. The memory of claim 29, wherein the corresponding value of each of the plurality of consecutive time periods other than the specific time period is the same value.

31. A memory comprising: A memory cell array, the memory cell array comprising a plurality of serially connected memory cell strings; as well as A controller for accessing the memory cell array, wherein the controller is configured to cause the memory to, during the operation of erasing memory cells of the plurality of cascaded memory cell strings: A first voltage level is applied to a first node selectively connected to the series-connected string of memory cells, and the first voltage level is also applied to the control gate of a transistor connected between the first node and the series-connected string of memory cells. The voltage level applied to the first node is maintained at the first voltage level, while the voltage level applied to the control gate of the transistor is reduced to the second voltage level; as well as For each of the multiple consecutive time periods: The voltage level applied to the first node will be increased by a corresponding amount during the time period; as well as During the time period, the voltage level applied to the control gate of the transistor is increased by the corresponding amount.

32. The memory of claim 31, wherein the controller is further configured to cause the memory to: After the last of the plurality of consecutive time periods, a voltage level intended to remove charge from the data storage structure of the memory cell is applied to the control gate of the memory cell in the series-connected string of memory cells.

33. The memory according to claim 31, wherein the corresponding value of a specific time period in the plurality of consecutive time periods is greater than the corresponding value of a subsequent time period in the plurality of consecutive time periods.

34. The memory of claim 33, wherein the duration of the specific time period is greater than the duration of the subsequent time period.

35. The memory of claim 33, wherein the slope of the voltage increase during the specific time period is greater than the slope of the voltage increase during the subsequent time periods.

36. A memory comprising: A memory cell array, the memory cell array comprising a plurality of serially connected memory cell strings; as well as A controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the method according to any one of claims 1 to 22.

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