A general peripheral interface test system for chips

Abstract

The present invention provides a chip general peripheral interface test system, which includes a PC-side test script, an interface conversion device, a gateway, and a verification platform. Among them, the PC-side test script includes methods such as reading, writing, and controlling the interface conversion device, as well as the device management function of the interface conversion device; the interface conversion device is configured to drive the upstream and downstream interfaces, perform protocol conversion on the upstream and downstream interfaces, and provide an interface access RPC service for the PC-side test script; the gateway is configured to perform network access conversion on the upstream interface of the interface conversion device; the verification platform is configured to complete the configuration and read / write functions of the interface, and receive test instructions or test data from the PC-side test script. By converting different chip interfaces into a unified interface, the present invention can meet the unified testing and automated testing of multiple interfaces, multiple verification platforms, and multiple test PCs.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to a general external device interface test system for chips. Background Art

[0002] With the progress of manufacturing technology, the size of transistors has become smaller and smaller, the scale of chips has become larger and larger, and the energy efficiency and performance have been continuously improved. As an integrated circuit with dedicated functions, a System-on-a-Chip (SOC) contains a complete circuit system and embeds a software program, and its design is usually very complex. Due to the continuous improvement of the complexity of chip design and performance complexity, higher requirements are put forward for the system test schemes of chip design companies and chip application manufacturers.

[0003] There are mainly two existing chip software test and verification architectures: First, download all the test code (including test vectors) and module driver code into the test chip; Second, separate the test code (including test vectors) and module driver. The former is stored in the form of a script on the PC side, and the latter is downloaded to the test chip, and the serial port is used as the connection between the PC and the verification platform. When testing the communication interface module, both architectures use the communication interface on the test control board to transmit data with the PC. The disadvantage of the first architecture is that the total code amount is limited by the capacity of the chip to be tested, and random and automated tests cannot be completed. This is solved in the second architecture, but the second architecture requires manual interface switching, the serial port data throughput is too low, different interfaces require different interface conversion devices, the interface conversion device often can only provide single interface conversion ability, the problem of unable to achieve multi-interface transmission at the same time, and different interface conversion devices require different programming interfaces. These problems will seriously affect the work efficiency and test coverage of software testing. The need for manual interface switching indicates that the verification platform does not achieve true automation. The low serial port data throughput and single interface conversion device are not conducive to the standardization of test scripts, increase the equipment cost at the same time, and cannot perform automatic transmission on multiple interfaces at the same time. It cannot meet the test requirements in the current situation where multi-interface chip applications are developing rapidly.

[0004] Therefore, one of the problems to be solved currently is to develop a general peripheral interface test system that converts different general chip interfaces into a unified upstream interface and interconnects them through a network; it is convenient to realize the access and control of the interface and the management of the interface conversion device. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a chip general peripheral interface test system, which can convert different chip interfaces into a unified interface through a PC - side test framework, an interface conversion device, and a verification platform, and can meet the unified test and automated test requirements for multiple interfaces, multiple verification platforms, and multiple test PCs.

[0006] Based on the above - mentioned purpose, the present invention provides a chip general peripheral interface test system, which includes a PC - side test script, an interface conversion device, a gateway, and a verification platform; wherein,

[0007] The PC - side test script is for methods such as reading, writing, and controlling the interface conversion device and the device management function of the interface conversion device; the interface conversion device includes an upstream and a downstream driver module, and an upstream and a downstream interface protocol conversion module; the upstream and downstream driver modules are configured to drive the upstream and downstream interfaces, and the upstream and downstream interface protocol conversion modules are for upstream and downstream interface protocol conversion and providing an interface access RPC service for the PC - side test script;

[0008] The gateway is configured to perform network access conversion on the upstream interface of the interface conversion device;

[0009] The verification platform includes an interface to be tested and a control module; the test interface driver is configured to complete the configuration and read - write functions of the interface; the control module is configured to receive test instructions or test data from the PC - side test script.

[0010] In some embodiments, the PC - side test script of the present application includes a device management module and an interface module. Among them, the device management module extracts information from the broadcast information of the interface conversion device received from the network through a broadcast protocol and stores the information in a device linked list; the interface module is configured to abstract the interfaces into classes respectively, and each class provides an interface access or control method for the interface.

[0011] In some embodiments, the interface conversion device of the present application includes a hardware driver module, a network configuration module, an interface service module, and a broadcast module, and each interface conversion device provides an interface conversion function.

[0012] In some embodiments, the hardware driver module of the present application is specifically an interface driver, which is configured to control the interface reading, writing, and configuration methods.

[0013] In some embodiments, the network configuration module of the present application is configured to set the Wi - Fi connection and configuration of the interface conversion device.

[0014] In some embodiments, the network configuration module of the present application being configured to set the Wi - Fi connection and configuration of the interface conversion device specifically includes,

[0015] The distribution network module broadcasts via BLE. The mobile terminal receives this broadcast, identifies the device, confirms the connection between the mobile terminal and the interface conversion device, and connects by inputting Wi-Fi information.

[0016] Synchronously, configure the interface conversion device.

[0017] In some embodiments, the interface service module of the present application is configured to share the interface driving method to the test PC side in the network through the RPC service.

[0018] In some embodiments, the broadcast module of the present application broadcasts its device information to the network through UDP broadcast.

[0019] In some embodiments, the verification platform of the present application is a chip simulation environment based on the FPGA platform.

[0020] In some embodiments, the verification platform of the present application includes an interface to be tested and a control module; wherein, the interface driver of the interface to be tested is configured to complete the configuration and read / write functions of the interface; the control module is configured to receive test instructions or test data from the test script of the PC side.

[0021] The present invention has at least the following beneficial technical effects:

[0022] 1. The system of the present application includes a PC-side test framework, an interface conversion device, and a verification platform. By setting the interface conversion device, different chip interfaces are converted into a unified interface, which can meet the unified testing and automated testing of multiple interfaces, multiple verification platforms, and multiple test PCs.

[0023] 2. The present application connects multiple interface conversion devices to a single or multiple verification PC sides through Wi-Fi wireless connection, simplifies and unifies the interface connection method. Each interface conversion device can operate independently to achieve parallel testing of multiple interfaces, and can also achieve joint verification of multiple verification platforms, with high efficiency.

[0024] 3. The present application shares more than one verification platform for multiple test PC sides to use. The high speed of the Wi-Fi bandwidth can meet the requirements of big data and low-latency testing.

[0025] 4. The present application adds an interface conversion device, abstracts different interfaces into unified read, write, or control methods, and shares these methods to the test PC side through the RPC protocol. When the test PC develops using Python scripts, it only needs to implement the test logic, which greatly improves the efficiency of test verification and the reusability of test code, and can achieve automated testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0027] Figure 1 FIG. is a schematic structural diagram of a chip general peripheral interface test system provided according to an embodiment of the present invention;

[0028] Figure 2 FIG. is a timing diagram of a general reception test system provided according to an embodiment of the present invention;

[0029] Figure 3 FIG. is a framework architecture diagram of a PC-side test script provided according to an embodiment of the present invention;

[0030] Figure 4 FIG. is a structural diagram of a device management module provided according to an embodiment of the present invention;

[0031] Figure 5 FIG. is an architecture diagram of an interface conversion device provided according to an embodiment of the present invention;

[0032] Figure 6 FIG. is an architecture diagram of a verification platform provided according to an embodiment of the present invention;

[0033] Figure 7 FIG. is a schematic diagram of a computer-readable storage medium of a chip general peripheral interface test system provided according to an embodiment of the present invention;

[0034] Figure 8 FIG. is a schematic hardware structure diagram of a chip general peripheral interface test system provided according to an embodiment of the present invention. Detailed Embodiments

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0036] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units inherently includes other steps or units.

[0037] For the above purposes, in the first aspect of the embodiments of the present invention, an embodiment of a chip general peripheral interface test system is proposed. As Figure 1 shown, a chip general peripheral interface test system provided by the present invention is as follows, which includes:

[0038] A PC-side test script, an interface conversion device, a gateway, and a verification platform; where

[0039] The PC-side test script includes methods such as reading, writing, and controlling the interface conversion device, as well as the device management function of the interface conversion device; the interface conversion device includes an upstream and a downstream driver module, and an upstream and a downstream interface protocol conversion module; the upstream and downstream driver modules are configured to drive the upstream and downstream interfaces, and the upstream and downstream interface protocol conversion modules perform upstream and downstream interface protocol conversion and provide an interface access RPC service for the PC-side test script;

[0040] The gateway is configured to perform network access conversion on the upstream interface of the interface conversion device;

[0041] The verification platform includes an interface to be tested and a control module; the test interface driver is configured to complete the configuration and read / write functions of the interface; the control module is configured to receive test instructions or test data from the PC-side test script.

[0042] In the embodiments of the present invention, the TCP (Transmission Control Protocol) is a connection-oriented, reliable, byte-stream-based transport layer communication protocol. The UDP (User Datagram Protocol) is a connectionless protocol provided to user processes, which only transmits data without performing correctness checks. RPC (Remote Procedure Call), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit) refers to an integrated circuit designed and manufactured according to the requirements of specific users and the needs of specific electronic systems;

[0043] UART (Universal Asynchronous Receiver / Transmitter) is a general-purpose serial data bus configured for asynchronous communication;

[0044] I2C (Inter-Integrated Circuit) is a simple, two-way, two-wire synchronous serial bus;

[0045] SPI: Serial Peripheral Interface, a high-speed, full-duplex, synchronous communication bus;

[0046] GPIO: General-purpose input / output;

[0047] AD: Analog to Digital Convert;

[0048] DA: Digital to Analog Convert;

[0049] Wi-Fi: A short-range wireless technology and a network transmission standard;

[0050] BLE: Bluetooth Low Energy (also known as Bluetooth LE, BLE, old trademark Bluetooth Smart), also known as low-power Bluetooth, is a personal area network technology.

[0051] In this embodiment, the general interface test method, as Figure 2 shown, includes the following test contents,

[0052] which can be divided into protocol interface tests and non-protocol interface tests:

[0053] 1. Protocol interface tests

[0054] Data sending process

[0055] (1) The PC-side test script performs a data write operation through the RPC call method and passes in the data to be written;

[0056] (2) The interface conversion device receives the RPC request and obtains the data to be written, sends the data to the verification platform through the interface, and the interface conversion device returns the operation result through the RPC protocol;

[0057] (3) The verification platform receives the data described in step (2) and performs tests;

[0058] (4) The PC-side test script obtains the RPC call result;

[0059] Data reading process

[0060] (1) The verification platform sends verification data to the interface conversion device through the interface;

[0061] (2) The interface conversion device receives the verification data and saves it;

[0062] (3) The PC - side test script performs data read operations through the RPC call method;

[0063] (4) The interface conversion device receives the RPC request and returns the verification data obtained from the interface to the PC - side through the RPC protocol;

[0064] (5) The PC - side test script obtains the RPC call result and the returned verification data.

[0065] 2 Non - protocol interface testing

[0066] Output control

[0067] (1) The PC - side test script performs interface output control operations through the RPC call method;

[0068] (2) The interface conversion device receives the RPC request and obtains the control data. The interface conversion device controls the interface output and returns the operation result through the RPC protocol;

[0069] Input acquisition

[0070] (1) The PC - side test script performs interface input acquisition operations through the RPC call method

[0071] (2) The interface conversion device receives the RPC request and obtains the control data. The interface conversion device obtains the interface input value and returns the operation result and the acquired signal through the RPC protocol.

[0072] In this embodiment, the PC - side test framework is as Figure 3 shown. The PC - side test framework includes a device management module and an interface module (including UART interfaces, SPI interfaces, I2C interfaces, GPIO interfaces, AD / DA interfaces, etc.).

[0073] Among them, the device management module is shown in Figure 4. It extracts information such as its ID, device type, and verification platform from the broadcast information of the interface conversion device received from the network through the broadcast protocol and stores it in the device linked list. When the device management module receives the broadcast information sent by the interface conversion device three consecutive times and it is not in the device linked list, then this device is added to the device linked list.

[0074] At the same time, the device management module monitors the status of the interface conversion device in real - time. When no new broadcast information of the device in the linked list is received for 30 consecutive seconds, this device will be deleted from the device linked list; the interface module abstracts different classes for different interfaces, and each class provides its own interface access or control methods for the test script to use.

[0075] Among them, when instantiating a class, the ID of the interface and the initialization parameters of the interface need to be provided to match the corresponding interface conversion device in the device list and bind it. Subsequently, this instance can be used to perform read / write or control operations with the bound interface conversion device, which helps improve efficiency.

[0076] In this embodiment, taking Wi-Fi as the uplink interface of the interface conversion device as an example, as shown in Figure 5, the interface conversion device includes a hardware driver, a network configuration module, an interface service, and a broadcast module. An interface conversion device provides the conversion function of one interface.

[0077] Among them, the hardware driver module is configured for interface driving to implement control methods such as reading, writing, and configuring the interface, BLE driver and protocol stack, Wi-Fi driver and protocol stack;

[0078] The network configuration module is configured to set the Wi-Fi connection work and configuration work of the interface conversion device. The specific method is as follows:

[0079] First, the network configuration module broadcasts through BLE, enabling the mobile terminal to receive this broadcast and identify the device. After user confirmation, the mobile terminal can be connected to the interface conversion device. The user can input Wi-Fi information for connection or configure the interface conversion device;

[0080] The interface service module is configured to share control methods such as reading, writing, and configuring the interface driver to the test PC side in the network through the RPC service;

[0081] The broadcast module broadcasts its device information to the network at a certain frequency in the form of UDP broadcast. The broadcast information is encrypted by AES to ensure security, and the protocol is shown in Table 1.

[0082] Table 1 Interface conversion device broadcast protocol

[0083]

[0084] Note: U8 refers to an 8-bit unsigned integer, U16 refers to a 16-bit unsigned integer, and U32 refers to a 32-bit unsigned integer

[0085] The verification platform described in this embodiment is as Figure 6 shown. The verification platform is a chip simulation environment based on the FPGA platform; it includes the interface to be tested and a control module. Among them, the interface driver of the interface to be tested is configured to complete the configuration and read / write functions of the interface;

[0086] The control module is configured to receive test instructions or test data from the test script of the PC side.

[0087] An embodiment of the present invention also provides a computer-readable storage medium,Figure 7 A schematic diagram of a computer-readable storage medium for implementing a method for testing a general-purpose peripheral interface of a chip according to an embodiment of the present invention is shown. As Figure 7 shown, the computer-readable storage medium 3 stores computer program instructions 31, and the computer program instructions 31 can be executed by a processor. When the computer program instructions 31 are executed, the method of any of the above embodiments is implemented.

[0088] It should be understood that, without conflict, all the embodiments, features, and advantages described above for the method for testing the general-purpose peripheral interface of a chip according to the present invention are equally applicable to the system and storage medium configured for testing the general-purpose peripheral interface of a chip according to the present invention.

[0089] An embodiment of the present invention further provides a computer device, including a memory 402 and a processor 401. A computer program is stored in the memory, and when the computer program is executed by the processor, the method of any of the above embodiments is implemented.

[0090] As Figure 8 shown, it is a schematic hardware structure diagram of an embodiment of a computer device for implementing a method for testing a general-purpose peripheral interface of a chip according to the present invention. Taking the computer device as shown Figure 8 as an example, in this computer device, there is a processor 401 and a memory 402, and it may further include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403, and the output device 404 can be connected through a bus or other means, Figure 8 and here, the connection through the bus is taken as an example. The input device 403 can receive input digital or character information, and generate key signal inputs related to user settings and function controls of the system for testing the general-purpose peripheral interface of the chip. The output device 404 may include a display device such as a display screen.

[0091] The memory 402, as a non-volatile computer-readable storage medium, can be configured to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for testing the chip general peripheral interface in the embodiments of the present application. The memory 402 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created by using the method for testing the chip general peripheral interface, etc. In addition, the memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 402 may optionally include a memory remotely disposed relative to the processor 401, and these remote memories can be connected to the local module through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0092] The processor 401 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 402, that is, implements the method for testing the chip general peripheral interface in the above method embodiments.

[0093] Finally, it should be noted that the computer-readable storage medium (for example, the memory) herein can be a volatile memory or a non-volatile memory, or can include both volatile memory and non-volatile memory. By way of example and not limitation, non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), and this RAM can serve as an external cache memory. By way of example and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include but are not limited to these and other suitable types of memory.

[0094] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithmic steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the functions have been generally described in terms of the various illustrative components, blocks, modules, circuits, and steps. Whether such functions are implemented as software or hardware depends upon the particular application and the design constraints imposed on the overall system. The functions that can be implemented in various ways for each particular application by those skilled in the art, but such implementation decisions should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0095] The various exemplary logical blocks, modules, and circuits described in connection with the disclosure herein can be implemented or performed using the following components designed to be configured to perform the functions herein: a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP and / or any other such configuration.

[0096] The above are exemplary embodiments of the disclosure of the present invention, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosure of the embodiments of the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements of the disclosure of the embodiments of the present invention may be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0097] It should be understood that, as used herein, unless the context clearly supports the exception, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the associated listed items. The above serial numbers of the disclosed embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0098] Those of ordinary skill in the art should understand that any discussion of the above embodiments is merely exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. A general peripheral interface test system for a chip, characterized in that The system includes a PC - side test script, an interface conversion device, a gateway, and a verification platform; among them, the PC - side test script includes a device management module and an interface module. Among them, the device management module extracts information from the broadcast information of the interface conversion device received from the network through the broadcast protocol and stores the information in the device linked list; the interface module is configured to abstract the interfaces into classes respectively, and each class provides interface access or control methods for the interfaces; the interface conversion device includes a hardware driver module, a network configuration module, an interface service module, and a broadcast module, and each interface conversion device provides an interface conversion function; The PC - side test script includes methods for reading, writing, and controlling the interface conversion device and the device management function of the interface conversion device; the interface conversion device includes an upstream and a downstream driver module, and an upstream and a downstream interface protocol conversion module; The upstream and downstream driver modules are configured to drive the upstream and downstream interfaces respectively, and the upstream and downstream interface protocol conversion modules are configured for upstream and downstream interface protocol conversion. The interface conversion device provides an interface access RPC service for the PC - side test script; The gateway is configured to perform network access conversion on the upstream interface of the interface conversion device; The verification platform includes an interface to be tested and a control module; the driver of the interface to be tested is configured to complete the configuration, reading, and writing functions of the interface; and, the control module is configured to receive test instructions or test data from the PC - side test script; The interface service module is configured to share the interface driver method through the RPC service with the test PC - sides within the network.

2. The chip general peripheral interface test system according to claim 1, wherein The hardware driver module is an interface driver, which is configured to control interface reading, writing, and configuration.

3. The chip general peripheral interface test system according to claim 1, characterized in that, The network configuration module is configured to set the Wi - Fi connection and configuration of the interface conversion device.

4. The general peripheral interface test system for a chip according to claim 3, wherein The network configuration module is configured to set the Wi - Fi connection and configuration of the interface conversion device, which specifically includes: The network configuration module broadcasts through BLE. The mobile terminal receives this broadcast and identifies the device, confirms the connection between the mobile terminal and the interface conversion device, and connects by inputting Wi - Fi information; and configures the interface conversion device.

5. A chip general peripheral interface test system according to claim 1, characterized in that The broadcast module broadcasts its device information to the network through UDP broadcast.

6. The chip general peripheral interface test system according to claim 1, characterized in that, The verification platform is a chip simulation environment based on the FPGA platform.

7. The chip general peripheral interface test system according to claim 1 or 6, characterized in that, The verification platform includes an interface to be tested and a control module; among them, the interface driver of the interface to be tested is configured to complete the configuration, reading, and writing functions of the interface; the control module is configured to receive test instructions or test data from the PC - side test script.

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