Chip Design File Generation Method, Device, Chip Design Method, and Device

Abstract

The present application provides a method and apparatus for generating a chip design file, a chip design method and apparatus. The method for generating a chip design file includes: obtaining a pin description file of the chip; the pin description file records the description information of each pin; generating RTL code and verification code of the chip according to the description information; outputting a chip design file; the chip design file includes RTL code and verification code. The present application can improve the efficiency of chip GPIO architecture design. When the chip design needs to be modified, designers only need to modify the corresponding information in the pin description file to automatically generate new RTL code and verification code, without manual recompilation, avoiding errors and omissions caused by manual compilation and shortening the chip R & D time.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of chip design, and particularly to a method and device for generating a chip design file, a chip design method, and a device. Background Art

[0002] With the development of chip technology, chip architectures tend to be more complex. In a GPIO mechanism compatible architecture, each pad, family, and community has several attributes respectively, such that an architecture can have hundreds of pads, organized into dozens of families and several communities, thereby resulting in a huge amount of data for compiled code. Therefore, it takes a long time for a GPIO design team to complete a GPIO architecture design. Summary of the Invention

[0003] Embodiments of the present application provide a method and device for generating a chip design file, a chip design method, a device, a computer device, and a storage medium, which can improve the efficiency of chip GPIO architecture design.

[0004] A method for generating a chip design file includes:

[0005] Obtaining at least one pin description file of a chip; wherein, the pin description file includes description information for describing one or more pins of the chip;

[0006] Generating RTL code and verification code of the chip according to the description information;

[0007] Outputting a chip design file; wherein, the chip design file includes the RTL code and the verification code.

[0008] A chip design method includes:

[0009] Obtaining a chip design file; the chip design file is obtained according to the above chip design file generation method;

[0010] Instantiating the chip according to the RTL code in the chip design file;

[0011] Verifying the chip according to the verification code in the chip design file.

[0012] A chip design file generation device includes:

[0013] A file acquisition module, configured to obtain at least one pin description file of a chip; wherein, the pin description file includes description information for describing one or more pins of the chip;

[0014] A code generation module, configured to generate the RTL code and verification code of the chip according to the description information;

[0015] A design file output module, configured to output a chip design file; wherein, the chip design file includes the RTL code and the verification code.

[0016] A chip design device, comprising:

[0017] A design file acquisition module, configured to acquire a chip design file; the chip design file is generated by the above-mentioned chip design file generation device;

[0018] A chip instantiation module, configured to instantiate the chip according to the RTL code in the chip design file;

[0019] A verification module, configured to verify the chip according to the verification code in the chip design file.

[0020] A computer device, comprising a memory and a processor, wherein a computer program is stored in the memory, and characterized in that when the computer program is executed by the processor, the processor performs the following steps:

[0021] Acquire at least one pin description file of the chip; wherein, the pin description file includes description information for describing one or more pins of the chip;

[0022] Generate the RTL code and verification code of the chip according to the description information;

[0023] Output a chip design file; wherein, the chip design file includes the RTL code and the verification code.

[0024] A computer-readable storage medium, on which a computer program is stored, and characterized in that when the computer program is executed by a processor, the following steps are implemented:

[0025] Acquire a pin description file of the chip; the pin description file records the description information of each pin;

[0026] Generate the RTL code and verification code of the chip according to the description information;

[0027] Output a chip design file; the chip design file includes the RTL code and the verification code.

[0028] The above chip design file generation method, device, chip design method, device, computer device and storage medium obtain the pin description file of the chip, obtain the description information from the pin description file, automatically compile and generate the RTL code and verification code of the chip according to the description information, and output the chip design file, replacing manual compilation, improving the efficiency of chip GPIO architecture design. When the chip design needs to be modified, the designer only needs to modify the corresponding information in the pin description file to automatically generate new RTL code and verification code, without the need for manual recompilation, avoiding errors and omissions caused by manual compilation and shortening the chip R & D time. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0030] Figure 1 It is a schematic diagram of the architecture of the chip in an embodiment;

[0031] Figure 2 It is a flowchart of the chip design file generation method in an embodiment;

[0032] Figure 3 It is a flowchart of the step of generating the RTL code and verification code of the chip according to the description information in an embodiment;

[0033] Figure 4 It is a flowchart of the chip design file generation method in another embodiment;

[0034] Figure 5 It is a flowchart of the chip design file generation method in yet another embodiment;

[0035] Figure 6 It is a flowchart of the chip design method in an embodiment;

[0036] Figure 7 It is one of the structural block diagrams of the chip design file generation device in an embodiment;

[0037] Figure 8 It is another structural block diagram of the chip design file generation device in an embodiment;

[0038] Figure 9 It is yet another structural block diagram of the chip design file generation device in an embodiment;

[0039] Figure 10It is the fourth structural block diagram of the chip design file generation device in an embodiment;

[0040] Figure 11 It is the structural block diagram of the chip design device in an embodiment;

[0041] Figure 12 It is the structural block diagram of the computing device in an embodiment. Detailed implementation manners

[0042] For the convenience of understanding the present application, in order to make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present application, and the preferred embodiments of the present application are given in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive. The present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0043] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0044] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0045] Such as Figure 1As shown, in a GPIO mechanism compatible architecture, each pad, family, and community have at least 20+, 30+, and approximately 10 attributes respectively. Such a GPIO architecture can have at least more than 100 pads, organized into dozens of families and several communities, resulting in a very large amount of data for chip design. In addition to this large dataset, designers also need to establish correct signal connections between the community soft IP (SIP) and the hard IP (HIP) of the pads. And the verification team needs to verify all the pins of the chip. Moreover, a large number of signals need to be correctly connected in the top-level module to achieve full-chip integration. Therefore, without any automation, it takes a long time to complete the design and verification of the GPIO architecture for a new project. Also, due to the extremely large amount of data, the process of manually implementing GPIO is very error-prone.

[0046] Based on the above problems, the chip design file generation method involved in the embodiments of this application can be applied to the design of the chip GPIO architecture and can automatically generate chip design files according to the pin description file of the chip provided by the designer. The chip involved in this application can be any digital circuit chip, specifically, it can be a processor chip such as a DSP (Digital Signal Processing) chip or a SOC (System on Chip) chip.

[0047] As Figure 2 shown, in one of the embodiments, the chip design file generation method includes steps 201 to 203.

[0048] Step 201, obtain at least one pin description file of the chip.

[0049] Among them, the pin description file includes the description information of one or more pins of the chip. The pin description file is provided by the designers responsible for the design of each module of the chip and includes all relevant description information for the implementation of the pin functions, such as function multiplexing of the pins, pin connection information, name, type, etc. Specifically, the pin description file can obtain the description information of each pin from the functional modules by using a template form to obtain the description information from each designer of the chip design, and gather them into one or more pin description files. If there are multiple pin description files, the generation of the chip design file is realized collaboratively based on the multiple pin description files.

[0050] In one of the embodiments, the pin description file can be an Excel file, and the designers only need to fill in the required description information in the table according to their respective responsibilities.

[0051] Step 202: Generate the RTL code and verification code of the chip according to the description information.

[0052] Among them, the RTL (Resistor Transistor Logic) code is the implementation code that describes the functions that the chip is ideally supposed to achieve using a hardware description language (Verilog or VHDL). The verification code is the verification code described in a hardware description language (Verilog or VHDL) for implementing the front-end self-check of the chip.

[0053] Read the pin description file of the chip, extract the description information in the pin description file, and convert the description information into a hardware description language. Specifically, the description information can be converted into a hardware description language using a preset conversion logic, and finally, the RTL code and verification code are generated.

[0054] In one embodiment, if a designer needs to modify the chip design, they only need to modify the relevant description information in the pin description file, regenerate the RTL code and verification code according to the new pin description file, without manual recompilation, and use a computer device to automatically compile according to the preset logic, which can reduce compilation errors.

[0055] Step 203: Output the chip design file.

[0056] Among them, the chip design file includes the RTL code and verification code. Based on the RTL code, the instantiation of the chip can be achieved, and the front-end simulation verification of the chip can be realized using the verification code.

[0057] The above method for generating a chip design file obtains the pin description file of the chip, obtains the description information from the pin description file, automatically compiles according to the description information to generate the RTL code and verification code of the chip, and outputs the chip design file, replacing manual compilation, improving the efficiency of chip GPIO architecture design. When the chip design needs to be modified, the designer only needs to modify the corresponding information in the pin description file to automatically generate new RTL code and verification code, without manual recompilation, avoiding errors and omissions caused by manual compilation, and shortening the chip R & D time.

[0058] In one embodiment, at least one pin description file includes a first description file and a second description file. The first description file is associated with the second description file at least through the description of a first pin, and the first pin is one of the pins of the chip. The method for generating a chip design file further includes:

[0059] Identify the changed content of the first description information of the first pin in the first description file;

[0060] Modify the second description file correspondingly according to the changed content.

[0061] In order to implement function multiplexing of pins in a chip, the design of different functional modules of the chip may be associated with the same pin. When the first description file of the first pin is modified, engineers also need to correspondingly modify the associated description files, which is prone to errors and omissions. In this embodiment, it is possible to identify that the first description information of the first pin in the first description file has changed, identify the changed content, and automatically modify the corresponding part in the second description file according to the changed content, avoiding omissions in the modification and improving the generation efficiency of the chip design file.

[0062] In one embodiment, correspondingly modifying the second description file according to the changed content includes:

[0063] Modifying the second description information of the first pin in the second description file according to the changed content;

[0064] Modifying the third description information of the second pin in the second description file.

[0065] Wherein, the second description information is the description information of the first pin involved in the second description file, which is the same as the first description information of the first pin. Therefore, when the first description information changes, the second description information can be automatically modified according to the changed content. The third description information is the description information about the second pin in the second description file. The second pin is another pin of the chip associated with the first pin, and the third description information and the second description information belong to the same description file, that is, they relate to the same functional module. Therefore, the third description information about the second pin in the second description file can be modified correspondingly according to the changed content.

[0066] In one embodiment, the description information includes pin function description information, register description information, and IO connection description information.

[0067] Among them, the pin function description information is the configuration parameter information used to describe the implementation of the chip pin function, which may include the multiplexing relationship of the pin, the I / O type used, the port name of the I / O pin, whether the pin belongs to ASIC or is only used for FPGA, and whether the pin is a special type such as test mode, clock and reset pins, and the control signal for control pin multiplexing, etc. The register description information records the configuration parameter information of the register, including the name, offset address, type, read / write permission, signal name of each signal domain, bit segment definition, default value, comment, etc. The IO connection description information is used to describe the hardware connection relationship of each IO port.

[0068] In one embodiment, the description information may only include pin function description information, and the register description information and the IO connection description information may be preset. The designer only needs to provide the pin function description information according to each iterative design or function modification to generate the iterative or modified chip design file.

[0069] In one embodiment, the description information may only include pin function description information and register description information, and the connection description information may be preset. The designer only needs to provide the pin function description information and the register description information according to each iterative design or function modification to generate the iterative or modified chip design file.

[0070] In one embodiment, the pin function description information includes function information and DFT (design for test) information. Among them, the hardware logic information inserted at various stages in the original chip design for improving the testability of the chip (including controllability and observability) is the DFT information, and the function information is the hardware logic information used to describe the functions of each functional module when the pin realizes its functions.

[0071] Some pins not only support the function multiplexing of functional modules but also involve DFT testing. By obtaining the pin description file including function information and DFT information, the RTL code capable of realizing function multiplexing and DFT can be directly generated, which can improve the efficiency of chip design compared with the prior art in which DFT design and insertion are carried out after the design of functional modules is completed.

[0072] In one embodiment, as Figure 3 shown, generating the RTL code and verification code of the chip according to the description information includes steps 301 to 303:

[0073] Step 301, generating the RTL code of the soft IP according to the pin function description information and the register description information.

[0074] Among them, the soft IP (Soft IP, SIP) is a functional block described by hardware description languages such as Verilog / VHDL and does not involve specific circuit elements. The RTL code of the soft IP needs to be generated according to the pin function description information and the register description information. When generating the RTL code of the soft IP, the pin function description information and the register description information can be captured from the pin description file, and then converted into RTL code based on the captured information.

[0075] Step 302, generating the RTL code of the hard IP according to the IO connection description information and the register description information.

[0076] Among them, a hard IP (Hard IP, HIP) is a functional module implemented by circuit elements. To realize its function in the chip, it is necessary to define the I / O ports of this part of the functional module. Therefore, it is also necessary to generate the corresponding RTL code. For the RTL code of the hard IP, it is necessary to capture the IP connection description information and register description information in the pin description file and convert them.

[0077] Step 303, generate the verification code according to the pin function description information, register description information, and IO connection description information.

[0078] When the pin function description information, register description information, and IO connection description information are determined, that is, the working logic of the chip is also determined. The DFT information includes test stimuli, which are the values to be loaded at the input end of the chip. Based on the working logic of the chip, the information that the chip should output based on this test stimulus can be generated. This part of the output information is the verification code. When performing a front-end simulation test on the chip, self-checking is achieved by comparing the simulation output results with the verification code.

[0079] In one embodiment, a script program can be used to identify the keyword information in the pin description file, so as to address and obtain the pin function description information, register description information, and IO connection description information corresponding to each pin.

[0080] As Figure 4 shown, in one embodiment, the chip design file generation method includes steps 401 to 405:

[0081] Step 401, obtain at least one pin description file of the chip.

[0082] Among them, the pin description file records the description information of one or more pins, and the description information includes pin function description information, register description information, and IO connection description information.

[0083] Step 402, detect whether there is a multiplexing function conflict in the pin function description information.

[0084] Among them, a multiplexing function conflict refers to a conflict between two or more functions implemented on a certain pin. If there is a multiplexing function conflict on the pin, the chip cannot normally realize its function. Specifically, the pin function description information can be detected by a preset multiplexing function conflict detection model. The multiplexing function conflict detection model can be configured with common pin multiplexing function conflicts. When using the multiplexing function conflict detection model for detection, if the corresponding multiplexing function conflict is recognized, it is determined that there is a multiplexing function conflict.

[0085] In one embodiment, the multiplexing function conflict detection model can also be updated according to the pin multiplexing function conflicts encountered by designers during the chip design process, optimizing the reliability of automatically detecting multiplexing function conflicts. In one embodiment, the multiplexing function conflict detection model can perform iterative learning based on simulation tests to update the types of pin multiplexing function conflicts.

[0086] Step 403, if there is a multiplexing function conflict, generate a function description error prompt.

[0087] Among them, the function description error prompt is used to prompt the description information of the multiplexing function conflict in the pin function description information, enabling designers to quickly determine the description information that needs to be modified without manual troubleshooting, improving the efficiency of chip design.

[0088] Step 404, if there is no multiplexing function conflict, generate the RTL code and verification code of the chip according to the description information.

[0089] Step 405, output the chip design file.

[0090] If it is detected that there is no multiplexing function conflict, generate the RTL code and verification code according to the description information in the pin description file, and form and output the chip design file.

[0091] This embodiment can perform validity detection on the description information in the pin description file before generating the chip design file, reducing the occurrence of the situation where pin multiplexing function conflicts are only discovered during the simulation stage, and improving the efficiency of chip design.

[0092] As Figure 5 shown, in one embodiment, the chip design file generation method includes steps 501 to 505:

[0093] Step 501, obtain at least one pin description file of the chip.

[0094] Among them, the pin description file records the description information of one or more pins of the chip, and the description information includes pin function description information, register description information, and IO connection description information.

[0095] Step 502, detect whether there is a connection conflict in the IO connection description information.

[0096] Among them, connection conflict refers to the conflict in the connection definition of a certain IO port. For example, opposite functional connections are defined for the same IO port. If there is a connection conflict in the IO port, the chip cannot normally implement its functions. Specifically, the IO connection description information can be detected through a preset IO connection conflict detection model. The IO connection conflict detection model can be configured with common IO port connection conflicts, and if the corresponding connection conflict is recognized during detection, it is determined that there is an IO connection conflict.

[0097] In one embodiment, the IO connection conflict detection model can also be updated according to the IO port connection conflicts encountered by designers during the chip design process to optimize the reliability of automatically detecting connection conflicts. In one embodiment, the IO connection conflict detection model can perform iterative learning based on simulation tests to update the IO connection conflict types.

[0098] Step 503, if there is a connection conflict, generate an IO connection error prompt.

[0099] Among them, the IO connection error prompt is used to prompt the description information of the IO port connection conflict in the IO connection description information, enabling designers to quickly determine the description information that needs to be modified without manual troubleshooting, thereby improving the efficiency of chip design.

[0100] Step 504, if there is no connection conflict, generate the RTL code and verification code of the chip according to the description information.

[0101] Step 505, output the chip design file.

[0102] After detection, if there is no connection conflict, continue to generate the RTL code and verification code of the chip according to the description information, and form a chip design file for output.

[0103] In this embodiment, by performing IO connection conflict detection before generating the chip design file, it is possible to effectively reduce design errors and omissions during the chip R & D process and improve the efficiency of chip R & D.

[0104] In one embodiment, the validity of the description information can also be detected semantically and / or syntactically to further reduce errors and omissions in the design stage.

[0105] In one embodiment, tools such as lint and Spyglass can be used to check the RTL code and verification code. Specifically, it refers to performing design rule checks on the chip circuit, including the writing styles of the RTL code and verification code, DFT, naming rules, and circuit synthesis-related rules, etc.

[0106] As Figure 6 shown, the embodiment of the present application also provides a chip design method, including steps 601 to 603:

[0107] Step 601: Obtain the chip design file.

[0108] The chip design file is obtained according to the chip design file generation method in the above embodiment.

[0109] Step 602: Instantiate the chip according to the RTL code in the chip design file.

[0110] The RTL code automatically generated in the above chip design file generation method can be used to instantiate the chip, that is, chip simulation is implemented based on the RTL code.

[0111] Step 603: Verify the chip according to the verification code in the chip design file.

[0112] If the logic of the RTL code of the chip design is correct, after inputting the test stimulus, the output result of the chip should be consistent with the verification code. The front-end self-check of the chip design can be realized through the verification code. If it is inconsistent with the verification code, the designer can check and modify the pin description file, regenerate the new RTL code and verification code, and perform instantiation and verification. The preliminary design of each chip requires multiple simulation test iterations to correct errors. The embodiments of the present application can reduce the time consumed by manual compilation of code and improve the efficiency of chip design.

[0113] It should be understood that although Figure 2-6 the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 2-6 at least a part of the steps in

[0114] Figure 7 include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps. Figure 7 As shown in

[0115] a structural block diagram of a chip design file generation device for an embodiment. The chip design file generation device 700 includes:

[0116] A file acquisition module 710, configured to acquire at least one pin description file of the chip; the pin description file includes description information for describing one or more pins of the chip;A code generation module 720, configured to generate the RTL code and verification code of the chip according to the description information;

[0117] A design file output module 730, configured to output a chip design file; the chip design file includes the RTL code and verification code.

[0118] As Figure 8 shown, in one embodiment, the code generation module 720 includes:

[0119] A first RTL code generation unit 721, configured to generate the RTL code of the soft IP according to the pin function description information and register description information;

[0120] A second RTL code generation unit 722, which generates the RTL code of the hard IP according to the IO connection description information and register description information;

[0121] A verification code generation unit 723, which generates verification code according to the pin function description information, register description information and IO connection description information.

[0122] As Figure 9 shown, in one embodiment, the chip design file generation device 700 further includes:

[0123] A first conflict detection module 740, configured to detect whether there is a multiplexing function conflict in the pin function description information;

[0124] A first error reporting module 750, configured to generate a function description error prompt when a multiplexing function conflict is detected.

[0125] As Figure 10 shown, in one embodiment, the chip design file generation device 700 further includes:

[0126] A second conflict detection module 760, configured to detect whether there is a connection conflict in the IO connection description information;

[0127] A second error reporting module 770, configured to generate an IO connection error prompt when a connection conflict is detected.

[0128] As Figure 11 shown, an embodiment of the present application further provides a chip design device 800, including:

[0129] A design file acquisition module 810, configured to acquire a chip design file; the chip design file is generated by the chip design file generation device in the above embodiment;

[0130] A chip instantiation module 820, configured to instantiate the chip according to the RTL code in the chip design file;

[0131] A verification module 830 is configured to verify the chip according to the verification code in the chip design file.

[0132] The division of each module in the above chip design file generation device and chip design device is only for illustrative purposes. In other embodiments, the chip design file generation device and chip design device can be divided into different modules as needed to complete all or part of the functions of the above chip design file generation device and chip design device.

[0133] For the specific limitations of the chip design file generation device, reference can be made to the limitations on the chip design file generation method in the above text. For the specific limitations of the chip design device, reference can be made to the limitations on the chip design method in the above text, which will not be elaborated here. Each module in the above chip design file generation device and chip design device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0134] In one embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 12 shown. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner. The wireless manner can be implemented through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it realizes a chip design file generation method and / or a chip design method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0135] Those skilled in the art can understand that Figure 12 the structure shown in

[0136] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented:

[0137] Obtain at least one pin description file of a chip; wherein, the pin description file includes description information for describing one or more pins of the chip;

[0138] Generate RTL code and verification code of the chip according to the description information;

[0139] Output a chip design file; wherein, the chip design file includes RTL code and verification code.

[0140] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0141] Generate RTL code of the soft IP according to the pin function description information and register description information;

[0142] Generate RTL code of the hard IP according to the IO connection description information and register description information;

[0143] Generate verification code according to the pin function description information, register description information and IO connection description information.

[0144] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0145] Detect whether there is a multiplexing function conflict in the pin function description information;

[0146] If there is a multiplexing function conflict, generate a function description error prompt;

[0147] If there is no multiplexing function conflict, execute the step of generating RTL code and verification code of the chip according to the description information.

[0148] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0149] Detect whether there is a connection conflict in the IO connection description information;

[0150] If there is a connection conflict, generate an IO connection error prompt;

[0151] If there is no connection conflict, generate RTL code and verification code of the chip according to the description information.

[0152] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0153] Identify the changed content of the first description information of the first pin in the first description file;

[0154] Modify the second description file according to the changes.

[0155] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0156] Modify the second description information of the first pin in the second description file according to the changes;

[0157] Modify the third description information of the second pin in the second description file; wherein, the second pin is another pin of the chip associated with the first pin.

[0158] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented:

[0159] Obtain a chip design file; the chip design file is obtained according to the above chip design file generation method;

[0160] Instantiate the chip according to the RTL code in the chip design file;

[0161] Verify the chip according to the verification code in the chip design file.

[0162] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0163] Obtain a pin description file of the chip; the pin description file records the description information of each pin;

[0164] Generate the RTL code and verification code of the chip according to the description information;

[0165] Output the chip design file; the chip design file includes the RTL code and verification code.

[0166] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0167] Generate the RTL code of the soft IP according to the pin function description information and register description information;

[0168] Generate the RTL code of the hard IP according to the IO connection description information and register description information;

[0169] Generate the verification code according to the pin function description information, register description information and IO connection description information.

[0170] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0171] Detect whether there is a conflict in the multiplexing function of the pin function description information;

[0172] If there is a conflict in the multiplexing function, generate an error prompt for the function description;

[0173] If there is no conflict in the multiplexing function, execute the step of generating the RTL code and verification code of the chip according to the description information.

[0174] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0175] Detect whether there is a connection conflict in the IO connection description information;

[0176] If there is a connection conflict, generate an error prompt for the IO connection;

[0177] If there is no connection conflict, generate the RTL code and verification code of the chip according to the description information.

[0178] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0179] Identify the changed content of the first description information of the first pin in the first description file;

[0180] Modify the second description file correspondingly according to the changed content.

[0181] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0182] Modify the second description information of the first pin in the second description file according to the changed content;

[0183] Modify the third description information of the second pin in the second description file; wherein, the second pin is another pin of the chip associated with the first pin.

[0184] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0185] Obtain a chip design file; the chip design file is obtained according to the above chip design file generation method;

[0186] Instantiate the chip according to the RTL code in the chip design file;

[0187] Verify the chip according to the verification code in the chip design file.

[0188] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0189] Obtain the pin description file of the chip; the pin description file records the description information of each pin;

[0190] Generate the RTL code and verification code of the chip according to the description information;

[0191] Output the chip design file; the chip design file includes the RTL code and verification code.

[0192] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0193] Generate the RTL code of the soft IP according to the pin function description information and the register description information;

[0194] Generate the RTL code of the hard IP according to the IO connection description information and the register description information;

[0195] Generate the verification code according to the pin function description information, the register description information and the IO connection description information.

[0196] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0197] Detect whether there is a multiplexing function conflict in the pin function description information;

[0198] If there is a multiplexing function conflict, generate a function description error prompt;

[0199] If there is no multiplexing function conflict, execute the step of generating the RTL code and verification code of the chip according to the description information.

[0200] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0201] Detect whether there is a connection conflict in the IO connection description information;

[0202] If there is a connection conflict, generate an IO connection error prompt;

[0203] If there is no connection conflict, generate the RTL code and verification code of the chip according to the description information.

[0204] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0205] Identify the changed content of the first description information of the first pin in the first description file;

[0206] Modify the second description file correspondingly according to the changed content.

[0207] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0208] Modify the second description information of the first pin in the second description file according to the change content;

[0209] Modify the third description information of the second pin in the second description file; wherein, the second pin is another pin of the chip associated with the first pin.

[0210] In one embodiment, a computer program product is provided, including a computer program which, when executed by a processor, implements the following steps:

[0211] Obtain a chip design file; the chip design file is obtained according to the above chip design file generation method;

[0212] Instantiate the chip according to the RTL code in the chip design file;

[0213] Verify the chip according to the verification code in the chip design file.

[0214] Any reference to memory, storage, database, or other media used in this application may include non-volatile and / or volatile memory. Non-volatile memory may include ROM (Read-Only Memory), PROM (Programmable Read-only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-only Memory), or flash memory. Volatile memory may include RAM (Random Access Memory), which serves as an external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), double data rate DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access memory), ESDRAM (Enhanced Synchronous Dynamic Random Access memory), SLDRAM (Sync Link Dynamic Random Access Memory), RDRAM (Rambus Dynamic Random Access Memory), DRDRAM (Direct Rambus Dynamic Random Access Memory).

[0215] The above embodiments merely represent several implementation manners of this application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application shall be subject to the appended claims.

Claims

1. A method for generating a chip design file, characterized in that, Including: Obtain at least one pin description file of the chip; wherein, the pin description file includes description information for describing one or more pins of the chip, and the description information includes pin function description information, register description information, and IO connection description information; Generate RTL code of the soft IP according to the pin function description information and the register description information; the soft IP is a functional block described in a hardware description language; Generate RTL code of the hard IP according to the IO connection description information and the register description information; the hard IP is a functional module implemented by a circuit element; Generate verification code according to the pin function description information, the register description information, and the IO connection description information; Output a chip design file; wherein, the chip design file includes the RTL code and the verification code.

2. The method according to claim 1, wherein The method is applied to chip GPIO architecture design.

3. The method according to claim 1, wherein The pin function description information includes function information and DFT information.

4. The method according to claim 3, characterized in that The DFT information includes test stimuli; the generating verification code according to the pin function description information, the register description information, and the IO connection description information includes: Based on the pin function description information, the register description information, and the IO connection description information, determine the working logic of the chip; Use the test stimuli as inputs of the chip, and based on the working logic, determine the output information of the chip; Determine the output information as the verification code.

5. The method according to claim 1, wherein Also including: Detect whether there is a multiplexing function conflict in the pin function description information; If there is a multiplexing function conflict, generate a function description error prompt; If there is no multiplexing function conflict, execute the step of generating the RTL code and verification code of the chip according to the description information.

6. The method according to claim 1, wherein Also including: Detect whether there is a connection conflict in the IO connection description information; If there is a connection conflict, generate an IO connection error prompt; If there is no connection conflict, generate the RTL code and verification code of the chip according to the description information.

7. The method according to any one of claims 1 to 6, characterized in that The at least one pin description file includes a first description file and a second description file, wherein the first description file is associated with the second description file at least through the description of a first pin, and the first pin is one of the pins of the chip. The method further includes: Identify the changed content of the first description information of the first pin in the first description file; Correspondingly modify the second description file according to the changed content.

8. The method according to claim 7, wherein Correspondingly modifying the second description file according to the changed content includes: Modify the second description information of the first pin in the second description file according to the changed content; Modify the third description information of a second pin in the second description file; wherein, the second pin is another pin of the chip associated with the first pin.

9. A chip design method, characterized in that, Including: Obtain a chip design file; the chip design file is obtained according to the chip design file generation method according to any one of claims 1 to 8; Instantiate the chip according to the RTL code in the chip design file; Verify the chip according to the verification code in the chip design file.

10. A chip design file generation device, characterized in that, Including: A file acquisition module, configured to acquire at least one pin description file of a chip; wherein, the pin description file includes description information for describing one or more pins of the chip, and the description information includes pin function description information, register description information, and IO connection description information; A code generation module, configured to generate RTL code of a soft IP according to the pin function description information and the register description information; the soft IP is a functional block described in a hardware description language; generate RTL code of a hard IP according to the IO connection description information and the register description information; the hard IP is a functional module implemented by a circuit element; generate verification code according to the pin function description information, the register description information, and the IO connection description information; A design file output module, configured to output a chip design file; wherein, the chip design file includes the RTL code and the verification code.

11. A chip design device, characterized in that, Comprising: A design file acquisition module, configured to acquire a chip design file; The chip design file is generated by the chip design file generation device described in claim 10; A chip instantiation module, configured to instantiate the chip according to the RTL code in the chip design file; A verification module, configured to verify the chip according to the verification code in the chip design file.

12. A computer device, comprising a memory and a processor, wherein a computer program is stored in the memory, characterized in that, When the computer program is executed by the processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 9.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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