Architecture and methods for physically unclonable functions

Abstract

The present invention relates to the architecture and method of a physical unclonable function, and discloses a memory cell, including a plurality of first access transistors connected in parallel and a first variable resistor connected in series between a bit line and a source line, and a plurality of second access transistors connected in parallel and a second variable resistor connected in series between the bit line and the source line. A write word line controls a pair of first and second access transistors so that during an initialization mode, the resistors are simultaneously subjected to the same write bias conditions so as to be programmed once to switch from an unprogrammed state (wherein the resistors have the same first resistance state) to a programmed state (wherein one resistor has been switched to a second resistance state and stores a bit). Discrete first and second read word lines control another pair of first and second access transistors to implement a discrete read process associated with the first and second variable resistors. Related circuits (e.g., PUF) and methods are also disclosed.

Description

Technical Field

[0001] The present invention relates to a physically unclonable function (PUF), and more particularly, to a PUF architecture and method. Background Art

[0002] With the increasing use of Internet of Things (IoT) objects, wireless communications and data are becoming increasingly vulnerable to various security threats. To prevent such security threats, Physical Unclonable Functions (PUFs) have been developed for cryptography (e.g., encryption and decryption), advanced authentication, etc. Typically, a PUF is a hardware-implemented random number generator. Ideally, a PUF will consistently generate and output exactly the same random number (i.e., exactly the same unique bitstring) in response to repeated challenges. Unfortunately, in current on-chip PUF architectures, variations in operating conditions (e.g., temperature variations, voltage variations, etc.) make it difficult to repeatedly and consistently generate exactly the same random number without applying less secure post-processing algorithms. Summary of the invention

[0003] Embodiments of a memory cell are disclosed herein. The memory cell may include a plurality of variable resistors, including a first variable resistor and a second variable resistor. The memory cell may also include a plurality of transistors, including two first access transistors connected in parallel and two second access transistors connected in parallel. The first access transistor and the first variable resistor may be connected in series between a bit line and a source line. The second access transistor and the second variable resistor may be connected in series between the same bit line and source line. Finally, the gate of the first access transistor may be connected to a common write word line and a first read word line, respectively, and the gate of the second access transistor may be connected to the same common write word line and a second read word line, respectively.

[0004] Also disclosed herein is an embodiment of an on-chip circuit (e.g., a physically unclonable function (PUF)) comprising an array of such memory cells arranged in columns and rows. That is, each memory cell in the memory array may include a plurality of variable resistors, including a first variable resistor and a second variable resistor. Each memory cell in the memory array may also include a plurality of transistors, including two first access transistors connected in parallel and two second access transistors connected in parallel. The first access transistor and the first variable resistor may be connected in series between a bit line and a source line of a column containing the memory cell. The second access transistor and the second variable resistor may be connected in series between the same bit line and source line of the column. Finally, for a row containing the memory cell, the gate of the first access transistor may be connected to a common write word line and a first read word line, respectively, and for the row, the gate of the second access transistor may be connected to the same common write word line and second read word line, respectively.

[0005] Also disclosed herein is a method embodiment for operating the above structure. The method embodiment may include providing an on-chip circuit (e.g., a physically unclonable function (PUF)). This circuit may include a memory array having memory cells arranged in columns and rows. Each memory cell in the memory array may include a plurality of variable resistors, including a first variable resistor and a second variable resistor. Each memory cell in the memory array may also include a plurality of transistors, including two first access transistors connected in parallel and two second access transistors connected in parallel. The first access transistor and the first variable resistor may be connected in series between a bit line and a source line of a column containing the memory cell. The second access transistor and the second variable resistor may be connected in series between the same bit line and source line of the column. Finally, for a row containing the memory cell, the gate of the first access transistor may be connected to a common write word line and a first read word line, respectively, and for the same row, the gate of the second access transistor may be connected to the same common write word line and a second read word line, respectively. The method embodiment may also include operating each memory cell in the memory array in an initialization mode. Operating the memory cell in the initialization mode may include causing a write process to be performed to achieve one-time programming of the memory cell from an unprogrammed state to a randomly programmed state. To cause the write process, a write bias condition may be applied to the bit line and the source line connected to the memory cell, and a common write word line connected to the memory cell may be activated, such that the memory cell switches from the unprogrammed state to the randomly programmed state in response to the write bias condition and activation of the common write word line, and further based on the possible presence of random process variations in the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0007] Figure 1 A schematic diagram for illustrating an exemplary prior art physically unclonable function (PUF);

[0008] Figure 2A and 2B For illustration purposes, Figure 1 In a PUF, the threshold voltages of the transistors in the memory cells may be so similar that repeated and consistent generation of the same random number is impossible given different operating conditions;

[0009] Figure 3A A schematic diagram showing an embodiment of a memory cell and a circuit (e.g., a PUF) including an array of such memory cells;

[0010] Figure 3B Schematic diagrams showing alternative embodiments of memory cells and circuits (e.g., PUFs) including arrays of such memory cells;

[0011] Figure 4A and 4B Cross-sectional views of an exemplary spin transfer torque type magnetic tunnel junction in parallel and antiparallel states, respectively;

[0012] Figure 5 As a diagram, it is shown in Figure 3A and 3B In a circuit embodiment of the present invention, different resistance states of the variable resistor of the memory cell in the programmed state will be sufficiently different that repeated and consistent generation of the same random number can be achieved even given different operating conditions; and

[0013] Figure 6 A flowchart of an embodiment of a method of operation is shown.

[0014] Main component symbols

[0015] 100PUF

[0016] 110 storage units

[0017] 111-112NFET

[0018] 121-122 bit line (BL)

[0019] 123 Common Source Line (CSL)

[0020] 133 Common word line (CWL)

[0021] 160 Comparator

[0022] 300A, 300B on-chip circuits, circuits

[0023] 310A, 310B storage unit

[0024] 321 bit lines

[0025] 323 source line

[0026] 331 first read word line

[0027] 332 second read word line

[0028] 333 Common write word line

[0029] 340.1ab first access transistor

[0030] 340.2ab Second access transistor

[0031] 350.1, 350.1(a)-(m) First variable resistor

[0032] 350.2, 350.2(a)-(m) Second variable resistor

[0033] 351 Free ferromagnetic layer

[0034] 352 Pinning ferromagnetic layer

[0035] 353 Thin dielectric layer (tunneling barrier)

[0036] 360 Comparator

[0037] 391-392 Peripheral Circuit

[0038] 393 sensing circuit

[0039] 395 Controller

[0040] 11First terminal

[0041] 12 Second terminal. DETAILED DESCRIPTION

[0042] As mentioned above, physically unclonable functions (PUFs) have been developed for use in cryptography (e.g., encryption and decryption), advanced authentication, etc. Typically, a PUF is a hardware-implemented random number generator. Ideally, a PUF will consistently generate and output exactly the same random number (i.e., exactly the same unique bit string) in response to repeated challenges. Unfortunately, in current on-chip PUF architectures, variations in operating conditions (e.g., temperature variations, voltage variations, etc.) make it difficult to repeatedly and consistently generate exactly the same random number without applying less secure post-processing algorithms.

[0043] For example, Figure 1 A schematic diagram illustrating the architecture of an exemplary prior art PUF 100. The PUF 100 includes an array of memory cells 110 arranged in columns and rows. Each memory cell 110 in the array includes a pair of n-type field effect transistors (NFETs) 111-112, which are respectively connected in series between a pair of bit lines 121-122 for the column containing the cell. The junction between the NFETs 111-112 is connected to a common source line (CSL) 123 for the column. Additionally, the gates of both NFETs 111-112 are connected to a common word line (CWL) 133 for the row containing the cell. The NFETs 111-112 are typically manufactured according to exactly the same design. However, due to random process variables that occur naturally during manufacturing (e.g., variations in channel length and width, fluctuations in dopant concentration in the channel, differences in the amount of charge stored in the gate dielectric, etc.), the NFETs 111-112 have different threshold voltages (i.e., VT1 and VT2 respectively). Thus, when the CWL 133 connected to the selected memory cell 110 is activated (i.e., raised to VDD) and the CSL 123 connected to the selected memory cell 110 is precharged during a read operation (also referred to herein as a sensing operation), one of the NFETs 111-112 within the selected memory cell 110 will turn on before the other, and a read current (Iread) will flow from the CSL 123 through the turned-on NFET to the corresponding bit line of the column. Specifically, if NFET 111 turns on first, the Iread will flow from the CSL 123 through NFET 111 to BL 121, such that the current on BL121 will be greater than the current on BL122; however, if NFET 112 turns on first, the Iread will flow from the CSL 123 through NFET 112 to BL 122, such that the current on BL 122 will be greater than the current on BL 121. A comparator 160 located at the end of the column receives inputs from the BL 121-122 and can compare the currents on each to identify which NFET within the memory cell turns on first. Depending on which NFET within the selected memory cell turns on first, the selected memory cell 110 will be read out as a bit storing a logic value of 0 (e.g., if NFET 111 has a lower threshold voltage (VT1 < VT2) and turns on first) or a logic value of 1 (e.g., if NFET 112 has a lower threshold voltage (VT1 > VT2) and turns on first). In response to a challenge to the PUF, the bits in all the memory cells stored in the array are sequential, thus outputting a unique bit string (i.e., a random number).

[0044] Figure 2A and Figure 2B is an illustration that, in Figure 1In the case of the prior art PUF 100 shown, changes in operating conditions (e.g., temperature changes, voltage changes, etc.) may make it difficult to repeatedly and consistently generate exactly the same random numbers.

[0045] Specifically, Figure 2A is a graph showing a probability distribution that indicates the frequency with which different storage cells 110 in the PUF 100 will have different VT1:VT2 combinations. As described above, any storage cell where VT1 < VT2 will output a bit with a logic value of 0 during a read operation, and any storage cell where VT1 > VT2 will output a bit with a logic value of 1 during a read operation. Since the design and manufacture of NFETs are typically optimized to minimize the threshold voltage variation between chips, most storage cells will have NFETs where VT1 and VT2 are very similar, such that VT1 - VT2 is only slightly negative or slightly positive (see the peak of the probability distribution), and only a few storage cells will have NFETs where VT1 is significantly less than VT2 (see the left end of the probability distribution) or significantly greater than VT2 (see the right end of the probability distribution). However, using NFETs with similar threshold voltages in a PUF becomes problematic because the threshold voltage can vary with changes in operating conditions (e.g., with changes in operating temperature and / or operating voltage). For each storage cell where the NFET has a similar threshold voltage (i.e., VT1 ≅ VT2), a change in operating conditions between an initial read operation and a subsequent read operation can cause VT1 and / or VT2 to shift such that VT1 is no longer greater than VT2, or vice versa. Therefore, the bit string output during the subsequent read operation will be different from the bit string output during the initial read operation.

[0046] Techniques have been developed to reduce the peak in the center of the probability distribution, particularly to reduce the frequency of storage cells where the NFETs have similar threshold voltages (i.e., VT1 ≅ VT2), to increase the likelihood that exactly the same random numbers are repeatedly and consistently output in response to each challenge. One exemplary technique for reducing the peak at the center of the probability distribution includes performing an initial read operation during which the bits stored in each storage cell are read out in sequence to generate a bit string (i.e., a random number), temporarily storing the bit string elsewhere (e.g., in a buffer), and then rewriting the same bit string back into the storage cells. During the rewrite process, each bit is rewritten into the storage cell in such a way as to force a large number of electrons into the gate dielectric layer of the NFET at a higher threshold voltage, thereby further increasing the difference between VT1 and VT2. While this technique reduces the likelihood that the storage cells in the array may have NFETs with VT1 ≅ VT2, it does not eliminate all possibilities (as Figure 2BFurthermore, the added complexity of unloading the bit string to a buffer and then rewriting it back to the storage unit may result in write errors.

[0047] In view of the above, embodiments of a memory cell are disclosed herein. The memory cell may include two first access transistors in parallel and a first variable resistor connected in series between a bit line and a source line (or, optionally, a plurality of first variable resistors in parallel), and two second access transistors in parallel and a second variable resistor connected in series between a bit line and a source line (or, optionally, a plurality of second variable resistors in parallel). A common write word line may control the gates of a first access transistor and a second access transistor so that the first and second variable resistors may be simultaneously subjected to the same limited write bias condition during one-time programming, which is designed in view of the possible existence of random process variables, switching less than all variable resistors from a high resistance state to a low resistance state, thereby storing a bit. A discrete read word line may control the gates of another first access transistor and another second access transistor to allow a selective read process. An embodiment of an on-chip circuit (e.g., a PUF) is also disclosed herein, which includes an array of memory cells and can be used to generate a random number (i.e., a unique bit string) by sequentially reading stored bits from memory cells. An associated method embodiment is also disclosed herein.

[0048] More specifically, Figure 3A and Figure 3B 1 and 2 show embodiments of on-chip circuits 300A, 300B (eg, PUF) and memory cells 310A integrated into the on-chip circuits 300A, 300B (see FIG. Figure 3A )、310B(See Figure 3B ) is a schematic diagram of an embodiment of the present invention. The circuit 300A, 300B may include a memory array having a plurality of memory cells 310A, 310B, wherein the memory cells 310A, 310B are arranged in columns A- N and line a- n and is randomly programmable.

[0049] The circuits 300A, 300B may further include a bit line 321 and a source line 323 for a column, and all memory cells 310A, 310B in the same column may be connected to the bit line 321 and the source line 323 for the column. The circuits 300A, 300B may further include a plurality of word lines for a row (including a common write word line 333, a first read word line 331, and a second read word line 332), and all memory cells 310A, 310B in the same row may be connected to the word lines of the row.

[0050] It should be understood that columns and rows of memory cells refer to memory cells that are arranged substantially linearly, with a first line of cells in the array oriented in a first direction, a second line of cells in the array oriented in a second direction substantially perpendicular to the first direction, and each cell being located at the intersection of the first line and the second line. For purposes of illustration, Figure 3A and Figure 3B Columns and bit lines and source lines associated with the columns in the Y direction are shown, and rows and word lines associated with the rows in the X direction are further shown. However, it should be understood that the drawings are not intended to be limiting, and alternatively, the columns, bit lines and source lines can be oriented in the X direction, and the rows and word lines can be oriented in the Y direction.

[0051] The circuits 300A, 300B may also include a controller 395 and peripheral circuits 391-392 that communicate with the controller 395 and are configured to operate in response to control signals from the controller 395. The peripheral circuit 391 may be electrically connected to the word lines of the rows and may include, for example, address decoding logic and drivers for activating and deactivating the selected word lines (i.e., for switching the selected word lines from a low voltage level to a high voltage level and back) according to the operating mode (as described below). The peripheral circuit 392 may be electrically connected to the bit lines and source lines of the columns and may include column address decoding logic and drivers for appropriately biasing the selected bit lines and source lines according to the operating mode (as described below). The circuits 300A, 300B may also include a sensing circuit 393 that communicates with the controller 395 and is configured to perform a sensing / comparison process according to the operating mode (as described below). Controllers, peripheral circuits, and sensing circuits for storage array operations are well known in the art. Therefore, their details are omitted from this specification to allow the reader to focus on the significant aspects of the disclosed embodiments.

[0052] The memory cells 310A, 310B may be configured to be randomly programmable. Specifically, each memory cell 310A, 310B may be a dual-cell memory cell (also referred to herein as a dual-cell memory cell) including a first cell segment connected between a bit line and a source line for a column and a second cell segment connected to the same bit line and the same source line for the column. More specifically, each memory cell 310A, 310B may include a plurality of two-terminal variable resistors including one or more first variable resistors in the first cell segment and one or more second variable resistors in the second cell segment.

[0053] For example, Figure 3AAs shown, each memory cell 310A may include a first variable resistor 350.1 in a first unit segment and a second variable resistor 350.2 in a second unit segment, the first variable resistor 350.1 having a first terminal at one end and a second terminal at the other end, and similarly, the second variable resistor 350.2 having a first terminal at one end and a second terminal at the other end.

[0054] Or, if Figure 3B As shown, each memory cell 310B may include a plurality of first variable resistors 350.1(a)-(b) connected in parallel in the first unit section. m ), in the second unit section, a plurality of second variable resistors 350.2(a)-( m ). In this case, each first variable resistor and each second variable resistor may have a first terminal at one end and a second terminal at the other end. First variable resistor 350.1(a)-( m ) can be connected in parallel. That is, all first variable resistors 350.1(a)-( m ) can be electrically connected at the first terminal junction, and all first variable resistors 350.1(a)-( m ) can also be electrically connected at the second terminal junction. Similarly, the second variable resistors 350.2(a)-(m) can be connected in parallel. That is, the first terminals of all the second variable resistors 350.2(a)-(m) can be electrically connected at the first terminal junction, and the second terminals of all the second variable resistors 350.2(a)-(m) can also be electrically connected at the second terminal junction. For ease of illustration, three parallel first variable resistors 350.1(a)-(m) and three parallel second variable resistors 350.2(a)-(m) are shown in each storage unit 310B. However, it should be understood that the drawings are not intended to be limiting, and, optionally, each storage unit 310B may include any number of two or more parallel first variable resistors and the same number of two or more parallel second variable resistors.

[0055] For purposes of the present invention, a two-terminal variable resistor refers to a device that can be switched between multiple resistance states. For example, a two-terminal variable resistor can be switched between a first resistance state (e.g., a high resistance state, characterized in that the device has a resistance above a specific high resistance level) and a second resistance state (e.g., a low resistance state, characterized in that the device has a resistance below a specific low resistance level, the specific low resistance level being lower than the specific high resistance level) according to a write bias condition applied to the first and / or second terminals of the device. All two-terminal variable resistors in each memory cell 310A, 310B can be the same type of two-terminal variable resistor and can be manufactured according to the same design.

[0056] In some embodiments, the two-terminal variable resistor in each memory cell 310A, 310B is a spin transfer torque magnetic tunnel junction (STT-MTJ). Those skilled in the art will recognize that the STT-MTJ is typically a back-end-of-line (BEOL) multilayer variable resistor structure. That is, it is a multilayer structure formed in the BEOL metal layer of a chip above a front-end-of-line (FEOL) device (e.g., a semiconductor device, etc.). Figure 4A and Figure 4B As shown, the STT-MTJ may include a thin dielectric layer 353 (also referred to as a tunneling barrier layer) located between a free ferromagnetic layer 351 (also referred to herein as a free layer or a data storage layer) at a first terminal 11 and a pinned ferromagnetic layer 352 (also referred to herein as a pinned layer or a fixed ferromagnetic layer) at a second terminal 12. The thin dielectric layer 353 may be, for example, a thin oxide layer, such as a magnesium oxide (MgO) layer, an aluminum oxide (Al2O3) layer (also referred to as aluminum oxide), or a bismuth ferrite (BiFeO3, also referred to as BFO) layer. The free ferromagnetic layer 351 may be, for example, a cobalt (Co), iron (Fe), boron (B) alloy layer. The pinned ferromagnetic layer 352 may be, for example, a gadolinium (Gd), iron (Fe) and cobalt (Co) alloy layer.

[0057] Depending on the write bias conditions applied to the first terminal 11 and the second terminal 12, the STT-MTJ can switch between two resistance states, including an antiparallel resistance (RAP) state (also called a high resistance state) and a parallel resistance (RP) state (also called a low resistance state). In the RAP state, the resistance of the STT-MTJ will be higher than some specific high resistance level. In the RP state, the resistance of the same STT-MTJ will be lower than a specific low resistance level, which is lower than the high resistance level. During a conventional RAP to RP write process in an STT-MTJ, a positive voltage pulse is applied to the first terminal 11 (i.e., the free ferromagnetic layer 311), and the second terminal 12 (i.e., the pinned ferromagnetic layer 352) is discharged to GND (e.g., 0V) so that the write current (Iwrite) flows from the first terminal to the second terminal in the direction of the pinned ferromagnetic layer 352, thereby switching the free ferromagnetic layer 351 to the RP state (i.e., the low resistance state) (see Figure 4A During a conventional RP to RAP write process in an STT-MTJ, a positive voltage pulse is applied to the second terminal 12 (i.e., the pinned ferromagnetic layer 352), and the first terminal 11 is discharged to ground (GND) (e.g., 0V) to cause a write current (Iwrite) to flow from the second terminal to the first terminal in the direction of the free ferromagnetic layer 351, thereby switching the free ferromagnetic layer 351 to a RAP state (i.e., a high resistance state) (see Figure 4B ). The voltage level and duration are typically chosen so that, given a STT-MJT design, the positive voltage pulse is at a high enough level and applied for a long enough duration to ensure that the desired switching occurs in most, if not all, STT MTJs fabricated according to the design, regardless of any process variations.

[0058] It should be understood that in other embodiments, different types of two-terminal variable resistors may also be incorporated into the memory cells 310A, 310B. Such variable resistors may include, but are not limited to, phase change memory (PCM) type variable resistors and memristors.

[0059] Those skilled in the art will recognize that a PCM type variable resistor employs a phase change material (e.g., a chalcogenide) having two different programmable structural phases. The phases include a low resistivity (high conductivity) crystalline phase and a high resistivity (low conductivity) amorphous phase. The switching of the phases depends on the local temperature, which is controlled by the length and magnitude of the voltage applied to the first and / or second terminals. Those skilled in the art will recognize that a memristor comprises two metal layers and a dielectric layer (e.g., hafnium oxide (HfO x ) or some other suitable oxide layer, also called switching layer).

[0060] Those skilled in the art will recognize that a memristor is a variable resistor that can be configured so that it can be switched between two resistance states, or so that it can be switched between more than two resistance states. For example, in some memristors, depending on the write bias conditions applied to the first and / or second terminals, ions in the dielectric layer can migrate to: (a) disconnect the conductive filament extending through the dielectric layer between the metal layers, so that the memristor is in a high resistance state, or (b) grow a conductive filament in the dielectric layer so that it extends between the metal layers, so that the memristor is in a low resistance state. In other memristors, there may be three or more different resistance states depending on the write bias conditions applied to the first and / or second terminals.

[0061] In any case, those skilled in the art will recognize that different types of variable resistors have different write bias conditions for switching resistance states.

[0062] For purposes of illustration, the memory cells 310A, 310B are described in greater detail below and are illustrated in the figures as comprising a variable resistor having two resistance states, and more specifically, as comprising an STT-MTJ.

[0063] In any case, each memory cell 310A, 310B may also include multiple access transistors, including two parallel first access transistors 340.1ab in the first cell section and two parallel second access transistors 340.2ab in the second cell section. For example, the access transistors may all be n-type field effect transistors (NFETs).

[0064] In each memory cell 310A, 310B in a given column and row, a first access transistor 340.1ab and a first variable resistor 350.1 in parallel in the first cell section (or, if applicable, first variable resistors 350.1(a)-(m) in parallel) may be connected in series between the bit line 321 and the source line 323 for the column. That is, each first access transistor 340.1ab may have a first source / drain region and a second source / drain region. The first source / drain regions of the two first access transistors 340.1ab may be electrically connected, and the second source / drain regions of the two first access transistors 340.1ab may also be electrically connected, so that the two first access transistors are connected in parallel. The first source / drain regions of the two first access transistors 340.1ab may be electrically connected to the bit line 321, and the second source / drain regions of the two first access transistors 340.1ab may be electrically connected to the first terminal of the first variable resistor 350.1 (or, if applicable, to the first terminal junction of the parallel first variable resistors 350.1(a)-(m)). The second terminal of the first variable resistor 350.1 (or, if applicable, to the second terminal junction of the parallel first variable resistors 350.1(a)-(m)) may be electrically connected to the source line 323.

[0065] The parallel second access transistors 340.2ab and the second variable resistors 350.2 (or, if applicable, the parallel second variable resistors 350.2(a)-(m)) in the second cell section may be connected in series between the same bit line 321 and the same source line 323 for the column. That is, each second access transistor 340.2ab may have a first source / drain region and a second source / drain region, and the first source / drain regions of the two second access transistors 340.2ab may be electrically connected, and the second source / drain regions of the two second access transistors 340.2ab may also be electrically connected, so that the two second access transistors are connected in parallel. The first source / drain regions of the two second access transistors 340.2ab may be electrically connected to the bit line 321. The second source / drain regions of the two second access transistors 340.2ab may be electrically connected to the first terminal of the second variable resistor 350.2 (or, if applicable, to the first terminal junction of the second variable resistors 350.2(a)-(m) in parallel). The second terminal of the second variable resistor 350.2 (or, if applicable, the second terminal junction of the second variable resistors 350.2(a)-(m) in parallel) may be electrically connected to the source line 323. For the STT MTJ, as discussed above and Figure 4A-4B As shown, the first terminal 11 is located at the free ferromagnetic layer 351 , and the second terminal 12 is located at the pinned ferromagnetic layer 352 .

[0066] Additionally, in each memory cell 310A, 310B in a given column and row, the gates of two parallel first access transistors 340.1ab may be connected to the common write word line 333 and the first read word line 331 of the row, respectively. The gates of two parallel second access transistors 340.2ab may be connected to the same common write word line 333 and the second read word line 332 of the row, respectively.

[0067] As discussed in more detail below, by connecting the gates of a first access transistor and a second access transistor in the memory cells 310A, 310B (e.g., see the gates of the first access transistor 340.1a and the second access transistor 340.2a) to the same common write word line 333, the first variable resistor 350.1 (or, if applicable, the parallel group of first variable resistors 350.1 (a)-(m)) and the second variable resistor 350.2 (or, if applicable, the parallel group of second variable resistors 350.2 (a)-(m)) can be simultaneously subjected to the same write bias conditions during the write process. As also discussed in more detail below, by connecting the gates of another first access transistor and another second access transistor (e.g., see the gates of the first access transistor 340.1b and the second access transistor 340.2b) to different read word lines (i.e., the first read word line 331 and the second read word line 332), the first variable resistor (or, if applicable, the first variable resistor group 350.1(a)-(m) in parallel) and the second variable resistor (or, if applicable, the second variable resistor group 350.2(a)-(m) in parallel) can be selectively subjected to the read bias conditions of a discrete read process. In other words, in each memory cell 310A, 310B, the write circuit (including the first access transistor in the first cell segment and having a gate controlled by a common write word line, and the second access transistor in the second cell segment and having a gate controlled by the same common write word line) enables the first variable resistor and the second variable resistor to be driven while being subjected to the same write bias conditions. In addition, in each memory cell 310A, 310B, a first read circuit (including another first access transistor in the first cell segment and having a gate controlled by the first read word line) enables a first read process associated only with the first variable resistor, and a separate second read circuit (including another second access transistor in the second cell segment and having a gate controlled by the second read word line) enables only a second read process associated with the second variable resistor.

[0068] More specifically, the circuits 300A, 300B may be configured to function as a PUF for consistently generating and outputting identical random numbers (ie, identical unique bit strings) in response to repeated challenges.

[0069] To achieve this, the controller 395 may be configured to selectively operate each memory cell 310A, 310B in an initialization mode for an initialization process before selectively operating the memory cell in a read-only mode of operation for bit string generation.

[0070] Operations on the selected memory cells 310A, 310B in the initialization mode may include causing a write process to be performed in the selected memory cells 310A, 310B to implement one-time programming of the memory cells from an unprogrammed state having no storage bits to a random programmed state having storage bits (wherein the 0 or 1 logic value of the storage bits is a function of random process variables and, therefore, is random and unknowable before the one-time programming is completed).

[0071] That is, in an unprogrammed state, multiple variable resistors of a memory cell may all have the same first resistance state, so that no bit is stored therein. For example, consider an STT-MTJ that is typically fabricated on a chip in a manner that causes all STT-MTJs to be initially in a RAP state. Thus, when the memory cells 310A, 310B of the circuits 300A, 300B include STT-MTJs as variable resistors, each memory cell 310A, 310B will initially have an unprogrammed state, in which all STT-MTJs are in a RAP state, or more specifically, in the same high resistance state, with a resistance above a specific high resistance level.

[0072] In order to enable a write process to be performed in the selected memory cell 310A, 310B, a limited write bias condition may be applied to the bit line 321 and the source line 323 connected to the selected memory cell (as discussed in more detail below), and the common write word line 333 connected to the selected memory cell may be activated (i.e., a high positive voltage, such as VDD, may be applied to the common write word line 333) so as to simultaneously turn on a first access transistor 340.1a and a second access transistor 340.2a, thereby simultaneously applying the limited write bias condition to the first variable resistor 350.1 (or, if applicable, to the parallel first variable resistors 350.1(a)-(m)) and the second variable resistor 350.2 (or, if applicable, to the parallel second variable resistors 350.2(a)-(m)). During the write process, the first read word line 331 and the second read word line 332 may remain disabled (e.g., discharged to ground) so that the other first and second access transistors 340.1b and 340.2b remain turned off. For the memory cell 310A, given the possible existence of random process variables, limited write bias conditions may be predetermined such that they cause only the first variable resistor 350.1 or the second variable resistor 350.2, but not both, to switch the resistance state to a second resistance state different from the first resistance state. For the memory cell 310B, given the possible existence of random process variables, limited write bias conditions may be predetermined such that at least one of the first variable resistors 350.1(a)-(m) or at least one of the second variable resistors 350.2(a)-(m), but not including the combination of the first variable resistor and the second variable resistor, switches the resistance state to the second resistance state.

[0073] For example, if the variable resistor in the memory cell 310A is an STT MTJ, then the limited write bias condition can be predetermined so that the resistance state of the first STT-MTJ or the second STT-MTJ switches to the RP state so as to have a resistance lower than a specific low resistance level (which is lower than the above-mentioned high resistance level associated with the RAP state). If the variable resistor in the memory cell 310B is an STT-MTJ, the limited write bias condition can be predetermined so that, ideally, the resistance state of one or more of the first STT-MTJs or one or more of the second STT-MTJs switches to the RP state (rather than both the first and second STT-MTJs). Therefore, in any of the memory cells 310A, 310B, the limited write bias condition can be selected so that the result of the programming process will be: R1 of the first variable resistor is less than R2 of the second variable resistor or R1 of the first variable resistor is greater than R2 of the second variable resistor.

[0074] As mentioned above, Figure 4AAs shown, when a positive voltage pulse is applied to the first terminal 11 (i.e., at the free ferromagnetic layer 351), the STT-MTJ switches to the RP state, and the second terminal 12 at the pinned ferromagnetic layer 352 is discharged to ground, causing a write current (Iwrite) to flow through the device from the first terminal 11 to the second terminal 12. The voltage level and duration of the positive voltage pulse are predetermined, so that, given the design of the STT-MTJ, the positive voltage pulse is at a sufficiently high level and applied for a sufficiently long duration to ensure that the Iwrite threshold for RAP to RP switching is reached in most, if not all, STT MTJs manufactured according to the design, without taking into account any random process variables.

[0075] In contrast, in the write process employed herein, which is designed to achieve one-time random programming of selected memory cells, the write bias conditions are limited. Specifically, instead of using a positive voltage pulse at a sufficiently high voltage level for a sufficiently long duration to ensure that the Iwrite threshold required for RAP to RP switching is reached in all STT MTJs of the memory cells regardless of any random process variations, the positive voltage pulse used should be at a relatively low voltage level for a relatively short time so that the Iwrite threshold required for RAP to RP switching is reached in only one STT MTJ in view of the possible existence of random process variations. Specifically, random process variations in STT MTJs manufactured according to the same design may result in the STT MTJs having different Iwrite thresholds for RAP to RP switching (e.g., ranging from a relatively low Iwrite threshold for fast switching to a relatively high Iwrite threshold for slow switching). When all STT MTJs are subjected to the same write bias conditions simultaneously, the optimal positive voltage pulse (i.e., voltage level and duration) for causing RAP to RP switching in only one STT-MTJ within the memory cells 310A, 310B can be predetermined, although the simulation gives the probability distribution of the Iwrite threshold variation due to random process variables.

[0076] For example, in a memory cell 310A having one first variable resistor 350.1 and one second variable resistor 350.2, the particular positive voltage pulse used may be a pulse that will achieve an Iwrite amount close to the peak of the Iwrite threshold change probability distribution, such that only one of the two variable resistors may have an Iwrite threshold higher than the actual Iwrite, while the other does not, and such that only one of the two resistors will switch from RAP to RP, while the other will not. In a memory cell 310B having a plurality of first variable resistors 350.1(a)-(m) in parallel and a plurality of second variable resistors 350.2(a)-(m) in parallel, a lower voltage level and / or a shorter pulse duration may be employed because only one of the four or more variable resistors within the memory cell 310B needs to switch from RAP to RP. It should be noted that the write process in the memory cell 310B may be considered successful if the plurality of first variable resistors or the plurality of second variable resistors switch resistance states, but not if a combination of both the first variable resistors and the second variable resistors switch resistance states.

[0077] Operations on the selected memory cells 310A, 310B in the initialization mode may also include causing discrete read processes to be performed in the selected memory cells to confirm the success of the write process, thereby confirming the states of the selected memory cells to be in random programmed states.

[0078] Specifically, the operation on the selected memory cells 310A, 310B in the initialization mode may include causing a first read process and a second read process to be performed.

[0079] To perform a first read process, a read bias condition may be applied to the bit line 321 and source line 323 connected to the selected memory cell. The read bias condition may include a relatively low positive voltage on the bit line 321 and a discharge of the source line 323. The first read word line 331 connected to the selected memory cell may be activated (i.e., a high positive voltage, such as VDD, may be applied to the first read word line 331) to turn on the first access transistor 340.1b. All other read word lines connected to the selected memory cell may be deactivated (e.g., discharged to ground) so that the other access transistors within the selected memory cell are all turned off. When the first variable resistor 350.1 (or, if applicable, any parallel first variable resistors 350.1 (a)-(m)) has a switched resistance state to have a resistance below a certain low resistance level, a relatively large amount of read current (Iread) will flow through the first access transistor 340.1b to the source line 323 to indicate that the R1 of the first variable resistor is less than the R2 of the second variable resistor. When the resistance of the first variable resistor 350.1 (or, if applicable, the resistance of all parallel first variable resistors 350.1(a)-(m)) remains above the high resistance level, little or no read current (Iread) will flow through the first access transistor 340.1b to the source line 323 to indicate that the first variable resistor R1 is less than the second variable resistor R2.

[0080] To perform the second read process, a read bias condition may be applied to the bit line 321 and source line 323 connected to the selected memory cell. The read bias condition may include a relatively low positive voltage on the bit line 321 and a discharge of the source line 323. However, in this case, the second read word line 332 connected to the selected memory cell may be activated (i.e., a high positive voltage, such as VDD, may be applied to the second read word line 332) so as to turn on the second access transistor 340.2b. All other read word lines connected to the selected memory cell may be deactivated (e.g., discharged to ground) so that the other access transistors within the selected memory cell are all turned off. When the second variable resistor 350.2 (or, if applicable, any parallel second variable resistors 350.2 (a)-(m)) has a switched resistance state to have a resistance below a specific low resistance level, a relatively large amount of read current (Iread) will flow through the second access transistor 340.2b to the source line 323. When the resistance of second variable resistor 350.2 (or, if applicable, the resistance of parallel second variable resistors 350.2(a)-(m)) remains above a certain high resistance level, little or no read current (Iread) will flow through second access transistor 340.1b to source line 323.

[0081] The sensing circuit 393 may be configured to sense any changes in the current on the source line 323 during the first and second read processes described above so that the success of the previously performed write process can be confirmed. For example, the sensing circuit 393 may include comparators 360 for the columns. Each comparator 360 may be connected to the source line 323 for the column and a reference circuit (not shown), and may compare (i.e., may be adapted to compare, configured to compare, etc.) a read current (Iread) input from the source line 323 and a reference current (Iref) input from the reference circuit. Iref may be set to a predetermined current level that is between a first expected Iread when the resistance of the variable resistor in the memory cell is above a specific high resistance level and a second expected Iread when the resistance of the variable resistor is below a specific low resistance level. Thus, if Iref is higher than the Iread input, the output of comparator 360 will indicate that none of the variable resistors subjected to the read bias condition during the read process are in a low resistance state; however, if Iref is lower than the Iread input, the output of comparator 360 will indicate that at least one variable resistor subjected to the read bias condition during the read bias condition is in a low resistance state.

[0082] The sensing circuit 393 can also be configured to transmit the output of the comparator 360 from the first and second read processes to the controller 395, and the controller 395 can be configured to analyze the output to determine: (a) whether the resistance state of any variable resistor in the selected memory cell was switched during the write process; and (b) if so, whether only the resistance state of the first variable resistor or the second variable resistor was switched, so that the selected memory cell is now in a random programming state and stores a bit. It should be noted that the logic value of the bit will depend on whether the first variable resistor 350.1 (or, if applicable, one or more parallel first variable resistors 350.1 (a)-(m)) or the second variable resistor 350.2 (or, if applicable, one or more parallel second variable resistors) has a switched resistance state (e.g., has been switched to a low resistance state with a resistance below a low resistance level).

[0083] In an exemplary embodiment, if the first variable resistor 350.1 has been switched to the low resistance state (or, if applicable, if one or more parallel first variable resistors 350.1(a)-(m) have been switched to the low resistance state), the storage cell can be considered to store a bit with a logical value of 1. In this same storage cell, the second variable resistor 350.2 will remain in the high resistance state (or, if applicable, all parallel second variable resistors will remain in the high resistance state). However, if the first variable resistor 350.1 remains in the high resistance state (or, if applicable, if all parallel first variable resistors remain in the high resistance state), the storage cell can be considered to store a bit with a logical value of 0. In this same storage cell, the second variable resistor 350.2 has been switched to the low resistance state (or, if applicable, one or more parallel second variable resistors 350.2(a)-(m) have been switched to the low resistance state). In other words, if the R1 of the first variable resistor > the R2 of the second variable resistor, the logical value of the stored bit is 0, and if R1 < R2, the logical value of the stored bit is 1.

[0084] Optionally, the operation of the selected storage cells 310A, 310B in the initialization mode may further include, when the write process is considered unsuccessful (e.g., because no variable resistor has switched state, because all variable resistors have switched state, or because, in storage cell 310B, the combined switching state of the first and second variable resistors), repeating the write process with adjusted write bias conditions and further repeating the first and second read processes to confirm the success of the subsequent write process. For example, if all variable resistors within the selected storage cell maintain their current resistance states (i.e., if no resistance state has been switched), a different positive voltage pulse with a higher voltage level and / or a longer duration can be used to repeat the write process. In other words, each storage cell can undergo a series of write processes, with the first and second read processes in between, until it is determined that the storage cell has been successfully programmed. For each successive write process, the bias (i.e., voltage level) can be fixed and the time (i.e., pulse duration) can be increased, the time can be fixed and the bias can be increased, or both the bias and time can be increased. Very small incremental adjustments of the bias and / or time can be used to attempt to capture the small differences in the resistance state switching thresholds due to minimal process variations. After each write process, the first and second read processes can be repeated until it is determined that the write process is ultimately successful (e.g., in storage cell 310A, the first variable resistor or the second variable resistor has been switched to the low resistance state; in storage cell 310B, one or more first variable resistors or one or more second variable resistors (but not a combination of both) have been switched to the low resistance state). Then, the initialization mode for the said storage cell can be terminated.

[0085] If all variable resistors within the selected memory cell (or, if in memory cell 310B, the combination of the first and second variable resistors) are in the switched resistance state, a reset process may be performed to reset all variable resistors to their original resistance states, and then the write process may be repeated using a different positive voltage pulse having a lower voltage level and / or shorter duration. Optionally, when the write process is deemed unsuccessful after an initial attempt or after one or more subsequent attempts, the controller 395 may mark the selected memory cell as unavailable / faulty and bypass the selected memory cell during subsequent operations (e.g., during bit string generation, discussed below).

[0086] After the initialization process, each memory cell 310A, 310B in the memory array will be in a random programming state, or, if applicable, marked as unavailable / faulty. It should be understood that the "random programming state" refers to the fact that the memory cell 310A, 310B has undergone successful one-time programming to store a bit, which randomly has a logic value of 0 or a logic value of 1. Specifically, the logic value of the storage bit depends on whether the first variable resistor (or, if applicable, one or more parallel first variable resistors) or the second variable resistor (or, if applicable, one or more parallel second variable resistors) has a low resistance state. Since the switching of the resistance state of only the first variable resistor or the second variable resistor in the presence of the same write bias conditions is due to random process variables, the conditions that lead to a storage bit with a logic value of 0 or a logic value of 1 in any given memory cell are random and unpredictable.

[0087] The controller 395 may also be configured to operate all memory cells 310A, 310B that have successfully undergone one-time programming in an operational read-only mode. Operating the memory cells 310A, 310B in an operational read-only mode may include causing a read process to be performed in each of these memory cells (e.g., in response to a challenge) to sequentially read out the stored bits so as to generate a unique bit string.

[0088] For example, as described above in the exemplary embodiment, if the memory cells 310A, 310B in the random programming state store bits with a logic value of 1, the first variable resistor 350.1 will switch to the low resistance state (or, if applicable, one or more parallel first variable resistors 350.1(a)-(m) will switch to the low resistance state) and the second variable resistor 350.2 (or, if applicable, all parallel second variable resistors 350.2(a)-(m)) will remain in the high resistance state. If the memory cells 310A, 310B in the random programming state store bits with a logic value of 0, the first variable resistor 350.1 will remain in the high resistance state (or, if applicable, all parallel first variable resistors 350.1(a)-(m) will remain in the resistance state) and the second variable resistor 350.2 (or, if applicable, one or more parallel second variable resistors 350.2(a)-(m)) will switch to the low resistance state. Thus, operating the memory cells 310A, 310B in the operation read-only mode may include causing each memory cell 310A, 310B to perform the same above-described read process employed during the initialization mode to determine the stored bit. However, since there are only two possible resistance states in this case, the first variable resistor of the memory cell in the random programming state will switch to the low resistance state or remain in the high resistance state, and thus only the first read process is actually needed to determine the value of the stored bit. That is, a read bias condition may be applied to the bit line 321 and the source line 323 connected to the selected memory cell. The first read word line 331 connected to the selected memory cell may be activated. All other read word lines connected to the selected memory cell may be deactivated. Then, the comparator 360 connected to the source line 323 may compare the read current (Iread) input from the source line 323 with the reference current (Iref) input. If Iref is higher than the Iread input (indicating R1 > R2), the output of the comparator 360 will indicate a stored bit with a logic value of 0; however, if Iref is lower than the Iread input (indicating R1 < R2), the output of the comparator 360 will indicate a stored bit with a logic value of 1. The stored bits from the memory cells may be read out in sequence to generate and output a unique bit string.

[0089] It should be noted that once the memory cells 310A, 310B in the memory array are in the random programming state, the bit storage (regardless of whether the bit has a logic value of 1 or a logic value of 0) will be stable. That is, during the operation read-only mode, each time the first read process is performed to read out the bit stored in the bit string, the same logic value will be consistently read out from a given memory cell. This is because, as described above, and further as Figure 5As shown in the graph of FIG. 5 , the resistance of the variable resistor in the high resistance state will be higher than a certain high resistance level 501, while the resistance of the variable resistor in the low resistance state will be lower than a certain low resistance level 502, which is lower than the high resistance level 501. In addition, there is a relatively large difference between the high resistance level 501 and the low resistance level 502, so that R1 will not be approximately equal to R2 in any programmed memory cell. Therefore, even when there is a change in operating conditions between repeated first read processes performed on the same memory cell, the probability that any change in R1 or R2 will result in a resistance state change or a read error is very low.

[0090] Therefore, the above-described on-chip circuits 300A, 300B are configured to generate and output identical unique bit strings in response to repeated challenges, and thus can be used as robust PUFs.

[0091] As mentioned above, for the purpose of illustration, the memory cells 310A, 310B in the circuits 300A, 300B are described above as including a variable resistor having two resistance states, and more specifically, including an STT-MTJ.

[0092] However, it should be understood that in other embodiments, the variable resistors in the memory cells 310A, 310B of the circuits 300A, 300B may be PCM type variable resistors, or may be memristors specifically configured to switch between only two resistance states. For the initialization mode, when the common word line connected to the memory cell is activated, the write bias conditions applied to the bit line and source line connected to the memory cell and thereby simultaneously applied to the two terminals of all variable resistors (which are initially in the same resistance state) will be predetermined to achieve, given the type of variable resistor and further in view of the possible existence of process variables, the switching of only the first variable resistor or only the second variable resistor in the case of the memory cell 310A (or, if applicable, the switching of only one or more parallel first variable resistors or only one or more parallel second variable resistors, but not a combination of the two) in the case of the memory cell 310B. During the initialization mode, the first and second reading processes may also be formed in the same manner as described above to confirm the success of the write process (i.e., to confirm the success of the one-time programming). During a read-only mode of operation, the stored bits may be sequentially read from the memory cells in the same manner as described above to generate a unique bit string.

[0093] It should also be understood that in other embodiments, the variable resistors in the memory cells 310A, 310B of the circuits 300A, 300B may be memristors specifically configured to switch between two or more resistance states (e.g., three different resistance states, low (L), medium (M), or high (H)). In this case, during the initialization mode, different schemes may be used to program the possible memory cells of a given random process variable, determine whether the programming is successful, and identify the logical value of the storage bit. For example, if the variable resistors in the memory cell 310A of the circuit 300A are all memristors with three programmable resistance states, the initialization mode programming may start with all memristors with the same high resistance state (H, H), and may be designed so that at least the first variable resistor or the second variable resistor is switched to the medium resistance state or the low resistance state, rather than both being switched to the low resistance state. The first and second read processes may be performed to determine the resistance states of the first and second variable resistors, thereby confirming that the programming is successful. Different resulting combinations of resistance states in the first and second variable resistors (e.g., LM, LH, ML, MM, MH, HL, or HM) can represent different storage values ​​(e.g., 0, 1, 2, 3, 4, 5, or 6) in the programmed memory cell. During a read-only mode of operation (e.g., in a PUF), the storage values ​​can be read out of the memory cells in sequence to generate a unique bit string. That is, a memory cell can be selected, and the first and second read processes can be performed in the selected memory cell to determine the resistance states of the first and second variable resistors therein. The controller can capture these resistance states and can output the storage value represented by the combination. Then, the next memory cell in the sequence can be selected, and so on.

[0094] refer to Figure 6 , disclosed herein are method embodiments for operating the above-mentioned on-chip circuits 300A, 300B (eg, physically unclonable functions (PUFs)) and the storage units 310A, 310B contained therein.

[0095] Specifically, the method embodiment may include providing on-chip circuits 300A, 300B (see Figure 3A and 3B ), which includes a memory array having a plurality of memory cells 310A, 310B, which are arranged in columns A- N and line a- n and is randomly programmable (see process step 602).

[0096] As discussed in more detail above, the circuits 300A, 300B may include bit lines 321 and source lines 323 for columns, and all memory cells 310A, 310B in the same column may be connected to the bit lines 321 and source lines 323 for the columns. The circuits 300A, 300B may also include a plurality of word lines for rows (including a common write word line 333, a first read word line 331, and a second read word line 332), and all memory cells 310, 310B in the same row may be connected to the word lines of the rows. The circuits 300A, 300B may also include a controller 395 and peripheral circuits 391-392 and sensing circuits that communicate with the controller 395.

[0097] Each memory cell 310A, 310B may be a twin-cell memory cell (also referred to herein as a dual-cell memory cell) comprising a first cell segment connected between a bit line and a source line for a column and a second cell segment connected to the same bit line and the same source line for the column. Specifically, each memory cell 310A, 310B may include a plurality of two-terminal variable resistors, in particular, one or more first variable resistors in the first cell segment and one or more second variable resistors in the second cell segment. For example, Figure 3A As shown, each memory cell 310A may include a first variable resistor 350.1 in the first unit section and a second variable resistor 350.2 in the second unit section. Figure 3B As shown, each memory cell 310B may include a plurality of first variable resistors 350.1(a)-(b) connected in parallel in a first unit section. m ) and a plurality of second variable resistors 350.2(a)-( m ).

[0098] In some embodiments, the two-terminal variable resistor in each memory cell 310A, 310B is a spin transfer torque type magnetic tunnel junction (STT-MTJ). In other embodiments, different types of two-terminal variable resistors (e.g., phase change memory type variable resistors, memristors, etc.) may be alternatively incorporated into the memory cells 310A, 310B. For purposes of illustration, the method is described in more detail below, and with respect to circuit operation when the memory cell includes an STT MTJ. Each memory cell 310A, 310B may also include a plurality of access transistors, the plurality of access transistors including two parallel first access transistors 340.1ab in the first cell segment and two parallel second access transistors 340.2ab in the second cell segment. For example, the access transistors may all be n-type field effect transistors (NFETs). In each memory cell 310A, 310B of a given column and row, a first access transistor 340.1ab and a first variable resistor 350.1 (or, if applicable, first variable resistors 350.1(a)-( m )) may be connected in series between the bit line 321 and the source line 323 of the column. In addition, the second access transistor 340.2ab and the second variable resistor 350.2 (or, if applicable, the second variable resistors 350.2(a)-( m )) can be connected in series between the same bit line 321 and the same source line 323 for the column. In addition, in each memory cell 310A, 310B in a given column and row, the gates of the two parallel first access transistors 340.1ab can be connected to the common write word line 333 and the first read word line 331 of the row, respectively. The gates of the two parallel second access transistors 340.2ab can be connected to the same common write word line 333 and the second read word line 332 of the row, respectively.

[0099] Method embodiments may also include operating the on-chip circuits 300A, 300B as a PUF to consistently generate and output identical random numbers (ie, identical unique bit strings) in response to repeated challenges.

[0100] To accomplish this, a method embodiment may first include selectively operating (eg, via controller 395) each memory cell 310A, 310B in an initialization mode (see process step 604) prior to allowing any read-only functions to be performed for bit string generation.

[0101] The operation on the selected memory cells 310A, 310B in the initialization mode of process step 604 may include performing a write process in the selected memory cells 310A, 310B to achieve one-time programming of the memory cells from an unprogrammed state without a storage bit to a random programmed state with a storage bit (wherein the 0 or 1 logic value of the storage bit is a function of a random process variable and, therefore, is random and unknowable before the one-time programming is completed).

[0102] Specifically, in the circuits 300A, 300B provided in process step 602, all memory cells 310A, 310B may be in an unprogrammed state. That is, in each memory cell, multiple variable resistors of the memory cell may have the same first resistance state, such that no bit is stored therein. For example, consider an STT MTJ that is typically fabricated on a chip in a manner that causes all STT MTJs to be initially in a RAP state. Thus, when the memory cells 310A, 310B of the circuits 300A, 300B include STT-MTJs as variable resistors, each memory cell 310A, 310B will initially have an unprogrammed state, wherein all STT-MTJs are in a RAP state, or more specifically, in the same high resistance state having a resistance above a particular high resistance level.

[0103] To perform a write process in a selected memory cell 310A, 310B, a limited write bias condition may be applied to the bit line 321 and the source line 323 connected to the selected memory cell (as discussed in more detail below), and a common write word line 333 connected to the selected memory cell may be activated (i.e., a high positive voltage, such as VDD, may be applied to the common write word line 333) to simultaneously turn on a first access transistor 340.1a and a second access transistor 340.2a, thereby simultaneously applying a limited write bias condition to the first variable resistor 350.1 (or, if applicable, the parallel first variable resistors 350.1(a)-( m )) and the second variable resistor 350.2 (or, if applicable, the second variable resistor 350.2(a)-( m )).

[0104] During this write process, the first read word line 331 and the second read word line 332 may remain disabled (e.g., discharged to ground) so that the other first and second access transistors 340.1b and 340.2b remain turned off. For the memory cell 310A, in view of the possible existence of random process variables, the limited write bias conditions may be predetermined so that they only cause the first variable resistor 350.1 or the second variable resistor 350.2 (but not both) to switch the resistance state to a second resistance state different from the first resistance state. For the memory cell 310B, in view of the possible existence of random process variables, the limited write bias conditions may be predetermined so that the first variable resistor 350.1(a)-(b) m ) or at least one of the second variable resistors 350.2(a)-( m ) (but not including the combination of the first variable resistor and the second variable resistor) switches the resistance state to the second resistance state. Therefore, in any memory cell 310A, 310B, the limited write bias condition applied during the write process can be selected so that the result of the programming process will be: R1 of the first variable resistor is smaller than R2 of the second variable resistor, or R1 of the first variable resistor is larger than R2 of the second variable resistor.

[0105] The operation on the selected memory cells 310A, 310B in the initialization mode of process step 604 may also include performing a discrete read process in the selected memory cells to confirm the success of the write process, thereby confirming that the state of the selected memory cells is in a random programming state. Specifically, the operation on the selected memory cells 310A, 310B in the initialization mode may include performing a first read process associated with the first variable resistor and a second read process associated with the second variable resistor.

[0106] During a first read process, a read bias condition may be applied to the bit line 321 and source line 323 connected to the selected memory cell. The read bias condition may include a relatively low positive voltage on the bit line 321 and a discharge of the source line 323. The first read word line 331 connected to the selected memory cell may be activated (i.e., a high positive voltage, such as VDD, may be applied to the first read word line 331) so as to turn on the first access transistor 340.1b. All other read word lines connected to the selected memory cell may be deactivated (e.g., discharged to ground) so that the other access transistors within the selected memory cell are all turned off. When the first variable resistor 350.1 (or, if applicable, any parallel first variable resistors 350.1(a)-( m)) has a switched resistance state to have a resistance below a certain low resistance level, a relatively large amount of read current (Iread) will flow through the first access transistor 340.1b to the source line 323 to indicate that the first variable resistor R1 is less than the second variable resistor R2. When the resistance of the first variable resistor 350.1 (or, if applicable, all the first variable resistors 350.1(a)-( m ) is maintained above a certain high resistance level, little or no read current (Iread) will flow through the first access transistor 340.1b to the source line 323, indicating that the first variable resistor R1 is less than the second variable resistor R2.

[0107] During the second read process, read bias conditions may be applied to the bit line 321 and source line 323 connected to the selected memory cell. The read bias conditions may include a relatively low positive voltage on the bit line 321 and the discharge of the source line 323. However, in this case, the second read word line 332 connected to the selected memory cell may be activated (i.e., a high positive voltage, such as VDD, may be applied to the second read word line 332) so as to turn on the second access transistor 340.2b. All other read word lines connected to the selected memory cell may be deactivated (e.g., discharged to ground) so that the other access transistors within the selected memory cell are all turned off. When the second variable resistor 350.2 (or, if applicable, any parallel second variable resistors 350.2 (a)-( m )) has a switched resistance state to have a resistance below a certain low resistance level, a relatively large amount of read current (Iread) will flow through the second access transistor 340.2b to the source line 323. When the resistance of the second variable resistor 350.2 (or, if applicable, the parallel second variable resistors 350.2(a)-( m ) is maintained above a certain high resistance level, little or no read current (Iread) will flow through the second access transistor 340.1b to the source line 323.

[0108] Both the first and second read processes may include sensing (e.g., using comparator 360) any change in the current on source line 323 as a result of the first read process and as a result of the second read process, so that the success of a previously performed write process can be confirmed. For example, during each read process, a read current (Iread) input from source line 323 and a reference current (Iref) input from a reference circuit can be compared (e.g., by a comparator). Iref can be set at a predetermined current level that is between a first expected Iread when the resistance of the variable resistor in the memory cell is higher than a particular high resistance level and a second expected Iread when the resistance of the variable resistor is lower than a particular low resistance level. Thus, if Iref is higher than the Iread input, the output of comparator 360 will indicate that none of the variable resistors subjected to the read bias condition during the read process are in the low resistance state; however, if Iref is lower than the Iread input, the output of comparator 360 will indicate at least one variable resistor subjected to the read bias condition during the read bias condition in the low resistance state.

[0109] Additional initialization mode processing at process step 604 may include comparing (e.g., by controller 395 in communication with comparator 360), the comparator outputs from the first and second read processes to determine: (a) whether the resistance state of any of the variable resistors in the selected memory cell was switched during the write process; and (b) if so, whether only the resistance state of the first variable resistor or the second variable resistor was switched such that the selected memory cell is currently in a random programming state and stores a bit. It should be noted that the logical value of the bit will depend on whether the first variable resistor 350.1 (or, if applicable, one or more parallel first variable resistors 350.1(a)-( m )) or the second variable resistor 350.2 (or, if applicable, one or more parallel second variable resistors) has its resistance state switched (e.g., switched to a low resistance state with a resistance lower than the low resistance level). In an exemplary embodiment, if the first variable resistor 350.1 has been switched to the low resistance state (or, if applicable, if one or more parallel first variable resistors 350.1(a)-( m ) have been switched to the low resistance state), the memory cell can be considered to store a bit with a logical value of 1. However, if the first variable resistor 350.1 remains in the high resistance state (or, if applicable, if all parallel first variable resistors remain in the high resistance state), the memory cell can be considered to store a bit with a logical value of 0. In other words, if R1 of the first variable resistor > R2 of the second variable resistor, the logical value of the stored bit is 0, and if R1 < R2, the logical value of the stored bit is 1.

[0110] Optionally, the additional initialization mode processing at process step 604 may include, when the write process is deemed unsuccessful, repeating the write process with adjusted write bias conditions (e.g., with a higher bias voltage and / or a longer pulse duration), and further repeating the first and second read processes to confirm the success of the subsequent write process. In other words, the memory cell may be subjected to a series of write processes with a first and second read process in between until it is determined that the memory cell is successfully programmed. For each consecutive write process, the bias (i.e., voltage level) may be fixed and the time (i.e., pulse duration) may be increased, the time may be fixed and the bias may be increased, or the bias and time may be increased simultaneously. Very small incremental adjustments of the bias and / or time may be used to try and capture very small differences in the resistance state switching thresholds due to minimal process variations. After each write process, the first and second read processes may be repeated until it is determined that the write process is ultimately successful (i.e., in the memory cell 310A, the first variable resistor or the second variable resistor has switched to the low resistance state; in the memory cell 310B, one or more of the first variable resistors or one or more of the second variable resistors (but not a combination of both) have switched to the low resistance state). Then, the initialization mode with respect to the memory cell may be terminated.

[0111] Optionally, additional initialization processing at process step 604 may also include, when the write process is deemed unsuccessful after an initial attempt or after one or more subsequent attempts, marking the selected storage cell as unavailable / faulty so as to be biased during subsequent operations (e.g., during bit string generation, discussed below).

[0112] The method embodiment may also operate (e.g., by the controller 395) all memory cells 310A, 310B that have successfully undergone one-time programming in an operational read-only mode (see process step 606) after the initialization process of process step 604. Operating the memory cells 310A, 310B in the operational read-only mode may include performing a read process (e.g., in response to a challenge) in each of these memory cells to sequentially read out the stored bits so as to generate a unique bit string.

[0113] For example, as described above in the exemplary embodiment, if the memory cell 310A, 310B in the random programming state stores a bit with a logic value of 1, the first variable resistor 350.1 will switch to a low resistance state (or, if applicable, one or more parallel first variable resistors 350.1(a)-(b)). m ) will switch to a low resistance state). If the memory cells 310A, 310B in the random programming state store a bit with a logic value of 0, the first variable resistor 350.1 will remain in a high resistance state (or, if applicable, all parallel first variable resistors 350.1(a)-(m ) will maintain the resistance state). Thus, operating the memory cells 310A, 310B in the operation read-only mode may include performing the same first read process as employed during the initialization mode. That is, a read bias condition may be applied to the bit line 321 and the source line 323 connected to the selected memory cell. The first read word line 331 connected to the selected memory cell may be activated. All other read word lines connected to the selected memory cell may be deactivated. A read current (Iread) input from the source line 323 may be compared with a reference current (Iref) input. If Iref is higher than the Iread input (indicating R1 > R2), the output from the comparator 360 to the controller 395 will indicate a stored bit with a logic value of 0; however, if Iref is lower than the Iread input (indicating R1 < R2), the output from the comparator 360 to the controller 395 will indicate a stored bit with a logic value of 1. The stored bits from the memory cells may be read out in sequence (e.g., by the controller 395), thereby generating and outputting a unique bit string.

[0114] It should be noted that after process step 604, one of the memory cells 310A, 310B in the memory array is in a random programming state, and the bit storage (regardless of whether the bit has a logic value of 1 or a logic value of 0) will be stable. That is, during the operation read-only mode, each time the first read process is performed to read out the stored bits included in the bit string, the same logic value will be consistently read out from a given memory cell. This is because, as described above, and further as Figure 5 shown in the diagram of, the resistance of the variable resistor in the high resistance state will be higher than a certain specific high resistance level 501, and the resistance of the variable resistor in the low resistance state will be lower than a certain specific low resistance level 502, where the low resistance level 502 is lower than the high resistance level 501. In addition, there is a relatively large difference between the high resistance level 501 and the low resistance level 502, such that in any programmed memory cell, R1 will not be approximately equal to R2. Therefore, even when there are variations in the operating conditions between repeated first read processes performed on the same memory cell, the likelihood of any change in R1 or R2 resulting in a change in the resistance state or a read error will be very low. Thus, in process step 606, in response to repeated challenges, an exactly identical unique bit string may be generated and output.

[0115] It should be understood that the terms used herein are intended to describe disclosed structures and methods, rather than being restrictive. For example, as used herein, unless the context clearly indicates otherwise, the singular forms "one", "one" and "described" are also intended to include plural forms. In addition, as used herein, the terms "include", "include", "include" and / or "include" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their combinations. In addition, as used herein, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "up", "down", "below", "below", "below", "above", "above", "parallel", "orthogonal", etc., are used to describe relative positions, as shown in the accompanying drawings (unless otherwise indicated), and terms such as "touching", "direct contact", "adjacent", "directly adjacent", "close to", etc., are intended to indicate that at least one element is in physical contact with another element (no other elements separate the elements). The term "laterally" is used herein to describe the relative position of elements, and more specifically, to indicate that one element is positioned to the side of another element relative to above or below another element as the elements are oriented and shown in the drawings. For example, an element that is laterally adjacent to another element will be located beside the other element, an element that is laterally adjacent to another element will be located directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed.

[0116] The description of various embodiments of the present invention is given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A memory cell, comprising: A plurality of variable resistors, including: a first variable resistor; and a second variable resistor, wherein if the R1 of the first variable resistor > the R2 of the second variable resistor, the logical value of the stored bit is 0, and if R1 < R2, the logical value of the stored bit is 1; and A plurality of transistors, including: two first transistors connected in parallel; and two second transistors connected in parallel, wherein the first transistor is connected in series with the first variable resistor between a bit line and a source line, and the first transistor has gates respectively connected to a common write word line and a first read word line, and wherein the second transistor and the second variable resistor are connected in series between the bit line and the source line, and the second transistor has gates respectively connected to the common write word line and a second read word line.

2. The memory cell according to claim 1, in, The memory cell is operable in an initialization mode for one-time programming from an unprogrammed state to a random programmed state, wherein, in the unprogrammed state, the plurality of variable resistors are all in a first resistance state, wherein, in the random programmed state, one of the first variable resistor and the second variable resistor is in a second resistance state different from the first resistance state, and the memory cell stores a bit having a logical value that depends on whether the first variable resistor is in the second resistance state, and wherein, when operating in the initialization mode, the memory cell performs a write process, including: in response to a write bias condition on the bit line and the source line and activation of the common write word line, and further in accordance with the presence of a random process variable, switching one of the plurality of variable resistors to the second resistance state.

3. The storage unit according to claim 2, wherein: The random process variable determines which one of the plurality of variable resistors switches to the second resistance state, such that the logical value of the bit is unknown before the one-time programming.

4. The storage unit according to claim 2, wherein: When operating in the initialization mode, the memory cell also performs a first read process and a second read process respectively using the first read word line and the second read word line to determine the success of the write process.

5. The memory cell according to claim 2, in, The first variable resistor includes a first spin transfer torque type magnetic tunnel junction, and the second variable resistor includes a second spin transfer torque type magnetic tunnel junction, wherein the first resistance state is a high resistance state associated with a resistance higher than a high resistance level, and the second resistance state is a low resistance state associated with a resistance lower than a low resistance level, the low resistance level being lower than the high resistance level, and wherein the write bias condition includes: a specific positive voltage pulse on the bit line and discharging the source line to ground.

6. The storage unit according to claim 1, wherein: The variable resistor includes any spin transfer torque type magnetic tunnel junction, phase change memory type variable resistor, and memristor.

7. The memory cell according to claim 1, in, The plurality of variable resistors includes: A first variable resistor, connected in parallel between the first transistor and the source line; and A second variable resistor, connected in parallel between the second transistor and the source line, wherein the memory cell is operable in an initialization mode for one-time programming from an unprogrammed state to a random programmed state, wherein, in the unprogrammed state, the plurality of variable resistors are all in a first resistance state, and wherein, in the random programmed state, at least one of the first variable resistors or at least one of the second variable resistors is in a second resistance state different from the first resistance state, and the memory cell stores a bit having a logical value that depends on whether any of the first variable resistors is in the second resistance state, wherein, when operating in the initialization mode, the memory cell performs a write process, including: in response to a write bias condition on the bit line and the source line and activation of the common write word line, and further in accordance with the presence of a random process variable, switching at least one of the first variable resistors or at least one of the second variable resistors to the second resistance state, and wherein the random process variable determines which one of the plurality of variable resistors switches to the second resistance state such that the logical value of the bit is unknown prior to the one-time programming.

8. A circuit for a physical unclonable function, the circuit comprising: An array of memory cells arranged in columns and rows, wherein each memory cell includes: A plurality of variable resistors, including: a first variable resistor; and a second variable resistor, wherein if R1 of the first variable resistor > R2 of the second variable resistor, the logical value of the stored bit is 0, and if R1 < R2, the logical value of the stored bit is 1; and A plurality of transistors, including: two first transistors connected in parallel; and two second transistors connected in parallel, wherein the first transistor and the first variable resistor are connected in series between the bit line and the source line, and the first transistor has gates respectively connected to a common write word line and a first read word line, and wherein the second transistor and the second variable resistor are connected in series between the bit line and the source line, and the second transistor has gates respectively connected to the common write word line and a second read word line.

9. The circuit according to claim 8, in, The circuit further includes: a peripheral circuit operably connected to the bit lines and the source line of each column and the common write word line, the first read word line and the second read word line of each row; and a controller in communication with the peripheral circuit, wherein the peripheral circuit is configured to respond to a control signal from the controller to operate each memory cell in an initialization mode, wherein the operation of the memory cell in the initialization mode includes causing a write process to be performed in the memory cell to achieve one-time programming of the memory cell from an unprogrammed state to a random programmed state, Wherein, in the unprogrammed state, the plurality of variable resistors of the memory cell are all in a first resistance state, wherein, in the random programming state, one of the first variable resistor and the second variable resistor is in a second resistance state different from the first resistance state, and the memory cell stores a bit having a logic value, the logic value depending on whether the first variable resistor is in the second resistance state, and wherein the write process in the memory cell is caused by applying a write bias condition to the bit line and the source line connected to the memory cell and activating the common write word line connected to the memory cell, such that in response to the write bias condition and the activation of the common write word line, and further based on the presence of random process variables in the memory cell, one of the plurality of variable resistors within the memory cell switches to the second resistance state, wherein the peripheral circuit is further configured to cause the memory cell programmed to the random programming state to be operated in an operation read-only mode in response to an additional control signal from the controller, wherein the operation of the memory cell in the read-only mode of operation comprises performing a read process to sequentially read out stored bits from the memory cell, and Wherein, the controller is further configured to generate and output a bit string using the stored bits.

10. The circuit according to claim 9, wherein: The random process variable determines which of the plurality of variable resistors switches to the second resistance state such that the logic value of the bit is unknown prior to the one-time programming.

11. The circuit according to claim 9, wherein: The operation of the memory cell in the initialization mode further includes causing a first read process and a second read process to be performed in the memory cell using the first read word line and the second read word line connected to the memory cell, respectively, to confirm success of the write process.

12. The circuit according to claim 9, in, In each memory cell, the first variable resistor includes a first spin transfer torque type magnetic tunnel junction, and the second variable resistor includes a second spin transfer torque type magnetic tunnel junction, wherein the first resistance state is a high resistance state associated with a resistance higher than a high resistance level, and the second resistance state is a low resistance state associated with a resistance lower than a low resistance level, the low resistance level being lower than the high resistance level, and The write bias condition includes: a specific positive voltage pulse on the bit line and the source line is discharged to ground.

13. The circuit according to claim 8, wherein: In each memory cell, the plurality of variable resistors include any of a spin transfer torque type magnetic tunnel junction, a phase change memory type variable resistor, and a memristor.

14. The circuit according to claim 8, in, The plurality of variable resistors in each storage unit include: a first variable resistor connected in parallel between the first transistor and the source line; and a second variable resistor connected in parallel between the second transistor and the source line, and wherein the circuit is configured to operate each memory cell in an initialization mode, Among them, the operations of each storage cell in the initialization mode include causing a write process to be performed in the storage cell to achieve one-time programming of the storage cell from the unprogrammed state to the random programmed state. Among them, in the unprogrammed state, the multiple variable resistors of the storage cell are all in the first resistance state. Among them, in the random programmed state, at least one of the first variable resistors or at least one of the second variable resistors is in a second resistance state different from the first resistance state, and the storage cell stores a bit with a logical value, and the logical value depends on whether any of the first variable resistors has the second resistance state. Among them, the causing of performing the write process in the storage cell includes: applying a write bias condition to the bit line and the source line connected to the storage cell, and activating the common write word line connected to the storage cell, so that in response to the write bias condition and the activation of the common write word line, and further according to the presence of a random process variable in the storage cell, at least one of the first variable resistors or at least one of the second variable resistors is switched to the second resistance state. Among them, the random process variable determines which one of the multiple variable resistors is switched to the second resistance state, so that the logical value of the bit is unknown before the one-time programming, and Among them, the circuit is further configured to operate all storage cells programmed to the random programmed state in an operation read-only mode, causing the stored bits to be sequentially read out from the storage cells, thereby generating a bit string.

15. A method for a physical unclonable function, the method comprising: Providing an array of storage cells arranged in columns and rows, wherein each storage cell includes: Multiple variable resistors, including: a first variable resistor; and a second variable resistor, wherein if R1 of the first variable resistor > R2 of the second variable resistor, the logical value of the stored bit is 0, and if R1 < R2, the logical value of the stored bit is 1; Multiple transistors, including: two first transistors connected in parallel; and two second transistors connected in parallel, wherein the first transistor and the first variable resistor are connected in series between the bit line and the source line, and the first transistor has gates respectively connected to the common write word line and the first read word line, and wherein the second transistor and the second variable resistor are connected in series between the bit line and the source line, and the second transistor has gates respectively connected to the common write word line and the second read word line; and Each memory cell is operated in an initialization mode, wherein the operation of the memory cell in the initialization mode includes: by applying a write bias condition on the bit line and the source line connected to the memory cell, and activating the common write word line connected to the memory cell, a write process is performed to achieve a one-time programming of the memory cell from an unprogrammed state to a random programmed state, so that in response to the write bias condition and the activation of the common write word line, and further according to the existence of a random process variable in the memory cell, the memory cell switches from the unprogrammed state to the random programmed state.

16. The method according to claim 15, in, The operation of each memory cell in the initialization mode further includes causing a first read process and a second read process to be performed in the memory cell using the first read word line and the second read word line connected to the memory cell, respectively, to confirm success of the write process, and The method further comprises operating all of the memory cells programmed to the random programming state in an operational read-only mode to cause the stored bits to be read out from the memory cells in sequence to generate a bit string.

17. The method according to claim 16, in, In the unprogrammed state, the plurality of variable resistors of the memory cell are all in a first resistance state, wherein, in the random programming state, one of the first variable resistor and the second variable resistor is in a second resistance state different from the first resistance state, and the memory cell stores a bit having a logic value, the logic value depending on whether the first variable resistor is in the second resistance state, wherein, in response to application of the write bias conditions on the bit line and the source line and activation of the common write word line, and further based on the presence of the random process variable, only one of the plurality of variable resistors switches to the second resistance state, and The random process variable determines which one of the plurality of variable resistors switches to the second resistance state, such that the logic value of the bit is unknown prior to the one-time programming.

18. The method according to claim 17, in, The first variable resistor includes a first spin transfer torque type magnetic tunnel junction, and the second variable resistor includes a second spin transfer torque type magnetic tunnel junction, wherein the first resistance state is a high resistance state associated with a resistance higher than a high resistance level, and the second resistance state is a low resistance state associated with a resistance lower than a low resistance level, the low resistance level being lower than the high resistance level, The write bias condition includes: a specific positive voltage pulse on the bit line and the source line is discharged to ground.

19. The method according to claim 17, wherein: In each memory cell, the plurality of variable resistors include any of a spin transfer torque type magnetic tunnel junction, a phase change memory type variable resistor, and a memristor.

20. The method according to claim 16, in, The plurality of variable resistors in each storage unit include: a first variable resistor connected in parallel between the two parallel-connected first transistors and the source line; and a second variable resistor connected in parallel between the two parallel-connected second transistors and the source line, and Wherein, in the unprogrammed state, the plurality of variable resistors of the memory cell are all in a first resistance state, wherein, in the random programming state, at least one of the first variable resistors or at least one of the second variable resistors is in a second resistance state different from the first resistance state, and the memory cell stores a bit having a logic value that depends on whether any of the first variable resistors is in the second resistance state, wherein in response to application of the write bias conditions on the bit line and the source line and activation of the common write word line, and further based on the presence of the random process variable, the at least one of the first variable resistors or the at least one of the second variable resistors switches to the second resistance state, and The random process variable determines which one of the plurality of variable resistors switches to the second resistance state, such that the logic value of the bit is unknown prior to the one-time programming.

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