Single-crystal horizontal access devices for vertical three-dimensional (3D) memory

Abstract

This application relates to single crystal horizontal access devices for vertical three dimensional (3D) memory. A vertically stacked array of memory cells has horizontally oriented access devices having first and second source / drain regions separated by a channel region and a gate opposite the channel region, the vertically oriented access lines coupled to the gate and separated from the channel region by a gate dielectric. The memory cells have epitaxially grown single crystal silicon to fill a first horizontal opening and house a first source / drain in electrical contact with a conductive material forming part of an integral horizontally oriented conductive digit line. The memory cells also have a horizontally oriented storage node coupled to the second source / drain region and a horizontally oriented digit line coupled to the first source / drain region. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separated from the first source / drain region and the horizontally oriented digit line by a dielectric.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to epitaxial growth of single-crystal silicon for semiconductor devices. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides permanent data by retaining stored data when no power is supplied and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), or the like.

[0003] As design rules tighten, less semiconductor space is available for manufacturing memory, including DRAM arrays. A corresponding memory cell in DRAM may contain access means, such as transistors, having first and second source / drain regions separated by a channel region. The gate may be opposite the channel region and separated from it by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may contain memory nodes, such as capacitor cells, coupled to digital lines via access means. By way of example, and not limitation, memory nodes may contain dielectric materials, such as ferroelectric materials. Ferroelectric materials may include (but are not limited to) zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (LaO2), and aluminum oxide (Al2O3), silicon-doped hafnium oxide (HfO2), aluminum-doped hafnium oxide (HfO2), other forms of doped hafnium oxide (HfO2), or combinations thereof. In embodiments, if doped hafnium oxide (HfO2) is included, the weight percentage (wt.%) of the dopant can be from 0.1 wt.% to 5 wt.%. The access device can be activated (e.g., to select a cell) via an access line coupled to an access transistor. A capacitor can store charge corresponding to the data value (e.g., logic "1" or "0") of the respective cell. Summary of the Invention

[0004] One embodiment of this disclosure provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines, comprising: vertically depositing alternating layers of a first dielectric material, a sacrificial material, and a second dielectric material in repeated iterations to form a vertical stack; forming a first vertical opening using a first etchant process to expose vertical sidewalls in the vertical stack; selectively etching back a first portion of the sacrificial material in a first region of the vertical stack along a first horizontal length from the first vertical opening to form a first horizontal opening; epitaxially growing single-crystal silicon to fill the first vertical opening and the first horizontal opening; selectively etching the single-crystal silicon to modify the first vertical opening; selectively etching the second dielectric material to form a second horizontal opening extending backward along a second length from the first vertical opening; and vapor-phase doping a first dopant in the top surface of the single-crystal silicon in the first horizontal opening to form a first source / drain region.

[0005] Another embodiment of this disclosure provides a method for forming a memory array having vertically stacked memory cells and having horizontally oriented access devices and vertically oriented access lines, comprising: forming the vertical stack by vertically depositing alternating layers of a first dielectric material, a sacrificial material, and a second dielectric material through at least four iterations in repeated iterations; forming a first vertical opening using a first etchant process to expose a semiconductor substrate and vertical sidewalls in the vertical stack; selectively etching back the sacrificial material from the first vertical opening for a first horizontal length to form a first horizontal opening having a first height; and allowing silane (Si2H6) gas to flow into the first vertical... Epitaxial growth of monocrystalline silicon in the opening and the first horizontal opening to fill the first vertical opening and the first horizontal opening; selective etching of the monocrystalline silicon to modify the first vertical opening; selective etching of the second dielectric material to form a second horizontal opening having a second height and such that the second dielectric material is recessed from the first vertical opening by a second length; vapor-phase doping of a dopant in the top surface of the monocrystalline silicon to form a first source / drain region; deposition of conductive material onto the first source / drain region below the second dielectric material; and etching of the vertical stack to maintain the first vertical opening and expose the sidewalls, the monocrystalline silicon, and the first dielectric material to form a body contact.

[0006] Another embodiment of this disclosure provides a memory device comprising: a vertically stacked array of memory cells, the vertically stacked array of memory cells comprising: a horizontally oriented access device having a first source / drain region and a second source / drain region separated by a channel region grown epitaxially in a single crystal, and a gate opposite to the channel region grown epitaxially and separated from the channel region grown epitaxially in a gate dielectric; a vertically oriented access line coupled to the gate and separated from the channel region grown epitaxially in a gate dielectric; a horizontally oriented memory node electrically coupled to the second source / drain region of the horizontally oriented access device; and a horizontally oriented digital line electrically coupled above the first source / drain region of the horizontally oriented access device; and a vertical body contact forming an electrical contact with a body region of one or more of the horizontally oriented access devices and separated from the first source / drain region and the horizontally oriented digital line by a dielectric. Attached Figure Description

[0007] Figure 1 This is an illustrative description of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 2 This is a perspective view illustrating a portion of the digital lines and body contacts of a semiconductor device according to several embodiments of the present disclosure.

[0009] Figure 3 This is a perspective view illustrating a portion of the digital lines and body contacts of a semiconductor device according to several embodiments of the present disclosure.

[0010] Figures 4A to 4N This is a cross-sectional view of a semiconductor device formed by forming a vertically stacked array of memory cells in multiple stages of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0011] Figures 5A to 5B This invention describes example methods for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines in another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0012] Figures 6A to 6E This invention describes example methods for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines in another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0013] Figures 7A to 7EThis invention describes example methods for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines in another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0014] Figures 8A to 8E This invention describes example methods for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines in another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0015] Figure 9 The illustration shows a cross-sectional view of an example of a horizontally oriented access device coupled to a horizontally oriented memory node and coupled to a vertically oriented access line and a horizontally oriented digital line, according to several embodiments of the present disclosure.

[0016] Figure 10 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure describe the epitaxial growth of monocrystalline silicon for use in semiconductor devices. Monocrystalline silicon can be epitaxially grown to form a semiconductor substrate to create silicon-based channel regions for horizontal access devices formed in a vertically stacked array of memory cells. The horizontal access devices are integrated with vertically oriented access lines and with horizontally oriented digital lines. The monocrystalline silicon can be formed to provide better electrical contacts for horizontally oriented access devices, such as transistors. Monocrystalline silicon can provide better (e.g., lower) off-state current (Ioff) than other materials such as polycrystalline silicon. For example, monocrystalline silicon can provide less than 1 Ioff per memory cell. e-16 Ampere (A) improves DRAM Ioff. This is achieved by using a higher Ioff (e.g., greater than 1 per memory cell). e-14 Compared to polycrystalline silicon materials, this provides better access channel control for silicon oxide channel access devices and provides device refresh improvements.

[0018] According to an embodiment, a semiconductor device having a horizontally oriented access device and a vertically oriented access line can be epitaxially grown in monocrystalline silicon to fill a first horizontal opening and accommodate a first source / drain electrode in electrical contact with a conductive material, forming a portion of an integrally horizontally oriented conductive digital line. As used herein, monocrystalline silicon refers to silicon rather than polycrystalline silicon, wherein the solid lattice is continuous, unbroken, and without grain boundaries.

[0019] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the figure number, and the remaining digits identify elements or components within the figure. Similar elements or components between different figures can be identified by using similar digits. For example, reference digit 104 may refer to... Figure 1 Component "04" in the text, and similar components in Figure 2 In this case, it can be referred to as 204. Multiple similar elements within a diagram can be designated by a reference number followed by a character and another number or letter. For example, 302-1 can refer to... Figure 3 In this context, components 302-1 and 302-2 can refer to components 302-2 that are similar to component 302-1. Such similar components are generally not designated with hyphens and additional numbers or letters. For example, components 302-1 and 302-2, or other similar components, are typically referred to as 302.

[0020] Figure 1 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1 The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1 The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each sub-cell array (e.g., sub-cell array 101-2) can contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be called word lines). Furthermore, each sub-cell array (e.g., sub-cell array 101-2) can contain multiple digital lines 107-1, 107-2, ..., 107-P (which may also be called bit lines, data lines, or sensing lines). Figure 1 In this document, digital lines 107-1, 107-2, ..., 107-P are described as extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are described as extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered as being in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered as being in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0021] A memory cell (e.g., 110) may include access means (e.g., access transistors) and a storage node located at the intersection of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-P. The memory cell can be written to or read from using the access lines 103-1, 103-2, ..., 103-Q and the digital lines 107-1, 107-2, ..., 107-P. The digital lines 107-1, 107-2, ..., 107-P may electrically interconnect the memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and the access lines 103-1, 103-2, ..., 103-Q may electrically interconnect the memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 103-2) and a digital line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P.

[0022] Digital lines 107-1, 107-2, ..., 107-P may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. Digital lines 107-1, 107-2, ..., 107-P in a sub-cell array (e.g., 101-2) are spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0023] Access lines 103-1, 103-2, ..., 103-Q may be or be contained in conductive patterns (e.g., metal lines) extending in a direction perpendicular to the substrate (e.g., in a third direction (D3) 111). Access lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0024] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 107-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a storage node (e.g., a capacitor). Although the references to the first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a single meaning. It is desirable that only one of the source / drain regions is connected to a digital line (e.g., 107-2), and the other is connected to a storage node.

[0025] Figure 2 The illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure (e.g., Figure 1 The image shows a perspective view of a sub-cell array 101-2 (shown as a portion of a vertically oriented stack of memory cells in the array). Figure 3 Explanation and display Figure 2 The unit cell of the 3D semiconductor memory device shown in the image (e.g.) Figure 1 A perspective view of the memory cell 110 shown in the image.

[0026] like Figure 2 As shown in the diagram, substrate 200 can be formed with related information. Figure 1 One of the described arrays of sub-cells (e.g., 101-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0027] like Figure 2 As shown in the example embodiments, a vertically oriented stack of memory cells extending in a vertical direction (e.g., third direction (D3) 111) can be fabricated on the substrate 200. Figure 1 Memory cell 110 in the memory. According to some embodiments, the vertically oriented stacking of memory cells can be manufactured such that each memory cell (e.g., memory cell 110) is stacked such that each memory cell ... Figure 1 The memory cells 110 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeated vertical levels L1, L2, and L3 can be located in the vertical direction (e.g., ...). Figure 1The third-party (D3) 111 shown is arranged, for example, "stacked". In some embodiments, when an insulating material 220 is present, the vertical layers L1, L2, and L3 can be separated from the substrate 200 by the insulating material 220. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) to a horizontally oriented access device 230 (e.g., a transistor) and a memory node (e.g., a capacitor) including access lines 103-1, 103-2, ..., 103-Q connections and digital lines 107-1, 107-2, ..., 107-P connections. The multiple discrete components to the horizontally oriented access device 230 (e.g., a transistor) may be formed in multiple iterations of the vertical repeating layers within each layer (as described below). Figures 4A to 4N (More detailed description), and can be in the second direction (D2) 205 (similar to) Figure 1 The second direction (D2)105) shown in the middle extends horizontally.

[0028] Multiple discrete components of a horizontally oriented access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225, laterally extending in a second direction (D2) 205, and formed within the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first and second source / drain regions 221 and 223 may comprise n-type dopant regions formed within a p-type doped body to the access device to form an n-type conductive transistor. In some embodiments, the first and second source / drain regions 221 and 223 may comprise p-type dopant formed within an n-type doped body to the access device to form a p-type conductive transistor. By way of example, and not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in the opposite doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0029] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2 As shown, a storage node 227 (e.g., a capacitor) may be connected to a second source / drain region 223 of the access device. The storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor comprising a phase change material, a magnetic tunneling junction pattern, and / or a variable resistor body. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1 The memory node associated with each access device of the memory cell 110 in the second direction (D2) 205 (similar to Figure 1 It extends in the second direction (D2)105) shown in the middle.

[0030] like Figure 2 As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P are displayed in the first direction (D1) 209 (similar to...). Figure 1 Extending along the first direction (D1) 109). Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be similar to... Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown are illustrated. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may be arranged along a third direction (D3) 211, for example, "stacked". The multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may contain conductive materials. For example, the conductive material may contain one or more of the following: doped semiconductors, such as doped silicon, doped germanium, etc.; conductive metal nitrides, such as titanium nitride, tantalum nitride, etc.; metals, such as tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.; and / or metal semiconductor compounds, such as tungsten silicide, cobalt silicide, titanium silicide, etc. However, the embodiments are not limited to these examples.

[0031] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g.) Figure 1The memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described in more detail below with respect to FIG4 and the following, multiple discrete components of the horizontally oriented access device 230 (e.g., first source / drain regions 221 and second source / drain regions 223 separated by channel region 225 and extending in the second direction (D2) 205) and multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in the first direction (D1) 209 may be formed in different vertical layers within each level. For example, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be disposed on and electrically contacted with the top surface of the first source / drain region 221 and orthogonal to the horizontally oriented access device 230 (e.g., transistors) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed within a vertical layer (e.g., within layer (L1)) that is higher and farther from the substrate 200 than the layer in which discrete components of the horizontally oriented access device (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0032] like Figure 2 As shown in the example embodiments, access lines 203-1, 203-2, ..., 203-Q extend in a direction perpendicular to the substrate 200 (e.g., on a third direction (D3) 211). Furthermore, as... Figure 2 As shown in the image, a sub-cell array (e.g.) Figure 1 Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other in a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be provided extending perpendicularly to the substrate 200 in a third direction (D3) 211 between a pair of horizontally oriented access devices 230 (e.g., transistors), the pair of horizontally oriented access devices 230 extending laterally in a second direction (D2) 205, but adjacent to each other in a layer (e.g., a first layer (L1)) in the first direction (D1) 209. Each of the access lines 203-1, 203-2, ..., 203-Q can extend vertically in a third direction (D3) on the sidewall of the corresponding one of the vertically stacked plurality of horizontally oriented access devices 230 (e.g., transistors).

[0033] For example, and such Figure 3 As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first of the horizontally oriented access devices 230 (e.g., transistors) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first of the horizontally oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first of the horizontally oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented access device 230 (e.g., transistor) in the first layer (L1) 213-1, which is spaced apart from the first horizontally oriented access device 230 (e.g., transistor) in the first layer (L1) 213-1 in the first direction (D1) 209. The second vertically extending access line (e.g., 203-2) may also be adjacent to the sidewall of the channel region 225 of the second horizontally oriented access device 230 (e.g., transistor) in the second layer (L2) 213-2 and the sidewall of the channel region 225 of the second horizontally oriented access device 230 (e.g., transistor) in the third layer (L3) 213-P. The embodiments are not limited to a specific number of layers.

[0034] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain conductive materials, such as (for example) a doped semiconductor material, conductive metal silicon nitride, a metal, and / or a metal-semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) of the description.

[0035] like Figure 2 As shown in the example embodiment, the conductive body contact 295 may extend along the end face of a horizontally oriented access device 230 (e.g., a transistor) in a first direction (D1) 209 in each of the layers (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200. The conductive body contact 295 may be connected to each memory cell (e.g., Figure 1 The body of the horizontally oriented access device 230 (e.g., a transistor) in the memory cell 110 (as in the memory cell 110) (such as the body of the horizontally oriented access device 230) (e.g., a transistor) Figure 3 (e.g., the main body region shown in 326). The conductive main body contact 295 may contain a conductive material, such as (for example) a doped semiconductor material, conductive metal silicon nitride, a metal and / or a metal semiconductor compound.

[0036] although Figure 2Not shown, but insulating material may fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0037] Figure 3 A more detailed description of memory cells according to some embodiments of the present disclosure (e.g., in) Figure 1 The unit cells of the vertically stacked array (e.g., within the sub-cell array 101-2) of the sub-cell array 101-2 Figure 1 (Memory unit 110 in the memory). For example Figure 3 As shown, the first and second source / drain regions 321 and 323 can be impurity-doped regions of a horizontally oriented access device 330 (e.g., a transistor). The first and second source / drain regions 321 and 323 can be similar to... Figure 2 The first and second source / drain regions 221 and 223 are shown in the diagram. The first and second source / drain regions can be separated by a channel region 325 formed in a semiconductor material body (e.g., body region 326) of a horizontally oriented access device 330 (e.g., a transistor). The first and second source / drain regions 321 and 323 can be formed by n-type or p-type dopants doped in the body region 326. The embodiments are not limited thereto.

[0038] For example, in the construction of an n-type conductive transistor, the body region 326 of the horizontally oriented access device 330 (e.g., a transistor) can be formed of a lightly doped (p-)p-type semiconductor material. In one embodiment, the body region 326 and the channel 325 separating the first and second source / drain regions 321 and 323 can comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material including boron (B) atoms as an impurity dopant to the polysilicon. The first and second source / drain regions 321 and 323 may also comprise metals formed using atomic layer deposition processes and / or highly doped degenerate semiconductor materials containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x Metal composites containing at least one of O3. However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor materials are intended to mean semiconductor materials containing highly doped materials (e.g., polycrystalline silicon) where dopants (e.g., phosphorus (P), boron (B), etc.) interact significantly with each other. In contrast, non-degenerate semiconductors contain moderate doping where dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0039] In this example, the first and second source / drain regions 321 and 323 may contain highly doped, n-type conductive impurities (e.g., highly doped (n+)) doped into the first and second source / drain regions 321 and 323. In some embodiments, the highly doped, n-type conductive first and second drain regions 321 and 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the horizontally oriented access device 330 (e.g., a transistor) may be of p-type conductive construction, in which case the conductivity type of the impurity (e.g., dopant) will be reversed.

[0040] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body region 326 of the horizontally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body region 326 of the horizontally oriented access device 330, positioned vertically above the bottom surface of the body region 326 of the laterally oriented access device 330 in a third direction (D3) 311. Thus, the laterally oriented transistor 330 may have a contact below the first source / drain region 321 and adjacent to a conductive body contact (e.g., a transistor). Figure 2 The main body area 326 of the electrical contact (295) is shown in the image. Furthermore, as... Figure 3 As shown in the example embodiments, similar to Figure 2 The number lines 207-1, 207-2, ..., 207-P and Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown in the figure (e.g., 307-1) can be disposed on the top surface 322 of the first source / drain region 321 and electrically coupled thereto.

[0041] like Figure 3 As shown in the example embodiments, similar to Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1Access lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) can extend vertically along the sidewall of the channel region 325 portion adjacent to the body region 326 on a third direction (D3) 311 to a horizontally oriented access device 330 (e.g., a transistor) horizontally conductive between the first and second source / drain regions 321 and 323 along a second direction (D2) 305. A gate dielectric 304 can be inserted between the access line 303-1 (a portion of which is formed to the gate of the horizontally oriented access device 330 (e.g., a transistor)) and the channel region 325. The gate dielectric 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Embodiments are not limited thereto. For example, in high-k dielectric material examples, the gate dielectric 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobite, etc.

[0042] Figure 4A It is used in a stage of semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g., Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0043] exist Figure 4A In the example embodiments shown in the examples, the method includes depositing alternating layers of first dielectric materials 430-1, 430-2, ..., 430-N (collectively referred to as first dielectric material 430), sacrificial materials 432-1, 432-2, ..., 432-N (collectively referred to as sacrificial material 432), and second dielectric materials 433-1, 433-2, ..., 433-N (collectively referred to as second dielectric material 433) in repeated iterations to form a vertical stack 401 on the working surface of a semiconductor substrate 400. In some embodiments, alternating materials may be deposited in at least four iterations to produce the vertical stack 401. In one embodiment, the first dielectric material 430 may be deposited to have a thickness ranging from twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, the sacrificial material 432 may be deposited to have a thickness ranging from twenty (20) nm to two hundred (200) nm, for example, a vertical height in a third direction (D3). In one embodiment, the second dielectric material 433 may be deposited to have a thickness ranging from ten (10) nm to thirty (30) nm, for example, a vertical height in a third direction (D3). However, the embodiments are not limited to these examples. As shown in FIG4, the vertical direction 411 is illustrated as a third direction (D3), for example, the z direction in the xyz coordinate system, similar to Figures 1 to 3The first, second, and third-party directions (D3) shown in the text.

[0044] In some embodiments, the first dielectric material 430 may be an interlayer dielectric (ILD). By way of example, and not limitation, the first dielectric material 430 may include an oxide material, such as SiO2. In another example, the first dielectric material 430 may include a nitride material or a silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, the first dielectric material 430 may include silicon oxycarbide (SiO2). x C y In another example, the first dielectric material 430 may comprise silicon oxynitride (SiO2). x N y Materials (also referred to herein as "SiON") and / or combinations thereof. Examples are not limited to these instances.

[0045] In some embodiments, the sacrificial material 432 may comprise silicon (Si) material in a polycrystalline and / or amorphous state. The sacrificial material 432 may be a lightly doped p-type (p-) silicon material. The sacrificial material 432 may be formed by using a low concentration of vapor-phase doped boron atoms (B) as an impurity dopant to form the lightly doped p-type (p-) silicon material. The lightly doped p-type (p-) silicon material may be polycrystalline silicon. However, the embodiments are not limited to these examples.

[0046] In some embodiments, the second dielectric material 433 may be an interlayer dielectric (ILD). By way of example, and not limitation, the second dielectric material 433 may include a nitride material. The nitride material may be silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the second dielectric material 433 may include silicon oxycarbide (SiOC) material. In yet another example, the second dielectric material 433 may comprise silicon oxynitride (SiON) and / or combinations thereof. Embodiments are not limited to these examples. For instance, the second dielectric material 433 may include an oxide material, such as SiO2. However, according to embodiments, the second dielectric material 433 is intentionally selected to be different in material or composition from the first dielectric materials 430-1, 430-2, ..., 430-N, such that a selective etching process can be performed on one of the first and second dielectric layers, selectively on the other of the first and second dielectric layers; for example, the second SiN dielectric material 433 may be selectively etched relative to the sacrificial material 432 and the first dielectric material 430.

[0047] Alternating layers of first dielectric material 430-1, 430-2, ..., 430-N, sacrificial material 432-1, 432-2, ..., 432-N, and second dielectric material 433-1, 433-2, ..., 433-N can be deposited in a semiconductor manufacturing apparatus according to a semiconductor manufacturing process (e.g., chemical vapor deposition (CVD)). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of first dielectric material, sacrificial material, and second dielectric material in repeated iterations to form a vertical stack 401.

[0048] Layers can occur vertically in repeated iterations. Figure 4A In the example, three layers numbered 1, 2, and 3 are shown in the repeated iterations. For example, the vertical stack may include: a first dielectric material 430-1, a sacrificial material 432-1, and a second dielectric material 433-1; another first dielectric material 430-2, another sacrificial material 432-2, and another second dielectric material 433-2; yet another first dielectric material 430-N, yet another sacrificial material 432-N, and yet another second dielectric material 433-N. Thus, the vertical stack may include, for example, a first oxide material 430-1, a sacrificial material 432-1, and a first nitride material 433-1 in further repeated iterations; another first oxide material 430-2, another sacrificial material 432-2, and another first nitride material 433-2; yet another first oxide material 430-N, yet another sacrificial material 432-N, and yet another first nitride material 433-N. However, the embodiments are not limited to this example and may include more or fewer repeated iterations. For example, a vertically stacked 401 can contain four layers of repeated iterations.

[0049] Figure 4B It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0050] According to an embodiment, Figures 4B to 4N The semiconductor manufacturing process described herein can be used to perform the formation of elongated pillars and access lines extending in a second direction (e.g. Figures 5A to 6E (This happened after the event was shown in the video).

[0051] like Figure 4BAs shown, a first vertical opening 471 can be formed through layers within a vertically stacked memory cell to expose vertical sidewalls 414 in the vertical stack. The first vertical opening 471 can be formed with a width (W1) 492 having a range from 20 nanometers (nm) to 400 nm. This includes all individual values ​​and sub-ranges from 20 nm to 400 nm; for example, the first vertical opening 471 can have a width (W1) 492 having a lower limit of 20 nm, 30 nm, 40 nm, 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, or 200 nm to an upper limit of 150 nm, 175 nm, 200 nm, 250 nm, 275 nm, 300 nm, 350 nm, 375 nm, or 400 nm. The first vertical opening 471 can be formed through repeated iterations of a first dielectric material 430, a sacrificial material 432, and a second dielectric material 433. However, the embodiments are not limited to this. Figure 4B A single vertical opening is shown. Multiple vertical openings may be formed through the material layers. A first vertical opening 471 may be formed to expose the vertical sidewalls 414 in the vertical stack. Additionally, the first vertical opening 471 may expose the semiconductor substrate 400 at the bottom of the vertical stack. In some embodiments, the semiconductor substrate 400 may be formed of silicon (Si) material.

[0052] In some embodiments, the first vertical opening 471 may be formed by a first etchant process. In one embodiment, the first etchant process may be a dry etchant process for exposing the vertical sidewalls 414 and the semiconductor substrate 400 in the vertical stack 401. The first etchant process exposes the semiconductor substrate 400 by repeatedly etching the vertical opening through the first dielectric material 430, the sacrificial material 432, and the second dielectric material 433. In some embodiments, when an insulating material is present, the first etchant process may etch through the insulating material and form a vertical opening through the insulating material. That is, when an insulating material is present, the first etchant process exposes the semiconductor substrate 400 by repeatedly forming a vertical opening through the first dielectric material 430, the sacrificial material 432, the second dielectric material 433, and the insulating material.

[0053] Figure 4C It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0054] A second etchant may flow into the first vertical opening 471 to selectively etch the sacrificial material 432. The second etchant may be applied to all iterations of the sacrificial material 432 within the stack. Therefore, the second etchant may not be applied to the first dielectric material 430 and the second dielectric material 433 within the stack.

[0055] A selective second etchant process can etch sacrificial material 432 to form a first horizontal opening 473. The selective second etchant process can be performed such that the first horizontal opening 473 has a first length (L1) 476, extending from the first vertical opening 471. The first length (L1) 476 can be controlled by controlling time, the composition of the etchant gases, and the etching rate (e.g., rate, concentration, temperature, pressure, and time parameters) of the reactant gases flowing into the first vertical opening 471. Thus, sacrificial material 432 can be etched from the first vertical opening 471 along the first length (L1) 476. The selective second etching can be isotropic but selective for sacrificial material 432, essentially stopping on the first dielectric material 430 and the second dielectric 433. Therefore, in one example embodiment, a selective second etchant process can substantially remove all sacrificial material 432 from the top surface of the first dielectric 430 to the bottom surface of the second dielectric material 433 in the previous layer, while horizontally etching a first length (L1) 476 between the first dielectric 430 and the second dielectric 433 from the first vertical opening 471. In this example, the first horizontal opening 473 will have a first height (H1) 435 that is substantially equal to and controlled by the thickness of the sacrificial material 432 deposited. For example, the first height (H1) 435 may be in the range of twenty (20) nm to two hundred (200) nm. This includes all individual values ​​and sub-ranges from 20 nm to 200 nm; for example, the first height (H1) 435 may have a height having a lower limit of 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm to an upper limit of 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm. However, the embodiments are not limited to this example. As described herein, a selective second etchant process can etch the sacrificial material 432 to the first length (L1) 476 and the first height (H1) 435.

[0056] The selective second etchant process may include one or more etch chemicals selected from aqueous etch chemistry, semi-aqueous etch chemistry, vapor etch chemistry, or plasma etch chemistry, and other possible selective etch chemistry. For example, a dry etch chemistry using oxygen (O2) or O2 and sulfur dioxide (SO2) (O2 / SO2) may be used. A dry etch chemistry using O2 or O2 and nitrogen (N2) (O2 / N2) may be used to selectively etch the sacrificial material 432. Alternatively or additionally, the selective second etching for removing the sacrificial material 432 may include a selective etch chemistry using phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or the use of a selective solvent (e.g., NH4OH or HF and other possible etch chemistry or solvent) to dissolve the sacrificial material 432.

[0057] Figure 4D It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0058] In some embodiments, the semiconductor substrate 400 can be used as a seed material for the epitaxial growth of single-crystal silicon 487. That is, the single-crystal silicon 487 can be grown by allowing silicon-based gas to flow into a first horizontal opening (e.g., ...). Figure 4C The first horizontal opening 473) and the first vertical opening (e.g. Figures 4B to 4C Epitaxial growth is performed in the first vertical opening 471 and in contact with the semiconductor substrate 400. For example, silane (Si2H6) gas can flow into the first horizontal opening (e.g., Figure 4C The first horizontal opening 473) and the first vertical opening (e.g. Figures 4B to 4C In the first vertical opening 471, such that single-crystal silicon 487 is epitaxially grown from the exposed semiconductor substrate 400 to the first vertical opening (e.g., Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C The first horizontal opening 473). However, the embodiments are not limited to this. For example, dichlorosilane (SiH2Cl2) gas can flow into the first horizontal opening (e.g., Figure 4C The first horizontal opening 473) and the first vertical opening (e.g. Figures 4B to 4C The first vertical opening 471) allows the single crystal silicon 487 to be epitaxially grown into the first vertical opening and the first horizontal opening.

[0059] Silicon-based gas can cause single-crystal silicon 487 to completely fill the first vertical opening (e.g. Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C The first horizontal opening 473). However, the embodiments are not limited to this example. For example, in some embodiments, the monocrystalline silicon 487 may fill the entire first vertical opening (e.g., Figures 4B to 4C The first vertical opening 471) can be filled with the first horizontal opening (e.g. Figure 4C A portion of the first horizontal opening 473. That is, the monocrystalline silicon 487 may not contact the portion remaining in the first horizontal opening (e.g., Figure 4C The sacrificial material 432 in the first horizontal opening 473) and may leave an unfilled (e.g., blank) area in the first horizontal opening. In some embodiments, the first horizontal opening (e.g. Figure 4C The width of the unfilled portion of the first horizontal opening 473 (e.g., in the third direction (D3) 411) may be the width of the first horizontal opening (e.g. Figure 4CThe length of the unfilled portion of the first horizontal opening (473) is half the size of the unfilled portion (e.g., in the second direction (D2) 405).

[0060] In some embodiments, silicon-based gas is allowed to flow into a first horizontal opening (e.g., at a temperature of 300 degrees Celsius (°C) to 1100°C) Figure 4C The first horizontal opening 473) and the first vertical opening (e.g. Figures 4B to 4C The first vertical opening 471 can cause the epitaxial growth of single-crystal silicon 487 and fill the first vertical opening and the first horizontal opening. This includes all individual values ​​and sub-ranges from 300°C to 1100°C; for example, silicon gas can flow into the first vertical opening and the first horizontal opening at temperatures ranging from a lower limit of 300°C, 400°C, 450°C, 500°C, 350°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, or 900°C to an upper limit of 900°C, 950°C, 1000°C, 1050°C, or 1100°C. However, the embodiments are not limited to these examples. For example, silicon-based gas can flow into the first vertical opening (e.g., at temperatures from 300°C to 4000°C) Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C The first horizontal opening 473) allows for the epitaxial growth of single-crystal silicon 487. This includes all individual values ​​and sub-ranges from 300°C to 4000°C.

[0061] Additionally, silicon-based gas can flow into the first vertical opening (e.g., within 1 to 15 minutes) Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C The first horizontal opening 473 allows for the epitaxial growth of single-crystal silicon 487. This includes all individual values ​​and sub-ranges from 1 minute to 15 minutes; for example, silicon gas can flow into the first vertical opening and the first horizontal opening over a period of time having a lower limit of 1 minute, 2 minutes, 3 minutes, 4 minutes, 5 minutes, 6 minutes, 7 minutes, 8 minutes, 9 minutes, or 10 minutes to an upper limit of 8 minutes, 9 minutes, 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes, or 15 minutes. For example, silicon-based gas can flow into the first vertical opening (e.g., at a temperature of 800°C to 900°C) over a period of 7 to 10 minutes. Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C Monocrystalline silicon 487 is epitaxially grown in the first horizontal opening 473. However, the embodiments are not limited to these examples. For example, the duration for which silicon-based gas flows into the first vertical opening and the first horizontal opening may vary depending on the temperature of the silicon-based gas. For example, silicon-based gas may flow into the first vertical opening (e.g., within 1 minute to 500 minutes) Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C The first horizontal opening 473) allows for the temperature-based epitaxial growth of single-crystal silicon 487. This includes all individual values ​​and sub-ranges from 1 minute to 500 minutes.

[0062] Figure 4E It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0063] In some embodiments, the first vertical opening 471 can be made by vertically etching through the monocrystalline silicon within the vertically stacked memory cells (e.g., Figure 4F The single-crystal silicon 487 is modified to expose the vertical sidewalls 414 in the vertical stack 401. In addition, the modified first vertical opening 471 can expose the semiconductor substrate 400 at the bottom of the vertical stack.

[0064] In some embodiments, the modified first vertical opening 471 can be modified using a third etchant process. In one embodiment, the third etchant process can be a wet etchant process used to vertically etch the single-crystal silicon 487 and expose the vertical sidewalls 414 and the semiconductor substrate 400 in the vertical stack 401. Figure 4E As shown, the third etchant process can remove a portion of the monocrystalline silicon 487 to modify the first vertical opening 471, while leaving the first horizontal opening (e.g., Figure 4C The portion of the monocrystalline silicon 487 inside the first horizontal opening 473). That is, the first vertical opening 471 can be selectively etched into the monocrystalline silicon 487 to... Figure 4C The modification involves leaving a portion of the monocrystalline silicon 487 inside the first horizontal opening 473 while keeping the first dielectric material 430, the sacrificial material 432, and the second dielectric 433 intact.

[0065] The third etching process can cause the etching to remain only at the first horizontal opening. Figure 4C The single-crystal silicon 487 is oxidized in the first horizontal opening 473). For example... Figure 4E As demonstrated in the example, the third etchant process can form a protective oxide coating, such as the second oxide material 434, on the remaining monocrystalline silicon 487. Therefore, the first dielectric material 430, the second dielectric material 433, the sacrificial material 432, and the monocrystalline silicon 487 inside the first horizontal opening can remain intact during the selective third etchant process.

[0066] As described herein, the remaining monocrystalline silicon 487 may be protected by a second oxide material 434 formed on the monocrystalline silicon 487 during the third etchant process. The second oxide material 434 may be present in the first horizontal opening (e.g., Figure 4CAll iterations of the monocrystalline silicon 487 inside the first horizontal opening 473).

[0067] Figure 4F It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0068] A selective fourth etchant process can etch the second dielectric material 433 to form a second horizontal opening 488. The selective fourth etchant process can be performed such that the second horizontal opening 488 has a second length (L2) 489 from the first vertical opening 471. The selective fourth etchant process can etch all iterations of the second length (L2) 489 of the second dielectric 433. The second length (L2) 489 can be controlled by controlling time, the composition of the etchant gas, and the etching rate (e.g., rate, concentration, temperature, pressure, and time parameters) of the reactant gas flowing into the first vertical opening 471. Thus, the second dielectric material 433 can be etched from the first vertical opening 471 to the second length 489. The selective etching can be isotropic but selective for the second dielectric material 433, essentially stopping at the first dielectric material 430 and the first horizontal opening (…). Figure 4F The second dielectric material 433 is etched onto the monocrystalline silicon 487 inside the first horizontal opening 473. Therefore, in one example embodiment, a selective fourth etchant process can substantially remove all of the second dielectric material 433 from the top surface of the monocrystalline silicon to the bottom surface of the first dielectric material in the preceding layer, while horizontally etching a length (L2) 489 between the monocrystalline silicon and the first dielectric material 430 from the first vertical opening 471. In this example, the second horizontal opening 488 will have a height (H2) 490 that is substantially equal to and controlled by the thickness of the second dielectric layer 433 deposited. However, the embodiments are not limited to this example. As described herein, a selective fourth etchant process can etch the second dielectric material 433 to a second length (L2) 489 and a second height (H2) 490.

[0069] Figure 4G It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0070] The first source / drain region 475 can be formed by vapor-phase doping of a dopant into the top surface 415 of a single-crystal silicon 487 via a second horizontal opening 488. Vapor-phase doping can be used to achieve highly isotropic (e.g., non-directional) doping. In another example, thermal annealing using a dopant gas (e.g., phosphorus) can be used in conjunction with a high-energy plasma to help break bonds. The embodiments are not limited thereto and other suitable semiconductor manufacturing techniques can be utilized. The width of the first source / drain region 475 doped into the top surface 415 of the single-crystal silicon 487 can be formed substantially entirely from the first vertical opening 471 along a second distance (L2) 489 of the second horizontal opening 488. The first source / drain region 475 can be formed by vapor-phase doping of phosphorus (P) atoms with high plasma energy as an impurity dopant (e.g., PECVD) to form a highly concentrated, n-type doped (n+) region in the top surface 415 of the single-crystal silicon 487.

[0071] Figure 4H It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0072] Conductive material 477 can be conformally deposited into a portion of the first vertical opening 471, for example, using a chemical vapor deposition (CVD) process, such that the conductive material can also be deposited into the second horizontal opening. Figure 4F to 4G The conductive material 477 can be deposited into the second horizontal opening (488). Figure 4F to 4G On the top surface 415 above the first source / drain region 475 in the second horizontal opening 488. In some embodiments, the conductive material 477 may comprise titanium nitride (TiN) material. In some embodiments, the conductive material 477 may be tungsten (W). In this example, some embodiments may include forming the tungsten (W) material according to the method described in U.S. Patent Application No. 16 / 943,108 (Agency File No. 1013.0510001), a co-application and co-pending application with at least one co-inventor entitled "Digital Line Formation for Horizontally Oriented Access Devices". The conductive material 477 may form a horizontally oriented digital line.

[0073] Figure 4I It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0074] The conductive material 477 may be recessed into the second horizontal opening 488, for example, by using a fifth etchant process, atomic layer etching (ALE), or other suitable techniques to etch it from the first vertical opening 471. In some instances, the conductive material 477 may be etched back from the first vertical opening 471 to a third distance (L3) 483 in the second horizontal opening 488. The conductive material 477 may be selectively etched to keep the first dielectric material 430, a portion of the conductive material 477, the sacrificial material 432, the monocrystalline silicon 487, and the first source / drain region 475 intact. The conductive material 477 may be etched using a fifth etchant process. In some embodiments, the conductive material 477 may be etched using an atomic layer etching (ALE) process. In some embodiments, the conductive material 477 may be etched using an isotropic etching process. The conductive material 477 may be recessed into the second horizontal opening 488 by a third length (L3) 483 to maintain direct electrical contact on the top surface of the first source / drain region 475 formed in the monocrystalline silicon 487. Therefore, the conductive material 477 maintains electrical contact with the first source / drain region 475 and can form an overall horizontally oriented conductive digital line (e.g., Figures 1 to 3 The corresponding horizontally oriented digital lines 107, 207 and 307 in the text.

[0075] Figure 4J It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0076] like Figure 4J The diagram shows a second oxide material (e.g., [material name missing]) protecting the sidewalls of the monocrystalline silicon 487 in the first vertical opening 471. Figures 4E to 4I The second oxide material 434, a portion of the first source / drain region 475, and a first portion 478 of the monocrystalline silicon 487 below the first source / drain region 475 can be selectively etched using a sixth etchant process to allow the formation of a body contact to the body region of the horizontal access device. In this example, a portion of the first source / drain region 475 and the top portion (e.g., the first portion 478) of the monocrystalline silicon 487 below the first source / drain region 475 can also be etched back from the first vertical opening 471 to a third length (L3) 483. Etching can be performed using a sixth etchant process, such as atomic layer etching (ALE) or other suitable techniques. In some embodiments, the first source / drain region 475 can be etched from the first vertical opening 471 to the same horizontal length (L3) 483 as the conductive material 477.

[0077] Therefore, the third horizontal opening 472 can be formed by etching a portion of the first source / drain region 475 from the first vertical opening 471 and the top portion (e.g., 478) of the single-crystal silicon 487 below the first source / drain region 475 by a third horizontal length (L3) 483. Thus, the third horizontal opening 472 may have a third vertical height (H3) 485. The third vertical height (H3) 485 may be greater than (e.g., vertically higher than) the second horizontal opening formed in the second dielectric material. Figure 4F to 4G The height (H2) 435 of the second horizontal opening 488 is a combination of the height (H2) 435 of the first source / drain region 475 (e.g., the depth to which vapor-phase doping is incorporated into the top surface 415 of the single-crystal silicon 487). For example, the third height (H3) 485 may also include the height of the top portion (e.g., 478) of the etched single-crystal silicon 487. Therefore, the third length (L3) 483 may be shorter than the second length (L2) 489, but the third height (H3) 485 may be shorter than the second height (e.g., the depth to which vapor-phase doping is incorporated into the top surface 415 of the single-crystal silicon 487). Figure 4F to 4G The second height (H2) 490) is high.

[0078] Figure 4K It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0079] like Figure 4K As shown, the third dielectric material 474 is conformally deposited into the first vertical opening 471 using a CVD process, and can conformally fill the first vertical opening 471 and the third horizontal opening (e.g. Figure 4J The third horizontal opening 472). The third dielectric material 474 may be horizontally adjacent to the conductive material 477 (e.g., the third horizontal opening 472). Figure 1 The first source / drain region 475 and the single-crystal silicon 487 extend along a first direction (D1) 109. For example, in some embodiments, a third dielectric material 474 may be in direct contact, for example, on a third direction (D3) 411 below the first dielectric material 430 and with the conductive material 477, the first source / drain region 475, and the single-crystal silicon 487 inside the first horizontal opening. However, the embodiments are not limited to this example.

[0080] The third dielectric material 474 may be the same as or different from the second dielectric material 433. For example, the second dielectric material may be Si2N3, and the third dielectric material may be Si3N4. In another example, the third dielectric material 474 may include silicon dioxide (SiO2) material. In yet another example, the third dielectric material 474 may include silicon oxycarbide (SiO2). x C yIn another example, the third dielectric material 474 may comprise silicon oxynitride (SiO2). x N y (and / or combinations thereof.) Examples are not limited to these instances.

[0081] Figure 4L It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0082] The third dielectric material 474 can be recessed to remove from the first vertical opening 471 and the first vertical opening 471 is maintained to allow the deposition of conductive material. Figure 4K (As shown in the image) to form a direct electrical contact between the conductive material deposited within the first vertical opening 471 and the second portion 479 of the monocrystalline silicon 487 inside the first horizontal opening, such as a horizontally oriented access device within a vertical stack (e.g., Figure 9 The main contact of the 901 in the middle. In some embodiments, the third dielectric material 474 may be etched from the first vertical opening 471 using a seventh etchant process to expose the vertical sidewall 414 of the first dielectric material 430, the third dielectric material 474 and the second portion 479 of the monocrystalline silicon 487.

[0083] Figure 4M It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0084] like Figure 4M As shown in the diagram, conductive material 495 is deposited onto the first vertical opening (e.g., Figure 4L The first vertical opening 471, as described herein, forms a direct electrical contact with the second portion 479 of the single-crystal silicon 487. In some embodiments, the conductive material may be a metal, such as tungsten (W). However, the embodiments are not limited thereto. In some embodiments, the conductive material 495 is a highly doped (e.g., p-type highly doped (p+)) semiconductor material that can be deposited into the first vertical opening 471. In this example, the conductive material 495 may be a highly doped p-type (p+) silicon material, such as a highly doped p-type (p+) polycrystalline silicon material.

[0085] For example, the conductive material 495 of a highly doped p-type (p+) silicon material can form a conductive host junction with a second portion 479 of a single-crystal silicon 487. In one example, forming a conductive host junction includes depositing a degenerate semiconductor material. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material containing highly doped materials (e.g., polycrystalline silicon) where the dopants (e.g., phosphorus (P), boron (B), etc.) have significant interactions with each other. In contrast, a non-degenerate semiconductor contains moderate doping where the dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0086] In some instances, the conductive material 495 may be a highly doped p-type (p+) silicon-germanium (SiGe) material. The SiGe material can be deposited into the first vertical opening 471 at a relatively lower temperature than other silicon-based conductive materials. However, the embodiments are not limited to these examples.

[0087] The highly doped p-type (p+) silicon material 495 can reduce holes generated during operation of a horizontally oriented access device due to gate-induced drain leakage (GIDL). The highly doped p-type (p+) silicon material 495 can control the channel potential within the single-crystal silicon 487 inside the first horizontal opening by controlling hole formation within the single-crystal silicon 487. For example, if the first source / drain region 475 is not electrically isolated from the conductive material 495 by the third dielectric material 474, hole formation can occur between the first source / drain region 475, the single-crystal silicon 487, and the body region of the horizontally oriented access device.

[0088] Figure 4N It is used in another stage of the semiconductor manufacturing process to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The semiconductor device (described in the illustration) and cross-sectional views according to several embodiments of the present disclosure.

[0089] In some embodiments, such as Figure 4N As explained, the vertically stacked 401 can be epitaxially grown on monocrystalline silicon 487 to the first vertical opening (e.g., Figures 4B to 4C The first vertical opening 471) and the first horizontal opening (e.g. Figure 4C It is then bonded to a complementary metal-oxide-semiconductor (CMOS) 445 in the first horizontal opening 473. In some embodiments, such as Figure 4N The text describes a semiconductor substrate (e.g.) Figures 4A to 4M The semiconductor substrate 400 can be removed after the vertical stack 401 is bonded to the CMOS 445.

[0090] Figure 4E to 4M The process described herein can occur after the vertically stacked 401 has been bonded to the CMOS 445 and the semiconductor substrate has been removed. However, this disclosure is not limited thereto. For example, Figure 4E to 4M The process described herein can occur before the vertical stack 401 is bonded to the CMOS 445. Therefore, in some embodiments, the vertical stack 401 can be made of a conductive material (e.g., Figure 4M The conductive material 495 is deposited into the first vertical opening and then bonded to the CMOS 445.

[0091] In some embodiments, CMOS 445 may include a silicon substrate material and transistors suitable for peripheral circuitry. That is, CMOS 445 may be formed on a silicon substrate material. In some embodiments, an untreated silicon layer may be bonded to a vertical stack 401 via an intermediate oxide layer, and the untreated silicon layer may be processed after being bonded to the vertical stack 401 to form CMOS 445.

[0092] Figure 5A This describes another stage in the semiconductor manufacturing process used to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The vertically stacked memory cell array (described in the description) and example methods according to several embodiments of the present disclosure. Figure 5A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 5A In the example embodiment shown in the example, the method includes forming a plurality of first vertical openings 515 having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505, through which the semiconductor substrate is vertically stacked. In one example, such as Figure 5A As shown, a plurality of first vertical openings 515 extend primarily in a second horizontal direction (D2) 505 and can form elongated vertical pillars 513 with sidewalls 514 in a vertical stack. The plurality of first vertical openings 515 can be formed using photolithography to pattern a photomask 535, for example, by forming a hard mask (HM) on the vertical stack before etching the plurality of first vertical openings 515.

[0093] Figure 5B It is along Figure 5A The image shows a cross-sectional view of the semiconductor structure at a specific point in the semiconductor manufacturing process, cut along the cutting line A-A'. Figure 5B The cross-sectional view shown in the figure illustrates the repeated iteration of alternating layers of a first dielectric material 530-1, 530-2, ..., 530-N, a sacrificial material 532-1, 532-2, ..., 532-N, and a second dielectric material 533-1, 533-2, ..., 533-N, which are vertically stacked (e.g., 401 shown in Figure 4) on a semiconductor substrate 500. Figure 5BThe conductive materials 540-1, 540-2, ..., 540-4 can be formed on the gate dielectric 538 in the plurality of first vertical openings 515. By way of example and not limitation, the gate dielectric 538 can be conformally deposited in the plurality of first vertical openings 515 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 can be deposited to a specific thickness (t1) suitable for a particular design rule, such as a gate dielectric thickness of about 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, the gate dielectric 538 may include silicon dioxide (SiO2) material, alumina (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material and / or combinations thereof, and so on. Figure 3 As described in the text.

[0094] In addition, such as Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited on the surface of the gate dielectric 538 in a plurality of first vertical openings 515. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited on the surface of the gate dielectric 538 in a plurality of first vertical openings 515 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings above the gate dielectric 538. Conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, for example shown as... Figure 1 The access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines) shown below are adapted to specific design rules. For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not by limitation, conductive materials 540-1, 540-2, ..., 540-4 may include one or more of the following: doped semiconductors, such as doped silicon, doped germanium, etc.; conductive metal nitrides, such as titanium nitride, tantalum nitride, etc.; metals, such as tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.; and / or metal semiconductor compounds, such as tungsten silicide, cobalt silicide, titanium silicide, etc.; and / or some other combinations thereof, such as Figure 3 As described in the text.

[0095] like Figure 5BAs shown in the diagram, conductive materials 540-1, 540-2, ..., 540-4 can be recessed to remain only along the vertical sidewalls of slender vertical columns. Figure 5B The cross-sectional views are now shown as 542-1, 542-2, and 542-3. Multiple separate, vertical access lines formed from conductive materials 540-1, 540-2, ..., 540-4 can be created from the first vertical opening (e.g., using a suitable selective anisotropic etching process). Figure 5A The bottom surface of 515) is recessed by removing conductive materials 540-1, 540-2, ..., 540-4, thereby exposing the gate dielectric 538 on the bottom surface to form discrete, vertical access lines 540-1, 540-2, ..., 540-4. For example... Figure 5B As shown, dielectric material 539 (e.g., oxide or other suitable spin-on dielectric (SOD)) is then deposited into the first vertical opening 515 using a process such as CVD to fill the first vertical opening 515. The dielectric can be planarized to the top surface of the hard mask 535 of the vertical semiconductor stack using chemical mechanical planarization (CMP) or other suitable semiconductor manufacturing techniques. Subsequent photolithography material 536 (e.g., a subsequent hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical opening 515 above the discrete vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0096] Figure 6A This describes another stage in the semiconductor manufacturing process used to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The vertically stacked memory cell array (described in the description) and example methods according to several embodiments of the present disclosure. Figure 6A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 6A In an example embodiment, the method includes patterning a photomask 636 using a photolithography process. Figure 5B 536 in the example, such as subsequent hard masks. Figure 6A The method further illustrates the use of selective, isotropic etchant processes to remove portions of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z to separate and individually form multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, for example... Figure 1Access lines 103-1, 103-2, ..., 103-Q below. Therefore, multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown as running along the sidewall of a slender vertical column, for example in... Figure 5B The cross-sectional view shows the sidewalls of the slender vertical columns 542-1, 542-2, and 542-3.

[0097] like Figure 6A The examples demonstrate that the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be removed back to the first vertical opening using a suitable selective, isotropic etching process (e.g., Figure 5A The gate dielectric 638 in (515) is shown. Figure 6A As shown, a subsequent dielectric material 641 (e.g., oxide or other suitable spin-on dielectric (SOD)) can then be deposited to fill the remaining openings from the locations where the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z have been removed using a process such as CVD or other suitable techniques. The dielectric material 641 can be planarized to the top surface of a previously hard mask 635 of a vertical semiconductor stack (e.g., 401 shown in Figure 4) using a process such as CMP or other suitable techniques. In some embodiments, subsequent photolithography material 537 (e.g., a hard mask) may be deposited using CVD and planarized using CMP to cover and enclose multiple discrete, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z above the working surface of the vertical semiconductor stack (401 in FIG. 4), thereby protecting the multiple discrete, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z along the sidewalls of the elongated vertical pillars. However, the embodiments are not limited to these process examples.

[0098] Figure 6B Explanation along Figure 6A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6BThe cross-sectional view shown is away from multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and shows the repeated iteration of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, sacrificial materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N, vertically stacked (e.g., 401 shown in Figure 4) on a semiconductor substrate 600. Figure 6B As shown in the diagram, the vertical direction 611 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The drawing shows the first, second, and third directions, specifically the third direction (D3) 111. The plane of the drawing extends left and right along the first direction (D1) 609. Figure 6B In the example embodiment, dielectric material 641 is shown to fill the vertical opening during the deposition of the residual gate dielectric 638. The hard mask 637 described above covers the illustrated structure.

[0099] Figure 6C Explanation along Figure 6A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6C The cross-sectional view shown is illustrated as extending along a repeating iterative axis in a second direction (D2) 605 along alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, sacrificial materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N. Along and on this axis, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of sacrificial materials 632-1, 632-2, ..., 632-N. Figure 6C In the middle, the adjacent opposite vertical access lines 640-3 are indicated by dashed lines that indicate the set of positions to be entered from the plane and orientation of the drawing.

[0100] Figure 6D Explanation along Figure 6A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6DThe cross-sectional view shown is illustrated as follows: along a repeating axis in the second direction (D2) 605 along the alternating layers of the first dielectric material 630-1, 630-2, ..., 630-N, the sacrificial material 632-1, 632-2, ..., 632-N, and the second dielectric material 633-1, 633-2, ..., 633-N, in which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) extend outside the regions formed within the layers of the sacrificial material 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, dielectric material 641 is shown filling the space between horizontally oriented access devices and horizontally oriented memory nodes for a three-dimensional array of vertically oriented memory cells, spaced along a first direction (D1) extending into and out of the plane of the drawing. At the left end of the drawing, a repetitive iteration of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, sacrificial materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N is shown, at which point horizontally oriented digital lines (e.g., ...) are also depicted. Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form electrical contacts with the second source / drain region or the digital line conductive contact material, as described in more detail below.

[0101] Figure 6E Explanation along Figure 6A The cut line D-D' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6E The cross-sectional view shown is illustrated as extending laterally along the axis of repeated iterations of alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, sacrificial material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N in the first direction (D1) 609 in the plane of the drawing, across multiple separation, vertical access lines 640-1. Intersecting with 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and intersecting with the regions (where channel regions may be formed) of sacrificial materials 632-1, 632-2, ..., 632-N separated from multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) via the gate dielectric 638. Figure 6EIn the diagram, the first dielectric filling material 639 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes. It can be formed into a plane extending into and out of the drawing (as described in more detail below) and can be spaced apart and vertically stacked along the first direction (D1) 609 in an array extending in the third direction (D3) 611 in the three-dimensional (3D) memory.

[0102] Figure 7A This describes another stage in the semiconductor manufacturing process used to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The vertically stacked memory cell array (described in the description) and example methods according to several embodiments of the present disclosure. Figure 7A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 7A In example embodiments, the method includes patterning photomasks 735, 736, and / or 737 using a photolithography process, for example... Figures 6A to 6E 635, 636 and / or 637. Figure 7A The method further illustrates the use of one or more etchant processes in the memory node region 750 (and Figure 7A and 7C A vertical opening 751 is formed in 744) through the vertical stack and extending primarily in the first horizontal direction (D1) 709. One or more etchant processes form the vertical opening 751 to expose Figures 7B to 7E The third sidewall is shown in the vertical stacking of the second region adjacent to the sacrificial material, in the repeated iterations of alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the sacrificial material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N. Other numbered components may be similar to those shown and discussed with respect to Figure 6.

[0103] In some embodiments, this process is about Figures 4A to 4N The semiconductor manufacturing process described is performed prior to this. However, Figures 7B to 7E The embodiments shown illustrate the storage node manufacturing process after it has undergone relevant procedures. Figures 4A to 4N The described digital lines and the first source / drain region form a sequence executed "afterwards," for example, the digital lines are formed first. Here, the digital lines can be described as along multiple separate, vertical access lines 740.

[0104] according to Figures 7B to 7E The example embodiments shown in the figure include methods in vertical stacking ( Figure 4A In the 401), a second vertical opening 751 is formed and a second region 744 of the sacrificial material 732-1, 732-2, ..., 732-N is selectively etched to form a vertical stack ( Figure 4A The second horizontal opening 779 is a second horizontal distance (D2 opening) backward from the vertical opening 751 in 401). According to an embodiment, selectively etching the second region 744 of the sacrificial materials 732-1, 732-2, ..., 732-N may include using an atomic layer etching (ALE) process. (See also: Regarding...) Figure 7C Further explanation: the second source / drain region 778 can be formed in monocrystalline silicon at the end of the second horizontal opening 779, away from the vertical opening. Figure 7C In monocrystalline silicon (487).

[0105] Figure 7B Explanation along Figure 7A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7B The cross-sectional view shown is away from multiple separate, vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and shows the repeated iteration of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1), sacrificial materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N, separated by vertical openings 751, formed vertically stacked on a semiconductor substrate 700. Figure 7B As shown in the diagram, the vertical direction 711 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The drawing shows the first, second, and third directions, specifically the third direction (D3) 111. The plane of the drawing extends left and right along the first direction (D1) 709. Figure 7B In an example embodiment, the materials within the vertical stack (dielectric materials 730-1, 730-2, ..., 730-(N+1), sacrificial materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N) extend into and out of the plane of the drawing in the second direction (D2) along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0106] Figure 7C Explanation along Figure 7A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7CThe cross-sectional view shown is illustrated as extending left and right along the plane of the drawing in the second direction (D2) 705, along the axis of repeated iterations of alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, monocrystalline silicon 787 and the second dielectric material 733-1, 733-2, ..., 733-N. Along and on said axis, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of monocrystalline silicon 787.

[0107] exist Figure 7C In an example embodiment, the vertical opening 751 and the first horizontal opening 779 are shown as being composed of about Figure 7A The masking, patterning, and etching processes described are used to create the image. For example... Figure 7C As shown, the sacrificial material in the second region 744 (e.g., sacrificial material 432 in Figure 4) has been selectively removed to form the first horizontal opening 779. In one example, an atomic layer deposition (ALE) process is used to selectively etch the sacrificial material and remove a second distance (D2 opening) backward from the vertical opening 751. Horizontally oriented memory nodes (e.g., capacitor cells) can be positioned relative to... Figures 4A to 4N The manufacturing process shown in the image may be followed or introduced later, such as... Figures 8A to 8E As shown in the diagram, it is formed in the first horizontal opening 779.

[0108] Figure 7C The diagram also shows that the first source / drain region 775 can be formed by vapor-doping a dopant into the top surface portion of the single-crystal silicon 787. In some embodiments, the first source / drain region 775 may be adjacent to the vertical access line 740. According to one example embodiment, such as Figure 7C As shown, the second source / drain region 778 can be formed at the end of the first horizontal opening 779 away from the vertical opening 751 by allowing a high-energy vapor dopant (e.g., phosphorus (P) for n-type transistors) to flow into the first horizontal opening 779 to dope the dopant in the single-crystal silicon 787. In one example, vapor doping can be used to achieve highly isotropic (e.g., non-directional) doping to form the second source / drain region 778 of the horizontally oriented access device in region 742. In another example, thermal annealing using a dopant gas (e.g., phosphorus) can be used in conjunction with a high-energy plasma to help break the bond. However, the embodiments are not limited to this and other suitable semiconductor manufacturing techniques can be utilized.

[0109] Conductive material 777 may be deposited adjacent to second dielectric material 733. Conductive material 777 may maintain electrical contact on the top surface of first source / drain region 775. Thus, conductive material 777 maintains electrical contact with first source / drain region 775. In some embodiments, third dielectric material 774 may be below first dielectric material 730, while maintaining direct contact with conductive material 777, first source / drain region 775, and a first portion of lightly doped single-crystal silicon 787. Third dielectric material 774 may be in direct electrical contact with heavily doped silicon material, such as the contact of body region 795 of a horizontally oriented access device.

[0110] like Figure 7C Further, it is shown that the first electrode (e.g., 761) of the horizontally oriented memory node is coupled to the second source / drain region 778 of the horizontal access device. As will be shown later. Figure 7C As shown in the diagram, such horizontally oriented storage nodes are depicted as being formed in a second horizontal opening 779, which extends laterally in the plane of the drawing in a second direction (D2), from the vertical stack (e.g., Figure 4A The vertical opening 751 in 401) extends a second distance (D2 opening) and is along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 7C In the middle, the adjacent opposite vertical access lines 740-3 are indicated by dashed lines that indicate the set of positions from the plane and orientation inwards of the drawing.

[0111] Figure 7D Explanation along Figure 7A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7D The cross-sectional view shown is illustrated as an axis along the second direction (D2) 705, in the plane of the drawing, extending laterally outside the area where the horizontally oriented access device and the horizontally oriented storage node are located, along the repeating iteration of alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the sacrificial material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N. The repeating iteration of alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the sacrificial material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N is shown at the left end of the drawing. At this location, the horizontally oriented digital lines (e.g., ...) Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form electrical contacts with the first source / drain region or the conductive contact material of the digital line, as described above. Figures 4A to 4N describe.

[0112] Furthermore, while the references to the first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a single meaning. It is desirable that only one of the source / drain regions is connected to a digital line (e.g., 107-2), and the other is connected to a memory node.

[0113] In some embodiments, the conductive material 777 may be described as being adjacent to the second dielectric material 733. The conductive material 777 may be adjacent to the dielectric material 741. The main contact area 795 may be described as a repeated iteration along alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the sacrificial material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N.

[0114] Figure 7E Explanation along Figure 7A The cut line D-D' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7E The cross-sectional view shown is illustrated as extending laterally along the axis of repeated iterations of alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, sacrificial materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N in the first direction (D1) 709 of the drawing, intersecting multiple separate, vertical access lines 740-1, 740-2, ..., 740-4, and intersecting with the areas of sacrificial materials 732-1, 732-2, ..., 732-N separated from the multiple separate, vertical access lines 740-1, 740-2, ..., 740-4 by the gate dielectric 738. Figure 7E In the diagram, the first dielectric filling material 739 is shown as a space separating adjacent horizontally oriented access devices, which can be formed into a plane extending into and out of the drawing (as per the diagram). Figures 4A to 4N (Description), and can be spaced and stacked vertically along the first direction (D1) 709 in an array extending on the third direction (D3) 711 in a three-dimensional (3D) memory.

[0115] Figure 8A This describes another stage in the semiconductor manufacturing process used to form horizontally oriented access devices and vertically oriented access lines (e.g. Figures 1 to 3 The vertically stacked memory cell array (described in the description) and example methods according to several embodiments of the present disclosure. Figure 8AA top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 8A In example embodiments, the method includes patterning photomasks 835, 836, and / or 837 using a photolithography process, for example... Figures 6A to 6E 635, 636 and / or 637 or Figures 7A to 7E 735, 736 and / or 737. Figure 8A The method further illustrates the use of one or more etchant processes in memory node region 850 (and Figure 8A and 8C A vertical opening 851 is formed in 844) through the vertical stack and extending primarily in the first horizontal direction (D1) 809. One or more etchant processes form the vertical opening 851 to expose Figures 8B to 8E The third sidewall is shown in the vertically stacked arrangement of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, sacrificial material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N. Other numbered components may be similar to those shown and discussed with respect to Figures 6 and 7.

[0116] In some embodiments, this process is performed after selectively removing the access device region in which sacrificial material will form the first source / drain region, the channel region, and the second source / drain region of the horizontally oriented access device is removed, as illustrated in FIG7. Figures 8B to 8E The example embodiment shown in the diagram includes a method that selectively etches a second region of sacrificial material to deposit a second source / drain region and a capacitor cell in a second horizontal opening region 842 extending a second horizontal distance backward from a vertical opening 851 in a vertical stack. In some embodiments, such as Figures 8B to 8E The method, as shown, includes forming capacitor cells as storage nodes within a second horizontal opening. By way of example, and not limitation, forming the capacitors includes sequentially depositing a first electrode 861 and a second electrode 856 separated by a cell dielectric 863 within the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used. Digital lines can be seen along multiple separate, vertical access lines 840.

[0117] Figure 8B Explanation along Figure 8A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8BThe cross-sectional view shown is away from multiple separate, vertically accessible lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and shows the repeated iteration of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) formed vertically stacked on a semiconductor substrate 800, separated by horizontally oriented capacitor cells having a first electrode 861 (e.g., bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., top common node electrode). Figure 8B As shown in the diagram, the vertical direction 811 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The drawing shows the first, second, and third directions, specifically the third direction (D3) 111. The plane of the drawing extends left and right along the first direction (D1) 809. Figure 8B In an example embodiment, the first electrode 861 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 856 are described as being separated by the cell dielectric 863 of the horizontal access device and the orientation axis of the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory extending in a second direction (D2) into and out of the plane of the drawing and along the orientation axis of the horizontal storage node.

[0118] Figure 8C Explanation along Figure 8A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8C The cross-sectional view shown is illustrated as extending laterally along the plane of the drawing in the second direction (D2) 805, along an axis of repeated iterations of alternating layers of the first dielectric material 830-1, 830-2, ..., 830-N, monocrystalline silicon 887, and the second dielectric material 833-1, 833-2, ..., 833-N. Horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within layers of monocrystalline silicon 887 along this axis. Figure 8CIn the example embodiment, horizontally oriented memory nodes (e.g., capacitor cells) are illustrated as having been formed in this semiconductor manufacturing process, and a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane (e.g., a ground plane)) separated by cell dielectric 863 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane (e.g., a ground plane) separated by cell dielectric 863 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in a region of single-crystal silicon 887, intended for the positioning (e.g., placement formation) of the horizontally oriented access device described below.

[0119] exist Figure 8C In an example embodiment, a horizontally oriented memory node having a first electrode 861 (e.g., a bottom electrode coupling to the source / drain region of a horizontal access device) and a second electrode 856 (e.g., a top electrode coupling to a common electrode plane (e.g., a ground plane)) is shown formed in a second direction (D2) in the plane of the drawing from a vertically stacked (e.g., Figure 4A The vertical opening in 401) (e.g.) Figure 7C The second horizontal opening (e.g., 751) extends to the left and right of the second distance (D2 opening) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 7C In (779) shown in the image. Figure 8C In the middle, adjacent opposite vertical access lines 840-3 are indicated by dashed lines that indicate the set of positions from the plane and orientation inwards of the drawing.

[0120] The conductive material 877 may be described as being adjacent to the second dielectric material 833. The conductive material 877 may maintain electrical contact on the top surface of the first source / drain region 875. Thus, the conductive material 877 maintains electrical contact with the first source / drain region 875. In some embodiments, the third dielectric material 874 may be below the first dielectric material 830, while maintaining direct contact with the conductive material 877, the first source / drain region 875, and a first portion of the lightly doped semiconductor material 832. The third dielectric material 874 may form direct electrical contact with a heavily doped silicon material, such as the body contact region 895 of a horizontally oriented access device.

[0121] In some embodiments, the horizontal access device may be coupled to a fully complementary metal-oxide-semiconductor (CMOS) array after the capacitor cell is formed (e.g., Figure 4N(CMOS 445). That is, a complete horizontal access device can be bonded to a complete CMOS.

[0122] Figure 8D Explanation along Figure 8A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8D The cross-sectional view shown is illustrated as follows: along the plane of the drawing in the second direction (D2) 805, along the repeating iterative axis of alternating layers of the first dielectric material 830-1, 830-2, ..., 830-N, monocrystalline silicon 887, and the second dielectric material 833-1, 833-2, ..., 833-N, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed outside the regions within the layers of monocrystalline silicon 887. Figure 8C In the diagram, dielectric material 841 is shown filling the space between horizontally oriented access devices for a three-dimensional array of vertically oriented memory cells, which may be spaced along a first direction (D1) extending into and out of the plane of the drawing. However, in Figure 8D In the cross-sectional view, the second electrode 856 (e.g., the common electrode at the top of the capacitor cell structure) is also shown as existing in the space between horizontally adjacent devices. The left end of the drawing shows a repeating iteration of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, monocrystalline silicon 887, and second dielectric materials 833-1, 833-2, ..., 833-N, at which point horizontally oriented digital lines (e.g., ...) are also shown. Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form electrical contacts with the second source / drain region or the digital line conductive contact material, as described in more detail below.

[0123] In some embodiments, the conductive material 877 may be described as adjacent to the second dielectric material 833 and the dielectric material 841. The main contact area 895 may also be described as a repeated iteration along alternating layers of the first dielectric material 830-1, 830-2, ..., 830-N, the monocrystalline silicon 887, and the second dielectric material 833-1, 833-2, ..., 833-N.

[0124] Figure 8E Explanation along Figure 8A The cut line D-D' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8EThe cross-sectional view shown is illustrated as extending laterally along the axis of repeated iterations of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, sacrificial materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N in the first direction (D1) 809 of the drawing, intersecting multiple separate, vertical access lines 840-1, 840-2, ..., 840-4, and intersecting with the areas of sacrificial materials 832-1, 832-2, ..., 832-N separated from the multiple separate, vertical access lines 840-1, 840-2, ..., 840-4 by the gate dielectric 838. Figure 8E In the diagram, a first dielectric filling material 839 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes. It can be formed into a plane extending into and out of the drawing (as described in more detail below) and can be spaced apart and vertically stacked along a first direction (D1) 809 in an array extending in a third direction (D3) 811 in a three-dimensional (3D) memory.

[0125] Figure 9 This illustration shows a cross-sectional view of a portion of an example horizontally oriented access device according to several embodiments of the present disclosure, which is coupled to a horizontally oriented memory node and to vertically oriented access lines and horizontally oriented digital lines (which may form portions of a vertically stacked array of memory cells). The horizontally oriented access device 901 may have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite to the channel region and separated from the channel region by a gate dielectric.

[0126] like Figure 9 As shown in the example, the first source / drain region 975-1 is illustrated as being in direct electrical contact with the horizontally oriented digital line 977-1. In some embodiments, the conductive digital lines 977-1 and 977-2 are formed of a metal composition including tungsten (W). However, the embodiments are not limited to this example. Although the terms “first” and “second” source / drain regions may be used herein to designate different and separate source / drain regions, the terms “first” and / or “second” are not limited to their counterparts in the source / drain regions, and their respective placements and their respective “first” or “second” designations used herein for convenience are interchangeable within the horizontally oriented access device described herein. For example, the first source / drain region 975-1 may also be referred to as the “second” source / drain region. Regardless of whether it is labeled “first” or “second”, the source / drain regions can be separated from the other source / drain region by a channel region in the body of the horizontal access device.

[0127] exist Figure 9In this example, the first source / drain region 975-1 is illustrated as being formed in the body of the lightly doped channel and body region of the horizontally oriented access device 901. The first source / drain region 975-1 is separated from the conductive vertical body contact 995 by a dielectric material 974. As shown, interlayer dielectric (ILD) materials 930-1 and 930-2 can separate the horizontally oriented access devices of the vertically stacked memory cells. ILDs 930-1 and 930-2 can be the first dielectric material, such as an oxide-based dielectric material. However, the embodiments are not limited to this example.

[0128] exist Figure 9 In one example, horizontally oriented digital lines (e.g., 977-1 and 977-2) are formed in a second dielectric material type (e.g., a nitride-based dielectric material). However, the embodiments are not limited to this example. According to an embodiment, the first dielectric material and the second dielectric material are different compositions and dissimilar, such that one (e.g., the second dielectric nitride material) can be selectively etched relative to the first dielectric material (e.g., an oxide material). The first dielectric materials 930-1 and 930-2, the horizontally oriented access device 901 including a first source / drain region 975-1 and a channel in the body region 987-1, and the digital lines 977-1 and 977-2 are formed into three layers of vertically stacked memory cells.

[0129] like Figure 9 As shown in the example embodiments, the conductive vertical body contact 995 may be formed to directly contact the body region 987-1 of one or more of the horizontally oriented access devices 901. In some embodiments, the conductive vertical body contact 995 may be a metal, such as tungsten (W). In some embodiments, the conductive vertical body contact 995 may be a conductive doped polysilicon material, such as a highly doped p-type (p+) polysilicon semiconductor material. However, the embodiments are not limited to these examples. As used herein, the term "highly doped" is intended to mean a high concentration of dopant impurities, such that there are significant interactions between dopant atoms. P-type dopant may contain boron atoms (B), and n-type dopant may contain phosphorus atoms (P). According to the embodiments, the conductive vertical body contact 995 is separated from the first source / drain region 975-1 and the horizontally oriented digital lines 977-1 and 977-2 by a dielectric material 974 (e.g., SiN in this example).

[0130] In some embodiments, the vertical body contact 995 may include a lower body conductive contact formed to be in direct electrical contact with a body region 987-1 of one or more of the horizontally oriented access devices 901. In some embodiments, the lower body conductive contact may be a metal, such as tungsten (W). In some embodiments, the lower body conductive contact may be a conductive doped polycrystalline silicon material, such as a highly doped p-type (p+) polycrystalline silicon semiconductor material or a p-type (p+) doped polycrystalline silicon germanium (SiGe). However, the embodiments are not limited to these examples.

[0131] In some embodiments, the dielectric material 974 further separates a first portion of the body region 987-1 of the horizontally oriented access device 901 (e.g., Figure 4H 478) and conductive vertical body contact 995 to reduce hole formation in body region 987-1 between conductive vertical body contact 995 and body region 987-1. In some embodiments, dielectric material 974 further separates a first portion of the body region 987-1 of the horizontally oriented access device 901 (e.g., 478) and conductive vertical body contact 995 to reduce hole formation in body region 987-1 between conductive vertical body contact 995 and body region 987-1. Figure 4H 478) and conductive vertical body contact 995 to reduce gate-induced drain leakage (GIDL) in the horizontally oriented access device 901. In some embodiments, the horizontally oriented memory node (e.g., Figure 7C The capacitor cell shown in the image is coupled to the second source / drain region. Figure 9 (Not shown in the image). In this example, the capacitor cell has a first horizontally oriented electrode electrically coupled to a second source / drain region and a second horizontally oriented electrode separated from the first horizontally oriented electrode by the cell dielectric.

[0132] Therefore, as Figure 9 As shown in the example embodiment, highly doped semiconductor material can be deposited into a vertical opening 995 to form a conductive vertical body contact 995 that directly contacts only a portion of the low-doped semiconductor material channel and body region 987-1 of the horizontally oriented access device.

[0133] According to an embodiment, a deposited dielectric material 974 forms a small-area electrical contact between the conductive vertical body contact 995 and the channel in the horizontally oriented access device body region 987-1, while also directly electrically isolating the first source / drain region 975-1 from the digital lines 977-1 and 977-2. The small-area electrical contact between the conductive vertical body contact 995 and the channel in the body region 987-1, and the electrical isolation between the first source / drain region 975-1 and the digital lines 977-1 and 977-2, reduces capacitive coupling between the conductive vertical body contact 995 and the first source / drain region 975-1 and the digital lines 977-1 and 977-2. The small-area electrical contact also prevents hole diffusion between the highly doped semiconductor material 995 and the body region 987-1.

[0134] Figure 10 This is a block diagram of a device in the form of a computing system 1000 including a memory device 1003, according to several embodiments of the present disclosure. As used herein, for example, the memory device 1003, the memory array 1010, and / or the host 1002 may also be individually considered as a "device". According to an embodiment, the host 1002 may include at least one memory array 1010 having memory cells formed with digital lines and body contacts according to embodiments described herein.

[0135] In this example, system 1000 includes a host 1002 coupled to memory device 1003 via interface 1004. The computing system 1000 can be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, and various other types of systems. Host 1002 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory device 1003. System 1000 may include a separate integrated circuit, or both host 1002 and memory device 1003 may be on the same integrated circuit. For example, host 1002 may be a system controller for a memory system including multiple memory devices 1003, wherein system controller 1005 provides access to the respective memory devices 1003 via another processing resource (e.g., a central processing unit (CPU)).

[0136] exist Figure 10 In the example shown, host 1002 is responsible for executing the operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., loaded onto it from memory device 1003 via system controller 1005). The OS and / or various applications can be loaded from memory device 1003 by providing access commands from host 1002 to memory device 1003, including access to data of the OS and / or various applications. Host 1002 can also access said data used by the OS and / or various applications by providing access commands to memory device 1003 to retrieve data for executing the OS and / or various applications.

[0137] For clarity, system 1000 has been simplified to focus on features specifically relevant to this disclosure. Memory array 1010 may be a DRAM array including at least one memory cell having digital lines and body contacts formed according to the techniques described herein. For example, memory array 1010 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1010 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although Figure 10 The illustration shows a single memory array 1010, but the embodiments are not limited thereto. For example, memory device 1003 may include several memory arrays 1010 (e.g., several banks of DRAM cells).

[0138] Memory device 1003 includes an address circuitry 1006 for latching address signals provided via interface 1004. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 1004 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, or the like. Address signals are received and decoded by row decoder 1008 and column decoder 1012 to access memory array 1010. Data can be read from memory array 1010 by sensing voltage and / or current changes on a sensing line using sensing circuitry 1011. Sensing circuitry 1011 may include, for example, a sense amplifier capable of reading and latching a page (e.g., a row) of data from memory array 1010. I / O circuitry 1007 can be used for bidirectional data communication with host 1002 via interface 1004. The read / write circuitry 1013 is used to write data to or read data from the memory array 1010. As an example, the circuitry 1013 may include various drivers, latching circuitry, etc.

[0139] System control 1005 decodes signals provided by host 1002. These signals may be commands provided by host 1002. These signals may include chip enable signals, write enable signals, and address latch signals, used to control operations performed on memory array 1010, including data read operations, data write operations, and data erase operations. In various embodiments, system control 1005 is responsible for executing instructions from host 1002. System control 1005 may include state machines, sequencers, and / or other types of control circuitry systems, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, host 1002 may be a controller external to memory device 1003. For example, host 1002 may be a memory controller coupled to the processing resources of a computing device.

[0140] The term "semiconductor" can refer to, for example, a material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referring to semiconductors as described above, prior process steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term "semiconductor" may include an underlying material containing such regions / junctions.

[0141] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the figure number and the remaining digits identify elements or components in the figure. Similar (e.g., identical) elements or components between different figures can be identified by using similar digits. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be considered as intended to be limiting.

[0142] As used herein, “several” or “a certain number” of something may refer to one or more such things. For example, “several” or “a certain number” of memory cells may refer to one or more memory cells. “A certain number” of something is intended to be two or more. As used herein, performing multiple actions simultaneously refers to actions that at least partially overlap within a specific time period. As used herein, the term “coupling” may include electrical coupling, direct coupling and / or direct connection without interventional elements (e.g., through direct physical contact), indirect coupling and / or connection using interventional elements, or wireless coupling. The term “coupling” may further include two or more elements that cooperate or interact with each other (e.g., in a causal relationship). An element coupled between two elements may be between the two elements and coupled to each of the two elements.

[0143] It should be recognized that the term "vertical" indicates a change from "completely" vertical due to variations in routine manufacturing, measurement, and / or assembly, and those skilled in the art should understand what the term "vertical" means. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or laterally to the other element, and / or may be in direct physical contact with the other element. "Laterally to" may refer to, for example, a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0144] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of the various embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon review of the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the foregoing structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the full scope of the appended claims and their equivalents.

Claims

1. A method for forming a vertically stacked array (101) of memory cells (110) having horizontally oriented access devices (901) and vertically oriented access lines (103, 203, 303), comprising: Alternating layers of a first dielectric material (430, 530, 630, 730, 830), a sacrificial material (432, 532, 632, 732, 832), and a second dielectric material (433, 533, 633, 733, 833) are vertically deposited in repeated iterations to form a vertical stack (401); A first vertical opening (471) is formed using a first etchant process to expose the vertical sidewalls (414, 514) in the vertical stack (401); Selectively etch back a first portion of the first horizontal length (476) of the sacrificial material (432, 532, 632, 732, 832) in the first region of the vertical stack (401) from the first vertical opening (471) to form the first horizontal opening (473); Epitaxial growth of single-crystal silicon (487, 787, 887) to fill the first vertical opening (471) and the first horizontal opening (473); Selectively etch the single-crystal silicon (487, 787, 887) to modify the first vertical opening (471); Selectively etch the second dielectric material (433, 533, 633, 733, 833) to form a second horizontal opening (488) extending rearward from the first vertical opening (471) for a second length (489); and A first dopant is vapor-doped in the top surface (415) of the monocrystalline silicon (487, 787, 887) in the first horizontal opening (473) to form a first source / drain region (321).

2. The method according to claim 1, wherein epitaxial growth of the single crystal silicon includes allowing silane (Si2H6) gas to flow into the first vertical opening and the first horizontal opening.

3. The method according to claim 2, further comprising allowing the silane (Si2H6) gas to flow into the first vertical opening and the first horizontal opening at a temperature of 600 degrees Celsius (°C) to 1100 degrees Celsius.

4. The method according to claim 1, wherein epitaxial growth of the single crystal silicon comprises allowing silicon-based gas to flow into the first vertical opening and the first horizontal opening at a temperature of 600 degrees Celsius (°C) to 1100°C.

5. The method according to claim 4, further comprising allowing dichlorosilane (SiH2Cl2) gas to flow into the first vertical opening and the first horizontal opening at a temperature of 600 degrees Celsius (°C) to 1100 degrees Celsius.

6. The method according to any one of claims 1 to 5, wherein forming the first vertical opening further comprises exposing the semiconductor substrate (400, 500, 600, 700, 800) using the first etchant process.

7. The method of claim 6, wherein the semiconductor substrate is formed of silicon (Si) material.

8. The method according to any one of claims 1 to 5, further comprising selectively etching a second portion of the sacrificial material in the second region of the vertical stack to form a storage node (227) of the memory cell of the vertical stack before depositing a horizontally oriented access device.

9. The method of claim 8, further comprising doping the sidewalls of the epitaxially grown single-crystal silicon with a second dopant to form a second source / drain region (323) prior to forming the memory node.

10. The method according to any one of claims 1 to 5, further comprising depositing titanium / titanium nitride (TiN) conductive material via the first vertical opening to form titanium silicide as a portion of a horizontally oriented digital line to each of the horizontally oriented access devices.

11. A method for forming a memory array (101) having vertically stacked memory cells (110) and having horizontally oriented access means (901) and vertically oriented access lines, comprising: The vertical stack (401) is formed by alternating layers of a first dielectric material (430, 530, 630, 730, 830), a sacrificial material (432, 532, 632, 732, 832), and a second dielectric material (433, 533, 633, 733, 833) through at least four iterations in repeated iterations. A first vertical opening (471) is formed using a first etchant process to expose the semiconductor substrates (400, 500, 600, 700, 800) and vertical sidewalls (414, 514) in the vertical stack (401); Selectively etch back the sacrificial material (432, 532, 632, 732, 832) along a first horizontal length (476) from the first vertical opening (471) to form a first horizontal opening (473) with a first height; Single-crystal silicon (487, 787, 887) is epitaxially grown by allowing silane (Si2H6) gas to flow into the first vertical opening (471) and the first horizontal opening (473) to fill the first vertical opening (471) and the first horizontal opening (473). Selectively etch the single-crystal silicon (487, 787, 887) to modify the first vertical opening (471); Selectively etch the second dielectric material (433, 533, 633, 733, 833) to form a second horizontal opening (488) having a second height and to make the second dielectric material (433, 533, 633, 733, 833) recessed from the first vertical opening (471) by a second length (489); Vapor dopant is applied to the top surface (415) of the single-crystal silicon (487, 787, 887) to form a first source / drain region (321); A conductive material is deposited onto the first source / drain region (321) beneath the second dielectric material (433, 533, 633, 733, 833); and The vertical stack (401) is etched to maintain the first vertical opening (471) and expose the sidewalls, the monocrystalline silicon (487, 787, 887) and the first dielectric material (430, 530, 630, 730, 830) to form the main contact.

12. The method of claim 11, further comprising forming the first vertical opening having a width (492) from 20 to 400 nanometers (nm).

13. The method of claim 11, further comprising allowing the silane (Si2H6) gas to flow into the first vertical opening and the first horizontal opening at a temperature of 600°C to 1100°C to grow the single-crystal silicon.

14. The method according to any one of claims 11 to 13, further comprising forming the first horizontal opening having a first height of 20 to 150 nanometers (nm).

15. The method according to any one of claims 11 to 13, further comprising forming the vertical stack on a complementary metal-oxide-semiconductor CMOS (445).

16. The method according to any one of claims 11 to 13, further comprising forming the vertical stack separate from the complementary metal-oxide-semiconductor CMOS (445) and bonding the vertical stack to the CMOS (445).

17. A method for forming a vertically stacked array of memory cells having horizontally oriented access means and vertically oriented access lines, comprising: A first vertical opening is formed by using a first etchant process to expose the vertical sidewalls in a vertical stack, wherein the vertical stack comprises a first dielectric material, a sacrificial material, and a second dielectric material that are repeatedly iterated. Selectively etch back a first portion of the sacrificial material in the first region of the vertically stacked first region from the first vertical opening to form the first horizontal opening; Epitaxial growth of single-crystal silicon to fill the first vertical opening and the first horizontal opening; Selectively etch the single-crystal silicon to modify the first vertical opening; Selectively etch the second dielectric material to form a second horizontal opening extending rearward from the first vertical opening for a second length; and A first dopant is vapor-doped into the top surface of the single-crystal silicon in the first horizontal opening to form a source / drain region.

18. The method of claim 17, further comprising etching the vertical stack to maintain the first vertical opening and expose the sidewalls, the monocrystalline silicon, and the first dielectric material to form a body contact.

19. The method of claim 17, further comprising depositing a conductive material onto the source / drain region beneath the second dielectric material.

20. The method of claim 17, further comprising bonding the vertical stack to a complementary metal-oxide-semiconductor (CMOS) chip, respectively.

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