Layout structure of chip ROM KEY and chip

Abstract

This invention discloses a layout structure and chip for a chip ROMKEY. The layout structure of the chip ROMKEY includes: M first logical layout areas, which implement first logical functions; N second logical layout areas, which implement second logical functions; and two edge layout areas, which are used to interface with other structures within the chip during chip routing. M and N are both positive integers. The M first logical layout areas and N second logical layout areas are arranged in a preset order and located between the two edge layout areas to implement an M+N bit ROM key. This chip ROMKEY layout structure offers high flexibility, good concealment, and can be directly identified and used by placement and routing tools, making it highly applicable.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a layout structure and chip for a chip ROMKEY. Background Technology

[0002] As a crucial carrier of information transmission, the functionality and reliability of chips play a vital role in information security. In recent years, with the continuous development of the integrated circuit industry, chip design capabilities have gradually improved, and the variety of chips has become increasingly diverse, including data protection circuits, cryptographic algorithm hardware accelerators, and System-on-Chip (SoC) systems with embedded CPUs (central processing units). At the same time, various attack methods against chips have also emerged. These attack methods infer and obtain the keys of the chip's internal cryptographic system by detecting and analyzing information such as power consumption, time, and electromagnetic waves leaked during chip operation, thereby gaining access to the data stored on the chip.

[0003] ROM (Read-Only Memory), as a crucial data storage module in a chip, is often a prime target for attackers. Once an attacker steals data from the ROM, the chip's security mechanisms are easily compromised. To better protect the data within the ROM, a common technique is to encrypt and store the data using a key, often referred to as a ROMKEY. Therefore, the design of the ROMKEY is critical to the overall security of the chip. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to provide a layout structure for a chip ROMKEY that is highly flexible, well-concealed, and can be directly identified and used by placement and routing tools, thus exhibiting strong applicability.

[0005] The second objective of this invention is to provide a chip.

[0006] To achieve the above objectives, a first aspect of the present invention provides a layout structure for a chip ROMKEY, comprising: M first logical layout areas, which are used to implement a first logical function; N second logical layout areas, which are used to implement a second logical function; and two edge layout areas, which are used to interface with other structures within the chip during chip routing; wherein M and N are both positive integers, the M first logical layout areas and the N second logical layout areas are arranged in a preset order and located between the two edge layout areas to implement an M+N bit ROM key.

[0007] In addition, the layout structure of the chip ROMKEY in this embodiment of the invention may also have the following additional technical features:

[0008] According to an embodiment of the present invention, the first logic layout area includes: a first NWELL region, a first PPLUS region, a first NPLUS region, a first active region, a second active region, a first metal layer, a second metal layer, a third metal layer, a first interconnect, a second interconnect, a third interconnect, and a fourth interconnect. The first active region, the first metal layer, the first interconnect, and the second interconnect are all located in the first PPLUS region; the second active region, the third interconnect, the fourth interconnect, and the third metal layer are all located in the first NPLUS region. The first metal layer is connected to the first active region via the first interconnect; the second metal layer is connected to the first active region via the second interconnect; the second metal layer is also connected to the second active region via the third interconnect and the fourth interconnect. The first metal layer is used to connect to the chip power supply, and the third metal layer is used to connect to the chip ground. The first logic layout area further includes: a first resistor label layer, which is located between the first interconnect and the second interconnect and covers the first active region.

[0009] According to one embodiment of the present invention, the second logic layout area includes: a second NWELL region, a second PPLUS region, a second NPLUS region, a third active region, a fourth active region, a fourth metal layer, a fifth metal layer, a sixth metal layer, a fifth interconnect, a sixth interconnect, a seventh interconnect, and an eighth interconnect. The third active region, the fourth metal layer, the fifth interconnect, and the sixth interconnect are all located in the second PPLUS region. The fourth active region, the seventh interconnect, the eighth interconnect, and the sixth metal layer are all located in the second NPLUS region. The fifth metal layer is connected to the third active region through the fifth and sixth interconnects. The fifth metal layer is also connected to the fourth active region through the seventh interconnect. The sixth metal layer is connected to the fourth active region through the eighth interconnect. The fourth metal layer is used to connect to the chip power supply, and the sixth metal layer is used to connect to the chip ground. The second logic layout area further includes: a second resistor identification layer, which is located between the seventh and eighth interconnects and covers the fourth active region.

[0010] According to one embodiment of the present invention, the edge layout area includes: a third NWELL region, a third PPLUS region, a third NPLUS region, a seventh metal layer and an eighth metal layer, wherein the seventh metal layer is located in the third PPLUS region and is used to connect the chip power supply, and the eighth metal layer is located in the third NPLUS region and is used to connect the chip ground.

[0011] According to one embodiment of the present invention, the first active region extends along a first direction, and the second active region extends along a second direction. Both the first active region and the second active region are symmetrical with respect to the central axis of the first logic layout region, wherein the first direction is perpendicular to the second direction.

[0012] According to one embodiment of the present invention, the first metal layer is T-shaped and symmetrical with respect to the central axis of the first logic layout area, and intersects with both sides of the first logic layout area. The two intersection points are used to connect metal layers in other logic layout areas or edge layout areas for connecting chip power supplies. One end of the first metal layer along the first direction is connected to the end of the first active area near the first metal layer through the first connection hole. The second metal layer extends along the first direction, and one end of the second metal layer is connected to the end of the first active area away from the first metal layer through the second connection hole. The third metal layer extends along the second direction and intersects with both sides of the first logic layout area. The two intersection points are used to connect metal layers in other logic layout areas or edge layout areas for connecting chip ground.

[0013] According to one embodiment of the present invention, the first PPLUS region of the first logic layout area is mirror-symmetrical to the second NPLUS region of the second logic layout area, and the first NPLUS region of the first logic layout area is mirror-symmetrical to the second PPLUS region of the second logic layout area.

[0014] According to one embodiment of the present invention, the distance between any logic layout area and its adjacent logic layout area or edge layout area is zero.

[0015] According to one embodiment of the present invention, the first logic layout area, the second logic layout area and the edge layout area have the same length, and the intersection of the metal layer used to connect the chip power supply and the corresponding layout area, and the intersection of the metal layer used to connect the chip ground and the corresponding layout area are all collinear.

[0016] According to one embodiment of the present invention, the two edge layout regions are axially symmetrical, and the seventh metal layer and the eighth metal layer both intersect one side of the connection logic layout region of the corresponding edge layout region.

[0017] According to one embodiment of the present invention, the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, the sixth metal layer, the seventh metal layer and the eighth metal layer are all located in the METAL1 layer, and the first connecting hole, the second connecting hole, the third connecting hole, the fourth connecting hole, the fifth connecting hole, the sixth connecting hole, the seventh connecting hole and the eighth connecting hole are all located in the contact layer.

[0018] To achieve the above objectives, a second aspect of the present invention provides a chip, comprising: a digital logic region located in the central region of the chip; a ROM storage unit located in the edge region of the chip; and a layout structure of a chip ROMKEY according to the above embodiment of the present invention, wherein the layout structure of the chip ROMKEY is located in the digital logic region.

[0019] In addition, the chip in this embodiment of the invention also has the following additional technical features:

[0020] According to one embodiment of the present invention, there are multiple layout structures of the chip ROMKEY, and the layout structures of the multiple chip ROMKEYs are distributed in the digital logic area.

[0021] According to the chip ROMKEY layout structure and chip of the present invention, the chip ROMKEY can be implemented in the form of digital standard units. Through different combinations of internal sub-units, multi-bit keys can be flexibly implemented. By mixing and laying out with other digital standard units within the chip's logic area, the ROMKEY unit becomes more difficult for attackers to discover. Furthermore, the ROMKEY layout uses low-level routing, with the highest metal layer being only METAL1, increasing the difficulty for attackers to attack the chip using methods such as FIB. The addition of a resistor identification layer to the ROMKEY layout design allows for direct verification of its correctness using tools, reducing the risks associated with human verification.

[0022] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the layout structure of the chip ROMKEY according to the first embodiment of the present invention;

[0024] Figure 2 This is a structural diagram of the first logic layout area according to an embodiment of the present invention;

[0025] Figure 3 This is a structural diagram of the second logic layout area according to an embodiment of the present invention;

[0026] Figure 4 This is a structural diagram of the edge layout area according to an embodiment of the present invention;

[0027] Figure 5 This is a structural diagram of the chip according to the second embodiment of the present invention. Detailed Implementation

[0028] Currently, ROM keys are typically implemented through hardware embedding. During the chip layout design phase, relevant units are fixedly connected to power or ground to achieve logic 1 or logic 0, thereby forming a binary key. The layout of such ROM keys exhibits certain regularity. However, with the increasing sophistication of chip attack methods, attackers can easily bypass existing chip defenses through layout reconstruction, FIB (Focused Ion Beam Microscopy), and other techniques. This makes the location of the ROM key within the chip more easily discoverable by attackers, making it a target for attack.

[0029] To address the aforementioned problems, this invention proposes a layout structure and chip for a chip ROMKEY.

[0030] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0031] The following is a reference appendix. Figure 1-5 The specific implementation methods described herein include the layout structure and chip of the chip ROMKEY in this embodiment of the invention.

[0032] Figure 1 This is a schematic diagram of the layout structure of the chip ROMKEY according to the first embodiment of the present invention.

[0033] like Figure 1 As shown, the layout structure 10 of the chip ROMKEY includes: M first logic layout areas 1, N second logic layout areas 2, and two edge layout areas 3, where M and N are both positive integers. Figure 1 In this case, M takes the value 3 and N takes the value 5.

[0034] In this embodiment, the first logic layout area 1 is used to implement a first logic function, such as the logic "1" function; the second logic layout area 2 is used to implement a second logic function, such as the logic "0" function; and the edge layout area 3 is used to achieve interfacing with other structures within the chip during chip routing. See also Figure 1 M first logic layout areas 1 and N second logic layout areas 2 are arranged in a preset order ( Figure 1The three first logic layout areas 1 are arranged in positions 1, 2, and 7, and the five second logic layout areas 2 are arranged in positions 3, 4, 5, 6, and 8, and are located between the two edge layout areas 3, in order to implement the M+N bit ROM key.

[0035] It should be noted that the number and preset order of the first logic layout area 1 and the second logic layout area 2 can be determined by the chip designer based on the binary key size. For example, to implement a 128-bit key, 16 ROMKEY standard units (i.e., the chip ROMKEY layout structure 10) can be generated, with each ROMKEY standard unit implementing an 8-bit key; alternatively, 32 ROMKEY standard units can be generated, with each ROMKEY standard unit implementing a 4-bit key, and so on.

[0036] Therefore, by setting up M first logic layout areas 1 and N second logic layout areas 2, the layout structure 10 of the chip ROMKEY is highly flexible. By setting up two edge layout areas 3 and placing the M first logic layout areas 1 and N second logic layout areas 2 in the two edge layout areas 3, the layout structure 10 of the chip ROMKEY can be implemented in the form of digital standard units, which can then be directly identified and used by placement and routing tools. This makes it highly applicable and allows for the interfacing between ROMKEY units and other standard units during chip placement and routing, avoiding problems that may arise during design rule checks.

[0037] As a possible implementation method, see Figure 1 The two edge layout regions 3 mentioned above can be axially symmetrical, and the lengths of the first logic layout region 1, the second logic layout region 2, and the edge layout region 3 are the same. The distance between any logic layout region and its adjacent logic layout region or edge layout region is zero. As a result, the layout structure 10 of the chip ROMKEY is convenient for design, layout, and routing, and is aesthetically pleasing.

[0038] Figure 2 This is a structural diagram of the first logic layout area according to an embodiment of the present invention.

[0039] In embodiments of the present invention, such as Figure 2 As shown, the first logic layout area 1 includes: a first NWELL area 11, a first PPLUS area 12, a first NPLUS area 13, a first active area a1, a second active area a2, a first metal layer m1, a second metal layer m2, a third metal layer m3, a first connection hole v1, a second connection hole v2, a third connection hole v3, and a fourth connection hole v4.

[0040] See Figure 2The first active region a1, the first metal layer m1, the first connection hole v1 and the second connection hole v2 are all located in the first PPLUS region 12. The second active region a2, the third connection hole v3, the fourth connection hole v4 and the third metal layer m3 are all located in the first NPLUS region 13. The first metal layer m1 is connected to the first active region a1 through the first connection hole v1. The second metal layer m2 is connected to the first active region a1 through the second connection hole v2. The second metal layer m2 is also connected to the second active region a2 through the third connection hole v3 and the fourth connection hole v4. The first metal layer m1 is used to connect to the chip power supply VCC, and the third metal layer m3 is used to connect to the chip ground GND.

[0041] As a possible implementation method, see Figure 2 The first active region a2 extends along the first direction, and the second active region a2 extends along the second direction, with the first direction perpendicular to the second direction (for example, if the first active region a2 extends along the vertical direction, then the second active region a2 extends along the horizontal direction). The first active region a1 and the second active region a2 are both symmetrical with respect to the central axis of the first logic layout region 1.

[0042] Further, see Figure 2 The first metal layer m1 is T-shaped and symmetrical to the central axis of the first logic layout area 1, and intersects with both sides of the first logic layout area 1. The two intersection points are used to connect the metal layers of other logic layout areas or edge layout areas used to connect the chip power supply. One end of the first metal layer m1 along the first direction is connected to the end of the first active area a1 near the first metal layer m1 through the first connection hole v1. The second metal layer m2 extends along the first direction, and one end of the second metal layer m2 is connected to the end of the first active area a2 away from the first metal layer m1 through the second connection hole v2. The third metal layer m3 extends along the second direction and intersects with both sides of the first logic layout area 1. The two intersection points are used to connect the metal layers of other logic layout areas or edge layout areas used to connect the chip ground.

[0043] Since existing ROM key layouts are typically connected only via metal, the ROM key cannot be identified by physical verification tools during layout verification. This means that the correctness of the ROM key cannot be guaranteed by verification tools, posing a significant risk. Therefore, the first logic layout area 1 of this invention also includes a first resistor identifier layer (RSYMBOL LAYER1).

[0044] See Figure 2The first resistor identification layer RSYMBOL LAYER1 is located between the first connection hole v1 and the second connection hole v2, and covers the first active region a1. Therefore, chip physical verification tools can directly identify the layout structure of the ROMKEY and determine its correctness, thus demonstrating that the layout structure of the chip ROMKEY of this invention is easy to verify.

[0045] Figure 3 This is a structural diagram of the second logic layout area according to an embodiment of the present invention.

[0046] In specific embodiments of the present invention, such as Figure 3 As shown, the second logic layout area 2 includes: a second NWELL region 21, a second PPLUS region 22, a second NPLUS region 23, a third active region a3, a fourth active region a4, a fourth metal layer m4, a fifth metal layer m5, a sixth metal layer m6, a fifth connection hole v5, a sixth connection hole v6, a seventh connection hole v7, and an eighth connection hole v8.

[0047] See Figure 3 The third active region a3, the fourth metal layer m4, the fifth connection hole v5 and the sixth connection hole v6 are all located in the second PPLUS region 22. The fourth active region a4, the seventh connection hole v7, the eighth connection hole v8 and the sixth metal layer m6 are all located in the second NPLUS region 23. The fifth metal layer m5 is connected to the third active region a3 through the fifth connection hole v5 and the sixth connection hole v6. The fifth metal layer m5 is also connected to the fourth active region a3 through the seventh connection hole v7. The sixth metal layer m6 is connected to the fourth active region a4 through the eighth connection hole v8. The fourth metal layer m4 is used to connect the chip power supply and the sixth metal layer m6 is used to connect the chip ground.

[0048] For ease of map verification, see [link / reference] Figure 3 The second logic layout area 2 also includes a second resistor identifier layer RSYMBOL LAYER2. ​​The second resistor identifier layer RSYMBOL LAYER2 is located between the seventh connection hole v7 and the eighth connection hole v8, and covers the fourth active area a4.

[0049] See Figure 2 , Figure 3 The first PPLUS region 12 of the first logic layout region 1 is mirror-symmetric to the second NPLUS region 23 of the second logic layout region 2, and the first NPLUS region 13 of the first logic layout region 1 is mirror-symmetric to the second PPLUS region 22 of the second logic layout region 2.

[0050] Figure 4 This is a structural diagram of the edge layout area according to an embodiment of the present invention.

[0051] In specific embodiments of the present invention, such as Figure 1 As shown, the two edge layout areas 3 are symmetrically placed on both sides, that is, the two edge layout areas 3 are axially symmetrical (for example, if one edge layout area is placed on the far left, then the other edge layout area is placed on the far right), and the first logic layout area 1 and the second logic layout area 2 are located between the two edge layout areas 3. Figure 4 As shown, the aforementioned edge layout area 3 includes: a third NWELL region 31, a third PPLUS region 32, a third NPLUS region 33, a seventh metal layer m7, and an eighth metal layer m8. The seventh metal layer m7 is located in the third PPLUS region 32 and is used to connect to the chip's power supply. The eighth metal layer m8 is located in the third NPLUS region 33 and is used to connect to the chip's ground.

[0052] Optionally, see Figure 4 The seventh metal layer m7 and the eighth metal layer m8 can both intersect with one side of the connection logic layout area of ​​the corresponding edge layout area.

[0053] In an embodiment of the present invention, see Figures 1-4 The first metal layer m1, the second metal layer m2, the third metal layer m3, the fourth metal layer m4, the fifth metal layer m5, the sixth metal layer m6, the seventh metal layer m7, and the eighth metal layer m8 can all be located on the METAL1 layer, using low-level routing. The highest metal layer is only the aforementioned METAL1, thereby increasing the difficulty for attackers to attack the chip. The first connector v1, the second connector v2, the third connector v3, the fourth connector v4, the fifth connector v5, the sixth connector v6, the seventh connector v7, and the eighth connector v8 can all be located on the contact layer, facilitating layout.

[0054] See Figure 1 The intersections of the metal layer used to connect the chip power supply and the corresponding layout area, and the intersections of the metal layer used to connect the chip ground and the corresponding layout area, are all collinear. This facilitates the layout and routing of the chip ROMKEY's layout structure 10.

[0055] In summary, the layout structure of the chip ROMKEY in this embodiment of the invention can be implemented in the form of digital standard units. Through different combinations of internal sub-units ROMKEY_1 (i.e., the first logical layout area 1) and ROMKEY_0 (i.e., the second logical layout area 2), multi-bit keys can be flexibly generated. Furthermore, there can be multiple such digital standard units (denoted as ROMKEY units) in the chip, which are then randomly distributed with other digital standard units in the chip's logical area, making the ROMKEY units more difficult for attackers to discover. Simultaneously, the use of low-level wiring, with the highest metal layer being only METAL1, increases the difficulty for attackers to attack the chip using methods such as FIB (Focused Ion Beam Microscopy). In addition, by adding an RSYMBOL LAYER during layout design, the ROMKEY can be recognized by layout verification tools, allowing for direct verification of its correctness and reducing the risks associated with manual verification. Finally, the ROMKEY layout structure is not limited by specific processes and has very strong applicability in the field of deep submicron CMOS (Complementary Metal Oxide Semiconductor) processes.

[0056] Figure 5 This is a structural diagram of the chip according to the second embodiment of the present invention.

[0057] In embodiments of the present invention, such as Figure 5 As shown, chip 100 includes: digital logic region 20, ROM storage unit 30 and the layout structure 10 of the chip ROMKEY described above.

[0058] See Figure 5 The digital logic region 20 is located in the central region of the chip 100, the ROM storage unit 30 is located in the edge region of the chip 100, and the layout structure 10 of the chip ROMKEY is located in the digital logic region 20.

[0059] In some implementations, there can be multiple chip ROMKEY layout structures 10, which can be randomly distributed in the digital logic region 20 in the form of standard ROMKEY cells. This makes the chip ROMKEY layout structure 10 more difficult for attackers to discover.

[0060] See Figure 5The chip 100 may also include a Flash memory unit 40, an analog IP unit 50, an I / O interface unit 60, and a power management unit 70. The Flash memory unit 40, the analog IP unit 50, the I / O interface unit 60, the power management unit 70, and the ROM storage unit 30 can all be laid out around the digital logic area 20, and the metal traces of the layout are called METAL1.

[0061] In some embodiments, when there are multiple ROMKEY standard units, there is no specific limitation on the number of bits of the key that each ROMKEY standard unit can implement and the number of ROMKEY standard units. Different combinations of the number and number of ROMKEY standard units can enable the ROM key required by the chip 100 design to be implemented in various forms.

[0062] As an example, to implement a chip containing a 128-bit ROM key, the layout structure 10 of the ROMKEY proposed in this invention first forms 16 digital standard units according to the order of the ROM key, namely ROMKEY1, ROMKEY2, ... ROMKEY15, ROMKEY16. Each ROMKEY standard unit layout structure can implement an 8-bit binary ROM key. The number and order of the structures of the first logical layout area 1 and the second logical layout area 2 correspond one-to-one with the 8-bit binary ROM key. That is, ROMKEY1_[1] to ROMKEY1_[8] of ROMKEY1 correspond to bits 1-8 of the ROM key, ROMKEY2_[1] to ROMKEY2_[8] of ROMKEY2 correspond to bits 9-16 of the ROM key, and so on. ROMKEY15_[1] to ROMKEY15_[8] of ROMKEY15 correspond to bits 113-120 of the ROM key, and ROMKEY16_[1] to ROMKEY16_[8] of ROMKEY16 correspond to bits 121-128 of the ROM key. After the layout structure of the 16 ROMKEY digital standard cells is completed, these ROMKEY digital standard cells are placed together into the digital standard cell library used by the chip 100. Then, the placement and routing tool completes the placement and routing by calling these digital standard cells, forming the final full chip layout, such as... Figure 5 As shown.

[0063] In summary, the chip 100 of this embodiment of the invention implements the ROMKEY in the form of a digital standard unit. Through different combinations of internal sub-units, multi-bit keys can be flexibly implemented. By mixing it with other digital standard units in the chip's logic area, the ROMKEY unit becomes more difficult for attackers to discover. Simultaneously, the ROMKEY layout uses low-level routing, with the highest metal layer being only METAL1, increasing the difficulty for attackers to compromise the chip. The addition of a resistor identification layer to the ROMKEY layout design allows for direct verification of its correctness using tools, reducing the risks associated with human verification.

[0064] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0067] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0068] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0069] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A layout structure of a chip ROM KEY, characterized by, include: M first logic layout areas, each first logic layout area is used to implement a first logic function; N second logic layout areas, each used to implement a second logic function; Two edge layout areas are used to connect with other structures within the chip during chip wiring. Where M and N are both positive integers, M first logical layout areas and N second logical layout areas are arranged in a preset order and located between the two edge layout areas to implement an M+N bit ROM key; The first logic layout area includes: a first NWELL region, a first PPLUS region, a first NPLUS region, a first active region, a second active region, a first metal layer, a second metal layer, a third metal layer, a first interconnect, a second interconnect, a third interconnect, and a fourth interconnect, wherein, The first active area, the first metal layer, the first connection hole, and the second connection hole are all located in the first PPLUS region. The second active area, the third connection hole, the fourth connection hole, and the third metal layer are all located in the first NPLUS region. The first metal layer is connected to the first active area through the first connection hole, and the second metal layer is connected to the first active area through the second connection hole. The second metal layer is also connected to the second active area through the third connection hole and the fourth connection hole. The first metal layer is used to connect to the chip power supply, and the third metal layer is used to connect to the chip ground.

2. The layout structure of the chip ROM KEY according to claim 1, wherein, The first logical layout area also includes: A first resistor identification layer is located between the first connection hole and the second connection hole, and covers the first active area.

3. The layout structure of the chip ROM KEY according to claim 1, wherein, The second logic layout area includes: a second NWELL region, a second PPLUS region, a second NPLUS region, a third active region, a fourth active region, a fourth metal layer, a fifth metal layer, a sixth metal layer, a fifth interconnect, a sixth interconnect, a seventh interconnect, and an eighth interconnect, wherein, The third active region, the fourth metal layer, the fifth connection hole, and the sixth connection hole are all located in the second PPLUS region. The fourth active region, the seventh connection hole, the eighth connection hole, and the sixth metal layer are all located in the second NPLUS region. The fifth metal layer is connected to the third active region through the fifth and sixth connection holes. The fifth metal layer is also connected to the fourth active region through the seventh connection hole. The sixth metal layer is connected to the fourth active region through the eighth connection hole. The fourth metal layer is used to connect to the chip power supply, and the sixth metal layer is used to connect to the chip ground.

4. The layout structure of the chip ROM KEY according to claim 3, wherein, The second logic layout area also includes: The second resistor identification layer is located between the seventh and eighth connection holes and covers the fourth active area.

5. The layout structure of the chip ROM KEY according to claim 3, wherein, The edge layout area includes: a third NWELL region, a third PPLUS region, a third NPLUS region, a seventh metal layer, and an eighth metal layer, wherein the seventh metal layer is located in the third PPLUS region and is used to connect the chip power supply, and the eighth metal layer is located in the third NPLUS region and is used to connect the chip ground.

6. The layout structure of the chip ROMKEY as described in claim 4, characterized in that, The first active region extends along a first direction, and the second active region extends along a second direction. Both the first active region and the second active region are symmetrical with respect to the central axis of the first logic layout area, wherein the first direction is perpendicular to the second direction.

7. The layout structure of the chip ROMKEY as described in claim 6, characterized in that, The first metal layer is T-shaped and symmetrical to the central axis of the first logic layout area, and intersects with both sides of the first logic layout area. The two intersection points are used to connect the metal layers of other logic layout areas or edge layout areas for connecting the chip power supply. One end of the first metal layer along the first direction is connected to the end of the first active area near the first metal layer through the first connection hole. The second metal layer extends along the first direction, and one end of the second metal layer is connected to the end of the first active region away from the first metal layer through the second connection hole; The third metal layer extends along the second direction and intersects with both sides of the first logic layout area. The two intersection points are used to connect the metal layers of other logic layout areas or edge layout areas used to connect the ground of the chip.

8. The layout structure of the chip ROMKEY as described in claim 7, characterized in that, The first PPLUS region of the first logical layout area is mirror-symmetrical to the second NPLUS region of the second logical layout area, and the first NPLUS region of the first logical layout area is mirror-symmetrical to the second PPLUS region of the second logical layout area.

9. The layout structure of the chip ROM KEY according to claim 4, wherein, The distance between any logical layout area and its adjacent logical layout areas or edge layout areas is zero.

10. The layout structure of the chip ROM KEY according to claim 8, wherein, The first logic layout area, the second logic layout area, and the edge layout area have the same length, and the intersection of the metal layer used to connect the chip power supply with the corresponding layout area and the intersection of the metal layer used to connect the chip ground with the corresponding layout area are all collinear.

11. The layout structure of the chip ROM KEY according to claim 5, wherein, The two edge layout regions are axially symmetrical, and the seventh metal layer and the eighth metal layer both intersect one side of the connection logic layout region of the corresponding edge layout region.

12. The layout structure of a chip ROM KEY according to claim 5, wherein, The first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, the sixth metal layer, the seventh metal layer, and the eighth metal layer are all located in the METAL1 layer, and the first connecting hole, the second connecting hole, the third connecting hole, the fourth connecting hole, the fifth connecting hole, the sixth connecting hole, the seventh connecting hole, and the eighth connecting hole are all located in the contact layer.

13. A chip, characterized by include: A digital logic region, which is located in the central region of the chip; A ROM storage unit, wherein the ROM storage unit is located in the edge region of the chip; The layout structure of the chip ROMKEY as described in any one of claims 1-12, wherein the layout structure of the chip ROMKEY is located in the digital logic region.

14. The chip of claim 13, wherein, There are multiple layout structures for the chip ROMKEY, and these multiple layout structures are distributed across the digital logic area.

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