Dynamic random access memory structure and method of forming the same
By forming stress-adjusting grooves within the capacitor plates, the warping problem of dynamic random access memory is solved, the alignment of bit lines and channel regions is improved, and the reliability of the memory is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ICLEAGUE TECH CO LTD
- Filing Date
- 2022-01-28
- Publication Date
- 2026-07-10
AI Technical Summary
Existing dynamic random access memory (DRAM) suffers from warping, which can lead to open circuits and loose connections between bit lines and channel regions, reducing the reliability of the memory.
Stress-adjusting grooves are formed within the capacitor plates, located in the spacing region. These grooves cut off stress, reduce warping, ensure alignment of the bit lines with the channel region, and improve reliability.
The design of the stress-adjusting groove reduces the risk of open circuits and loose connections between the bit lines and the channel region, thereby improving the reliability of the memory.
Smart Images
Figure CN114334983B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access memory and a method for forming the same. Background Technology
[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.
[0003] Typically, dynamic random access memory (DRAM) consists of multiple memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through word lines and bit lines.
[0004] However, existing dynamic random access memory still has many problems. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a dynamic random access memory and a method for forming the same, so as to reduce the warpage of the dynamic random access memory and improve the reliability of the memory.
[0006] To solve the above-mentioned technical problems, the present invention provides a dynamic random access memory (DRAM), comprising: a substrate having a first surface and a second surface opposite to each other; the substrate including a plurality of independent storage regions, with a spacer region between adjacent storage regions; a plurality of independent active regions in each storage region, the active regions extending in a first direction, each active region including a plurality of independent channel regions arranged along the first direction; a plurality of word line gate structures located within the active regions of the storage regions, each word line gate structure adjacent to one channel region, the plurality of word line gate structures penetrating the active regions along a second direction perpendicular to the first direction; a dielectric layer located on the first surface and the surfaces of the plurality of word line gate structures; a plurality of capacitors located within the dielectric layer, each capacitor electrically connected to one channel region; capacitor plates located on the dielectric layer, the capacitor plates electrically connected to the capacitors; a plurality of stress-adjusting grooves located in the spacer region within the capacitor plates; and a plurality of bit lines located on the second surface, each bit line electrically connected to a plurality of channel regions in one active region.
[0007] Optionally, a plurality of the storage areas are arranged in an array along the first direction and the second direction, and a plurality of stress-adjusting grooves include a plurality of first grooves extending in the first direction.
[0008] Optionally, the stress-adjusting grooves may further include a number of second grooves extending in the second direction.
[0009] Optionally, among the plurality of first grooves and the plurality of second grooves, at least one first groove and one second groove are connected.
[0010] Optionally, a plurality of the storage areas are arranged in an array along the first and second directions, and a plurality of stress-adjusting grooves include a plurality of second grooves extending in the second direction.
[0011] Optionally, the bottom of the stress-adjusting groove exposes the surface of the dielectric layer.
[0012] Optionally, each bit line has a bit line projection on the second surface, and each bit line projection is within the range of an active region.
[0013] Optionally, it further includes: a capacitor plate connection layer located on the surface of the capacitor and the dielectric layer; the capacitor plate is located on the surface of the capacitor plate connection layer; the stress adjustment groove further extends into the capacitor plate connection layer.
[0014] Optionally, it may also include: a bonding dielectric layer located on the dielectric layer and the capacitor plate; and a carrier substrate bonded to the bonding dielectric layer.
[0015] Accordingly, the technical solution of the present invention also provides a method for forming a dynamic random access memory, comprising: providing a substrate having opposing first and second surfaces, the substrate including a plurality of mutually independent memory regions, adjacent memory regions having a spacer region, the memory regions having a plurality of mutually independent active regions extending in a first direction, the active regions including a plurality of mutually independent channel regions arranged along the first direction; forming a plurality of word line gate structures within the active regions in the memory regions, each word line gate structure being adjacent to one channel region, the plurality of word line gate structures being... The active region is penetrated along a second direction, which is perpendicular to the first direction. A dielectric layer is formed on the first surface and the surfaces of several word line gate structures. Several capacitors are formed within the dielectric layer, each capacitor being electrically connected to a channel region. Capacitor plates are formed on the dielectric layer, and the capacitor plates are electrically connected to the capacitors. Several stress-adjusting grooves are formed within the capacitor plates, and the stress-adjusting grooves are located on the spacing region. After forming several stress-adjusting grooves, several bit lines are formed on the second surface, each bit line being electrically connected to several channel regions within an active region.
[0016] Optionally, the method of forming a plurality of stress-adjusting grooves in the capacitor plate includes: forming a first mask layer on the surface of the capacitor plate, the first mask layer exposing the surface of the capacitor plate on the interval region; using the first mask layer as a mask, etching the capacitor plate until the surface of the dielectric layer is exposed.
[0017] Optionally, it further includes: forming a capacitor electrode connection layer on a plurality of capacitor surfaces and on the dielectric layer before forming capacitor electrodes on the dielectric layer; the method of forming capacitor electrodes on the dielectric layer includes: forming the capacitor electrodes on the surface of the capacitor electrode connection layer.
[0018] Optionally, the stress-adjusting groove also extends into the capacitor plate connection layer.
[0019] Optionally, the method for forming a plurality of capacitors within the dielectric layer includes: forming a plurality of capacitor openings within the dielectric layer, wherein the bottom of each capacitor opening exposes a channel region surface; forming a first electrode layer on the inner wall surface of the capacitor opening and the exposed channel region surface; forming a capacitor dielectric film on the surface of the first electrode layer and the dielectric layer; and forming a second electrode film on the surface of the capacitor dielectric film.
[0020] Optionally, after forming the capacitor plate, the method for forming a plurality of bit lines on the second surface includes: forming a bit line material layer on the second surface; forming a plurality of mutually independent bit line mask structures on the surface of the bit line material layer, wherein the projection of each bit line mask structure on the second surface is within the range of one active region; and etching the bit line material layer using the plurality of bit line mask structures as masks.
[0021] Optionally, before forming the plurality of bit lines, the method further includes: forming a bonding dielectric layer on the surface of the capacitor plate and in the plurality of stress-adjusting grooves, wherein the surface of the bonding dielectric layer is higher than the surface of the capacitor plate; providing a carrier substrate; bonding the carrier substrate to the bonding dielectric layer; and thinning the substrate from the second surface after the carrier substrate is bonded to the bonding dielectric layer.
[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0023] In the method for forming a dynamic random access memory (DRAM) according to the technical solution of the present invention, since several stress-adjusting grooves are formed in the capacitor plate before forming several bit lines on the second surface, and the stress-adjusting grooves are located on the interval region, it is possible to cut off one or all of the stress in the first direction and the second direction according to the warping of the memory structure without affecting the structure in and on the memory region, thereby achieving local stress adjustment. This reduces the warping degree of the second surface before forming the bit lines, and thus, when forming the photolithographic pattern layer for patterning the bit lines, the pattern of the photolithographic pattern layer is easily aligned with the pattern of the active region on the second surface. This reduces the risk of open circuits and loose connections between the bit lines and the channel region, and improves the reliability of the memory. Attached Figure Description
[0024] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a dynamic random access memory.
[0025] Figure 4 yes Figure 2 A schematic diagram of the overall warping of the structure;
[0026] Figures 5 to 17 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to an embodiment of the present invention. Detailed Implementation
[0027] As described in the background section, existing dynamic random access memories (DRAMs) still need improvement. This will now be analyzed and explained in conjunction with specific embodiments.
[0028] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a dynamic random access memory.
[0029] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 having a first surface 101 and a second surface 102 opposite to each other, the substrate 100 also having a plurality of mutually independent active regions S1, the active regions S1 extending in a first direction X, and the active regions S1 having a plurality of mutually independent channel regions S2 arranged along the first direction X.
[0030] Please continue to refer to this. Figure 1 In each active region S1, a plurality of word line grid structures S2 are formed. The plurality of word line grid structures 120 penetrate the active region S1 along a second direction (not shown in the figure). Each word line grid structure 120 is adjacent to one channel region S2.
[0031] The second direction is perpendicular to the first direction X. The word line gate structure 120 includes a word line gate 121 and a word line gate dielectric layer 122 located between the word line gate and the channel region S2.
[0032] Please continue to refer to this. Figure 1 A plurality of capacitors 130 are formed on the first surface 101, and each capacitor 130 is electrically connected to a channel region S2.
[0033] Please continue to refer to this. Figure 1 A carrier wafer 140 is provided, and after forming a plurality of capacitors 130, the carrier wafer 140 is bonded to the substrate 100, with the carrier wafer 140 facing the first surface 101.
[0034] Please refer to Figure 2 After bonding the carrier wafer 140 to the substrate 100, the substrate 100 is flipped, and the substrate 100 is thinned from the second surface 102.
[0035] Please refer to Figure 3 After thinning the substrate 100, a bit line material layer (not shown in the figure) is formed on the second surface 102; a bit line mask layer (not shown in the figure) is formed on the surface of the bit line material layer; the bit line material layer is etched using the bit line mask layer as a mask, and a plurality of bit lines 150 extending in the first direction X are formed on the second surface 102, the bit lines 150 being in contact with the surface of the channel region S2 of the second surface 102.
[0036] In the above method, before forming several bit lines 150 on the second surface 102, it is necessary to form structures such as the active region S1 and the word line gate structure 120 from the first surface 101. Furthermore, it is necessary to bond the carrier wafer 140 towards the first surface 101 and thin the substrate 100 from the second surface 102. Therefore, before forming the bit line patterning layer, due to the influence of factors such as local stress caused by each process step and the already formed structure, the substrate 100 and the structure formed before forming the bit line patterning layer exhibit overall warping (e.g., ...). Figure 4 As shown, the photolithography process for forming the bit line mask layer is difficult to align with the active region S1 pattern of the second surface 102 (i.e., the active region S1 surface exposed by the second surface 102). As a result, the formed bit line 150 is prone to disconnection from the channel region S2, causing partial or complete failure of the memory and poor memory reliability.
[0037] To solve the above-mentioned technical problems, the present invention provides a dynamic random access memory and a method for forming the same. A substrate is provided, having opposing first and second surfaces. The substrate includes a plurality of independent memory regions with spacing between adjacent memory regions. Each memory region has a plurality of independent active regions extending in a first direction. Each active region includes a plurality of independent channel regions arranged along the first direction. A plurality of word line gate structures are formed within the active regions of the memory regions, each word line gate structure being adjacent to one channel region. A grid structure extends through the active region along a second direction perpendicular to the first direction. A dielectric layer is formed on the first surface and the surfaces of several word grid structures. Several capacitors are formed within the dielectric layer, each electrically connected to a channel region. Capacitor plates are formed on the dielectric layer and electrically connected to the capacitors. Several stress-adjusting grooves are formed within the capacitor plates, located on the spacing region. After forming the stress-adjusting grooves, several bit lines are formed on the second surface, each electrically connected to several channel regions within an active region. Therefore, warpage of the dynamic random access memory can be reduced, improving memory reliability.
[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0039] Figures 5 to 17 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to an embodiment of the present invention.
[0040] Please refer to Figures 5 to 7 , Figure 6 yes Figure 5 A magnified view of a portion of region Z in the middle, and Figure 6 yes Figure 7 A top view of the structure along direction A. Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along the central direction A1-A2, with substrate 200 provided.
[0041] The substrate 200 has a first surface 201 and a second surface 202 facing each other.
[0042] The substrate 200 includes several independent storage regions S, with a spacing region G between adjacent storage regions S.
[0043] In this embodiment, several storage areas S are arranged in an array along a first direction X and a second direction Y, wherein the second direction Y is perpendicular to the first direction X.
[0044] Since several storage areas S are arranged in an array along mutually perpendicular first direction X and second direction Y, it is easier to form stress adjustment grooves with regular shapes, thus reducing the difficulty of the process.
[0045] The storage area S has several mutually independent active areas I, which extend in a first direction X, and each active area I includes several mutually independent channel areas II arranged along the first direction X.
[0046] The substrate 200 is made of semiconductor material.
[0047] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0048] In this embodiment, the method of forming the substrate 200 includes: providing an initial substrate (not shown in the figure); forming a plurality of mutually discrete first isolation masks (not shown in the figure) on the surface of the initial substrate, wherein the first isolation masks extend along a first direction X and the plurality of first isolation masks are arranged along a second direction Y; etching the initial substrate using the plurality of first isolation masks as masks to form a plurality of first isolation openings (not shown in the figure) in the initial substrate, wherein the first isolation openings extend along the first direction X and the plurality of first isolation openings are arranged along the second direction Y, and a first surface 201 exposes the first isolation openings.
[0049] Thus, a substrate 200 is formed, and adjacent active regions I are separated by the first isolation opening.
[0050] In this embodiment, adjacent active regions I have a first isolation structure 210.
[0051] The first isolation structure 210 is made of a dielectric material, which includes silicon oxide or a low-k (k less than 3.9) material. The purpose of using a low-k material is to further reduce parasitic capacitance through a material with a low dielectric constant.
[0052] The method of forming the first isolation structure 210 includes: forming an isolation structure material layer in a plurality of first isolation openings and the first surface 201, wherein the surface of the isolation structure material layer is higher than the first surface 201; planarizing the isolation structure material layer until the first surface 201 is exposed, thereby forming the first isolation structure 210 in the first isolation openings.
[0053] It should be noted that, for ease of understanding, Figure 5The first isolation structure 210 is not shown in the diagram.
[0054] Please refer to Figure 8 and Figure 9 , Figure 8 and Figure 6 The view orientation is consistent, and Figure 8 yes Figure 9 A top view of the structure along direction A. Figure 9 yes Figure 8 A cross-sectional structural diagram along direction B1-B2 shows that a plurality of word line gate structures 220 are formed in the active region I of the storage region S. Each word line gate structure 220 is adjacent to a channel region II, and the plurality of word line gate structures 220 penetrate the active region I along the second direction Y.
[0055] The word line gate structure 220 includes: a gate 221 and a gate dielectric layer 222 located between the gate 221 and the substrate 200.
[0056] In this embodiment, the method for forming a plurality of word line gate structures 220 includes: etching the first surface 201 and a plurality of first isolation structures 210 to form a plurality of word line gate openings (not shown in the figure) in the substrate 200 and the plurality of first isolation structures 210, wherein the channel region II is located between adjacent word line gate openings and is adjacent to at least one word line gate opening; forming a gate dielectric layer 222 on the inner wall surface of the word line gate opening; and forming a gate 221 in the word line gate opening after forming the gate dielectric layer 222.
[0057] In this embodiment, the gate 221 is a single layer. The material of the gate 221 is, for example, polycrystalline silicon or a metal material.
[0058] In other embodiments, the gate is a composite gate, comprising a first gate and a second gate located on top of the first gate, wherein the first and second gates are made of different materials. The first gate is made of a metallic material, and the second gate structure comprises polysilicon. Because the gate comprises a first gate and a second gate made of different materials, the threshold voltage of the word line gate structure can be adjusted by adjusting the volume ratio of the first and second gates to meet different device design requirements.
[0059] In this embodiment, the material of the gate dielectric layer 222 includes silicon oxide or a low-k material.
[0060] In other embodiments, the gate dielectric layer is made of a high-K (K greater than 3.9) material, which includes alumina or hafnium oxide.
[0061] In this embodiment, the top surface of the gate 221 is lower than the first surface 201, and after the word line gate structure 220 is formed, a covering dielectric layer 223 is formed in the word line gate opening, and the covering dielectric layer 223 is located on the top surface of the gate 221.
[0062] The function of the covering dielectric layer 223 is to protect the word line gate structure 220, reduce the damage to the word line gate structure 220 in subsequent processes, and ensure the insulation between the word line gate structure 220 and the capacitors formed later, so as to meet the circuit design requirements of the memory.
[0063] In this embodiment, the material of the covering dielectric layer 223 includes a dielectric material, which includes silicon oxide or a low-k material. The purpose of using a low-k material is to further reduce parasitic capacitance through a material with a low dielectric constant.
[0064] In this embodiment, after forming the covering dielectric layer 223, a second isolation structure 224 is formed between adjacent word line gate structures 220. The second isolation structure 224 is also located in the channel region II and is adjacent to one word line gate structure 220. Through the second isolation structure 224, each word line gate structure 220 can be adjacent to one channel region II on one side and spaced from one channel region II on the other side in the first direction X, so as to meet the device design requirements.
[0065] Since the second isolation structure 224 is formed before the stress adjustment groove is formed, the steps between forming the stress adjustment groove and forming the bit lines can be reduced, thereby enabling more accurate stress adjustment to better reduce warping.
[0066] In other embodiments, a second isolation structure may be formed after the substrate 200 is subsequently thinned from the second surface 202.
[0067] It should be noted that, for ease of understanding, Figure 7 The covering dielectric layer 223 is not shown in the figure.
[0068] It is necessary to understand that Figure 8 and Figure 9 The diagram only schematically illustrates one arrangement of the word line grid structures 220 and the second isolation structure 224. The word line grid structures 220 and the second isolation structure 224 can be arranged according to actual design requirements. The specific arrangement of the word line grid structures 220 and the second isolation structure 224 should not be construed as a feature that limits the scope of protection of this invention.
[0069] In this embodiment, after forming the covering dielectric layer 223 and before forming the subsequent dielectric layer, an ion implantation process is performed on the first surface 201 to implant dopant ions into the substrate 200, thereby forming a first doped region (not shown in the figure) exposed by the first surface 201 within the channel region II. The dopant ions in the first doped region include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions, and the P-type ions include boron ions, boron-fluorine ions, or indium ions.
[0070] Please refer to Figure 10 , Figure 10 and Figure 9 With the view orientation consistent, a dielectric layer 232 is formed on the surface of the first surface 201 and the surface of several word line gate structures 220.
[0071] In this embodiment, the dielectric layer 232 is made of a dielectric material, which includes silicon oxide or a low-k material.
[0072] The process for forming the dielectric layer 232 includes deposition process, spin coating process, etc.
[0073] Please continue to refer to this. Figure 10 A plurality of capacitors 231 are formed within the dielectric layer 232, and each capacitor 231 is electrically connected to a channel region II.
[0074] In this embodiment, each capacitor 231 is in contact with the surface of a first doped region in a channel region II.
[0075] In this embodiment, the capacitor 231 includes: a first electrode layer 231a, a second electrode layer 231c, and a capacitor dielectric layer 231b located between the first electrode layer 231a and the second electrode layer 231c.
[0076] In this embodiment, the capacitor dielectric layer 231b is U-shaped.
[0077] In other embodiments, the shape of the capacitor dielectric layer includes a planar shape, and correspondingly, the surface of the first electrode layer is flat and the surface of the second electrode layer is flat.
[0078] The material of the first electrode layer 231a includes: metal or metal nitride; the material of the second electrode layer 231c includes: metal or metal nitride; wherein the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; and the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.
[0079] The dielectric layer 231b of the capacitor is made of high-K materials such as titanium oxide, zirconium oxide, and hafnium oxide.
[0080] In this embodiment, the method for forming a plurality of capacitors 231 includes: etching the dielectric layer 232 to form a plurality of capacitor openings (not shown in the figure) within the dielectric layer 232, wherein the bottom of each capacitor opening exposes the surface of a first doped region in a channel region II; forming a first electrode layer 231a on the inner wall surface of the capacitor opening and the exposed surface of the channel region II; forming a capacitor dielectric film (not shown in the figure) on the surface of the first electrode layer and the surface of the dielectric layer 232, wherein the portion of the capacitor dielectric film located on the surface of the first electrode layer 231a is the capacitor dielectric layer 231b; and forming a second electrode film (not shown in the figure) on the surface of the capacitor dielectric film, wherein the portion of the second electrode film located on the surface of the capacitor dielectric layer 231b is the second electrode layer 231c.
[0081] In other embodiments, a lower dielectric layer is formed on the first surface and the surfaces of several word line gate structures; several capacitive conductive structure openings are formed within the lower dielectric layer, the bottom of which exposes the surface of a first doped region in a channel region; a capacitive conductive structure is formed within the openings, the bottom surface of which contacts the surface of the first doped region; an upper dielectric layer is formed on the lower dielectric layer and the surfaces of the capacitive conductive structures, the lower and upper dielectric layers constituting a dielectric layer; several capacitor openings (not shown in the figure) are formed within the upper dielectric layer, the bottom of which exposes the surface of the capacitive conductive structure; a first electrode layer is formed on the inner wall of the capacitor openings and the exposed surface of the capacitive conductive structure; a capacitive dielectric film is formed on the surface of the first electrode layer and the surface of the upper dielectric layer, wherein the portion of the capacitive dielectric film located on the surface of the first electrode layer is a capacitive dielectric layer; a second electrode film is formed on the surface of the capacitive dielectric film, wherein the portion of the second electrode film located on the surface of the capacitive dielectric layer is a second electrode layer. In this way, an electrical connection between the capacitor and the channel region is achieved through several capacitive conductive structures.
[0082] Please refer to Figure 11 , Figure 11 and Figure 10 With the view direction consistent, a capacitor plate 240 is formed on the dielectric layer 232, and the capacitor plate 240 is electrically connected to the capacitor 231.
[0083] In this embodiment, the material of the capacitor plate 240 includes tungsten.
[0084] In this embodiment, the process for forming the capacitor plate 240 includes deposition processes, etc.
[0085] In this embodiment, before forming the capacitor plates 240 on the dielectric layer 232, a capacitor plate connection layer 241 is formed on the surfaces of a plurality of capacitors 231 and on the dielectric layer 232. Furthermore, the method for forming the capacitor plates 240 on the dielectric layer 232 includes forming the capacitor plates 240 on the surface of the capacitor plate connection layer 241.
[0086] Specifically, in this embodiment, after forming a plurality of capacitors 231 and before forming capacitor plates 240 on the dielectric layer 232, a capacitor plate connection layer 241 is formed inside the capacitor opening and on the dielectric layer 232, and the surface of the capacitor plate connection layer 241 is higher than the surface of the second electrode film.
[0087] In this embodiment, the material of the capacitor plate connection layer 241 includes silicon.
[0088] In this embodiment, the process for forming the capacitor plate connection layer 241 includes a deposition process.
[0089] Please refer to Figures 12 to 14 , Figure 13 yes Figure 12 A magnified view of a portion of region Z in the middle, and Figure 13 yes Figure 14 A top view of the structure along direction A. Figure 14 yes Figure 13 A cross-sectional structural diagram along the direction B1-B2 shows that several stress-adjusting grooves 250 are formed within the capacitor plate 240, and the stress-adjusting grooves 250 are located on the interval region G.
[0090] Since several stress-adjusting grooves 250 are formed in the capacitor plate 240 before the subsequent formation of several bit lines on the second surface 202, and the stress-adjusting grooves 250 are located on the interval region G, it is possible to cut off one or all of the stress in the first direction X and the second direction Y according to the warping of the memory structure without affecting the structure in the memory region S. This achieves local stress adjustment, thereby reducing the warping degree of the second surface 202 before the formation of the bit lines. As a result, when forming the photolithographic pattern layer for patterning the bit lines, the pattern of the photolithographic pattern layer is easily aligned with the pattern of the active region I on the second surface 202. This reduces the risk of open circuits or loose connections between the bit lines and the channel region II, and improves the reliability of the memory.
[0091] The method for forming a plurality of stress-adjusting grooves in the capacitor plate includes: forming a first mask layer (not shown in the figure) on the surface of the capacitor plate 240, the first mask layer exposing the surface of the capacitor plate 240 on the spacer region G; using the first mask layer as a mask, etching the capacitor plate 240 until the surface of the dielectric layer 232 is exposed.
[0092] In this embodiment, during the etching of the capacitor plate 240 using the first mask layer as a mask, the capacitor plate connection layer 241 and the second electrode film are also etched using the first mask layer as a mask to expose the surface of the dielectric layer 232.
[0093] Correspondingly, the stress adjustment groove 250 also extends into the capacitor plate connection layer 241 and the second electrode film.
[0094] In this embodiment, the plurality of stress-adjusting grooves 250 include: a plurality of first grooves 250a extending in the first direction X.
[0095] The first groove 250a is used to cut off the stress in the second direction Y.
[0096] It should be understood that those skilled in the art can adjust the length of each first groove 250a in the first direction X according to the warping of the memory structure. Therefore, the length of each first groove 250a in the first direction X can be the same or different.
[0097] In this embodiment, the plurality of stress-adjusting grooves 250 further include: a plurality of second grooves 250b extending in the second direction Y.
[0098] In this embodiment, among the plurality of first grooves 250a and the plurality of second grooves 250b, at least one first groove 250a and one second groove 250b are connected.
[0099] In some other embodiments, the stress-adjusting grooves include: a plurality of first grooves or a plurality of second grooves.
[0100] In some other embodiments, the stress-adjusting grooves include: a plurality of first grooves and a plurality of second grooves that are not connected.
[0101] Please refer to Figure 15 , Figure 15 and Figure 14 With the same viewing direction, a bonding dielectric layer 260 is formed on the surface of the capacitor plate 240 and in a plurality of stress adjustment grooves 250, and the surface of the bonding dielectric layer 260 is higher than the surface of the capacitor plate 240.
[0102] Please continue to refer to this. Figure 15A carrier substrate 270 is provided, and the carrier substrate 270 is bonded to a bonding dielectric layer 260.
[0103] Next, please refer to Figure 16 and Figure 17 , Figure 16 yes Figure 17 A top view of the structure along direction C. Figure 17 yes Figure 16 A cross-sectional structural diagram along the C1-C2 direction, showing the substrate 200 being thinned from the second surface 202.
[0104] Specifically, in this embodiment, after the carrier substrate 270 is bonded to the bonding dielectric layer 260, the substrate 200 and the carrier substrate 270 are flipped, and the substrate 200 is thinned from the second surface 202 until the bottom surface of the first isolation structure 210 is exposed.
[0105] In this embodiment, the process of thinning the substrate 200 includes a chemical mechanical polishing process.
[0106] In this embodiment, after thinning the substrate 200 from the second surface 202, an ion implantation process is performed on the second surface 202 to implant dopant ions into the substrate 200, thereby forming a second doped region (not shown in the figure) exposed by the second surface 202 within the channel region II. The dopant ions in the second doped region include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions, and the P-type ions include boron ions, boron-fluorine ions, or indium ions.
[0107] Please continue to refer to this. Figure 16 and Figure 17 After forming several stress-adjusting grooves 250, several bit lines 280 are formed on the second surface 202, and each bit line 280 is electrically connected to several channel regions II in an active region I.
[0108] Specifically, in this embodiment, after the second doped region is formed, a plurality of bit lines 280 are formed on the second surface 202, and each bit line 280 is in contact with the surface of the second doped region of a plurality of channel regions II in an active region I.
[0109] Preferably, each bit line 280 has a bit line projection (not shown) on the second surface 202, and each bit line projection is within the range of one active region I. This further reduces the risk of open circuits or loose connections between the bit line 280 and the channel region II.
[0110] It should be noted that the bit line projection within the range of one active region I means that the bit line projection is within the area of one active region I surface exposed by the second surface 202.
[0111] In this embodiment, the method for forming bit line 280 includes: forming bit line dielectric layer 290 on the second surface 202; etching the bit line dielectric layer 290 to form a plurality of bit line openings (not shown in the figure) in the bit line dielectric layer 290, the bottom of the bit line openings exposing the surface of the second doped region; and forming bit line 280 in the bit line openings.
[0112] Accordingly, one embodiment of the present invention also provides a dynamic random access memory formed by the above method. Please refer to [link / reference needed]. Figure 16 and Figure 17 It includes: a substrate 200, the substrate 200 having opposing first surfaces 201 and second surfaces 202, the substrate 200 including a plurality of mutually independent storage regions S (e.g., Figure 11 As shown), adjacent storage areas S are separated by an interval area G (as shown). Figure 11 (As shown); the storage area S has several mutually independent active areas I, the active areas I extending in a first direction X, the active areas I including several mutually independent channel areas II arranged along the first direction X; several word line grid structures 220 located in the active areas I in the storage area S, each word line grid structure 220 adjacent to one channel area II, the several word line grid structures 220 penetrating the active areas I along a second direction Y, the second direction Y being perpendicular to the first direction X; located on the first surface 201 and several word... A dielectric layer 232 on the surface of the wire grid structure 220; a plurality of capacitors 231 located within the dielectric layer 232, each capacitor 231 being electrically connected to a channel region II; capacitor plates 240 located on the dielectric layer 232, the capacitor plates 240 being electrically connected to the capacitors 231; a plurality of stress-adjusting grooves 250 located within the capacitor plates 240 on the spacer region G; a plurality of bit lines 280 located on the second surface 202, each bit line 280 being electrically connected to a plurality of channel regions II within an active region I.
[0113] The substrate 200 is made of semiconductor material.
[0114] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0115] In this embodiment, several of the storage areas S are arranged in an array along the first direction X and the second direction Y.
[0116] In this embodiment, the channel region II has a first doped region (not shown in the figure) and a second doped region. The first doped region is exposed by a first surface 201, and the second doped region is exposed by a second surface 202. The dopant ions in the first doped region include N-type ions or P-type ions, and the dopant ions in the second doped region include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions, and the P-type ions include boron ions, boron-fluorine ions, or indium ions.
[0117] In this embodiment, each capacitor 231 is in contact with the surface of a first doped region in a channel region II, and each bit line 280 is in contact with the surface of a second doped region in a plurality of channel regions II in an active region I.
[0118] In other embodiments, the dynamic random access memory further includes: a plurality of bit line conductive structures (not shown in the figure) located between the second surface and a plurality of bit lines, wherein the surface of each bit line conductive structure is in contact with the surface of the bit line and the surface of the second doped region, thereby electrically connecting each bit line to a plurality of channel regions in an active region.
[0119] In this embodiment, adjacent active regions I are provided with a first isolation structure 210, the first surface 201 exposing the top surface of the first isolation structure 210, and the second surface 202 exposing the bottom surface of the first isolation structure 210. The material of the first isolation structure 210 includes a dielectric material, which includes silicon oxide or a low-k (k less than 3.9) material. The purpose of using a low-k material is to further reduce parasitic capacitance through a material with a low dielectric constant.
[0120] In this embodiment, the word line gate structure 220 includes: a gate 221 and a gate dielectric layer 222 located between the gate 221 and the substrate 200.
[0121] In this embodiment, the gate 221 is a single layer. The material of the gate 221 is, for example, polysilicon or a metal. In other embodiments, the gate is a composite gate, comprising a first gate and a second gate located on top of the first gate, and the first and second gates are made of different materials. The first gate is made of a metal, and the second gate structure is made of polysilicon. Because the gate comprises a first gate and a second gate made of different materials, the threshold voltage of the word line gate structure can be adjusted by adjusting the volume ratio of the first gate and the second gate to meet different device design requirements.
[0122] In this embodiment, the gate dielectric layer 222 is made of silicon oxide or a low-k material. In other embodiments, the gate dielectric layer is made of a high-k (K greater than 3.9) material, which includes aluminum oxide or hafnium oxide.
[0123] In this embodiment, the top surface of the gate 221 is lower than the first surface 201, and after the word line gate structure 220 is formed, a cover dielectric layer 223 is formed within the word line gate opening. The cover dielectric layer 223 is located on the top surface of the gate 221. The material of the cover dielectric layer 223 includes a dielectric material, which includes silicon oxide or a low-k material. The purpose of using a low-k material is to further reduce parasitic capacitance through a material with a low dielectric constant.
[0124] In this embodiment, the dynamic random access memory further includes a second isolation structure 224 located between adjacent word line gate structures 220, the first surface exposing the surface of the second isolation structure 224, the second isolation structure 224 also being located in the channel region II and adjacent to one word line gate structure 220.
[0125] It should be understood that the word line grid structures 220 and the second isolation structure 224 can be arranged according to actual design requirements. The specific arrangement of the word line grid structures 220 and the second isolation structure 224 should not be considered a feature that limits the scope of protection of this invention.
[0126] In other embodiments, the dynamic random access memory further includes: a second isolation structure located between adjacent word line gate structures, a second surface exposing the surface of the second isolation structure, the second isolation structure also being located in a channel region and adjacent to one word line gate structure.
[0127] In this embodiment, the dielectric layer 232 is made of a dielectric material, which includes silicon oxide or a low-k material. In other embodiments, the dielectric layer includes: a lower dielectric layer located on the first surface and the surfaces of a plurality of word line gate structures; an upper dielectric layer located on the surface of the lower dielectric layer; and a plurality of capacitors located within the upper dielectric layer. The dynamic random access memory further includes: a plurality of capacitive conductive structures located within the lower dielectric layer, the bottom surface of the capacitive conductive structures contacting the surface of the first doped region, and the top surface of the capacitive conductive structures contacting the capacitors.
[0128] In this embodiment, the capacitor 231 includes: a first electrode layer 231a, a second electrode layer 231c, and a capacitor dielectric layer 231b located between the first electrode layer 231a and the second electrode layer 231c.
[0129] In this embodiment, the capacitor dielectric layer 231b is U-shaped. In other embodiments, the capacitor dielectric layer may be planar, and correspondingly, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.
[0130] The first electrode layer 231a is made of a metal or a metal nitride; the second electrode layer 231c is made of a metal or a metal nitride; wherein the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; and the metal nitride includes one or more combinations of tantalum nitride and titanium nitride. The capacitor dielectric layer 231b is made of high-k materials such as titanium oxide, zirconium oxide, and hafnium oxide.
[0131] In this embodiment, the plurality of stress-adjusting grooves 250 include: a plurality of first grooves 250a extending in the first direction X.
[0132] The first groove 250a is used to cut off the stress in the second direction Y.
[0133] It should be understood that those skilled in the art can adjust the length of each first groove 250a in the first direction X according to the warping of the memory structure. Therefore, the length of each first groove 250a in the first direction X can be the same or different.
[0134] In this embodiment, the plurality of stress-adjusting grooves 250 further include: a plurality of second grooves 250b extending in the second direction Y.
[0135] In this embodiment, among the plurality of first grooves 250a and the plurality of second grooves 250b, at least one first groove 250a and one second groove 250b are connected.
[0136] In some other embodiments, the stress-adjusting grooves include: a plurality of first grooves or a plurality of second grooves.
[0137] In some other embodiments, the stress-adjusting grooves include: a plurality of first grooves and a plurality of second grooves that are not connected.
[0138] In this embodiment, the material of the capacitor plate 240 includes tungsten.
[0139] In this embodiment, the dynamic random access memory further includes a capacitor plate connection layer 241 located on the surfaces of a plurality of capacitors 231 and on the dielectric layer 232. Furthermore, the capacitor plates 240 are located on the surface of the capacitor plate connection layer 241. The material of the capacitor plate connection layer 241 includes silicon.
[0140] In this embodiment, the stress-adjusting groove 250 also extends into the capacitor plate connection layer 241. Specifically, the bottom of the stress-adjusting groove 250 exposes the surface of the dielectric layer 232.
[0141] Preferably, each bit line 280 has a bit line projection (not shown) on the second surface 202, and each bit line projection is within the range of one active region I. This further reduces the risk of open circuits or loose connections between the bit line 280 and the channel region II.
[0142] In this embodiment, the dynamic random access memory further includes a bit line dielectric layer 290 located on the second surface 202, and a plurality of bit lines 280 are located within the bit line dielectric layer 290.
[0143] In this embodiment, the dynamic random access memory further includes: a bonding dielectric layer 260 located on the dielectric layer 232 and the capacitor plate 240; and a carrier substrate 270 bonded to the bonding dielectric layer 260.
[0144] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A dynamic random access memory, characterized in that, include: A substrate having a first surface and a second surface opposite to each other, the substrate including a plurality of mutually independent storage regions, with a spacer region between adjacent storage regions, the storage regions having a plurality of mutually independent active regions, the active regions extending in a first direction, the active regions including a plurality of mutually independent channel regions arranged along the first direction; A plurality of word line gate structures are located within the active region of the storage area, each word line gate structure being adjacent to one channel region, the plurality of word line gate structures penetrating the active region along a second direction, the second direction being perpendicular to the first direction; The dielectric layer located on the first surface and the surfaces of several word line gate structures; Several capacitors are located within the dielectric layer, each capacitor being electrically connected to one channel region; A capacitor plate located on the dielectric layer, the capacitor plate being electrically connected to the capacitor; The capacitor plate has a plurality of stress-adjusting grooves located on the interval region, and the stress-adjusting grooves extend in at least one of the first direction and the second direction. Several bit lines are located on the second surface, and each bit line is electrically connected to several channel regions within an active region.
2. The dynamic random access memory as described in claim 1, characterized in that, The storage areas are arranged in an array along the first and second directions, and the stress-adjusting grooves include a number of first grooves extending in the first direction.
3. The dynamic random access memory as described in claim 2, characterized in that, The stress-adjusting grooves also include several second grooves extending in the second direction.
4. The dynamic random access memory as described in claim 3, characterized in that, Among the plurality of first grooves and the plurality of second grooves, at least one first groove and one second groove are connected.
5. The dynamic random access memory as described in claim 1, characterized in that, The storage areas are arranged in an array along the first and second directions, and the stress-adjusting grooves include a number of second grooves extending in the second direction.
6. The dynamic random access memory as described in claim 1, characterized in that, The bottom of the stress-adjusting groove exposes the surface of the dielectric layer.
7. The dynamic random access memory as described in claim 1, characterized in that, Each of the bit lines has a bit line projection on the second surface, and each bit line projection is within the range of an active region.
8. The dynamic random access memory as described in claim 1, characterized in that, Also includes: A capacitor electrode connection layer located on the capacitor surface and the dielectric layer; The capacitor plates are located on the surface of the capacitor plate connecting layer; The stress-adjusting groove also extends into the capacitor plate connection layer.
9. The dynamic random access memory as described in claim 1, characterized in that, Also includes: Bonded dielectric layer located on the dielectric layer and capacitor plate; The carrier substrate bonded to the bonding dielectric layer.
10. A method for forming a dynamic random access memory, characterized in that, include: A substrate is provided having a first surface and a second surface opposite to each other. The substrate includes a plurality of mutually independent storage regions with a spacer region between adjacent storage regions. Each storage region has a plurality of mutually independent active regions extending in a first direction. Each active region includes a plurality of mutually independent channel regions arranged along the first direction. A plurality of word line gate structures are formed in the active region of the storage area, each word line gate structure is adjacent to one channel region, and the plurality of word line gate structures penetrate the active region along a second direction, the second direction being perpendicular to the first direction; A dielectric layer is formed on the first surface and the surface of several word line gate structures; A plurality of capacitors are formed within the dielectric layer, and each capacitor is electrically connected to one channel region; A capacitor plate is formed on the dielectric layer, and the capacitor plate is electrically connected to the capacitor. A plurality of stress-adjusting grooves are formed within the capacitor plates, and the stress-adjusting grooves are located on the interval area; After forming several stress-adjusting grooves, several bit lines are formed on the second surface, and each bit line is electrically connected to several channel regions in an active region.
11. The method for forming a dynamic random access memory as described in claim 10, characterized in that, A method for forming a plurality of stress-adjusting grooves within the capacitor plate includes: forming a first mask layer on the surface of the capacitor plate, the first mask layer exposing the surface of the capacitor plate on the interval region; using the first mask layer as a mask, etching the capacitor plate until the surface of the dielectric layer is exposed.
12. The method for forming a dynamic random access memory as described in claim 10, characterized in that, Also includes: Before forming capacitor plates on the dielectric layer, a capacitor plate connection layer is formed on several capacitor surfaces and on the dielectric layer. A method for forming a capacitor plate on the dielectric layer includes forming the capacitor plate on the surface of the capacitor plate connection layer.
13. The method for forming a dynamic random access memory as described in claim 12, characterized in that, The stress-adjusting groove also extends into the capacitor plate connection layer.
14. The method for forming a dynamic random access memory as described in claim 10, characterized in that, A method for forming a plurality of capacitors within the dielectric layer includes: forming a plurality of capacitor openings within the dielectric layer, wherein the bottom of each capacitor opening exposes a channel region surface; forming a first electrode layer on the inner wall surface of the capacitor opening and the exposed channel region surface; forming a capacitor dielectric film on the first electrode layer and the surface of the dielectric layer; and forming a second electrode film on the surface of the capacitor dielectric film.
15. The method for forming a dynamic random access memory as described in claim 10, characterized in that, After forming the capacitor plate, the method for forming a plurality of bit lines on the second surface includes: forming a bit line material layer on the second surface; forming a plurality of mutually independent bit line mask structures on the surface of the bit line material layer, wherein the projection of each bit line mask structure on the second surface is within the range of one active region; and etching the bit line material layer using the plurality of bit line mask structures as masks.
16. The method for forming a dynamic random access memory as described in claim 10, characterized in that, Before forming the plurality of bit lines, the method further includes: forming a bonding dielectric layer on the surface of the capacitor plate and in the plurality of stress-adjusting grooves, wherein the surface of the bonding dielectric layer is higher than the surface of the capacitor plate; providing a carrier substrate; bonding the carrier substrate to the bonding dielectric layer; and after the carrier substrate is bonded to the bonding dielectric layer, thinning the substrate from the second side.