Three-dimensional memory, methods of making the same, and memory systems

Abstract

The application provides a three-dimensional memory, a manufacturing method thereof, and a storage system. The method comprises the following steps: providing a substrate, the substrate having a stack thereon, forming a step structure in a step region of the stack, the step structure having a first surface on a side away from the substrate, each first surface being part of a surface of a different sacrificial layer on a side away from the substrate, the sacrificial layer in which the first surface is located being a first sacrificial layer, and the sacrificial layer other than the first sacrificial layer being a second sacrificial layer; disposing an etching stop layer on the first surface; forming a pseudo-tunnel in the step region, the pseudo-tunnel sequentially penetrating through the substrate and the step structure to the etching stop layer; sequentially forming an insulating layer and a conductive support in each pseudo-tunnel; replacing the first sacrificial layer with a first control gate structure, replacing the second sacrificial layer with a second control gate structure, and electrically connecting the conductive support with the first control gate structure. The above method avoids the short circuit of the word line caused by the connection between the adjacent gates due to the high process difficulty.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a method for fabricating the same, and a memory system. Background Technology

[0002] With the increasing demand for integration and storage capacity, 3D NAND flash memory emerged. 3D NAND flash memory significantly saves silicon wafer area, reduces manufacturing costs, and increases storage capacity.

[0003] In 3D NAND memory structures, a stacked 3D NAND memory structure is achieved by vertically stacking multiple layers of data storage cells. However, other circuits, such as decoders, page buffers, and latches, are peripheral circuits formed using CMOS devices, whose fabrication processes cannot be integrated with 3D NAND devices. Currently, different processes are used to form the 3D NAND memory array and peripheral circuits, which are then bonded together using bonding technology. In the process of forming the 3D NAND memory array, a stack of alternating sacrificial and isolation layers is first formed. Then, the sacrificial layer is replaced with a control gate structure to obtain a gate stack structure. The gate stack structure includes a core region and a step region (SS region). A dummy channel hole (DCH) is formed in the step region, and a support structure is formed in the DCH to support the step region during sacrificial layer replacement. To achieve bonding between the 3D NAND memory array and peripheral circuits, the above process also requires forming contact holes (SSCTs) in the step region that communicate with different control gate structures, and filling the contact holes with conductive material.

[0004] However, as the number of layers in the 3D NAND memory structure increases, the etching difficulty of DCH and SSCT becomes increasingly greater. Furthermore, as the process window for DCH and SSCT becomes smaller, the process difficulty of forming SSCT also increases, which can easily lead to over-etching of SSCT in the SS region. This can cause adjacent DCHs to merge through SSCT, resulting in word line short circuits. Summary of the Invention

[0005] The main objective of this application is to provide a three-dimensional memory, its fabrication method, and a storage system to solve the problem of word line short circuits that easily occur in existing memory structures as the number of stacked layers increases.

[0006] To achieve the above objectives, according to one aspect of this application, a method for fabricating a three-dimensional memory is provided, comprising the following steps: providing a substrate, the substrate having a stack body, the stack body including multiple alternating layers of sacrificial layers and isolation layers stacked in a direction away from the substrate, the stack body including a step region, a step structure formed in the step region, the step structure having a first surface on the side away from the substrate, each first surface being a portion of the surface of a different sacrificial layer on the side away from the substrate, the sacrificial layer containing the first surface being a first sacrificial layer, and the sacrificial layers excluding the first sacrificial layer being second sacrificial layers; providing an etch stop layer on the first surface; forming pseudo-channel holes sequentially penetrating the substrate and the step structure to the etch stop layer in the step region, the pseudo-channel holes being correspondingly provided with the etch stop layer; sequentially forming an insulating layer and a conductive support portion in each pseudo-channel hole, replacing the first sacrificial layer with a first control gate structure, replacing the first sacrificial layer with a second control gate structure, and electrically connecting the conductive support portion to the first control gate structure, and isolating the conductive support portion from the second control gate structure through the insulating layer.

[0007] Furthermore, the stack also includes a core region, and the fabrication method further includes the following steps: forming a channel structure extending through the substrate in the core region.

[0008] Furthermore, an insulating layer and a conductive support portion are sequentially formed in each pseudo-channel hole, including: forming an insulating layer on the sidewall of each pseudo-channel hole; forming a conductive support portion in each pseudo-channel hole so that the conductive support portion contacts the etch barrier layer, and the insulating layer wraps around the outer periphery of the conductive support portion.

[0009] Furthermore, before forming a channel structure penetrating to the substrate in the core region, the fabrication method further includes: forming a channel hole penetrating to the substrate in the core region; forming a first high-K dielectric layer covering the sidewall of the channel hole; and after forming the channel structure penetrating to the substrate in the core region, the first high-K dielectric layer is located between the channel structure and the sidewall of the channel hole.

[0010] Furthermore, an etching barrier layer is provided on each of the first surfaces, including: covering each of the first surfaces with a first conductive material to form an etching barrier layer.

[0011] Further, replacing the first sacrificial layer with a first control gate structure, replacing the second sacrificial layer with a second control gate structure, and electrically connecting the conductive support to the first control gate structure, while isolating the conductive support from the second control gate structure through an insulating layer, includes: forming a gate gap extending through the substrate in the stack body so that the sacrificial layer has an exposed end face located in the gate gap; etching away the sacrificial layer along the exposed end face; filling the region where the sacrificial layer has been removed with a first gate material so that the first gate material is isolated from the conductive support through the insulating layer, the first gate material filling the region where the first sacrificial layer has been removed contacts an etch stop layer, and is electrically connected to the conductive support through the etch stop layer.

[0012] Further, replacing the first sacrificial layer with a first control gate structure, and replacing the first sacrificial layer with a second control gate structure, includes: forming a gate gap extending through the substrate in the stack, so that the sacrificial layer has an exposed end face located in the gate gap; etching away the sacrificial layer along the exposed end face to form a first channel corresponding to the removed first sacrificial layer and a second channel corresponding to the removed second sacrificial layer; forming a second high-k dielectric layer on the sidewalls of the first channel and the second channel, so that a portion of the second high-k dielectric layer covers the insulating layer; and filling the first channel and the second channel with a second gate material, so that the second high-k dielectric layer encapsulates the second gate material.

[0013] Further, to electrically connect the conductive support portion to the first control gate structure, and to isolate the conductive support portion from the second control gate structure through an insulating layer, the method includes: removing the etch stop layer to expose a portion of the second high-k dielectric layer; removing the exposed portion of the second high-k dielectric layer; filling the area where the etch stop layer and the second high-k dielectric layer are removed with a second conductive material, so that the second gate material located in the first channel contacts the second conductive material, the second gate material is electrically connected to the conductive support portion through the second conductive material, and the second high-k dielectric layer located in the second channel is isolated from the conductive support portion through an insulating layer.

[0014] Furthermore, the above manufacturing method also includes forming a common source electrode in the gate gap.

[0015] According to another aspect of this application, a three-dimensional memory is provided, including a substrate and a memory array located on the substrate. The memory array includes: a gate stack structure disposed on the substrate, the gate stack structure including multiple alternating control gate structures and isolation layers along a direction away from the substrate, the gate stack structure including a step region, the step region forming a step structure, the side of the step structure away from the substrate having a plurality of second surfaces, each second surface being a portion of the surface of a different control gate structure away from the substrate, the control gate structure where the second surface is located being a first control gate structure, and the control gate structure other than the first control gate structure being a second control gate structure, the step structure having a pseudo-channel via penetrating to the substrate; an etch stop layer disposed on each of the second surfaces, and the etch stop layer being formed of a conductive material; an insulating layer disposed in the pseudo-channel via; and a conductive support portion disposed in the pseudo-channel via, the conductive support portion being electrically connected to the first control gate structure and isolated from the second control gate structure through the insulating layer.

[0016] Furthermore, the gate stack structure also includes a core region, in which a channel hole extending through to the substrate is formed, and the three-dimensional memory also includes a channel structure disposed in the channel hole.

[0017] Furthermore, the control gate structure includes a gate, the first gate located in the first control gate structure is in contact with an etch barrier layer, and the first gate is electrically connected to the conductive support through the etch barrier layer. The three-dimensional memory also includes a first high-k dielectric layer, disposed between the channel structure and the sidewall of the channel hole, and the first high-k dielectric layer is in contact with the first gate.

[0018] Furthermore, the control gate structure includes a second high-k dielectric layer and a gate, a portion of the second high-k dielectric layer is located between the channel structure and the gate, and the first gate located in the first control gate structure is in contact with the etch barrier layer, and the first gate is electrically connected to the conductive support through the etch barrier layer.

[0019] Furthermore, the three-dimensional memory also includes a common source electrode, disposed in the gate stack structure and extending through the substrate.

[0020] According to another aspect of this application, a storage system is provided, including a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, the three-dimensional memory being prepared by the above-described method for manufacturing a three-dimensional memory, or the three-dimensional memory being the above-described type of three-dimensional memory.

[0021] Applying the technical solution of this application, a method for fabricating a three-dimensional memory is provided. The method first provides a substrate having a stack, the stack comprising multiple sacrificial layers and isolation layers alternately stacked along a direction away from the substrate. At least one end of the stack has a stepped structure, and the side of the stepped structure away from the substrate has multiple first surfaces. Each first surface is a portion of the surface of a different sacrificial layer away from the substrate, and the sacrificial layer containing the first surface is a first sacrificial layer. Then, by covering the first surfaces with an etch stop layer, pseudo-channel holes are formed sequentially from one side of the substrate to the etch stop layer. Subsequently, conductive support portions are formed in each pseudo-channel hole. The sacrificial layer is replaced with a control gate structure, and the first control gate structure after the first sacrificial layer replacement is electrically connected to the conductive support. Thus, the conductive support can not only lead out word lines from the back side, but also support the stack. Compared with the prior art, which has a smaller process window due to the separate formation of support structure and conductive channel, this application can combine the functions of support structure and conductive channel by forming the above-mentioned conductive support, thereby increasing the process window and reducing the process difficulty. This avoids word line short circuits caused by the connection between adjacent gates due to the greater process difficulty in the prior art, and improves device performance. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 A flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application is shown.

[0024] Figure 2 The illustration shows a cross-sectional view of a substrate with a stacked structure after providing a method for fabricating a three-dimensional memory according to an embodiment of this application.

[0025] Figure 3 It shows in Figure 2 A schematic diagram of the cross-sectional structure of the substrate after an etching barrier layer is covered on the first surface of the stack.

[0026] Figure 4 It shows the formation sequence through Figure 3 A schematic diagram of the cross-sectional structure of the substrate and the pseudo-channel hole of the etch barrier layer shown;

[0027] Figure 5 It shows in Figure 4 A schematic diagram of the cross-sectional structure of the substrate after an insulating layer is formed on the sidewall of the pseudo-channel hole;

[0028] Figure 6 It shows in Figure 5 The diagram shows a cross-sectional structure of the substrate after a conductive support portion is formed in the pseudo-channel hole to make the conductive support portion contact the etch barrier layer.

[0029] Figure 7 A method is shown Figure 6 The diagram shows a cross-sectional structure of the substrate after the sacrificial layer has been replaced with a control gate structure.

[0030] Figure 8 It shows Figure 7 The diagram shows a cross-sectional view of region A.

[0031] Figure 9 Another method was shown. Figure 7 The diagram shows a cross-sectional structure of the substrate after the sacrificial layer has been replaced with a control gate structure.

[0032] Figure 10 It shows Figure 9 A schematic diagram of the cross-sectional structure of region B shown;

[0033] Figure 11 It shows Figure 9 The diagram shows a cross-sectional view of region C.

[0034] Figure 12 It shows the removal Figure 9 A schematic diagram of the cross-sectional structure of the substrate after the etching barrier layer and part of the high-k dielectric layer is shown.

[0035] Figure 13 It shows Figure 12 A schematic diagram of the cross-sectional structure of region C' in the middle;

[0036] Figure 14 It shows in Figure 12 A schematic diagram of the cross-sectional structure of the substrate after the second conductive material is filled in the area where the etch barrier layer and high-k dielectric layer have been removed;

[0037] Figure 15 It shows Figure 14 A schematic diagram of the cross-sectional structure of region C'' in the middle;

[0038] Figure 16 A schematic diagram of the connection relationship of a storage system provided according to an embodiment of this application is shown;

[0039] Figure 17 A schematic diagram of the structure of a mobile phone provided according to an embodiment of this application is shown.

[0040] The above figures include the following reference numerals:

[0041] 10. Substrate; 20. Stacked structure; 200. Gate stacked structure; 210. Sacrificial layer; 220. Isolation layer; 230. Step region; 240. Control gate structure; 241. Second high-k dielectric layer; 242. Second gate material; 310. Channel structure; 311. Gate dielectric layer; 312. Channel layer; 313. Dielectric filling layer; 320. First high-k dielectric layer; 40. Interlayer dielectric layer; 50. Etch barrier layer; 60. Pseudo-channel via; 710. Insulating layer; 720. Conductive support; 80. Second conductive material; 90. Epitaxial layer; 1000. 3D memory; 2000. Controller; 3000. Host; 4000. Chip; 10000. Mobile phone; 20000. Storage system. Detailed Implementation

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] As described in the background section, as the number of layers in a 3D NAND memory structure increases, the etching difficulty of dummy channel holes (DCHs) and side contact holes (SSCTs) in stepped regions becomes increasingly difficult. Furthermore, as the process windows for DCHs and SSCTs become smaller, the process difficulty of forming SSCTs also increases, which can easily lead to over-etching of SSCTs in the SS region. This can cause adjacent DCHs to merge through SSCTs, resulting in word line short circuits.

[0046] The inventors of this application have researched the above-mentioned problems and proposed a method for manufacturing a three-dimensional memory, such as... Figure 1 The method includes the following steps: providing a substrate having a stack, the stack including multiple alternating layers of sacrificial layers and isolation layers stacked in a direction away from the substrate, the stack including a step region, forming a step structure in the step region, the step structure having a first surface on the side away from the substrate, each first surface being a portion of the surface of a different sacrificial layer on the side away from the substrate, the sacrificial layer containing the first surface being a first sacrificial layer, and the sacrificial layers excluding the first sacrificial layer being second sacrificial layers; providing an etch stop layer on the first surface; forming pseudo-channel holes sequentially penetrating the substrate and the step structure to the etch stop layer in the step region, the pseudo-channel holes being correspondingly provided with the etch stop layer; sequentially forming an insulating layer and a conductive support portion in each pseudo-channel hole, replacing the first sacrificial layer with a first control gate structure, replacing the first sacrificial layer with a second control gate structure, and electrically connecting the conductive support portion to the first control gate structure, and isolating the conductive support portion from the second control gate structure through the insulating layer.

[0047] By employing the fabrication method described in this application, a pseudo-channel via is formed, and a conductive support portion is directly formed within the pseudo-channel via. This allows the conductive support portion to not only lead out word lines from the back side but also to support the stack. Compared to the prior art, where the process window is smaller due to the separate formation of support structures and conductive channels, this application, by forming the conductive support portion, can combine the functions of support structures and conductive channels, thereby increasing the process window and reducing the process difficulty. This avoids word line short circuits caused by the connection between adjacent gates due to the greater process difficulty in the prior art, thus improving device performance.

[0048] On the other hand, in the prior art, as the number of stacked layers in the stack increases, the aperture of the pseudo-channel holes used to set the support structure gradually decreases. At the same time, contact holes are also required between adjacent pseudo-channels to set conductive channels. This results in a large distance between adjacent pseudo-channel holes near the bottom of the substrate, which makes it impossible for the support structure to provide effective support. This causes the sacrificial layer below to bend, which in turn affects the replacement of the sacrificial layer by the control gate structure. By forming the above-mentioned conductive support portion, this application can reduce the distance between adjacent pseudo-channel holes, thereby alleviating the bending of the sacrificial layer below caused by the inability of the support structure to provide effective support in the prior art, and thus reducing the impact on the replacement of the sacrificial layer by the control gate structure.

[0049] On the other hand, by forming the aforementioned conductive support portion, this application simplifies the process flow and reduces process costs compared to the prior art, which involves separately forming support structures and conductive channels. It also effectively saves space in the step area.

[0050] Exemplary embodiments of the method for fabricating a three-dimensional memory according to this application will now be described in more detail. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0051] First, a substrate 10 is provided, on which a stack 20 is provided. The stack 20 includes multiple sacrificial layers 210 and isolation layers 220 alternately stacked in a direction away from the substrate 10. The stack 20 includes a step region 230, in which a step structure is formed. The step structure has multiple first surfaces on the side away from the substrate 10. Each first surface is a portion of the surface of a different sacrificial layer 210 on the side away from the substrate 10. The sacrificial layer 210 containing the first surface is a first sacrificial layer, and the sacrificial layers other than the first sacrificial layers are second sacrificial layers. An etching barrier layer 50 is formed on the first surface. Figure 2 As shown.

[0052] The substrate 10 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0053] The sacrificial layer 210 and the isolation layer 220 can be formed using conventional deposition processes of the prior art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). Those skilled in the art can reasonably determine the number of layers in the sacrificial layer 210 and the isolation layer 220 according to actual needs. The material of the sacrificial layer 210 may include nitrides, such as silicon nitride, but is not limited thereto; the material of the isolation layer 220 may be an oxide, such as silicon dioxide, but is not limited thereto.

[0054] For example, the step of forming a step structure in the step region 230 includes: first coating a photoresist layer on the stack, and then forming a step structure with multiple step portions by repeatedly trimming the photoresist layer and etching adjacent sets of sacrificial layers 210 and isolation layers 220.

[0055] like Figure 2 As shown, the stepped structure has a plurality of first surfaces on the side away from the substrate 10, each first surface being a portion of the surface of a different sacrificial layer 210 on the side away from the substrate 10, and the stepped region 230 is used to form a pseudo-channel hole.

[0056] After the steps that form the above-mentioned stepped structure, as Figure 3 As shown, etch barrier layers 50 are correspondingly covered on each of the aforementioned first surfaces. These etch barrier layers 50 can be formed using conventional deposition and etching processes in the prior art. Specifically, etch barrier material is covered on the surface of the stack 20 so that at least part of the etch barrier material covers the first surface of the stepped structure. Then, the etch barrier material on the sidewalls of the stepped structure is removed, ultimately forming etch barrier layers 50 that at least partially cover the first surfaces. The process for removing the etch barrier material includes, but is not limited to, photolithography.

[0057] In an alternative embodiment, a first conductive material is coated on each of the first surfaces to form an etch barrier layer.

[0058] The region in the aforementioned stack 20, excluding the step region 230, is the core region, used to form the channel structure 310. Specifically, multiple channel holes extending to the substrate 10 are formed in the stack 20, and channel structures 310 are formed in the channel holes, such as... Figure 2 and Figure 3 As shown.

[0059] The step of forming the channel structure 310 in the channel hole may include: forming an epitaxial layer 90 at the bottom of the channel hole; sequentially depositing a gate dielectric layer 311 and a channel layer 312 on the sidewall of the channel hole, the channel layer 312 penetrating the gate dielectric layer 311 and contacting the epitaxial layer 90; filling the channel hole with a dielectric material to form a dielectric filling layer 313 located on the side of the channel layer 312 away from the gate dielectric layer 311, thereby obtaining a channel structure 310 penetrating to the substrate 10, such as... Figure 3 As shown. In other embodiments, the epitaxial layer may not be included, and the channel layer penetrates the functional layer and contacts the substrate.

[0060] In a preferred embodiment, the step of forming the gate dielectric layer 311 includes: sequentially forming a charge blocking layer, an electron trapping layer and a tunneling layer on the sidewall of the channel hole.

[0061] Those skilled in the art can rationally select the materials of each functional layer in the gate dielectric layer 311, the channel layer 312, and the filling dielectric material based on existing technology. For example, the charge blocking layer can be made of SiO2, the electron trapping layer can be made of SiN, the tunneling layer and the filling dielectric material can be made of SiO2, and the channel layer 312 can be made of polysilicon. Those skilled in the art can use conventional deposition processes in the prior art to form the above-mentioned channel structure 310, which will not be elaborated here.

[0062] In an optional embodiment, before forming the channel structure 310 extending through the substrate 10 in the core region, the above-described fabrication method of this application further includes: forming a first high-k dielectric layer 320 covering the sidewalls of the channel hole, such as... Figure 2 and 3 As shown.

[0063] The material of the first high-K dielectric layer 320 can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 and BaSrTiO.

[0064] After forming the aforementioned channel structure 310, pseudo-channel holes 60 are formed in the step region 230, sequentially penetrating the substrate 10 and the step structure to the etch barrier layer 50. Each pseudo-channel hole 60 corresponds one-to-one with an etch barrier layer 50. Figure 4 As shown.

[0065] Prior to the step of forming the aforementioned pseudo-channel via 60, the fabrication method of this application may include the following steps: forming an interlayer dielectric layer 40 on the substrate 10 covering the stack 20 and the etch barrier layer 50, such as... Figure 3 As shown. The interlayer dielectric layer 40 can be a conventional insulating dielectric material in the prior art, such as SiO2.

[0066] In one alternative embodiment, a mask layer can be covered on the side of the substrate 10 away from the stack 20, and the mask layer can be patterned to have cutout regions corresponding one-to-one with the etch stop layer 50. Then, the substrate 10 and the stack 20 are sequentially etched through the cutout regions until the etch stop layer 50 is reached, to obtain a pseudo-channel via 60 penetrating from the substrate 10 to the etch stop layer 50. Finally, the mask layer is removed. The mask layer can be formed using conventional mask materials in the prior art, such as SiN, and the patterning process of the mask layer can be a conventional photolithography process in the prior art, which will not be described in detail in this application.

[0067] After forming the aforementioned pseudo-channel vias 60 penetrating to the etch barrier layer 50, an insulating layer 710 and a conductive support portion 720 are sequentially formed in each pseudo-channel via 60. The first sacrificial layer is replaced with a first control gate structure, and the second sacrificial layer is replaced with a second control gate structure. The conductive support portion 720 is electrically connected to the first control gate structure and isolated from the second control gate structure by the insulating layer 710. Figures 5 to 15 As shown.

[0068] In one alternative embodiment, after forming pseudo-channel holes 60 extending to the etch barrier layer 50 in the step region 230, an insulating layer 710 is formed on the sidewall of each pseudo-channel hole 60, such as... Figure 5 As shown; conductive support portions 720 are formed in each pseudo-channel hole 60 so that the conductive support portions 720 are in contact with the etch barrier layer 50, and the insulating layer 710 surrounds the outer periphery of the conductive support portions 720, as shown. Figure 6 As shown.

[0069] In the above optional embodiments, insulating material can be deposited in the pseudo-channel via 60 using ALD (atomic layer deposition) or chemical vapor deposition (CVD) processes, such as... Figure 5 As shown, anisotropic etching is then used to remove a portion of the insulating layer 710 located at the bottom of the dummy channel hole 60 and in contact with the etching barrier layer 50. The anisotropic etching described above can be a conventional dry etching process in the prior art. Those skilled in the art can reasonably select the etching gas according to the specific type of insulating material, and this application does not make any specific limitations.

[0070] The insulating layer 710 can be formed using conventional insulating materials in the prior art, such as SiO2, and the conductive support portion 720 can be formed using conventional conductive materials in the prior art, such as tungsten metal. Those skilled in the art can make reasonable selections of the materials for the insulating layer 710 and the conductive support portion 720 based on the prior art.

[0071] To electrically connect the control gate structure 240 to the conductive support 720, in the first embodiment of this application, a first high-k dielectric layer 320 is covered on the sidewall of the channel hole. The first high-k dielectric layer 320 is located between the channel structure 310 and the sidewall of the channel hole, and the etching barrier layer 50 is formed by correspondingly covering each of the first surfaces of the stack 20 with a first conductive material. After forming the insulating layer 710 and the conductive support 720, a gate gap extending through the substrate 10 is formed in the stack 20 so that the sacrificial layer 210 has an exposed end face located in the gate gap; the sacrificial layer 210 is etched away along the exposed end face; the area where the sacrificial layer 210 is removed is filled with a first gate material so that the control gate structure 240 formed of the first gate material is isolated from the conductive support 720 through the insulating layer 710, and the control gate structure 240 contacts the etching barrier layer 50 and is electrically connected to the conductive support 720 through the etching barrier layer 50. Figure 7 As shown.

[0072] In the first embodiment described above, the first conductive material can be a conductor material or a semiconductor material with high hardness, thereby acting as an etching barrier while conducting electricity, such as polycrystalline silicon, tungsten metal, or molybdenum metal. Those skilled in the art can make reasonable selections of the type of first conductive material based on existing technology.

[0073] In the first embodiment described above, by forming the gate gap, the sacrificial layer 210 can have an exposed end face, thereby enabling wet etching of the sacrificial layer 210 using an etchant starting from the exposed end face, thus removing the sacrificial layer 210. Furthermore, by removing the sacrificial layer 210, a laterally extending channel can be formed at the location where the sacrificial layer 210 was removed, and then a first gate material can be deposited in the channel to form a control gate structure 240, such as... Figure 8 As shown. The above deposition process can be atomic layer deposition (ALD). The first gate material is typically a metal, and can be selected from one or more of metal nitrides, W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0074] In the second embodiment of this application, the sidewalls of the channel via directly cover the channel structure 310. After forming the insulating layer 710 and the conductive support portion 720, a gate gap extending through the substrate 10 is formed in the stack 20 so that the sacrificial layer 210 has an exposed end face located in the gate gap. The sacrificial layer 210 is removed by etching along the exposed end face to form a first channel corresponding to the removed first sacrificial layer and a second channel corresponding to the removed second sacrificial layer. A second high-k dielectric layer 241 is formed on the sidewalls of the first and second channels so that a portion of the second high-k dielectric layer 241 covers the insulating layer 710. Then, a second gate material 242 is filled into the first and second channels so that the second high-k dielectric layer 241 encapsulates the second gate material 242, as shown below. Figures 9 to 11 As shown, the control gate structure 240 in this embodiment is specifically as follows: Figure 10 As shown, the control gate structure 240 includes a second high-k dielectric layer 241 and a second gate material 242.

[0075] In the second embodiment described above, by forming the gate gap, the sacrificial layer 210 can have an exposed end face, thereby enabling wet etching of the sacrificial layer 210 using an etchant starting from the exposed end face, thus removing the sacrificial layer 210. Furthermore, by removing the sacrificial layer 210, a laterally extending channel, namely the first channel and the second channel, can be formed at the location where the sacrificial layer 210 was removed. Then, using the first channel and the second channel as deposition channels, a high-k dielectric material is first deposited on the inner surface to form a second high-k dielectric layer 241. Then, a second gate material 242 is deposited to obtain a gate layer. A portion of the second high-k dielectric layer 241 is disposed between the second gate material 242 and the channel structure 310 to form a gate dielectric layer, and another portion of the second high-k dielectric layer 241 is disposed between the second gate material 242 and the adjacent isolation layer 220, such as... Figure 10 As shown. The above deposition processes include, but are not limited to, atomic layer deposition (ALD).

[0076] The material of the second high-k dielectric layer 241 can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 and BaSrTiO; the second high-k dielectric layer 241 is usually a metal layer and can be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0077] In the second embodiment described above, to electrically connect the control gate structure 240 to the conductive support portion 720, the above-described electrical connection may include: removing the etch barrier layer 50 to expose a portion of the second high-k dielectric layer 241; removing the exposed portion of the second high-k dielectric layer 241, such as... Figure 12 and Figure 13 As shown; in the region where the etch barrier layer 50 and the second high-k dielectric layer 241 are removed, a second conductive material 80 is filled so that the second gate material 242 located in the first channel contacts the second conductive material 80. The second gate material 242 is electrically connected to the conductive support portion 720 through the second conductive material 80, and the second high-k dielectric layer 241 located in the second channel is isolated from the conductive support portion 720 through the insulating layer 710, as shown. Figure 14 and Figure 15 As shown.

[0078] In the second embodiment described above, the etch barrier layer 50 may only have an etch-blocking function. By removing the etch barrier layer 50 and filling it with the second conductive material 80, the gate layer composed of the second gate material 242 is electrically connected to the conductive support portion 720 through the second conductive material 80. Those skilled in the art can also rationally select the second conductive material 80 according to existing technology, such as tungsten metal or molybdenum metal.

[0079] In the second embodiment described above, wet etching can be performed along the exposed end face of the etch barrier layer 50 to remove the etch barrier layer 50, thereby forming a third channel. The second high-k dielectric layer 241 has an exposed surface exposed in the third channel. Then, wet etching is performed along the exposed surface of the second high-k dielectric layer 241 to expose the second gate material 242 covered by the second high-k dielectric layer 241. Figure 13 As shown. Those skilled in the art can rationally select the wet etching solvent based on the material type of the etching barrier layer 50 and the second high-k dielectric layer 241.

[0080] After forming the gate gap described above, a sidewall insulating layer can be deposited and formed in the gate gap, and then a common source electrode can be formed in the gate gap covered with the sidewall insulating layer. The common source electrode is isolated from the control gate structure 240 by the sidewall insulating layer, and the memory structure is connected to the common source electrode via the substrate 10.

[0081] According to another aspect of the present invention, a three-dimensional memory, such as Figure 7 , Figure 8 , Figure 14 as well as Figure 15 As shown, the device includes a substrate 10 and a memory array located on the substrate 10. The memory array includes a gate stack structure 200, an etch barrier layer 50, an insulating layer 710, and a conductive support portion 720.

[0082] The gate stack structure 200 is disposed on the substrate 10. The gate stack structure 200 includes multiple alternating control gate structures 240 and isolation layers 220 along the direction away from the substrate 10. The gate stack structure 200 includes a step region 230, which has a step structure. The side of the step structure away from the substrate 10 has multiple second surfaces. Each second surface is a part of the surface of a different control gate structure 240 away from the substrate 10. The control gate structure 240 where the second surface is located is a first control gate structure, and the control gate structure 240 other than the first control gate structure is a second control gate structure. The step structure has a pseudo-channel hole that penetrates to the substrate 10. An etch stop layer 50 is disposed on each second surface and is formed of a conductive material. An insulating layer 710 is disposed in the pseudo-channel hole. A conductive support portion 720 is disposed in the pseudo-channel hole and is electrically connected to the first control gate structure and isolated from the second control gate structure through the insulating layer 710.

[0083] In the three-dimensional memory described in this application, the conductive support portion can simultaneously support the stack and lead out word lines. Compared with the prior art, which has a smaller process window due to the separate formation of support structures and conductive channels, the conductive support portion of this application can serve as both a support structure and a conductive channel, thereby increasing the process window and reducing the process difficulty. This avoids word line short circuits caused by the connection between adjacent gates due to the greater process difficulty in the prior art, and improves device performance.

[0084] Furthermore, by replacing the support structure and conductive channel in the prior art with the aforementioned conductive support portion, this application can alleviate the bending of the lower sacrificial layer caused by the inability of the support structure to provide effective support in the prior art by reducing the distance between adjacent pseudo-channel holes, thereby reducing the impact on the replacement of the sacrificial layer in the control gate structure and further improving device performance.

[0085] The aforementioned gate stack structure 200 further includes a core region, in which a channel hole extending to the substrate 10 is formed. The aforementioned three-dimensional memory of this application may further include a channel structure 310 disposed within the channel hole, such as... Figure 7 , Figure 8 , Figure 14 as well as Figure 15 As shown.

[0086] In one embodiment of this application, the channel structure 310 includes: a gate dielectric layer 311 and a channel layer 312 sequentially disposed on the sidewall of the channel hole, and a dielectric filling layer 313 located on the side of the channel layer 312 away from the gate dielectric layer 311, such as Figure 7 , Figure 8 , Figure 14 as well as Figure 15 As shown.

[0087] For example, the gate dielectric layer 311 includes a charge blocking layer, an electron trapping layer and a tunneling layer sequentially stacked on the sidewall of the channel hole.

[0088] In one embodiment of this application, such as Figure 7 and Figure 8 As shown, the control gate structure includes a gate, and the first gate located in the first control gate structure is in contact with the etch barrier layer 50. The first gate is electrically connected to the conductive support portion 720 through the etch barrier layer 50. The three-dimensional memory also includes a first high-K dielectric layer 320, which is disposed between the channel structure 310 and the sidewall of the channel hole, and is in contact with the first gate.

[0089] In another embodiment of this application, such as Figure 14 and Figure 15 As shown, the control gate structure 240 includes a second high-k dielectric layer 241 and a gate formed by a second gate material 242. A portion of the second high-k dielectric layer 241 is located between the channel structure 310 and the gate, and the first gate located in the first control gate structure is in contact with the etch stop layer 50. The first gate is electrically connected to the conductive support portion 720 through the etch stop layer 50.

[0090] The three-dimensional memory described above in this application may also include a common source electrode, which is disposed in the gate stack structure 200 and extends through the substrate 10, and the memory structure forms a common source electrode connection through the substrate 10.

[0091] According to one embodiment of this application, a storage system 20000 is also provided. Figure 16 This is an internal block diagram of a storage system 20000 according to an embodiment of this application. For example... Figure 16 As shown, the storage system 20000 may include a three-dimensional memory 1000 and a controller 2000.

[0092] The three-dimensional memory 1000 may be the same as the three-dimensional memory described in any of the above embodiments, and this application will not repeat it further.

[0093] The controller 2000 can control the three-dimensional memory 1000 via channel CH, and the three-dimensional memory 1000 can perform operations based on the control of the controller 2000 in response to requests from the host 3000. The three-dimensional memory 1000 can receive commands CMD and addresses ADDR from the controller 2000 via channel CH and access the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 1000 can perform internal operations corresponding to commands on the region selected by the address.

[0094] In some implementations, the aforementioned storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0095] This application also provides an electronic device, including the memory structure described above.

[0096] In the above embodiments of this application, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, and power bank. In this embodiment, the memory structure of this application can be used in any electronic device because the memory structure of this application reduces leakage problems caused by defects and improves product reliability; therefore, the performance of electronic devices using this memory structure is further improved. Figure 17 A schematic diagram of the structure of a mobile phone according to an embodiment of this application is shown, such as... Figure 17 As shown, the mobile phone 10000 includes a chip 4000 employing the memory structure of this application.

[0097] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0098] 1. By forming the above-mentioned conductive support portion, this application can serve as both a support structure and a conductive channel, thereby increasing the process window and reducing the process difficulty. This avoids word line short circuits caused by the connection between adjacent gates due to the high process difficulty in the prior art, and improves device performance.

[0099] 2. By forming the above-mentioned conductive support portion, this application can reduce the distance between adjacent pseudo-channel holes, thereby alleviating the bending of the lower sacrificial layer caused by the inability of the support structure to effectively support in the prior art, and thus reducing the impact on the replacement sacrificial layer of the control gate structure.

[0100] 3. By forming the above-mentioned conductive support portion, this application simplifies the process flow and reduces the process cost compared with the prior art, which forms a support structure and a conductive channel separately, while effectively saving space in the step area.

[0101] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, Includes the following steps: A substrate is provided, the substrate having a stack comprising multiple alternating layers of sacrificial layers and isolation layers stacked in a direction away from the substrate, the stack comprising a step region forming a step structure in the step region, the step structure having a first surface on the side away from the substrate, each first surface being a portion of the surface of a different sacrificial layer on the side away from the substrate, the sacrificial layer containing the first surface being a first sacrificial layer, and the sacrificial layers excluding the first sacrificial layers being second sacrificial layers; An etching barrier layer is formed on the first surface; A pseudo-channel hole is formed in the step region, sequentially penetrating the substrate and the step structure to the etch barrier layer, and the pseudo-channel hole is disposed corresponding to the etch barrier layer; An insulating layer and a conductive support are sequentially formed in each of the pseudo-channel holes. The first sacrificial layer is replaced with a first control gate structure, and the second sacrificial layer is replaced with a second control gate structure. The conductive support is electrically connected to the first control gate structure, and the conductive support is isolated from the second control gate structure through the insulating layer.

2. The manufacturing method according to claim 1, characterized in that, The stacked body further includes a core region, and the manufacturing method further includes the following steps: A channel structure extending through the substrate is formed in the core region.

3. The manufacturing method according to claim 2, characterized in that, The step of sequentially forming an insulating layer and a conductive support portion in each of the dummy channel holes includes: The insulating layer is formed on the sidewall of each of the pseudo-channel holes; The conductive support portion is formed in each of the pseudo-channel holes so that the conductive support portion contacts the etch barrier layer, and the insulating layer wraps around the outer periphery of the conductive support portion.

4. The manufacturing method according to claim 3, characterized in that, Before forming the channel structure extending through the substrate in the core region, the fabrication method further includes: A channel hole extending through the substrate is formed in the core region; A first high-k dielectric layer is formed covering the sidewalls of the channel hole. After a channel structure extending through the substrate is formed in the core region, the first high-K dielectric layer is located between the channel structure and the sidewall of the channel hole.

5. The manufacturing method according to claim 4, characterized in that, The step of providing an etching barrier layer on each of the first surfaces includes: A first conductive material is coated on each of the first surfaces to form the etching barrier layer.

6. The manufacturing method according to claim 5, characterized in that, The step of replacing the first sacrificial layer with a first control gate structure, replacing the second sacrificial layer with a second control gate structure, and electrically connecting the conductive support portion to the first control gate structure, wherein the conductive support portion is isolated from the second control gate structure through the insulating layer, includes: A gate slot extending through the substrate is formed in the stack, so that the sacrificial layer has an exposed end face located in the gate slot; The sacrificial layer is removed by etching along the exposed end face; A first gate material is filled in the region where the sacrificial layer is removed, such that the first gate material is isolated from the conductive support through the insulating layer. The first gate material filled in the region where the first sacrificial layer is removed is in contact with the etch barrier layer and is electrically connected to the conductive support through the etch barrier layer.

7. The manufacturing method according to claim 3, characterized in that, The step of replacing the first sacrificial layer with a first control gate structure and replacing the second sacrificial layer with a second control gate structure includes: A gate slot extending through the substrate is formed in the stack, so that the sacrificial layer has an exposed end face located in the gate slot; The sacrificial layer is removed by etching along the exposed end face to form a first channel corresponding to the removed first sacrificial layer and a second channel corresponding to the removed second sacrificial layer; A second high-k dielectric layer is formed on the sidewalls of the first channel and the second channel, such that a portion of the second high-k dielectric layer covers the insulating layer; A second gate material is filled in the first channel and the second channel so that the second high-k dielectric layer encapsulates the second gate material.

8. The manufacturing method according to claim 7, characterized in that, The step of electrically connecting the conductive support portion to the first control gate structure, and isolating the conductive support portion from the second control gate structure through the insulating layer, includes: Remove the etching barrier layer to expose a portion of the second high-k dielectric layer; Remove the exposed portion of the second high-k dielectric layer; A second conductive material is filled in the area where the etch barrier layer and the second high-k dielectric layer are removed, so that the second gate material located in the first channel is in contact with the second conductive material, the second gate material is electrically connected to the conductive support through the second conductive material, and the second high-k dielectric layer located in the second channel is isolated from the conductive support through the insulating layer.

9. The manufacturing method according to claim 6 or 7, characterized in that, Also includes: A common source electrode is formed in the gate gap.

10. A three-dimensional memory, characterized in that, Includes a substrate and a memory array located on the substrate, the memory array comprising: A gate stack structure is disposed on the substrate. The gate stack structure includes multiple alternating control gate structures and isolation layers along a direction away from the substrate. The gate stack structure includes a step region, and the step region is formed with a step structure. The side of the step structure away from the substrate has a plurality of second surfaces. Each second surface is a portion of the surface of a different control gate structure away from the substrate. The control gate structure where the second surface is located is a first control gate structure. The control gate structures other than the first control gate structure are second control gate structures. The step structure has a pseudo-channel via penetrating to the substrate. An etching barrier layer is disposed on each of the second surfaces, and the etching barrier layer is formed of a conductive material; An insulating layer is disposed in the pseudo-channel hole; A conductive support portion is disposed in the pseudo-channel hole, and the conductive support portion is electrically connected to the first control gate structure and isolated from the second control gate structure through the insulating layer; The gate stack structure further includes a core region, in which a channel hole extending to the substrate is formed; the three-dimensional memory further includes: A channel structure is provided in the channel hole; The control gate structure includes a second high-k dielectric layer and a gate. A portion of the second high-k dielectric layer is located between the channel structure and the gate. The first gate located in the first control gate structure is in contact with the etch barrier layer. The first gate is electrically connected to the conductive support through the etch barrier layer.

11. The three-dimensional memory according to claim 10, characterized in that, The control gate structure includes a gate, a first gate located in the first control gate structure is in contact with the etch barrier layer, and the first gate is electrically connected to the conductive support through the etch barrier layer. The three-dimensional memory further includes: A first high-k dielectric layer is disposed between the channel structure and the sidewall of the channel hole, and the first high-k dielectric layer is in contact with the first gate.

12. The three-dimensional memory according to claim 10 or 11, characterized in that, The three-dimensional memory also includes: A common source electrode is disposed in the gate stack structure and extends through the substrate.

13. A storage system comprising a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, characterized in that... The three-dimensional memory is prepared by the method for manufacturing a three-dimensional memory according to any one of claims 1 to 9, or the three-dimensional memory is the three-dimensional memory according to any one of claims 10 to 12.

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