Active pixel sensor and method of manufacturing the same, display device

Abstract

The embodiment of the present disclosure provides an active pixel sensor and a preparation method thereof and a display device, wherein the active pixel sensor comprises: at least two first heavily doped regions, at least one second heavily doped region and at least two I-type regions arranged in the same layer, the first heavily doped regions and the second heavily doped region are arranged at intervals along a first direction and are alternately arranged, and each I-type region is located between adjacent first heavily doped regions and second heavily doped regions. The technical scheme of the embodiment of the present disclosure can effectively improve the distribution density of the I-type region in the PIN device, so that it is suitable for high-PPI display products.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an active pixel sensor, a manufacturing method thereof, and a display device. BACKGROUND

[0002] An active pixel sensor (APS) is basically integrated with a thin film transistor and a PIN device. In order to improve the photoelectric conversion rate of the PIN device, the PIN device is arranged laterally on one side of the driving substrate in a direction parallel to the driving substrate in the related technology, so as to reduce the absorption loss of the light signal by the heavily doped region. However, due to the low distribution density of the I-type region in the PIN device, the PIN device is not suitable for high PPI (Pixels Per Inch, sampling rate of image) display products. SUMMARY

[0003] Embodiments of the present disclosure provide an active pixel sensor, a manufacturing method thereof, and a display device, to solve or alleviate one or more technical problems in the prior art.

[0004] As an aspect of the embodiments of the present disclosure, an active pixel sensor is provided, comprising: a substrate and a PIN device arranged on one side of the substrate, the PIN device comprising:

[0005] at least two first heavily doped regions, at least one second heavily doped region, and at least two I-type regions arranged in the same layer, the first heavily doped regions and the second heavily doped region are arranged alternately and spaced apart along a first direction, and each I-type region is located between adjacent first heavily doped regions and second heavily doped regions.

[0006] In an embodiment, the first heavily doped regions, the second heavily doped region, and the I-type regions are arranged in rows, and the first direction is a direction in which the rows are located.

[0007] In an embodiment, the second heavily doped region comprises a first sub-doped region, and the at least two first heavily doped regions and the at least two I-type regions are arranged in pairs on opposite sides of the first sub-doped region; the end portions of the I-type regions arranged in pairs extend towards the first sub-doped region, so that the orthographic projection of the first sub-doped region on the substrate is within the orthographic projection of the I-type regions arranged in pairs on the substrate; the end portions of the first heavily doped regions arranged in pairs extend towards the first sub-doped region, so that the orthographic projection of the first sub-doped region on the substrate is within the orthographic projection of the first heavily doped regions arranged in pairs on the substrate, and the first direction is a direction perpendicular to the center of the first sub-doped region and pointing to the circumferential edge of the first sub-doped region.

[0008] In an embodiment, the at least two second heavily doped regions comprise a pair of second sub-doped regions, the pair of second sub-doped regions are respectively located on opposite sides of the first sub-doped region, and ends of the pair of second sub-doped regions both extend towards the first sub-doped region, so that a projection of the pair of second sub-doped regions on the substrate encloses a projection of the first sub-doped region on the substrate.

[0009] In an embodiment, the active pixel sensor further comprises:

[0010] A thin film transistor is located on the side of the substrate where the PIN device is arranged, an active layer of the thin film transistor is arranged in the same layer as the first heavily doped region, the second heavily doped region and the I-type region, and the first semiconductorized region and the second semiconductorized region of the active layer are of the same doping type as the first heavily doped region.

[0011] In an embodiment, the active pixel sensor further comprises:

[0012] An interlayer dielectric layer is located on a side of the first heavily doped region, the second heavily doped region and the I-type region away from the substrate, at least two first vias and at least one second via are formed in the interlayer dielectric layer, the at least two first vias correspond one-to-one to the at least two first heavily doped regions, and the at least one second via corresponds one-to-one to the at least one second heavily doped region; a projection of each first via on the substrate overlaps a projection of the corresponding first heavily doped region on the substrate, and a projection of each second via on the substrate overlaps a projection of the corresponding second heavily doped region on the substrate.

[0013] A first electrode and a second electrode are both located on a side of the interlayer dielectric layer away from the substrate, the first electrode is connected to the corresponding first heavily doped region through each first via, and the second electrode is connected to the corresponding second heavily doped region through each second via.

[0014] In an embodiment, a third via and a fourth via are formed in the interlayer dielectric layer, a projection of the third via on the substrate overlaps a projection of the first semiconductorized region on the substrate, and a projection of the fourth via on the substrate overlaps a projection of the second semiconductorized region on the substrate, and the active pixel sensor further comprises:

[0015] A third electrode and a fourth electrode are both located on a side of the interlayer dielectric layer away from the substrate, the third electrode is connected to the first semiconductorized region through the third via, and the fourth electrode is connected to the second semiconductorized region through the fourth via.

[0016] As another aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device comprising the active pixel sensor of any of the above embodiments.

[0017] As still another aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for manufacturing an active pixel sensor, comprising:

[0018] forming a p-Si layer on one side of the substrate;

[0019] forming at least two first heavily doped regions, at least one second heavily doped region and at least two I-type regions on the p-Si layer, the first heavily doped regions and the second heavily doped regions being arranged alternately and spaced apart along a first direction, and each I-type region being located between adjacent first heavily doped region and second heavily doped region.

[0020] In one embodiment, the forming of the p-Si layer on one side of the substrate comprises simultaneously forming the p-Si layer and the active layer on one side of the substrate.

[0021] In one embodiment, the forming of the at least two first heavily doped regions, the at least one second heavily doped region and the at least two I-type regions on the p-Si layer comprises:

[0022] simultaneously forming the first heavily doped regions on the p-Si layer and the spaced-apart first semiconductorization region and the second semiconductorization region on the active layer;

[0023] forming the second heavily doped regions on the p-Si layer;

[0024] forming the regions on the p-Si layer between the first heavily doped regions and the second heavily doped regions as the I-type regions.

[0025] In one embodiment, the method further comprises:

[0026] forming an interlayer dielectric layer on the side of the p-Si layer and the active layer away from the substrate;

[0027] forming at least two first vias, at least one second via, a third via and a fourth via on the interlayer dielectric layer; wherein the at least two first vias correspond one-to-one to the at least two first heavily doped regions, the at least one second via corresponds one-to-one to the at least one second heavily doped region, the orthographic projection of each first via on the substrate is located within the orthographic projection range of the corresponding first heavily doped region on the substrate, the orthographic projection of each second via on the substrate is located within the orthographic projection range of the corresponding second heavily doped region on the substrate, the orthographic projection of the third via on the substrate is located within the orthographic projection range of the first semiconductorization region on the substrate, and the orthographic projection of the fourth via on the substrate is located within the orthographic projection range of the second semiconductorization region on the substrate;

[0028] A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on the side of the interlayer dielectric layer away from the substrate, such that the first electrode passes through each first via and is connected to the corresponding first heavily doped region, the second electrode passes through each second via and is connected to the corresponding second heavily doped region, the third electrode passes through the third via and is connected to the first semiconductorized region, and the fourth electrode passes through the fourth via and is connected to the second semiconductorized region.

[0029] According to the above-described scheme of the embodiments of this disclosure, the PIN device has at least two first heavily doped regions, at least one second heavily doped region, and at least two type I regions disposed on the same layer. The first and second heavily doped regions are spaced apart and alternately arranged along a first direction, and each type I region is located between adjacent first and second heavily doped regions. This results in a configuration ratio of type I regions to first heavily doped regions greater than 1, and a configuration ratio of type I regions to second heavily doped regions equal to or greater than 1, thereby increasing the configuration ratio of type I regions in the PIN device. Furthermore, with the same number and size of type I regions, the PIN device of the embodiments of this disclosure can occupy less area. Based on this, the technical solution of the embodiments of this disclosure can effectively improve the distribution density of type I regions in the PIN device, making the PIN device suitable for high PPI products and further contributing to improving the integration density of the PIN device.

[0030] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0031] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this disclosure and should not be construed as limiting the scope of this disclosure.

[0032] Figure 1 This diagram shows a partial cross-sectional view of an active pixel sensor in the prior art.

[0033] Figure 2 A partial cross-sectional schematic diagram of an active pixel sensor according to an embodiment of the present disclosure is shown.

[0034] Figure 3 A top view schematic diagram of a PIN device according to a first embodiment of the present disclosure is shown.

[0035] Figure 4 A top view schematic diagram of a PIN device according to a second embodiment of the present disclosure is shown.

[0036] Figure 5 A top view schematic diagram of a PIN device according to a third embodiment of the present disclosure is shown. Detailed Implementation

[0037] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0038] like Figure 1 As shown, currently, the PIN device 120 in the active pixel sensor 100 is typically vertically disposed on one side of the driving substrate 110 in a direction perpendicular to the driving substrate 110. When an optical signal is incident from the light-incident side of the PIN device 120, part of the optical signal is absorbed by the heavily doped region 121 located on the light-incident side of the PIN device 120, causing optical signal loss and reducing the optical signal transmitted to the type I region 122, thereby reducing the photoelectric conversion efficiency of the PIN device 120.

[0039] To improve the photoelectric conversion efficiency of PIN devices, please refer to... Figure 1 The related technology arranges the PIN device 120 laterally on one side of the driving substrate 110 in a direction parallel to the driving substrate 110 to reduce the absorption loss of optical signals by the heavily doped region. However, due to the low arrangement density of the I-type region 122 in the PIN device 120, the PIN device 120 is not suitable for high PPI products.

[0040] To address the aforementioned problems, this disclosure provides an active pixel sensor. The following description, in conjunction with the accompanying drawings, will illustrate this solution.

[0041] Figure 2 A partial cross-sectional schematic diagram of an active pixel sensor according to an embodiment of the present disclosure is shown. Figure 3 A top view schematic diagram of a PIN device according to a first embodiment of the present disclosure is shown. Figure 4 A top view schematic diagram of a PIN device according to a second embodiment of the present disclosure is shown. For ease of explanation, the direction perpendicular to the substrate is referred to as vertical, and the direction parallel to the substrate is referred to as horizontal.

[0042] like Figure 2 to Figure 4 As shown, the active pixel sensor 200 may include a substrate 210 and a PIN device 220 disposed on one side of the substrate 210. The substrate 210 may be made of a material such as glass.

[0043] The PIN device 220 may include at least two first heavily doped regions 221, at least one second heavily doped region 222, and at least two type I regions 223 disposed on the same layer. The first heavily doped regions 221 and the second heavily doped regions 222 are spaced apart and alternately arranged along a first direction, and each type I region 223 is located between adjacent first heavily doped regions 221 and second heavily doped regions 222.

[0044] For example, the doping type of the first heavily doped region 221 is opposite to that of the second heavily doped region 222. For instance, the first heavily doped region 221 can be a P-type region, and the second heavily doped region 222 can be an N-type region; or, the first heavily doped region 221 can be an N-type region, and the second heavily doped region 222 can be a P-type region. In one example, such as Figure 3 and Figure 4 As shown, the first heavily doped region 221 is an N-type region, and the second heavily doped region 222 is a P-type region. Therefore, in the lateral direction, the arrangement of the PIN devices 220 along the first direction is NIPIN. In another example, the first heavily doped region 221 is a P-type region, and the second heavily doped region 222 is an N-type region. Therefore, in the lateral direction, the arrangement of the PIN devices 220 along the first direction is PINIP. It is understood that the doping type of the first heavily doped region 221 and the doping type of the second heavily doped region 222 can be selected and adjusted according to actual needs, and this disclosure does not limit their doping types.

[0045] Furthermore, the number of the first doped region 221, the second doped region 222, and the I-type region 223 can be selected and adjusted according to actual needs, as long as the above arrangement rule is met. For example, taking the first doped region 221 as an N-type region and the second doped region 222 as a P-type region as an example, if the number of the first doped region 221 and the number of the second doped region 222 are both two, and the number of the I-type region 223 is three, then the arrangement rule of the PIN device 220 in the horizontal direction is NIPINIP; if the number of the first doped region 221 is three, the number of the second doped region 222 is two, and the number of the I-type region 223 is four, then the arrangement rule of the PIN device 220 in the horizontal direction is NIPINIPIN.

[0046] In related technologies, the number of first-doped regions, second-doped regions, and I-type regions in lateral PIN devices is one each. That is, one I-type region requires one first-doped region and one second-doped region, with a ratio of 1:1 between the I-type region and the first and second-doped regions. Furthermore, these technologies increase the number of I-type regions by increasing the number of PIN devices, which occupies a larger area.

[0047] In the above scheme, the PIN device 220 has at least two first heavily doped regions 221, at least one second heavily doped region 222, and at least two I-type regions 223 arranged in the same layer. The first heavily doped regions 221 and the second heavily doped regions 222 are spaced apart and alternately arranged along a first direction, and each I-type region 223 is located between adjacent first heavily doped regions 221 and second heavily doped regions 222. This results in a configuration ratio of I-type regions 223 to first heavily doped regions 221 greater than 1, and a configuration ratio of I-type regions 223 to second heavily doped regions 222 equal to or greater than 1, thus increasing the configuration ratio of I-type regions 223 in the PIN device 220. Furthermore, with the same number and size of I-type regions 223, the PIN device 220 of this embodiment can occupy less area. Based on this, the technical solution of this embodiment can effectively improve the distribution density of I-type regions 223 in the PIN device 220, making the PIN device 220 suitable for high PPI products and further contributing to improving the integration density of the PIN device 220.

[0048] In one application scenario, when the PIN device 220 of this embodiment is applied to a display product, the number and size of the first heavily doped region 221, the second heavily doped region 222 and the I-type region 223 can be adjusted and selected according to the pixel density in the display product in order to flexibly adapt to pixels with different densities.

[0049] In the aforementioned PIN device 220, the substrate 210 can be made of materials such as glass. A buffer layer 230 can be provided between the substrate 210 and the PIN device 220, with the first heavily doped region 221, the second heavily doped region 222, and the I-type region 223 located on the side of the buffer layer 230 away from the substrate 210.

[0050] In one implementation, such as Figure 2 and Figure 3 As shown, the first heavily doped region 221, the second heavily doped region 222, and the type I region 223 are arranged in a row, with the first direction being the direction of the row. Figure 3 The direction in which the row is located, i.e., the first direction, is horizontal. It should be noted that the direction in which the row is located in this article is not limited to the horizontal direction. The direction in which the row is located can be horizontal or vertical. The term "row" in this article is only used to indicate that the first doped region 221, the second doped region 222, and the type I region 223 are arranged in the same direction.

[0051] In one example, such as Figure 3As shown, the first heavily doped region 221, the second heavily doped region 222, and the type I region 223 are arranged in a row along the width direction of the type I region 223. The orthographic projections of the first heavily doped region 221, the second heavily doped region 222, and the type I region 223 onto the substrate 210 are all rectangular and do not overlap. That is, in the lateral direction, the first heavily doped region 221, the second heavily doped region 222, and the type I region 223 do not overlap. The lengths of the orthographic projections of the first heavily doped region 221, the second heavily doped region 222, and the type I region 223 onto the substrate 210 are equal, and the width of the orthographic projection of the first heavily doped region 221 and the second heavily doped region 222 onto the substrate 210 is greater than the width of the orthographic projection of the type I region 223 onto the substrate 210. For example, the width of the orthographic projection of the first heavily doped region 221 and the second heavily doped region 222 onto the substrate 210 ranges from 1.8 μm to 2.2 μm (inclusive), such as any value among 1.8 μm, 1.9 μm, 2.0 μm, 2.1 μm, and 2.2 μm. The width of the orthographic projection of the type I region 223 onto the substrate 210 ranges from 0.8 μm to 1.2 μm (inclusive), such as any value among 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, and 1.2 μm. It is understood that the shapes of the orthographic projections of the first heavily doped region 221, the second heavily doped region 222, and the type I region 223 onto the substrate 210 can be selected and adjusted according to actual needs, and this disclosure does not limit them.

[0052] In one implementation, such as Figure 4 and Figure 5 As shown, the second heavily doped region 222 includes a first sub-doped region 222A. At least two first heavily doped regions 221 and at least two type I regions 223 are arranged in pairs on opposite sides of the first sub-doped region 222A. The ends of the paired type I regions 223 extend toward the first sub-doped region 222A, such that the orthographic projection of the first sub-doped region 222A on the substrate is within the range of the orthographic projection of the paired type I regions 223 on the substrate. The ends of the paired first heavily doped regions 221 extend toward the first sub-doped region 222A, such that the orthographic projection of the first sub-doped region 222A on the substrate is within the range of the orthographic projection of the paired first heavily doped regions 221 on the substrate. The first direction is a direction perpendicular from the center of the first sub-doped region 222A to the peripheral edge of the first sub-doped region 222A.

[0053] In this way, the two pairs of I-type regions 223 and the pair of first heavily doped regions 221 in the vertical PIN device 220 form a surrounding structure, which makes it easy to flexibly adjust the number and size of each region in the PIN device 220 along the first direction to suit pixels of different densities.

[0054] In one implementation, such as Figure 4 and Figure 5 As shown, the second heavily doped region 222 includes at least two second sub-doped regions 222B. The at least two second sub-doped regions 222B are arranged in pairs on opposite sides of the first sub-doped region 222A. The ends of the paired second sub-doped regions 222B extend towards the first sub-doped region 222A, such that the orthographic projection of the paired second sub-doped regions 222B onto the substrate 210 surrounds the orthographic projection of the first sub-doped region 222A onto the substrate 210. Thus, in the vertical direction, the paired first heavily doped region 221, the paired second sub-doped regions 222B, and the paired I-type regions 223 of the PIN device 220 all form a surrounding structure, and the paired first heavily doped region 221 and the paired second sub-doped regions 222B are spaced apart and alternately arranged along a first direction. The paired I-type regions 223 are located between the first sub-doped region 222B and the paired first heavily doped region 221, or between the paired first heavily doped region 221 and the paired second sub-doped region 222B.

[0055] In one embodiment, the active pixel sensor 200 may further include a thin-film transistor 240, which is located on the side of the substrate 210 where the PIN device 220 is disposed. The active layer 241 of the thin-film transistor 240 is disposed on the same layer as the first heavily doped region 221, the second heavily doped region 222 and the type I region 223. The active layer 241 includes a channel region 241A and a first semiconductorized region 241B and a second semiconductorized region 241C located on opposite sides of the channel region 241A. The doping type of the first semiconductorized region 241B and the second semiconductorized region 241C is the same as the doping type of the first heavily doped region 221.

[0056] For example, such as Figure 2As shown, the active layer 241 of the thin-film transistor 240 and the first heavily doped region 221, the second heavily doped region 222, and the I-type region 223 of the PIN device 220 are all located on the side of the buffer layer 230 facing away from the substrate 210. By setting the active layer 241 of the thin-film transistor 240 in the same layer as the first heavily doped region 221, the second heavily doped region 222, and the I-type region 223, it is convenient to integrate some fabrication processes of the active layer 241 with some fabrication processes of the PIN device 220, thereby saving fabrication steps and improving fabrication efficiency. Furthermore, the doping type of the first semiconductorized region 241B and the second semiconductorized region 241C of the active layer 241 is the same as the doping type of the first heavily doped region 221, so that the ion implantation and heavy doping processes of the first semiconductorized region 241B, the second semiconductorized region 241C, and the first heavily doped region 221 can be performed simultaneously, which also helps to save fabrication steps and improve fabrication efficiency.

[0057] In one implementation, such as Figure 2 As shown, the thin-film transistor 240 may further include a gate insulating layer 242 and a gate 243. The gate insulating layer 242 is located on the side of the active layer 241, the first heavily doped region 221, the second heavily doped region 222, and the I-type region 223 that is away from the substrate 210. The gate 243 is located on the side of the gate insulating layer 242 that is away from the substrate 210, and the orthogonal projection of the gate 243 on the substrate 210 overlaps with the orthogonal projection of the active layer 241 on the substrate 210 and is located within the orthogonal projection range of the active layer 241 on the substrate 210.

[0058] The active pixel sensor 200 may also include an interlayer dielectric layer 250, a first electrode 261, and a second electrode 262.

[0059] An interlayer dielectric layer 250 is located on the side of the gate 243 and the gate insulating layer 242 facing away from the substrate 210. At least two first vias 251 and at least one second via 252 are formed on the interlayer dielectric layer 250. The at least two first vias 251 correspond one-to-one with at least two first heavily doped regions 221, and the at least one second via 252 corresponds one-to-one with at least one second heavily doped region 222. Each first via 251 penetrates the gate insulating layer 242 and its orthographic projection on the substrate 210 overlaps with the orthographic projection of the corresponding first heavily doped region 221 on the substrate 210, so that the corresponding first heavily doped region 221 is exposed from the first via 251. Each second via 252 penetrates the gate insulating layer 242 and its orthographic projection on the substrate 210 overlaps with the orthographic projection of the corresponding second heavily doped region 222 on the substrate 210, so that the corresponding second heavily doped region 222 is exposed from the second via 252.

[0060] The first electrode 261 and the second electrode 262 are both located on the side of the interlayer dielectric layer 250 away from the substrate 210. The first electrode 261 passes through each first via 251 and is connected to the corresponding first heavily doped region 221. The second electrode 262 passes through each second via 252 and is connected to the corresponding second heavily doped region 222.

[0061] In one embodiment, a third via 253 and a fourth via 254 are formed on the interlayer dielectric layer 250. The third via 253 penetrates the gate insulating layer 242, and its orthographic projection on the substrate 210 overlaps with the orthographic projection of the first semiconductorized region 241B on the substrate 210, thereby exposing the first semiconductorized region 241B. The fourth via 254 penetrates the gate insulating layer 242, and its orthographic projection on the substrate 210 overlaps with the orthographic projection of the second semiconductorized region 241C on the substrate 210, thereby exposing the second semiconductorized region 241C.

[0062] The active pixel sensor 200 also includes a third electrode 263 and a fourth electrode 264. Both the third electrode 263 and the fourth electrode 264 are located on the side of the interlayer dielectric layer 250 away from the substrate 210. The third electrode 263 is connected to the first semiconductorized region 241B through a third via 253, and the fourth electrode 264 is connected to the second semiconductorized region 241C through a fourth via 254.

[0063] The first heavily doped region 221, the second heavily doped region 222, the I-type region 223, and the active layer 240 are made of polycrystalline silicon (p-Si). Related technologies typically use amorphous silicon (a-Si) as the material for PIN devices and the active layer, resulting in higher contact resistance between the electrodes and the PIN device and the active layer. The above solution uses polycrystalline silicon as the material for the first heavily doped region 221, the second heavily doped region 222, the first semiconductorized region 241B, and the second semiconductorized region 241C, which effectively reduces the contact resistance between the first electrode 261 and the first heavily doped region 221, between the second electrode 262 and the second semiconductorized region 241C, between the third electrode 263 and the first semiconductorized region 241B, and between the fourth electrode 264 and the second semiconductorized region 241C. Furthermore, compared to amorphous silicon, using polycrystalline silicon as the material for the PIN device 220 is beneficial for achieving higher ion mobility, thereby improving the photoelectric conversion efficiency of the PIN device 220. Integrating the active pixel sensor 200 with the PIN device 220 and the thin-film transistor 240 further helps to improve the signal-to-noise ratio and responsivity of the active pixel sensor 200.

[0064] This disclosure also provides a display device, which may include the active pixel sensor 200 of any of the above embodiments. Exemplarily, the display device may be a display panel or a display product having a display panel, such as a smartphone, tablet computer, display screen, smart wearable device, electronic photo frame, etc.

[0065] Other configurations of the active pixel sensor 200 and display device in the above embodiments can be adopted from various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0066] This disclosure also provides a method for fabricating an active pixel sensor 200, which can be referred to in conjunction with the above. Figure 2 to Figure 4 The preparation method may include:

[0067] Step S510: A buffer layer 230 and a p-Si layer are sequentially formed on one side of the substrate 210.

[0068] Exemplarily, the steps for forming the p-Si layer include: forming an a-Si film on the side of the buffer layer 230 facing away from the substrate 210 using a deposition process; converting the a-Si film into a p-Si film using excimer laser annealing technology; and patterning the p-Si film to form the p-Si layer. Preferably, patterning the p-Si film to form the p-Si layer may include: patterning the p-Si film while simultaneously forming the p-Si layer and the active layer 241. Simultaneously forming the p-Si layer and the active layer 241 effectively saves fabrication steps and improves fabrication efficiency. The patterning process includes dry etching or photolithography.

[0069] Step S520: At least two first heavily doped regions 221, at least one second heavily doped region 222, and at least two type I regions 223 are formed on the p-Si layer. The first heavily doped regions 221 and the second heavily doped regions 222 are spaced apart and alternately arranged along a first direction. Each type I region 223 is located between adjacent first heavily doped regions 221 and second heavily doped regions 222. The arrangement pattern of the first heavily doped regions 221, second heavily doped regions 222, and type I regions 223 can be referred to the previous embodiment and will not be repeated here.

[0070] In one example, step S520 may include: setting a first mask on the side of the p-Si layer, active layer 241, and buffer layer 230 facing away from the substrate 210, so as to expose the first region of the p-Si layer and the first and second regions of the active layer 241; simultaneously performing ion implantation heavy doping on the first region of the p-Si layer and the first and second regions of the active layer 241 using an ion implantation doping process, so that the first region of the p-Si layer is transformed into a first heavily doped region 221, the first region of the active layer 241 is transformed into a first semiconductor region 241B, and the second region of the active layer 241 is transformed into a first heavily doped region 221. A channel region 241A is formed between the second semiconductor region 241C and the first semiconductor region 241B and the second semiconductor region 241C. A second mask is provided on the side of the p-Si layer, the active layer 241 and the buffer layer 230 away from the substrate 210 to expose the second region of the p-Si layer. The second region of the p-Si layer is heavily doped with ion implantation using an ion implantation doping process to transform the second region of the p-Si layer into a second heavily doped region 222. The doping type of the second heavily doped region 222 is opposite to that of the first heavily doped region 221.

[0071] Step S530: An interlayer dielectric layer 250 is formed on the side of the p-Si layer and the active layer 241 facing away from the substrate 210. Exemplarily, step S530 may include: forming a gate insulating layer 242 on the side of the p-Si layer, the active layer 241, and the buffer layer 230 facing away from the substrate 210 using a coating process or a thin film deposition process; forming a gate metal film on the side of the gate insulating layer 242 facing away from the substrate 210 using a coating process or a thin film deposition process; patterning the gate metal film to form a gate 243, such that the orthogonal projection of the gate 243 on the substrate 210 overlaps with the orthogonal projection of the active layer 241 on the substrate 210, and the orthogonal projection of the gate 243 on the substrate 210 is within the range of the orthogonal projection of the active layer 241 on the substrate 210; and forming the interlayer dielectric layer 250 on the side of the gate 243 and the gate insulating layer 242 facing away from the substrate 210 using a coating process or a thin film deposition process. The interlayer dielectric layer 250 can be a transparent insulating material such as resin.

[0072] Step S540: At least two first vias 251, at least one second via 252, a third via 253, and a fourth via 254 are formed on the interlayer dielectric layer 250, and the first vias 251 to the fourth via 254 all penetrate the gate insulating layer 242; wherein, at least two first vias 251 correspond one-to-one with at least two first heavily doped regions 221, and at least one second via 252 corresponds one-to-one with at least one second heavily doped region 222; the orthographic projection of each first via 251 on the substrate 210 is respectively located within the orthographic projection range of each first heavily doped region 221 on the substrate 210, so that each first heavily doped region 221 is within the range of the orthographic projection range of the corresponding first via 251 on the substrate 210, so that each first heavily doped region 221 is within the range of the orthographic projection range of the corresponding first via 251 on the substrate 210. The via 251 is exposed; the orthographic projection of each second via 252 on the substrate 210 lies within the orthographic projection range of each second heavily doped region 222 on the substrate 210, so that each second heavily doped region 222 is exposed from the corresponding second via 252; the orthographic projection of the third via 253 on the substrate 210 lies within the orthographic projection range of the first semiconductor region 241B on the substrate 210, so that the first semiconductor region 241B is exposed from the third via 253; the orthographic projection of the fourth via 254 on the substrate 210 lies within the orthographic projection range of the second semiconductor region 241C on the substrate 210, so that the second semiconductor region 241C is exposed from the fourth via 254.

[0073] In step S550, a first electrode 261, a second electrode 262, a third electrode, and a fourth electrode are formed on the side of the interlayer dielectric layer 250 away from the substrate 210 using a coating process or a thin film deposition process, such that the first electrode 261 passes through each first via 251 and is connected to the corresponding first heavily doped region 221, the second electrode 262 passes through each second via 252 and is connected to the corresponding second heavily doped region 222, the third electrode passes through the third via 253 and is connected to the first semiconductor region 241B, and the fourth electrode passes through the fourth via 254 and is connected to the second semiconductor region 241C.

[0074] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0076] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0077] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0078] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements have been described above. Of course, these are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0079] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An active pixel sensor, characterized in that, include: A substrate and a PIN device disposed on one side of the substrate, the PIN device comprising: The system comprises at least two first heavily doped regions, at least one second heavily doped region, and at least two type I regions disposed in the same layer. The first heavily doped regions and the second heavily doped regions are spaced apart and alternately arranged along a first direction. Each type I region is located between adjacent first heavily doped regions and second heavily doped regions, such that the configuration ratio of the type I region to the first heavily doped region is equal to or greater than 1, and the configuration ratio of the type I region to the second heavily doped region is equal to or greater than 1. Furthermore, when the configuration ratio of the type I region to the first heavily doped region is equal to 1, the configuration ratio of the type I region to the second heavily doped region is greater than 1, or when the configuration ratio of the type I region to the second heavily doped region is equal to 1, the configuration ratio of the type I region to the first heavily doped region is greater than 1. The second heavily doped region includes a first sub-doped region, and at least two first heavily doped regions and at least two type I regions are arranged in pairs on opposite sides of the first sub-doped region; the ends of the paired type I regions extend toward the first sub-doped region, such that the orthographic projection of the first sub-doped region on the substrate is within the range of the orthographic projection of the paired type I regions on the substrate; The ends of the paired first heavily doped regions extend toward the first sub-doped region, such that the orthographic projection of the first sub-doped region onto the substrate is within the range of the orthographic projection of the paired first heavily doped regions onto the substrate, and the first direction is a direction perpendicular from the center of the first sub-doped region to the peripheral edge of the first sub-doped region.

2. The active pixel sensor according to claim 1, characterized in that, The first heavily doped region, the second heavily doped region, and the type I region are arranged in a row, and the first direction is the direction in which the row is located.

3. The active pixel sensor according to claim 1, characterized in that, At least two second doped regions include paired second sub-doped regions, which are located on opposite sides of the first sub-doped region, and the ends of the paired second sub-doped regions extend toward the first sub-doped region such that the orthographic projection of the paired second sub-doped regions on the substrate surrounds the orthographic projection of the first sub-doped region on the substrate.

4. The active pixel sensor according to any one of claims 1 to 3, characterized in that, Also includes: A thin-film transistor is located on the side of the substrate where the PIN device is disposed; the active layer of the thin-film transistor is disposed on the same layer as the first heavily doped region, the second heavily doped region and the type I region, and the doping type of the first semiconductorization region and the second semiconductorization region of the active layer is the same as the doping type of the first heavily doped region.

5. The active pixel sensor according to claim 4, characterized in that, Also includes: An interlayer dielectric layer is located on the side of the first heavily doped region, the second heavily doped region, and the type I region away from the substrate. At least two first vias and at least one second via are formed on the interlayer dielectric layer. The at least two first vias correspond one-to-one with the at least two first heavily doped regions, and the at least one second via corresponds one-to-one with the at least one second heavily doped region. The orthographic projection of each of the first vias on the substrate overlaps with the orthographic projection of the corresponding first heavily doped region on the substrate, and the orthographic projection of each of the second vias on the substrate overlaps with the orthographic projection of the corresponding second heavily doped region on the substrate; The first electrode and the second electrode are both located on the side of the interlayer dielectric layer away from the substrate. The first electrode passes through each of the first vias and is connected to the corresponding first heavily doped region. The second electrode passes through each of the second vias and is connected to the corresponding second heavily doped region.

6. The active pixel sensor according to claim 5, characterized in that, A third via and a fourth via are formed on the interlayer dielectric layer. The orthographic projection of the third via on the substrate overlaps with the orthographic projection of the first semiconductor region on the substrate, and the orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the second semiconductor region on the substrate. The active pixel sensor further includes: The third electrode and the fourth electrode are both located on the side of the interlayer dielectric layer opposite to the substrate. The third electrode passes through the third via and is connected to the first semiconductorized region, and the fourth electrode passes through the fourth via and is connected to the second semiconductorized region.

7. A display device, characterized in that, Includes the active pixel sensor according to any one of claims 1 to 6.

8. A method for fabricating an active pixel sensor, characterized in that, include: A p-Si layer is formed on one side of the substrate; At least two first heavily doped regions, at least one second heavily doped region, and at least two type I regions are formed on the p-Si layer. The first heavily doped regions and the second heavily doped regions are spaced apart and alternately arranged along a first direction. Each type I region is located between adjacent first heavily doped regions and second heavily doped regions, such that the configuration ratio of the type I region to the first heavily doped region is equal to or greater than 1, and the configuration ratio of the type I region to the second heavily doped region is equal to or greater than 1. Furthermore, when the configuration ratio of the type I region to the first heavily doped region is equal to 1, the configuration ratio of the type I region to the second heavily doped region is greater than 1, or when the configuration ratio of the type I region to the second heavily doped region is equal to 1, the configuration ratio of the type I region to the first heavily doped region is greater than 1. The second heavily doped region includes a first sub-doped region, and at least two first heavily doped regions and at least two type I regions are arranged in pairs on opposite sides of the first sub-doped region; the ends of the paired type I regions extend toward the first sub-doped region, such that the orthographic projection of the first sub-doped region on the substrate is within the range of the orthographic projection of the paired type I regions on the substrate; The ends of the paired first heavily doped regions extend toward the first sub-doped region, such that the orthographic projection of the first sub-doped region onto the substrate is within the range of the orthographic projection of the paired first heavily doped regions onto the substrate, and the first direction is a direction perpendicular from the center of the first sub-doped region to the peripheral edge of the first sub-doped region.

9. The preparation method according to claim 8, characterized in that, A p-Si layer is formed on one side of the substrate, including: The p-Si layer and the active layer are formed simultaneously on one side of the substrate.

10. The preparation method according to claim 9, characterized in that, At least two first heavily doped regions, at least one second heavily doped region, and at least two type I regions are formed on the p-Si layer, including: Simultaneously, the first heavily doped region is formed on the p-Si layer, and the first and second semiconductorized regions are formed on the active layer; A second doped region is formed on the p-Si layer; The region on the p-Si layer located between the first heavily doped region and the second heavily doped region is designated as the Type I region.

11. The preparation method according to claim 10, characterized in that, Also includes: An interlayer dielectric layer is formed on the side of the p-Si layer and the active layer opposite to the substrate; At least two first vias, at least one second via, a third via, and a fourth via are formed on the interlayer dielectric layer; wherein, at least two first vias correspond one-to-one with at least two first heavily doped regions, at least one second via corresponds one-to-one with at least one second heavily doped region, the orthographic projection of each first via on the substrate is located within the orthographic projection range of the corresponding first heavily doped region on the substrate, the orthographic projection of each second via on the substrate is located within the orthographic projection range of the corresponding second heavily doped region on the substrate, the orthographic projection of the third via on the substrate is located within the orthographic projection range of the first semiconductorized region on the substrate, and the orthographic projection of the fourth via on the substrate is located within the orthographic projection range of the second semiconductorized region on the substrate; A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on the side of the interlayer dielectric layer opposite to the substrate, such that the first electrode passes through each of the first vias and is connected to the corresponding first heavily doped region, the second electrode passes through each of the second vias and is connected to the corresponding second heavily doped region, the third electrode passes through the third via and is connected to the first semiconductorized region, and the fourth electrode passes through the fourth via and is connected to the second semiconductorized region.

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