Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate, a method for preparing the same, and a display device. The display substrate includes a first display area and a second display area, the second display area at least partially surrounding the first display area, the first display area being configured to display images and transmit light, and the second display area being configured to display images; in a plane perpendicular to the display substrate, the first display area includes at least a substrate and a light-emitting structure layer disposed on the substrate, the light-emitting structure layer including a stacked anode, an organic light-emitting layer, and a cathode, a phase modulation layer being disposed on the side of the anode close to the substrate, the phase modulation layer being configured to reduce diffraction in the first display area. The present disclosure reduces diffraction of light when passing the edge of the anode by disposing a phase modulation layer on the side of the anode close to the substrate, thereby solving the problem of poor camera performance in existing display devices.

Description

Technical Field

[0001] This article relates to but is not limited to display technology, in particular to a display substrate and its preparation method, and a display device. Background Art

[0002] With the continuous development of display technology, cameras are usually installed on display devices to meet shooting needs. In order to maximize the screen-to-body ratio, technologies such as bangs screen, beauty peak, water drop screen, and hole screen have appeared one after another. These technologies are achieved by digging holes in part of the display area and placing a camera under the hole area to reduce the area occupied by the camera in the surrounding area, thereby increasing the screen-to-body ratio. However, these technologies will cause some areas of the display screen to be unable to be displayed. The use of under-display camera or under-panel camera (UDC or UPC) technology has gradually become a better choice.

[0003] For OLED display devices, since pixel driving circuits need to be set up, metal occupies most of the pixel area, making the proportion of the light-transmitting area in the pixel small. When light passes through the opaque area, diffraction will occur, affecting the normal operation of the under-screen camera. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device, which solve the problem of poor imaging effects caused by diffraction in existing display devices.

[0006] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a first display area and a second display area, wherein the second display area at least partially surrounds the first display area, the first display area is configured to display images and transmit light, and the second display area is configured to display images; in a plane perpendicular to the display substrate, the first display area comprises at least a substrate and a light-emitting structure layer arranged on the substrate, the light-emitting structure layer comprises a stacked anode, an organic light-emitting layer and a cathode, a phase modulation layer is provided on the side of the anode close to the substrate, and the phase modulation layer is configured to reduce the diffraction of the first display area.

[0007] In some exemplary embodiments, the display substrate further includes a third display area located between the first display area and the second display area, the third display area being configured to provide a pixel driving circuit connected to the anode of the first display area.

[0008] In some exemplary embodiments, an edge of the anode is retracted by a certain distance relative to an edge of the phase modulation layer, and an orthographic projection of the phase modulation layer on the substrate includes an orthographic projection of the anode on the substrate.

[0009] In some exemplary embodiments, the phase modulation layer is configured so that light undergoes a phase delay of π / 2 after passing through an edge region of the phase modulation layer.

[0010] In some exemplary embodiments, the phase modulation layer includes an alignment layer and a polymer liquid crystal layer disposed on a side of the alignment layer away from the substrate.

[0011] In some exemplary embodiments, the alignment layer includes a first alignment layer and a second alignment layer arranged at intervals, the edge of the anode is retracted a certain distance relative to the edge of the first alignment layer, and the orthographic projection of the first alignment layer on the substrate includes the orthographic projection of the anode on the substrate.

[0012] In some exemplary embodiments, the first alignment layer is configured to align liquid crystals so that light undergoes a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first alignment layer, and the second alignment layer is configured not to align liquid crystals.

[0013] In some exemplary embodiments, the first alignment layer is configured to align the liquid crystal so that light undergoes a right-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the first alignment layer; and the second alignment layer is configured to align the liquid crystal so that light undergoes a left-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the second alignment layer.

[0014] In a second aspect, an embodiment of the present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a first display area and a second display area, the second display area at least partially surrounding the first display area, the first display area being configured to display images and transmit light, and the second display area being configured to display images; the method includes: forming a phase modulation layer and a light-emitting structure layer on a substrate of the first display area, the light-emitting structure layer including a stacked anode, an organic light-emitting layer and a cathode, the phase modulation layer being arranged on a side of the anode close to the substrate, and the phase modulation layer being configured to reduce diffraction of the first display area.

[0015] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate of the first display area, including: sequentially forming an orientation layer and a polymer liquid crystal layer on the substrate, patterning the orientation layer and the polymer liquid crystal layer through a patterning process, forming a phase modulation layer in the first display area, and causing a phase delay of π / 2 after light passes through the phase modulation layer; forming an anode on the polymer liquid crystal layer, wherein the edge of the anode is retracted a certain distance relative to the edge of the phase modulation layer, and the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0016] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate in the first display area, including: forming an orientation layer and a polymer liquid crystal layer in sequence on the substrate to form an initial phase modulation layer located in the first display area; forming the anode on the polymer liquid crystal layer, and etching the initial phase modulation layer using the photoresist of the anode as a mask to form the phase modulation layer; etching the anode a second time, and retracting the edge of the anode by a certain distance relative to the edge of the phase modulation layer, so that the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0017] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate of the first display area, comprising: sequentially forming an orientation layer and a polymer liquid crystal layer on the substrate, patterning the orientation layer and the polymer liquid crystal layer through a patterning process, and forming a phase modulation layer in the first display area; wherein the orientation layer comprises a first orientation layer and a second orientation layer arranged at intervals, and light undergoes a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first orientation layer; and forming the anode on the polymer liquid crystal layer, wherein the edge of the anode is retracted a certain distance relative to the edge of the first orientation layer, and the orthographic projection of the first orientation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0018] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate of the first display area, comprising: sequentially forming an orientation layer and a polymer liquid crystal layer on the substrate, patterning the orientation layer and the polymer liquid crystal layer through a patterning process, and forming a phase modulation layer in the first display area; wherein the orientation layer comprises a first orientation layer and a second orientation layer arranged at intervals, and light undergoes a phase delay of π / 2 after passing through adjacent first orientation layers and second orientation layers; and forming the anode on the polymer liquid crystal layer, wherein the edge of the anode is retracted a certain distance relative to the edge of the first orientation layer, and the orthographic projection of the first orientation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0019] In some exemplary embodiments, the light undergoes a phase delay of π / 2 after passing through the adjacent first alignment layer and second alignment layer, including: through optical alignment treatment, causing the light to undergo a right-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the first alignment layer; and through optical alignment treatment, causing the light to undergo a left-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the second alignment layer.

[0020] In a third aspect, an embodiment of the present disclosure further provides a display device comprising the display substrate as described above.

[0021] In the display substrate provided by the embodiment of the present disclosure, by setting a phase modulation layer on the side of the anode close to the substrate, the diffraction of light when passing through the edge of the anode can be reduced, the diffraction of the first display area is reduced, and the problem of poor camera effect caused by diffraction in existing display devices is solved.

[0022] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0025] Figure 1 is a structural schematic diagram of an electronic device;

[0026] Figure 2 It is a structural schematic diagram of a display substrate;

[0027] Figure 3 A schematic diagram of the planar structure of a display substrate;

[0028] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0029] Figure 5 This is a working timing diagram of a pixel driving circuit;

[0030] Figure 6 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 7is a schematic cross-sectional structure diagram of a first display area according to an exemplary embodiment of the present disclosure;

[0032] Figure 8 A schematic cross-sectional structure diagram of a substrate according to an exemplary embodiment of the present disclosure;

[0033] Figure 9 Schematic diagram of a cross-sectional structure of a circuit structure layer according to an exemplary embodiment of the present disclosure;

[0034] Figure 10 This is a schematic cross-sectional structure diagram of an initial phase modulation layer according to an exemplary embodiment of the present disclosure;

[0035] Figure 11 A schematic cross-sectional structure diagram of an anode and a photoresist according to an exemplary embodiment of the present disclosure;

[0036] Figure 12 This is a schematic diagram of a cross-sectional structure of an exemplary embodiment of the present disclosure after etching the initial phase modulation layer;

[0037] Figure 13 This is a schematic diagram of the cross-sectional structure of an exemplary embodiment of the present disclosure after secondary etching of the anode;

[0038] Figure 14 A schematic cross-sectional structure diagram of a pixel definition layer according to an exemplary embodiment of the present disclosure;

[0039] Figure 15 This is a schematic cross-sectional view of a light-emitting structure layer according to an exemplary embodiment of the present disclosure;

[0040] Figure 16 This is a schematic cross-sectional view of a packaging structure layer according to an exemplary embodiment of the present disclosure;

[0041] Figure 17 This is a schematic cross-sectional view of a touch structure layer according to an exemplary embodiment of the present disclosure;

[0042] Figure 18 This is a schematic cross-sectional structure diagram of a color filter structure layer and a protective layer according to an exemplary embodiment of the present disclosure;

[0043] Figure 19 A schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0044] Figure 20 A schematic diagram of the working principle of a phase modulation layer according to an exemplary embodiment of the present disclosure;

[0045] Figure 21 A schematic cross-sectional view of a phase modulation layer formed by another method in an exemplary embodiment of the present disclosure;

[0046] Figure 22A schematic cross-sectional view of an anode formed by another method in an exemplary embodiment of the present disclosure;

[0047] Figure 23 A schematic cross-sectional structure diagram of an alignment layer formed by another method in an exemplary embodiment of the present disclosure;

[0048] Figure 24 A schematic cross-sectional view of a phase modulation layer formed by another method in an exemplary embodiment of the present disclosure;

[0049] Figure 25 FIG. 1 is a schematic cross-sectional view of an anode formed by another method in an exemplary embodiment of the present disclosure.

[0050] Description of reference numerals:

[0051] 1-substrate; 2-circuit layer; 3-light-emitting layer; 4-encapsulation layer; 5-pixel definition layer; 6-anode; 7-organic light-emitting layer; 8-cathode; 9-phase modulation layer; 11-alignment layer; 12-polymer liquid crystal layer; 13-first alignment layer; 14-second alignment layer; 31-first insulating layer; 32-second insulating layer; 33-third insulating layer; 34-fourth insulating layer; 35-fifth insulating layer; 36-sixth insulating layer; 41-first transistor; 45-first capacitor; 61-first touch metal layer; 62-first touch insulating layer; 63-second touch metal layer; 64-touch protection layer; 71-first black matrix; 72-second black matrix; 73-color filter Unit; 81-protective layer; 100-first display area; 101-base substrate; 200-second display area; 201-circuit structure layer; 251-first conductive line; 300-light-emitting structure layer; 301-glass substrate; 302-first flexible material layer; 303-first inorganic material layer; 304-second flexible material layer; 305-second inorganic material layer; 400-touch structure layer; 501-first connecting electrode; 502-second connecting electrode; 511a-first anode; 511b-second anode; 512a-first pixel definition layer; 512b-second pixel definition layer; 513a-first organic light-emitting layer; 513b-second organic light-emitting layer. DETAILED DESCRIPTION

[0052] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0053] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0054] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0055] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0056] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.

[0057] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0058] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0059] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0060] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0061] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0062] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0063] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0064] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0065] Figure 1 Figure 1 is a schematic diagram of the structure of an electronic device. Figure 1As shown, the electronic device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values and control signals received from a timing controller. For example, the data driver can sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0066] With the development of display technology, full-screen or narrow-bezel products, with their larger screen-to-body ratios and ultra-narrow bezels, have gradually become the development trend of display products. Products such as smart terminals typically require hardware such as front-facing cameras, fingerprint sensors, or light sensors. To increase the screen-to-body ratio, full-screen or narrow-bezel products often utilize under-screen camera technology (FDC) or under-screen fingerprint technology. These sensors are placed in the under-display camera (UDC) area of the display substrate. This area not only has a certain degree of transmittance but also provides display functionality.

[0067] Figure 2 Schematic diagram of the structure of a display substrate. Figure 2 As shown, on a plane parallel to the display substrate, the display substrate may include a first display area 100 and a second display area 200. The second display area 200 may at least partially surround the first display area 100. In an exemplary embodiment, the position of the first display area 100 may correspond to the position of the optical device. The first display area 100 is configured to display images and transmit light, and the transmitted light is received by the optical device. The first display area 100 may be referred to as an under-screen camera display area. The second display area 200 is configured to display images and may be referred to as a normal display area.

[0068] In an exemplary embodiment, the position of the first display area 100 within the second display area 200 is not limited and may be located above or below the second display area 200, or at an edge of the second display area 200. In an exemplary embodiment, within a plane parallel to the display substrate, the shape of the first display area 100 may be any one or more of the following: square, rectangular, polygonal, circular, and elliptical, and the optical device may be a fingerprint recognition device, a camera, or an optical sensor such as a 3D imaging device. When the first display area 100 is circular, the diameter of the circle may be approximately 3 mm to 5 mm. When the first display area 100 is rectangular, the side length of the rectangle may be approximately 3 mm to 5 mm, although this is not limited in this disclosure.

[0069] In an exemplary embodiment, the resolutions of the first display area 100 and the second display area 200 may be the same, or the resolution of the first display area 100 may be lower than that of the second display area 200. For example, the resolution of the first display area 100 may be approximately 50% to 100% of the resolution of the second display area 200. Pixels Per Inch (PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display substrate can display images at a higher density, resulting in richer image details.

[0070] Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 3 As shown, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0071] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in this disclosure. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally, vertically, or in a square pattern, which is not limited in this disclosure.

[0072] Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit is connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0073] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0074] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0075] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0076] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0077] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0078] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0079] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0080] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0081] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first pole (anode), an organic light-emitting layer and a second pole (cathode), or can be a QLED, including a stacked first pole (anode), a quantum dot light-emitting layer and a second pole (cathode).

[0082] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0083] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0084] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0085] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0086] Figure 5 This is a working timing diagram of a pixel driving circuit. Figure 4 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 4 The pixel driving circuit includes 7 transistors (a first transistor T1 to a sixth transistor T7) and a storage capacitor C.

[0087] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0088] The first phase A1, known as the reset phase, is characterized by a low-level signal on the second scan signal line S2, and a high-level signal on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1, and the signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0089] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initialization signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal of the second scanning signal line S2 is a high-level signal, turning off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0090] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0091] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0092] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0093] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0094] An embodiment of the present disclosure provides a display substrate, including a first display area and a second display area, the second display area at least partially surrounding the first display area, the first display area being configured to display images and transmit light, and the second display area being configured to display images; in a plane perpendicular to the display substrate, the first display area includes at least a substrate and a light-emitting structure layer arranged on the substrate, the light-emitting structure layer including a stacked anode, an organic light-emitting layer and a cathode, a phase modulation layer being provided on the side of the anode close to the substrate, and the phase modulation layer being configured to reduce diffraction in the first display area.

[0095] In the solution of the embodiment of the present disclosure, by arranging a phase modulation layer on the side of the anode close to the substrate, the diffraction of light when passing through the edge of the anode can be reduced, thereby reducing the diffraction of the first display area.

[0096] In some exemplary embodiments, the display substrate further includes a third display area located between the first display area and the second display area, the third display area being configured to provide a pixel driving circuit connected to the anode of the first display area.

[0097] In this embodiment, the light-emitting device in the first display area is a first light-emitting element, and the anode of the first light-emitting element is connected to the first pixel driving circuit. By arranging the first pixel driving circuit that drives the first light-emitting element in the first display area in the third display area, the wiring in the first display area is reduced, which helps to increase the light transmittance of the first display area. In other embodiments, the first pixel driving circuit that drives the first light-emitting element in the first display area can be arranged in the second display area.

[0098] In some exemplary embodiments, an edge of the anode is retracted by a certain distance relative to an edge of the phase modulation layer, and an orthographic projection of the phase modulation layer on the substrate includes an orthographic projection of the anode on the substrate.

[0099] In some exemplary embodiments, the phase modulation layer is configured so that light undergoes a phase delay of π / 2 after passing through an edge region of the phase modulation layer.

[0100] In this embodiment, the phase of the light will change after passing through the phase modulation layer. The phase of the light will be delayed by π / 2 after passing through the phase modulation layer. The light passing through the phase modulation layer and the light not passing through the phase modulation layer will undergo destructive interference, which will cancel each other out and reduce the light passing through the edge of the anode, thereby reducing the diffraction that occurs when the light passes through the edge of the anode.

[0101] In some exemplary embodiments, the phase modulation layer may be made of an inorganic material. For example, molybdenum oxynitride silicon (MoSiNxOx) may be used to form the phase modulation layer. Different locations in the phase modulation layer may have different refractive indices, so that light takes different times to pass through different parts of the phase modulation layer. This, in turn, changes the phase of light passing through the phase modulation layer, thereby reducing diffraction at the edge of the anode. Alternatively, other inorganic materials or combinations of inorganic materials may be used to form the phase modulation layer. The presently disclosed embodiments do not limit the materials used to form the phase modulation layer.

[0102] In some exemplary embodiments, the phase modulation layer includes an alignment layer and a polymer liquid crystal layer disposed on a side of the alignment layer away from the substrate.

[0103] In this embodiment, the phase modulation layer can be made of an organic material. For example, the phase modulation layer can be configured as a dual-layer composite structure consisting of an orientation layer and a polymer liquid crystal layer. The orientation layer is responsible for aligning the liquid crystals, while the polymer liquid crystal layer is responsible for modulating the phase of light. The orientation layer can be made of polyimide (PI). Alternatively, the phase modulation layer can be made of other organic materials or combinations of organic materials. The disclosed embodiments do not limit the materials used to make the phase modulation layer.

[0104] In some exemplary embodiments, the alignment layer includes a first alignment layer and a second alignment layer arranged at intervals, the edge of the anode is retracted a certain distance relative to the edge of the first alignment layer, and the orthographic projection of the first alignment layer on the substrate includes the orthographic projection of the anode on the substrate.

[0105] In some exemplary embodiments, the first alignment layer is configured to align liquid crystals so that light undergoes a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first alignment layer, and the second alignment layer is configured not to align liquid crystals.

[0106] In some exemplary embodiments, the first alignment layer is configured to align the liquid crystal so that light undergoes a right-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the first alignment layer; and the second alignment layer is configured to align the liquid crystal so that light undergoes a left-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the second alignment layer.

[0107] In some exemplary embodiments, the alignment layer and the polymer liquid crystal layer can be used together to produce a phase delay of π / 2 for light passing through the phase modulation layer. For example, the alignment layer can be adjusted so that the phase delay of light after passing through the corresponding polymer liquid crystal layer is π / 2. Alternatively, the alignment layer can be configured to include a first alignment layer and a second alignment layer arranged in an alternating pattern, so that the light after passing through the polymer liquid crystal layer corresponding to the first alignment layer produces a phase delay of π / 2. The second alignment layer may not align the liquid crystals, and the anode is positioned corresponding to the first alignment layer. Alternatively, the alignment layer can be configured to include a first alignment layer and a second alignment layer arranged in an alternating pattern, with the first and second alignment layers being configured to orient the liquid crystals in opposite directions. This can produce a right-handed phase delay of π / 4 for light after passing through the polymer liquid crystal layer corresponding to the first alignment layer, a left-handed phase delay of π / 4 for light after passing through the polymer liquid crystal layer corresponding to the second alignment layer, and a phase delay of π / 2 for light after passing through adjacent first and second alignment layers. Alternatively, adjacent first and second alignment layers can use other combinations of phase delay values to achieve the above effect, which is not limited in the presently disclosed embodiments.

[0108] In some exemplary embodiments, the display substrate further includes a photosensor, and an orthographic projection of the photosensor on the base is located within an orthographic projection of the first display area on the base.

[0109] In some exemplary embodiments, the light-sensitive sensor may be, for example, an under-screen camera, which is not limited in the present disclosure.

[0110] An embodiment of the present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a first display area and a second display area, the second display area at least partially surrounding the first display area, the first display area being configured to display images and transmit light, and the second display area being configured to display images; the method includes: forming a phase modulation layer and a light-emitting structure layer on a substrate of the first display area, the light-emitting structure layer including a stacked anode, an organic light-emitting layer and a cathode, the phase modulation layer being arranged on a side of the anode close to the substrate, and the phase modulation layer being configured to reduce diffraction of the first display area.

[0111] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate of the first display area, including: sequentially forming an orientation layer and a polymer liquid crystal layer on the substrate, patterning the orientation layer and the polymer liquid crystal layer through a patterning process, forming a phase modulation layer in the first display area, and causing a phase delay of π / 2 after light passes through the phase modulation layer; forming an anode on the polymer liquid crystal layer, wherein the edge of the anode is retracted a certain distance relative to the edge of the phase modulation layer, and the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0112] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate in the first display area, including: forming an orientation layer and a polymer liquid crystal layer in sequence on the substrate to form an initial phase modulation layer located in the first display area; forming the anode on the polymer liquid crystal layer, and etching the initial phase modulation layer using the photoresist of the anode as a mask to form the phase modulation layer; etching the anode a second time, and retracting the edge of the anode by a certain distance relative to the edge of the phase modulation layer, so that the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0113] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate of the first display area, comprising: sequentially forming an orientation layer and a polymer liquid crystal layer on the substrate, patterning the orientation layer and the polymer liquid crystal layer through a patterning process, and forming a phase modulation layer in the first display area; wherein the orientation layer comprises a first orientation layer and a second orientation layer arranged at intervals, and light undergoes a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first orientation layer; and forming the anode on the polymer liquid crystal layer, wherein the edge of the anode is retracted a certain distance relative to the edge of the first orientation layer, and the orthographic projection of the first orientation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0114] In some exemplary embodiments, the phase modulation layer and the light-emitting structure layer are formed on the substrate of the first display area, comprising: sequentially forming an orientation layer and a polymer liquid crystal layer on the substrate, patterning the orientation layer and the polymer liquid crystal layer through a patterning process, and forming a phase modulation layer in the first display area; wherein the orientation layer comprises a first orientation layer and a second orientation layer arranged at intervals, and light undergoes a phase delay of π / 2 after passing through adjacent first orientation layers and second orientation layers; and forming the anode on the polymer liquid crystal layer, wherein the edge of the anode is retracted a certain distance relative to the edge of the first orientation layer, and the orthographic projection of the first orientation layer on the substrate includes the orthographic projection of the anode on the substrate.

[0115] In some exemplary embodiments, the light undergoes a phase delay of π / 2 after passing through the adjacent first alignment layer and second alignment layer, including: through optical alignment treatment, causing the light to undergo a right-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the first alignment layer; and through optical alignment treatment, causing the light to undergo a left-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the second alignment layer.

[0116] An embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0117] The following describes the solutions of the embodiments of the present disclosure with reference to the accompanying drawings.

[0118] Figure 6 FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 6 As shown, the display substrate includes: a display area AA and a frame area BB located around the display area AA. The display area AA may include: a first display area A1 and a second display area A2, the second display area A2 at least partially surrounding the first display area A1, the first display area A1 being configured to display images and transmit light, and the second display area A2 being configured to display images. In some examples, the first display area A1 may also be referred to as an under-screen camera (UDC or UPC) area, and the second display area A2 may also be referred to as a normal display area. However, this embodiment is not limited to this.

[0119] In some exemplary embodiments, a display substrate may include: a plurality of sub-pixels disposed on a base substrate, at least one of which may include a pixel driving circuit and a light-emitting element. The pixel driving circuit is configured to drive the light-emitting element. For example, the pixel driving circuit is configured to provide a driving current to drive the light-emitting element to emit light. For example, the light-emitting element may be an organic light-emitting diode (OLED), which, when driven by its corresponding pixel driving circuit, emits red, green, blue, or white light. The color of the light emitted by the light-emitting element can be determined as desired.

[0120] In some exemplary embodiments, to improve the light transmittance of the first display area A1, only light-emitting elements may be provided in the first display area A1, while the pixel driving circuit that drives the light-emitting elements in the first display area A1 may be provided in the second display area A2. In other words, the light transmittance of the first display area A1 is improved by separating the light-emitting elements and the pixel driving circuit. In this example, no pixel driving circuit is provided in the first display area A1.

[0121] In an exemplary embodiment, the display area AA may further include a third display area A3, which may be located between the first display area A1 and the second display area A2. The third display area A3 is configured to set a pixel driving circuit, and the pixel driving circuit is connected to the light-emitting device of the first display area A1. The third display area A3 may be referred to as a transition display area.

[0122] In some exemplary embodiments, Figure 6 As shown, the first display area A1 and the third display area A3 can be located in the top center of the display substrate. However, this embodiment is not limited to this. For example, the first display area A1 and the third display area A3 can be located in other positions such as the upper left corner or the upper right corner of the display substrate.

[0123] In some exemplary embodiments, Figure 6 As shown, the third display area A3 can be located on two opposite sides of the first display area A1 in the first direction X. However, this embodiment is not limited to this. For example, the third display area can be located on one side of the first display area in the first direction, or can be located on at least one side of the first display area in the second direction, or the third display area can be arranged to surround the first display area.

[0124] In some exemplary embodiments, Figure 6 As shown, the display area AA can be a rectangle, for example, a rounded rectangle. Alternatively, the first display area A1 can be circular or elliptical. Alternatively, the first display area A1 can be rectangular. However, this embodiment is not limited to this. For example, the first display area can be other shapes such as a quadrilateral or a pentagon.

[0125] In some exemplary embodiments, the orthographic projection of hardware such as a light sensor (eg, a camera) on the display substrate may be located within the first display area A1. Figure 6 As shown, the first display area A1 can be rectangular, and the size of the orthographic projection of the light sensor on the display substrate can be smaller than or equal to the size of the inscribed circle of the first display area A1. In other examples, the first display area A1 can be circular, and the size of the orthographic projection of the light sensor on the display substrate can be smaller than or equal to the size of the first display area A1. However, this embodiment is not limited to this.

[0126] Figure 7 FIG. 1 is a schematic cross-sectional view of the first display area of an exemplary embodiment of the present disclosure, illustrating the structure of three sub-pixels. Figure 7As shown, in a plane perpendicular to the display substrate, the display substrate of the first display area may include a circuit layer 2 disposed on a substrate 1, a light-emitting layer 3 disposed on the side of the first circuit layer 2 away from the substrate 1, and an encapsulation layer 4 disposed on the side of the light-emitting layer 3 away from the substrate 1. In an exemplary embodiment, the light-emitting layer 3 of each sub-pixel may include at least a pixel definition layer 5, an anode 6, an organic light-emitting layer 7, a cathode 8, and a phase modulation layer 9. The phase modulation layer 9 is disposed on the side of the circuit layer 2 away from the substrate, the anode 6 is disposed on the side of the phase modulation layer 9 away from the substrate, and the pixel definition layer 5 is disposed on the side of the anode 6 away from the substrate. A pixel opening is defined in the pixel definition layer 5, exposing the anode 6. The organic light-emitting layer 7 is connected to the anode 6 through the pixel opening, and the cathode 8 is connected to the organic light-emitting layer 7. In an exemplary embodiment, the orthographic projection of the phase modulation layer 9 on the substrate includes the orthographic projection of the anode 6 on the substrate. The phase modulation layer 9 is configured to reduce diffraction at the edge of the anode 6.

[0127] Because the anode is opaque, a large number of light-emitting elements in the first display area A1 can result in high diffraction of light passing through the anode edge, hindering the operation of hardware such as light-sensitive sensors (such as cameras). Conversely, a small number of light-emitting elements in the first display area A1 can result in significant display differences between the first display area A1 and the second and third display areas A2 and A3, adversely affecting the display quality. The disclosed embodiments significantly reduce diffraction at the anode edge by providing a phase modulation layer on the side of the anode closest to the substrate, effectively addressing these issues.

[0128] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0129] In an exemplary embodiment, Figures 8 to 18 The schematic diagram of the preparation process of a display substrate is shown in FIG. Figure 19 The preparation process of the display substrate may include the following steps.

[0130] (1) Forming a base substrate. In an exemplary embodiment, forming the base substrate may include: coating a first flexible material film on a glass substrate 301, depositing a first inorganic material film on the first flexible material film, patterning the first flexible material film and the first inorganic material film through a patterning process, removing the first flexible material layer film and the first inorganic material film in the first display area A1, and forming a stacked first flexible material layer 302 and a first inorganic material layer 303 in the second display area A2. Subsequently, coating a second flexible material film, depositing a second inorganic material film on the second flexible material film, forming a stacked second flexible material layer 304 and a second inorganic material layer 305, and completing the preparation of the base substrate 101, as shown in FIG. Figure 8 shown.

[0131] In an exemplary embodiment, the base substrate 101 of the first display area A1 may include a stacked second flexible material layer 304 and a second inorganic material layer 305, and the base substrate 101 of the second display area A2 may include a stacked first flexible material layer 302, a first inorganic material layer 303, a second flexible material layer 304, and a second inorganic material layer 305. The thickness of the base substrate of the first display area A1 is less than the thickness of the base substrate of the second display area A2, which is beneficial to improving the light transmittance of the first display area A1.

[0132] In an exemplary embodiment, the substrate may also be a rigid substrate. The rigid substrate may be made of materials such as glass or quartz, which is not limited in the present disclosure.

[0133] In some exemplary embodiments, the first and second flexible materials may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic materials may be made of silicon nitride (SiNx) or silicon oxide (SiOx). The first and second inorganic material layers 303 and 305 may be referred to as barrier layers, and the second inorganic material layer 305 may be referred to as a buffer layer.

[0134] (2) Forming a circuit structure layer pattern. In an exemplary embodiment, forming a circuit structure layer pattern may include:

[0135] A semiconductor thin film is deposited on the base substrate, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer pattern. The semiconductor layer pattern may at least include: a plurality of active layers located in the second display area A2.

[0136] Subsequently, a first insulating film and a first conductive film are deposited in sequence, and the first conductive film is patterned through a patterning process to form a first insulating layer 31 covering the entire base substrate, and a first conductive layer pattern arranged on the first insulating layer 31. The first conductive layer pattern includes at least: a plurality of gate electrodes and a plurality of first plates located in the second display area A2.

[0137] Subsequently, a second insulating film and a second conductive film are deposited in sequence, and the second conductive film is patterned through a patterning process to form a second insulating layer 32 covering the entire base substrate, and a second conductive layer pattern arranged on the second insulating layer 32, wherein the second conductive layer pattern includes at least: a plurality of second electrodes located in the second display area A2, and the orthographic projections of the plurality of second electrodes on the substrate at least partially overlap with the orthographic projections of the plurality of first electrodes on the substrate.

[0138] Subsequently, a third insulating film is deposited and patterned through a patterning process to form a third insulating layer 33 covering the entire base substrate. Light-transmitting holes and multiple active vias are also formed. The light-transmitting holes are located in the first display area A1. The third insulating layer 33, the second insulating layer 32, and the first insulating layer 31 within the light-transmitting holes are removed, exposing the surface of the base substrate 101. Multiple active vias are located in the second display area A2. The third insulating layer 33, the second insulating layer 32, and the first insulating layer 31 within the multiple active vias are removed, exposing the surfaces at both ends of the active layer.

[0139] Subsequently, a third conductive film is deposited and patterned through a patterning process to form a third conductive layer pattern disposed on the third insulating layer 33. The third conductive layer pattern includes at least: a plurality of source electrodes and drain electrodes located in the second display area A2, and the source electrodes and the drain electrodes are respectively connected to the active layer through active vias.

[0140] At this point, the transistor structure layer pattern is completed. In an exemplary embodiment, the transistor structure layer of the second display area A2 may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 9 In the figure, the pixel driving circuit of one sub-pixel including one first transistor 41 and one first capacitor 45 is taken as an example.

[0141] In an exemplary embodiment, the first transistor 41 may include an active layer, a gate electrode, a source electrode, and a drain electrode, and the first capacitor 45 may include a first plate and a second plate. In an exemplary embodiment, the first transistor 41 may be a driving transistor in a pixel driving circuit, a portion of the first transistor may be used to drive sub-pixels located in the first display area A1, and another portion of the first transistor may be used to drive sub-pixels located in the second display area A2. The driving transistor may be a thin film transistor (TFT).

[0142] In some examples, the first insulating layer 31 and the second insulating layer 32 are called gate insulating layers, and the third insulating layer 33 is an interlayer insulating layer. In some examples, the first to third insulating layers can be inorganic insulating layers. For example, the first insulating layer, the second insulating layer, and the third insulating layer are made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first conductive layer, the second conductive layer, and the third conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The semiconductor layer can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0143] A fourth insulating film is deposited on the base substrate on which the aforementioned pattern is formed, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 34 pattern covering the first display area A1 and the second display area A2. A plurality of first connection vias are formed on the fourth insulating layer pattern located in the second display area A2, and the plurality of first connection vias expose the surface of the drain electrode of the first transistor 41.

[0144] Subsequently, a fourth conductive film is deposited and patterned through a patterning process to form a fourth conductive layer pattern arranged on the fourth insulating layer. The fourth conductive layer pattern includes at least: a plurality of first connecting electrodes 501 located in the second display area A2, and the first connecting electrode 501 is connected to the drain electrode of the first transistor 41 through a first connecting via.

[0145] Subsequently, a fifth insulating film is deposited and patterned through a patterning process to form a fifth insulating layer 35 pattern covering the first display area A1 and the second display area A2. A plurality of second connection vias are formed on the fifth insulating layer 35 located in the second display area A2, and the plurality of second connection vias expose the surface of the first connection electrode 501.

[0146] Subsequently, a fifth conductive film is deposited and patterned through a patterning process to form a fifth conductive layer pattern disposed on the fifth insulating layer. The fifth conductive layer pattern includes at least a second connecting electrode 502 and a first conductive line 251. The second connecting electrode 502 can be located in the second display area A2 and connected to the first connecting electrode 501 via a second connecting via. The first conductive line 251 can be located in the first display area A1 and extend to the second display area A2, connecting to the first connecting electrode 501 via a second connecting via. The first conductive line 251 is configured to connect to a first anode subsequently formed in the first display area A1, and the second connecting electrode 502 is configured to connect to a second anode subsequently formed in the second display area A2.

[0147] Subsequently, a sixth insulating film is deposited and patterned through a patterning process to form a sixth insulating layer 36 pattern covering the first display area A1 and the second display area A2. A plurality of third connection vias are formed on the sixth insulating layer 36, and the plurality of third connection vias respectively expose the surfaces of the first conductive line 251 and the second connection electrode 502.

[0148] At this point, the pattern of the circuit structure layer 201 is completed, as shown in FIG. Figure 9 shown.

[0149] In some exemplary embodiments, Figure 9 As shown, the connection wiring layer of the second display area A2 may include: a first connection layer and a second connection layer. The second connection layer is located on a side of the first connection layer away from the base substrate. The connection wiring layer of the first display area A1 may include: a second connection layer. Conductive wires connecting the pixel drive circuit and the first light-emitting element may be located in the connection wiring layer. In this exemplary embodiment, by providing conductive wires in two connection layers, the arrangement of the conductive wires can be facilitated.

[0150] In some exemplary embodiments, Figure 9 As shown, the first connection layer of the second display area A2 includes at least: a plurality of connection electrodes 501. The second connection layer includes at least: a second connection electrode 502. The second connection electrode 502 is located in the second display area A2. A fourth insulating layer 34 is provided between the third conductive layer and the first connection layer of the circuit structure layer, and a fifth insulating layer 35 is provided between the first connection layer and the second connection layer. In some examples, the fourth insulating layer 34 may be an inorganic or organic insulating layer, and the fifth insulating layer 35 may be an organic insulating layer. The first connection layer and the second connection layer may be made of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), which is not limited in this embodiment.

[0151] (3) Forming an initial phase modulation layer pattern. In an exemplary embodiment, forming the phase modulation layer pattern may include:

[0152] An alignment film is coated on the substrate with the aforementioned pattern formed thereon, and after curing and alignment, an alignment layer is formed. A liquid crystal polymer is then coated and cured to form a polymer liquid crystal layer. The alignment layer and the polymer liquid crystal layer are patterned through a patterning process to form an initial phase modulation layer located in the first display area A1. A plurality of fourth connection vias are formed on the initial phase modulation layer. The alignment layer and the polymer liquid crystal layer within the fourth connection vias are removed, and the fourth connection vias are connected to the third connection vias, exposing the surface of the first conductive line 251. Figure 10 shown.

[0153] In an exemplary embodiment, the material of the alignment layer may employ polyimide.

[0154] In some exemplary embodiments, after the alignment layer is aligned, light passing through the polymer liquid crystal layer can be delayed by π / 2.

[0155] (4) Forming an anode pattern. In an exemplary embodiment, forming an anode pattern may include:

[0156] A sixth conductive film is deposited on the base substrate on which the aforementioned pattern is formed, and the sixth conductive film is patterned by a patterning process to form an anode pattern. The anode pattern may include at least: a plurality of first anodes located in the first display area A1 and a plurality of second anodes located in the second display area A2. The first anodes are connected to the first conductive line 251 through the fourth connection via and the third connection via, and the second anodes are connected to the second connection electrode 502 through the third connection via to achieve connection with the corresponding pixel driving circuits, such as Figure 11 In this patterning process, the photoresist on the anode is retained after the anode is etched.

[0157] Subsequently, the initial phase modulation layer (including the alignment layer and the polymer liquid crystal layer) located in the first display area A1 is etched using the photoresist on the first anode as a mask to obtain a phase modulation layer including the alignment layer 11 and the polymer liquid crystal layer 12, as shown in FIG. Figure 12 As shown. Figure 12 As shown, the anode and the phase modulation layer in the first display area A1 are perpendicular to the direction of the substrate (ie, Figure 12 By using the anode photoresist as a mask to etch the initial phase modulation layer and then obtain the phase modulation layer, the vertical alignment accuracy of the anode and the phase modulation layer is improved, and there is no alignment error.

[0158] Then, the anode is etched twice so that the anode is offset from the edge of the phase modulation layer. The edge of the anode is retracted by a distance d relative to the edge of the phase modulation layer. After the second etching of the anode is completed, the photoresist of the anode is stripped off. Figure 13As shown, the anode pattern includes a first anode 511a located in the first display area A1 and a second anode 511b located in the second display area A2, the orthographic projection of the phase modulation layer on the base substrate includes the orthographic projection of the first anode 511a on the base substrate, and the distance between the edge of the first anode 511a and the edge of the phase modulation layer is d.

[0159] At this point, the phase modulation layer pattern and the anode pattern are completed.

[0160] In an exemplary embodiment, the sixth conductive film may be made of a metal material, a transparent conductive material, or a multilayer composite structure of a metal material and a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). The multilayer composite structure may be ITO / Al / ITO, etc.

[0161] (5) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include:

[0162] A first pixel definition film is coated on the substrate having the aforementioned pattern formed thereon. The first pixel definition film is patterned through a patterning process to form a first pixel definition layer pattern. The first pixel definition layer pattern may include at least a first pixel definition layer 512a located in the first display area A1. The first pixel definition layer 512a is provided with a plurality of first pixel openings. The first pixel definition film within the first pixel openings is removed, exposing the surface of the first anode 511a. In some exemplary embodiments, the first pixel definition film may be transparent. The transparent first pixel definition layer 512a can provide an optical path for a light sensor (e.g., an under-screen camera) located below the first display area A1, thereby facilitating the operation of the light sensor.

[0163] Subsequently, a second pixel definition film is applied and patterned through a patterning process to form a second pixel definition layer pattern. The second pixel definition layer pattern may include at least a second pixel definition layer 512b located in the second display area A2. A plurality of second pixel openings are defined on the second pixel definition layer 512b. The second pixel definition film within the second pixel openings is removed, exposing the surface of the second anode 511b. In some exemplary embodiments, the second pixel definition film may be black.

[0164] The first pixel definition layer 512a and the second pixel definition layer 512b may be as follows Figure 14As shown. In an exemplary embodiment, the material of the pixel definition film may include polyimide or acrylic, etc. The present disclosure does not limit the preparation order of the first pixel definition layer and the second pixel definition layer. In an exemplary embodiment, a patterning process of a halftone mask plate can be used to form a spacer column pattern when forming the pixel definition layer pattern. The spacer column can be arranged on the outside of the pixel opening, and the spacer column is configured to support the fine metal mask in the subsequent evaporation process, which is not limited by the present disclosure.

[0165] (6) Forming a light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the light-emitting layer and the cathode pattern may include:

[0166] On the substrate on which the aforementioned pattern is formed, an organic light-emitting layer pattern is formed by evaporation or inkjet printing. The organic light-emitting layer pattern may at least include: a first organic light-emitting layer 513a located in the first display area A1 and a second organic light-emitting layer 513b located in the second display area A2. The first organic light-emitting layer 513a is connected to the first anode 511a through the first pixel opening, and the second organic light-emitting layer 513b is connected to the second anode 511b through the second pixel opening.

[0167] Subsequently, a cathode pattern is formed on the patterned substrate by vapor deposition using an open mask. The entire cathode structure covers both the first display area A1 and the second display area A2. The cathode 53 is connected to the first organic light-emitting layer 513a and the second organic light-emitting layer 513b, respectively, achieving simultaneous connection of the organic light-emitting layers to both the anode and cathode. The cathode can be a transparent cathode, for example, made of a transparent conductive material such as ITO or IZO.

[0168] At this point, the light emitting structure layer pattern is prepared, and the light emitting structure layer pattern may include a first light emitting layer pattern located in the first display area A1 and a second light emitting layer pattern located in the second display area A2, such as Figure 15 As shown in 300.

[0169] In exemplary embodiments, the organic light emitting layer may include an emission layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0170] (7) Forming an encapsulation layer pattern. In an exemplary embodiment, forming an encapsulation layer pattern may include:

[0171] On the substrate with the aforementioned pattern formed, a first packaging film is first deposited using an open mask plate by a deposition method to form a first layer pattern, and then a second packaging material is printed using an open mask plate by an inkjet printing process to form a second layer pattern, and then a third packaging film is deposited using an open mask plate by a deposition method to form a third layer pattern.

[0172] At this point, the pattern of the encapsulation layer 4 is completed, and the pattern of the encapsulation structure layer can be as follows Figure 16 The encapsulation layer 4 may also adopt other structures, which are not limited in this disclosure.

[0173] In an exemplary embodiment, the first and third encapsulation films can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers, ensuring that external water and oxygen cannot enter the light-emitting structure layer. Deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) can be used. The second encapsulation film can be made of an organic material, such as a resin, to cover the various film layers of the display substrate, improving structural stability and flatness.

[0174] (8) Forming a touch structure layer pattern. In an exemplary embodiment, forming a touch structure layer pattern may include:

[0175] 1. Forming a first touch metal layer pattern. In an exemplary embodiment, forming the first touch metal layer pattern may include:

[0176] A first metal film is deposited on the substrate with the aforementioned pattern and patterned by a patterning process to form a first touch metal layer pattern. The first touch metal layer pattern includes at least a first touch metal layer 61, which can be located in the second display area A2.

[0177] 2. Forming a first touch insulating layer pattern. In an exemplary embodiment, forming the first touch insulating layer pattern may include:

[0178] A seventh insulating film is deposited on the substrate with the aforementioned pattern. This film is then patterned using a patterning process to form a seventh insulating layer pattern that covers the first display area A1 and the second display area A2. The seventh insulating layer pattern includes at least a first touch insulating layer 62 that covers the first display area A1 and the second display area A2. Multiple vias are formed in the first touch insulating layer 62, exposing the surface of the first touch metal layer 61.

[0179] 3. Forming a second touch metal layer pattern. In an exemplary embodiment, forming the second touch metal layer pattern may include:

[0180] A second metal film is deposited on the substrate with the aforementioned pattern and patterned through a patterning process to form a second touch metal layer pattern. The second touch metal layer pattern includes at least a second touch metal layer 63. The second touch metal layer 63 can be located in the second display area A2. Some of the second touch metal layers 63 are connected to the first touch metal layer 61 through vias.

[0181] In an exemplary embodiment, the first touch metal layer 61 may include a plurality of connection bridges, and the second touch metal layer 63 may include a plurality of driving electrodes and sensing electrodes. The driving electrodes or the sensing electrodes may be connected to the bridge electrodes through vias.

[0182] 4. Forming a touch protection layer pattern. In an exemplary embodiment, forming a touch protection layer pattern may include:

[0183] Epoxy resin is coated on the substrate with the aforementioned pattern to form a touch protection layer 64. In other embodiments, the touch protection layer may be formed using materials such as polyacrylate (acrylic) or silicone resin, which is not limited in this disclosure.

[0184] At this point, the touch structure layer pattern is completed, and the touch structure layer can be Figure 17 As shown in 400 in FIG. The touch structure layer may adopt other structures, which are not limited in the present disclosure.

[0185] (9) Forming a color filter structure layer pattern. In an exemplary embodiment, forming a color filter structure layer pattern may include:

[0186] 1. Forming a black matrix pattern. In an exemplary embodiment, forming the black matrix pattern may include coating a black matrix film on the substrate having the aforementioned pattern formed thereon, and patterning the black matrix film through a patterning process to form a black matrix pattern. The black matrix pattern may include at least a first black matrix 71 pattern located in the first display area A1 and a second black matrix 72 pattern located in the second display area A2.

[0187] In an exemplary embodiment, the first black matrix 71 and the second black matrix 72 are provided with multiple light-transmitting openings. The black matrix film within each of these light-transmitting openings is removed, exposing the surface of the touch structure layer. The multiple light-transmitting openings are configured to house different color filter units, and the shapes and sizes of the multiple light-transmitting openings can vary. The pattern of the first black matrix 71 also includes partitions between adjacent light-transmitting openings. Light can pass through the partitions and exit the first display area A1, achieving light transmission and helping to improve the light transmittance of the first display area A1.

[0188] Forming a color filter unit pattern. In an exemplary embodiment, forming the color filter unit pattern may include coating a green filter film on the substrate having the aforementioned pattern formed thereon, and patterning the green filter film through a patterning process to form a green filter unit. After forming the green filter unit, a red filter unit and a blue filter unit are sequentially formed, thereby completing the preparation of the color filter unit 73. The steps for forming the red filter unit and the blue filter unit are similar to those for forming the green filter unit and are not further described here. The present disclosure does not limit the order in which the color filter unit 73 is prepared.

[0189] In an exemplary embodiment, the color filter units located in the first display area A1 and the second display area A2 not only fill the light-transmitting openings but also cover the adjacent first black matrix 71 (or second black matrix 72), so that the distance between the surface of the color filter unit away from the substrate and the substrate is greater than the distance between the surface of the first black matrix 71 (or second black matrix 72) away from the substrate and the substrate, that is, relative to the color filter unit, the first black matrix 71 (or second black matrix 72) is closer to the substrate.

[0190] At this point, the color film structure layer pattern is completed, such as Figure 18 By directly forming the color filter structure layer on the touch structure layer, the display substrate can be made thinner and more flexible, and the light extraction efficiency can be improved and the power consumption can be reduced.

[0191] (10) Forming a protective layer. In an exemplary embodiment, forming a protective layer may include: coating epoxy resin on the substrate on which the aforementioned pattern is formed to form a protective layer 81, such as Figure 18 In other embodiments, the protective layer may be formed using materials such as polyacrylate (acrylic) or silicone resin, which is not limited in the present disclosure.

[0192] After the above preparation, the structure of the display substrate obtained is as follows Figure 19 As shown, Figure 19 The result after peeling off the glass substrate 301 is shown in FIG. Figure 19 As shown, within a plane perpendicular to the display substrate, the second display area A2 may include: a base substrate, a circuit structure layer disposed on the base substrate, a connection wiring layer, a light-emitting structure layer, an encapsulation layer, a touch structure layer, and a color filter structure layer. The first display area A1 may include: a base substrate, a connection wiring layer disposed on the base substrate, a light-emitting structure layer, an encapsulation layer, a touch structure layer, and a color filter structure layer. However, this embodiment is not limited to this. The cross-sectional structure of the third display area A3 is similar to that of the second display area, and therefore will not be further described here.

[0193] Figure 20 This is a schematic diagram of the working principle of a phase modulation layer according to an exemplary embodiment of the present disclosure. Figure 20 The phase modulation layer 9 is arranged between the anode 6 and the substrate 1, and other structures are schematically omitted. For the light from the under-screen camera, the phase (Phase) of the light after passing through the blank area between adjacent anodes 6 is above 0, while the light undergoes a phase delay of π / 2 after passing through the phase modulation layer 9, and becomes below 0. That is, since the phase difference between the light passing through the phase modulation layer 9 and the light passing through the blank area is π / 2, the light located in the edge area of the phase modulation layer 9 will undergo destructive interference, offsetting part of the incident light in the edge area of the phase modulation layer 9, thereby reducing the light intensity (Intensity) in the edge area of the phase modulation layer 9. Since the incident light offset by the edge area of the phase modulation layer 9 contains the diffraction light of the anode edge, the diffraction light at the anode edge is effectively eliminated, and the diffraction light in the first display area is effectively eliminated. In the embodiment of the present disclosure, by setting a phase modulation layer in the first display area, the optical quality of the under-screen camera is effectively improved, and the shooting effect is maximized.

[0194] In exemplary embodiments, the phase modulation layer and the anode may be formed using other process forms.

[0195] Figures 21 to 22 Another method of forming a phase modulation layer and an anode is disclosed in the present invention.

[0196] An alignment film is applied to the base substrate and, after curing and alignment, forms an alignment layer. A liquid crystal polymer is then applied and, after curing, forms a polymer liquid crystal layer. The alignment layer and the polymer liquid crystal layer are patterned through a patterning process to form a phase modulation layer pattern located in the first display area A1. The phase modulation layer pattern includes at least an alignment layer 11 and a polymer liquid crystal layer 12. A plurality of fourth connection vias are formed on the phase modulation layer. The alignment layer and the polymer liquid crystal layer within the fourth connection vias are removed and connected to the third connection vias, exposing the surface of the first conductive line 251. Figure 21 shown.

[0197] In an exemplary embodiment, the material of the alignment layer may employ polyimide.

[0198] In some exemplary embodiments, after the alignment layer is aligned, light passing through the polymer liquid crystal layer can be delayed by π / 2.

[0199] In this step, during the process of forming the phase modulation layer, the phase modulation layer is prepared after the orientation layer and the polymer liquid crystal layer are patterned. There is no need to first prepare an initial phase modulation layer and then etch the initial phase modulation layer using the anode photoresist as a mask. The steps are simple.

[0200] A sixth conductive film is deposited on the base substrate on which the aforementioned pattern is formed, and the sixth conductive film is patterned by a patterning process to form an anode pattern. The anode pattern may include at least: a plurality of first anodes 511a located in the first display area A1 and a plurality of second anodes 511b located in the second display area A2. The first anodes 511a are connected to the first conductive line 251 through the fourth connection via and the third connection via, and the second anodes 511b are connected to the second connection electrode 502 through the third connection via to achieve connection with the corresponding pixel driving circuits, such as Figure 22 As shown. Figure 22 As shown, the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the first anode 511 a on the substrate, and relative to the edge of the phase modulation layer, the edge of the first anode 511 a is retracted by a distance d.

[0201] Since the phase modulation layer is directly formed in the previous step, when preparing the anode in this step, the edge misalignment between the anode and the polymer liquid crystal layer can be directly formed without the need for secondary etching of the anode.

[0202] In this embodiment, the alignment layer and the polymer liquid crystal layer are prepared first, and then the anode is prepared, without the need for additional etching. The preparation steps are simple, but the accuracy of the alignment of the anode and the polymer liquid crystal layer needs to be paid attention to during the preparation process.

[0203] Figures 23 to 25 The present invention discloses another method for forming a phase modulation layer and an anode.

[0204] An alignment film is coated on a base substrate, and after curing and alignment, an alignment layer is formed. The alignment layer is patterned by a patterning process to form a first alignment layer 13 and a second alignment layer 14 arranged alternately in the first display area A1. A plurality of fifth connection vias are formed on the first alignment layer 13. The alignment layer in the fifth connection via is removed and connected to the third connection via, exposing the surface of the first conductive line 251. Figure 23 As shown in the figure, during the photo-alignment process, the first alignment layer 13 is formed where the alignment layer is illuminated. The first alignment layer 13 can align the liquid crystals, causing light to experience a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first alignment layer 13. The second alignment layer 14 is formed where the alignment layer is not illuminated. The second alignment layer 14 cannot align the liquid crystals. By controlling the illumination position, the alignment layer forms the first alignment layer 13 and the second alignment layer 14, which are arranged in the same layer with an alternating pattern.

[0205] In an exemplary embodiment, the material of the alignment layer may employ polyimide.

[0206] Then, a liquid crystal polymer is coated to form a polymer liquid crystal layer after curing. The polymer liquid crystal layer is patterned by a patterning process to form a polymer liquid crystal layer 15 located in the first display area A1. A plurality of sixth connection vias are formed on the polymer liquid crystal layer 15. The polymer liquid crystal layer in the sixth connection via is removed and connected to the third connection via, exposing the surface of the first conductive line 251. Figure 24 The phase modulation layer includes a first alignment layer 13 and a second alignment layer 14 arranged at intervals and a polymer liquid crystal layer 15, as shown in FIG. Figure 24 shown.

[0207] In this step, after patterning the alignment layer and polymer liquid crystal layer, the phase modulation layer is complete, eliminating the need for additional etching. Furthermore, in this step, the second alignment layer 14 and the corresponding polymer liquid crystal layer located in the first display area A1 can be retained without completely etching them away, simplifying the etching process.

[0208] A sixth conductive film is deposited on the base substrate on which the aforementioned pattern is formed, and the sixth conductive film is patterned by a patterning process to form an anode pattern. The anode pattern may include at least: a plurality of first anodes 511a located in the first display area A1 and a plurality of second anodes 511b located in the second display area A2. The first anodes 511a are connected to the first conductive line 251 through the sixth connection via, the fifth connection via, and the third connection via, and the second anodes 511b are connected to the second connection electrode 502 through the third connection via to achieve connection with the corresponding pixel driving circuits, such as Figure 25 As shown. Figure 25 As shown, the orthographic projection of the first alignment layer 13 on the substrate includes the orthographic projection of the first anode 511a on the substrate, and the edge of the anode is indented by a distance d relative to the edge of the first alignment layer 13. Since the phase modulation layer has been prepared in the previous step, the anode 511a can be directly offset from the edge of the first alignment layer 13 in this step.

[0209] At this point, the phase modulation layer and anode pattern are prepared, as shown in FIG. Figure 25 shown.

[0210] In this embodiment, the alignment layer and polymer liquid crystal layer are prepared first, followed by the anode. By controlling the illumination position to form the alignment layer into a first alignment layer and a second alignment layer, and then preparing the anode based on this, the preparation process is more targeted and flexible. During the preparation process, attention must be paid to the accuracy of the photo-alignment treatment and the alignment accuracy of the anode and polymer liquid crystal layer.

[0211] In another embodiment, the first orientation layer 13 and the second orientation layer 14 generated by optical orientation are different from those in the previous embodiment, and the remaining processing steps are the same as those in the previous embodiment. In this embodiment, the first orientation layer 13 can orient the liquid crystal so that the light will have a right-handed π / 4 phase delay after passing through the corresponding polymer liquid crystal layer; the second orientation layer 14 can orient the liquid crystal so that the light will have a left-handed π / 4 phase delay after passing through the corresponding polymer liquid crystal layer. During the preparation process, the first orientation layer 13 can be prepared first, and then the second orientation layer 14 can be prepared by controlling the illumination conditions and the position of the illumination. For other preparation steps of this embodiment, please refer to the Figures 24 to 25 The description is not repeated here.

[0212] In this embodiment, the photo-alignment treatment is controlled to form a first alignment layer 13 and a second alignment layer 14 with opposite phase retardation orientations. The coordination of the first and second alignment layers 13, 14 causes light to experience a phase retardation of π / 2 after passing through the phase modulation layer. In other embodiments, the orientation and phase retardation values of the first and second alignment layers 13, 14 can be set as needed, as long as the phase of light experiences a π / 2 delay after passing through the polymer liquid crystal layer corresponding to the adjacent first and second alignment layers 13, 14.

[0213] In this embodiment, the alignment layer and polymer liquid crystal layer are prepared first, followed by the anode. By controlling the photo-alignment treatment, the alignment layer forms a first and second alignment layer with opposite phase retardation orientations. The coordination of the first and second alignment layers results in a phase retardation of π / 2 after light passes through the polymer liquid crystal layer. This makes the entire preparation process more targeted and the method more flexible. During the preparation process, attention must be paid to the accuracy of the photo-alignment treatment and the alignment of the anode and polymer liquid crystal layer.

Claims

1. A display substrate, characterized in that: The display device comprises a first display area and a second display area, wherein the second display area at least partially surrounds the first display area, the first display area being configured to display images and transmit light, and the second display area being configured to display images; in a plane perpendicular to a display substrate, the first display area comprises at least a substrate and a light-emitting structure layer disposed on the substrate, the light-emitting structure layer comprising a stacked anode, an organic light-emitting layer, and a cathode, a phase modulation layer being disposed on a side of the anode adjacent to the substrate, the phase modulation layer being configured to reduce diffraction in the first display area; The edge of the anode is retracted by a certain distance relative to the edge of the phase modulation layer, and the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

2. The display substrate according to claim 1, wherein: The display substrate further includes a third display area, the third display area is located between the first display area and the second display area, and the third display area is configured to be provided with a pixel driving circuit, and the pixel driving circuit is connected to the anode of the first display area.

3. The display substrate according to claim 1, wherein The phase modulation layer is configured so that light undergoes a phase delay of π / 2 after passing through an edge region of the phase modulation layer.

4. The display substrate according to claim 3, wherein: The phase modulation layer includes an alignment layer and a polymer liquid crystal layer arranged on a side of the alignment layer away from the substrate.

5. The display substrate according to claim 4, wherein: The alignment layer includes a first alignment layer and a second alignment layer arranged at intervals. The edge of the anode is retracted a certain distance relative to the edge of the first alignment layer. The orthographic projection of the first alignment layer on the substrate includes the orthographic projection of the anode on the substrate.

6. The display substrate according to claim 5, wherein: The first alignment layer is configured to align liquid crystals so that light undergoes a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first alignment layer. The second alignment layer is configured not to align liquid crystals.

7. The display substrate according to claim 5, wherein: The first orientation layer is configured to orient the liquid crystal so that light undergoes a right-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the first orientation layer; the second orientation layer is configured to orient the liquid crystal so that light undergoes a left-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the second orientation layer.

8. A method for preparing a display substrate, characterized in that: The display substrate includes a first display area and a second display area, the second display area at least partially surrounding the first display area, the first display area is configured to display images and transmit light, and the second display area is configured to display images; the method includes: A phase modulation layer and a light-emitting structure layer are formed on the substrate of the first display area, wherein the light-emitting structure layer includes a stacked anode, an organic light-emitting layer and a cathode, and the phase modulation layer is arranged on the side of the anode close to the substrate, and the phase modulation layer is configured to reduce the diffraction of the first display area; relative to the edge of the phase modulation layer, the edge of the anode is retracted a certain distance, and the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

9. The method according to claim 8, characterized in that The phase modulation layer and the light emitting structure layer are formed on the substrate of the first display area, comprising: An alignment layer and a polymer liquid crystal layer are sequentially formed on the substrate, and the alignment layer and the polymer liquid crystal layer are patterned by a patterning process, and a phase modulation layer is formed in the first display area, and a phase delay of π / 2 occurs when light passes through the phase modulation layer; An anode is formed on the polymer liquid crystal layer.

10. The method according to claim 9, characterized in that The phase modulation layer and the light emitting structure layer are formed on the substrate of the first display area, comprising: forming an alignment layer and a polymer liquid crystal layer on the substrate in sequence to form an initial phase modulation layer located in the first display area; forming the anode on the polymer liquid crystal layer, and etching the initial phase modulation layer using the photoresist of the anode as a mask to form the phase modulation layer; The anode is etched twice, and the edge of the anode is retracted by a certain distance relative to the edge of the phase modulation layer, and the orthographic projection of the phase modulation layer on the substrate includes the orthographic projection of the anode on the substrate.

11. The method according to claim 8, characterized in that The phase modulation layer and the light emitting structure layer are formed on the substrate of the first display area, comprising: An alignment layer and a polymer liquid crystal layer are sequentially formed on the substrate, and the alignment layer and the polymer liquid crystal layer are patterned by a patterning process to form a phase modulation layer in the first display area; wherein the alignment layer includes a first alignment layer and a second alignment layer arranged at intervals, and light undergoes a phase delay of π / 2 after passing through the polymer liquid crystal layer corresponding to the first alignment layer; The anode is formed on the polymer liquid crystal layer, with an edge of the anode being retracted a certain distance relative to an edge of the first alignment layer, and an orthographic projection of the first alignment layer on the substrate includes an orthographic projection of the anode on the substrate.

12. The method according to claim 8, characterized in that The phase modulation layer and the light emitting structure layer are formed on the substrate of the first display area, comprising: An alignment layer and a polymer liquid crystal layer are sequentially formed on the substrate, and the alignment layer and the polymer liquid crystal layer are patterned by a patterning process to form a phase modulation layer in the first display area; wherein the alignment layer includes a first alignment layer and a second alignment layer arranged at intervals, and light undergoes a phase delay of π / 2 after passing through adjacent first and second alignment layers; The anode is formed on the polymer liquid crystal layer, with an edge of the anode being retracted a certain distance relative to an edge of the first alignment layer, and an orthographic projection of the first alignment layer on the substrate includes an orthographic projection of the anode on the substrate.

13. The method according to claim 12, characterized in that The light undergoes a phase delay of π / 2 after passing through the adjacent first alignment layer and the second alignment layer, comprising: Through optical alignment treatment, the light undergoes a right-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the first alignment layer; through optical alignment treatment, the light undergoes a left-handed phase delay of π / 4 after passing through the polymer liquid crystal layer corresponding to the second alignment layer.

14. A display device, characterized in that: A display substrate comprising the display substrate according to any one of claims 1 to 7.

Images