A transverse field-effect transistor and its fabrication method

Abstract

This application provides a lateral field-effect transistor (PLT) and its fabrication method, relating to the field of semiconductor technology. In the lateral field-effect transistor, a gate pad and a source pad are disposed in the passive region, extending from the first surface of the device functional layer to the substrate surface. The gate pad is insulated from both the device functional layer and the substrate, while the source pad is short-circuited to the substrate. This allows the gate pad to form a capacitor structure through the short-circuited source pad, increasing the gate-source capacitance C between the gate and source pads. This effectively mitigates oscillations, reduces power device losses, and prevents false turn-on of the lateral field-effect transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a lateral field-effect transistor and its fabrication method. Background Technology

[0002] When lateral field-effect transistors (LDMOS / GaN HEMT, etc.) are used in hard switching, parasitic oscillations in the gate drive signal can occur due to factors such as internal gate-source parasitic capacitance and trace inductance, increasing the power losses of the device. When the oscillation amplitude is large, it may cause the lateral field-effect transistor to turn on falsely.

[0003] Due to material and structural limitations, existing lateral field-effect transistors (LDMOS / GaN HEMT, etc.) typically have low threshold voltages. Therefore, they are more sensitive to oscillations in the gate drive signal and are more prone to false turn-on. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a lateral field-effect transistor and its fabrication method, which can improve the oscillation of the gate drive signal during the application of the lateral field-effect transistor.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In one aspect of this application, a lateral field-effect transistor is provided. In the passive region of the lateral field-effect transistor, the gate pad and the source pad are respectively extended from the first surface of the device functional layer to the substrate surface. The gate pad is insulated from the device functional layer and the substrate, and the source pad is shorted to the substrate.

[0007] Another aspect of this application provides a method for fabricating a lateral field-effect transistor (FET), which involves fabricating a first trench and a second trench in the passive region of the FET. The gate pad is partially filled in the first trench and is insulated from the device functional layer and the substrate, respectively. The source pad is partially filled in the second trench and is short-circuited to the substrate.

[0008] The beneficial effects of this application include:

[0009] It can improve the oscillation of the gate drive signal during the application of lateral field-effect transistors. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A top view of a lateral field-effect transistor provided in an embodiment of this application;

[0012] Figure 2 This is one of the schematic diagrams of a lateral field-effect transistor provided in an embodiment of this application;

[0013] Figure 3 This is a second schematic diagram of the state of a lateral field-effect transistor provided in an embodiment of this application;

[0014] Figure 4 This is the third schematic diagram of the state of a lateral field-effect transistor provided in the embodiments of this application;

[0015] Figure 5 This is the fourth schematic diagram of the state of a lateral field-effect transistor provided in the embodiments of this application;

[0016] Figure 6 for Figure 1 A sectional view of line A-A';

[0017] Figure 7 A cross-sectional view of a lateral field-effect transistor located in the active region, provided for an embodiment of this application;

[0018] Figure 8 A schematic diagram of the parasitic parameter distribution of a lateral field-effect transistor provided in an embodiment of this application;

[0019] Figure 9 This is a schematic flowchart illustrating a method for fabricating a lateral field-effect transistor, as provided in an embodiment of this application.

[0020] Icons: 101-Active region; 102-Passive region; 103-Drain pad; 104-Gate pad; 105-First trench; 106-Source pad; 107-Second trench; 108-Substrate; 109-Buffer layer; 110-Channel layer; 111-Barrier layer; 112-Photoresist layer; 113-Dielectric layer; 116-Passivation layer; 117-Source; 118-Drain; 119-P-type doped layer; 120-Gate metal. Detailed Implementation

[0021] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0022] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," there is no intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "above another element" or "extending above another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "extending directly to another element," there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0024] Related terms such as “below”, “above”, “upper”, “lower”, “horizontal”, or “vertical” are used herein to describe the relationship of one element, layer, or region to another, as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “described” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless explicitly defined herein.

[0027] One aspect of this application provides a lateral field-effect transistor, combined with... Figure 1 and Figure 6 As shown, it includes: a substrate 108; a device functional layer disposed on the substrate 108 and having a first surface away from the substrate 108; a lateral field-effect transistor having an active region 101 and a passive region 102, wherein the passive region 102 includes the substrate 108 and the device functional layer disposed on the substrate 108, the device functional layer having a first surface away from the substrate 108; a gate pad 104 disposed in the passive region 102, the gate pad 104 extending from the first surface to the surface of the substrate 108, the gate pad 104 being insulated from the substrate 108 and the device functional layer; and a source pad 106 disposed in the passive region 102, the gate pad 104 extending from the first surface to the surface of the substrate 108, the source pad 106 being shorted to the substrate 108.

[0028] In this application, the gate pad 104 and source pad 106 of the lateral field-effect transistor are disposed in the passive region 102, extending from the first surface of the device functional layer to the surface of the substrate 108. The gate pad 104 is insulated from both the device functional layer and the substrate 108, while the source pad 106 is short-circuited to the substrate 108. This allows the gate pad 104 to form a capacitor structure through the source pad 106 short-circuited to the substrate 108, thereby increasing the gate-source capacitance C of the device formed between the gate pad 104 and the source pad 106. This effectively alleviates the oscillations, reduces the power device losses, and prevents the lateral field-effect transistor from being turned on unnecessarily.

[0029] In some implementations, such as Figures 4 to 6 As shown, a first trench 105 corresponding to the gate pad 104 and a second trench 107 corresponding to the source pad 106 are respectively provided on the device functional layer of the passive region 102. Specifically, for the first trench 105: as shown... Figure 4 As shown, the first trench 105 extends downward from the first surface of the device functional layer to the surface of the substrate 108, as... Figure 5 As shown, the first portion of the dielectric layer 113 covers the peripheral and bottom walls of the first groove 105, and the second portion of the dielectric layer 113 is continuous with the first portion and covers the first surface of the periphery of the first groove 105, as shown. Figure 6As shown, the second portion of the gate pad 104 fills the first trench 105 completely covered by the dielectric layer 113. The first portion of the gate pad 104 is located outside the first trench 105 and is continuous with the second portion of the gate pad 104 and located above the second portion of the dielectric layer 113, thereby forming a structure insulated and isolated by the dielectric layer 113 between the gate pad 104 and the device functional layer and between the gate pad 104 and the substrate 108; for the second trench 107: as Figure 4 As shown, the second trench 107 also extends downward from the first surface of the device functional layer to the surface of the substrate 108, as... Figure 6 As shown, the second part of the source pad 106 is directly filled in the second groove 107, and the first part of the source pad 106 is located outside the second groove 107 and is continuous with the second part of the source pad 106 and covers the first surface of the edge of the second groove 107, thereby forming a structure in which the source pad 106 is short-connected to the device functional layer and the substrate 108 respectively.

[0030] The lateral field-effect transistor (FET) has an active region 101 and a passive region 102. The passive region 102 has a first side portion located on one side of the active region 101. A first slot 105 and a second slot 107 formed on the device functional layer of the passive region 102 are both located on the first side portion. This prevents the first slot 105 and the second slot 107 from being blocked by the active region 101, thus limiting the increase in the device's gate-source capacitance C. For example, in some embodiments, such as... Figure 1 As shown, the passive region 102 surrounds the outer periphery of the active region 101, and the first side portion of the passive region 102 is located on one side of the active region 101. Figure 1 When the first trench 105 and the second trench 107 are formed on the device functional layer in the first side of the passive region 102 (below the middle), the positions of the first trench 105 and the second trench 107 can be located in the first side of the passive region 102. In this way, the second trench 107 and the first trench 105 can be avoided from being blocked by the active region 101, which would limit the increase of the gate-source capacitance C of the device.

[0031] In some implementations, the number of first slots 105 provided on the device functional layer can be multiple, and the specific number can be reasonably set according to actual needs. For example... Figure 1 As shown, when there are two first slots 105, the two first slots 105 can be distributed diagonally in the orthogonal projection area of ​​the gate pad 104 on the substrate 108.

[0032] In some implementations, the number of second slots 107 provided on the device functional layer can also be multiple, and the specific number can be reasonably set according to actual needs. For example Figure 1 As shown, when there are four second slots 107, the four second slots 107 can be distributed diagonally in the orthogonal projection area of ​​the source pad 106 on the substrate 108.

[0033] In some implementations, combined Figure 6 As shown, a gate pad 104 and a source pad 106 are disposed within the passive region 102, as follows: Figure 7 As shown, the lateral field-effect transistor also includes a gate, a source 117, and a drain 118 disposed in the active region 101. The gate pad 104 is electrically connected to the gate, and the source pad 106 is electrically connected to the source 117. When the lateral field-effect transistor is configured such that the gate pad 104 is connected in series with the gate driving circuit, the resistance of the circuit structure formed by the gate, gate pad 104, and gate driving circuit is R, and the parasitic inductance of the circuit structure formed by the gate, gate pad 104, and gate driving circuit is L. The lateral field-effect transistor has... The gate-source capacitance C is increased by the gate pad 104 and source pad 106, which are disposed in the passive region 102, extending from the first surface of the device functional layer to the surface of the substrate 108. The gate pad 104 is insulated from both the device functional layer and the substrate 108, while the source pad 106 is short-circuited to the substrate 108. This allows the gate pad 104 to form a capacitor structure through the source pad 106 short-circuited to the substrate 108, thereby increasing the gate-source capacitance C formed between the gate pad 104 and the source pad 106. In some embodiments, such as... Figure 8 As shown, the parasitic parameter distribution of a transverse field-effect transistor is illustrated, under the condition that... When the transverse field-effect transistor is in an overdamped state, it can further alleviate gate oscillation, reduce device losses, and avoid false turn-on of the device through the RLC series resonant circuit.

[0034] In some implementations, such as Figure 1 As shown, a drain pad 103 is also provided on the device functional layer in the passive region 102. The drain pad 103 can be connected to the drain 118 of the active device in the active region 101.

[0035] In some implementations, the source pad 106 may be configured to be grounded, and the drain 118 may be configured to be connected to a power supply.

[0036] In some embodiments, since the dielectric layer 113 acts as the dielectric for the capacitor formed by the gate pad 104 and the source pad 106 shorted to the substrate 108, the size of the device gate-source capacitance C can be adjusted by changing the thickness and material of the dielectric layer 113. For example, when it is necessary to adjust the device gate-source capacitance C to a certain value, the device gate-source capacitance C can be adjusted to a certain value by changing one or a combination of the thickness and material.

[0037] In some implementations, the breakdown voltage of the capacitor formed by the gate pad 104 and the source pad 106 shorted to the substrate 108 should be higher than the actual operating voltage of the lateral field-effect transistor, thereby effectively improving the stability of the device.

[0038] In some embodiments, the thickness and material of the dielectric layer 113 should be reasonably selected in view of the breakdown voltage requirements of the capacitor formed by the gate pad 104 and the source pad 106 and the requirements of the device gate-source capacitance C.

[0039] In some implementations, the depth of the first trench 105 and / or the second trench 107 is greater than the thickness of the functional layer of the device. For example, the typical epitaxial thickness of a 650V GaN HEMT is 5μm, and the depth of the first trench 105 and / or the second trench 107 needs to be greater than 5μm to be etched onto the surface of the substrate 108.

[0040] In some implementations, the thickness of the dielectric layer 113 can be greater than 5 nm, such as 5 nm, 10 nm, or 15 nm, to meet the requirements for breakdown voltage and the gate-source capacitance C of the device. For example, if the GaN E-HEMT gate operating voltage is 6 V, the dielectric material is SiO2, and the typical breakdown electric field is 6 MV / cm, then the thickness of the dielectric layer 113 needs to be greater than 10 nm.

[0041] In some embodiments, the dielectric layer 113 may be made of one of SiO2, Si3N4, and Al2O3. In some embodiments, the dielectric layer 113 may be a Si3N4 / Al2O3 stack, meaning that the dielectric layer 113 is a dielectric stack, that is, a Si3N4 layer is first deposited and then an Al2O3 layer is deposited on the Si3N4 layer.

[0042] In some embodiments, the lateral field-effect transistor is a HEMT device, which includes a substrate 108 and a device functional layer on the substrate 108. Both the substrate 108 and the device functional layer include a portion located in an active region 101 and a portion located in a passive region 102.

[0043] In some embodiments, the device functional layer may include a plurality of active semiconductor layers formed on a substrate 108, all of which are located in an active region 101 and a passive region 102. A two-dimensional electron gas is present at the heterojunction formed between at least two active semiconductor layers in the active region 101, while a two-dimensional electron gas is not present at the heterojunction formed between two active semiconductor layers in the passive region 102 (the absence of a two-dimensional electron gas may be achieved by removing it through processes such as ion implantation).

[0044] In some embodiments, when the lateral field-effect transistor is a HEMT device, the HEMT device includes a substrate 108 and a device functional layer formed on the substrate 108, wherein, for example Figure 7As shown, the multiple active semiconductor layers included in the device functional layer can be: a nucleation layer (not shown) formed on the substrate 108, which can reduce the lattice mismatch between the substrate 108 and the next active semiconductor layer; a buffer layer 109 and a channel layer 110 formed sequentially on the nucleation layer; a barrier layer 111 formed on the channel layer 110, forming a two-dimensional electron gas between the channel layer 110 and the barrier layer 111 (the portion located in the passive region 102 is removed); a passivation layer 116 formed on the barrier layer 111; a source 117 and a drain 118 in contact with the barrier layer 111 formed on the passivation layer 116, and a gate in contact with the barrier layer 111 formed between the source 117 and the drain 118.

[0045] In some implementations, such as Figure 7 As shown, the gate may include a P-type doped layer 119 formed on the barrier layer 111 and a gate metal 120 formed on the P-type doped layer 119.

[0046] In some embodiments, the substrate 108 is made of silicon carbide, sapphire, spinel, zinc oxide, silicon, gallium nitride, aluminum nitride, or any other material capable of supporting the growth of group III nitride materials.

[0047] In some implementations, the nucleation layer may include a variety of different materials, such as Al. x Ga 1-x N (0≤x≤1). A nucleation layer can be formed on substrate 108 using known semiconductor growth techniques such as metal oxide chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0048] In some embodiments, the buffer layer 109 and the channel layer 110 may be made of materials such as Al x Ga y In (1-x-y) The buffer layer 109 and the channel layer 110 are fabricated using group III nitride materials such as N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the buffer layer 109 and the channel layer 110 are GaN layers, and in some other embodiments, Fe can be doped into the GaN layer. The buffer layer 109 and the channel layer 110 can be fabricated using the same methods used to grow nucleation layers.

[0049] In some embodiments, each of the barrier layer 111 and the channel layer 110 may comprise a doped or undoped group III nitride material. The barrier layer 111 may comprise one or more layers of different materials such as InGaN, AlGaN, AlN, or combinations thereof. The barrier layer 111 may be fabricated using the same methods used to grow nucleation layers.

[0050] In some embodiments, the source pad 106 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of these materials. In some embodiments, the gate pad 104 is made of one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or an alloy of several of these materials, or platinum silicide. In some embodiments, the drain pad 103 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of these materials. In some embodiments, the source 117 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of these materials. In some embodiments, the gate is made of one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or an alloy of several of these materials, or platinum silicide. In some embodiments, the drain 118 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of these materials.

[0051] Another aspect of this application provides a method for fabricating a lateral field-effect transistor, such as... Figure 9 As shown, the method includes:

[0052] S010: A device structure is provided, the device structure including a substrate and a device functional layer, the device functional layer being disposed on the substrate and having a first surface away from the substrate; the device structure is provided with a first region for fabricating an active region and a second region for fabricating a passive region.

[0053] S020: In the second region, a first trench and a second trench are formed that extend from the first surface to the substrate.

[0054] S030: Fabricate a dielectric layer, the dielectric layer comprising a first part and a second part, the first part of the dielectric layer being disposed on the peripheral wall and bottom wall of the first groove, and the second part of the dielectric layer being disposed on the first surface.

[0055] S040: Fabricate a gate pad, the gate pad having a first part and a second part, the first part of the gate pad being located on a first surface at the periphery of a first trench, and the second part of the gate pad filling the first trench.

[0056] S050: Fabricate source pads. The source pads consist of a first part and a second part. The first part of the source pads is located on the first part of the first surface at the edge of the second groove, and the second part of the source pads fills the second groove.

[0057] Since this application does not change the structure of the active devices within the active region, it can reduce the extent of modifications to the original device process and lower costs. Furthermore, since both the second and first trenches in this application are located within the original source pad and gate pad regions, it also avoids occupying additional area and resulting in a larger device size.

[0058] In some implementations, such as Figure 2 As shown, in S010: the device structure includes a substrate 108 and a device functional layer. The device functional layer is disposed on the substrate 108 and has a first surface away from the substrate 108. The device structure has a first region and a second region. An active region 101 can be fabricated in the first region, and a passive region 102 can be fabricated in the second region. Specifically, the fabrication method can be to perform mesa etching or ion implantation on the second region, so that the second region forms the passive region 102, while the first region serves as the active region 101.

[0059] In some implementations, in S020: such as Figure 3 As shown, a full layer of photoresist 112 can be coated on the first surface of the device functional layer in the passive region 102. Then, through processes such as exposure and development, windows are opened in the photoresist layer 112 to expose the device functional layer, thereby defining the positions of the first trench 105 and the second trench 107. Figure 4 As shown, the device functional layer is etched at the window position to form a first trench 105 and a second trench 107 on the device functional layer. During etching, the first trench 105 and the second trench 107 formed should extend from the first surface of the device functional layer to the surface of the substrate 108, and the surface of the substrate 108 should be exposed in the first trench 105 and the second trench 107, and the photoresist layer 112 should be peeled off.

[0060] In some implementations, in S030: such as Figure 5 As shown, a full-length dielectric layer 113 can be deposited on the functional layer of the device. The dielectric layer 113 is retained by etching, covering a first portion of the peripheral and bottom walls of the first trench 105 and a second portion that is continuous with the first portion of the dielectric layer 113 and covers the first surface of the periphery of the first trench 105.

[0061] In some implementations, such as Figure 6 As shown, in S040: the gate pad 104 can be fabricated by photolithography, vapor deposition, and metal stripping. Depending on the position of the window, the second part of the gate pad 104 is filled in the first trench 105 which is completely covered by the dielectric layer 113. The first part of the gate pad 104 is located outside the first trench 105 and is continuous with the second part of the gate pad 104 and located above the second part of the dielectric layer 113, thereby forming a structure insulated and isolated between the gate pad 104 and the device functional layer and between the gate pad 104 and the substrate 108 by the dielectric layer 113.

[0062] In some implementations, such as Figure 6As shown, in S050: the source pad 106 can be fabricated by photolithography, vapor deposition, and metal stripping. Depending on the position of the window, the second part of the source pad 106 is directly filled in the second groove 107. The first part of the source pad 106 is located outside the second groove 107 and is continuous with the second part of the source pad 106 and covers the first surface of the edge of the second groove 107, thereby forming a structure in which the source pad 106 is in contact with the device functional layer and short-circuited with the substrate 108.

[0063] In some implementations, such as Figure 7 As shown, when fabricating an active device on the device functional layer of the active region 101, a passivation layer 116 can be formed on the surface of the device functional layer first. Then, a source 117 window and a drain 118 window can be formed on the passivation layer 116 by photolithography. The source 117 and drain 118 can be formed in the source 117 window and drain 118 window respectively by photolithography, evaporation, and metal lift-off processes. Similarly, referring to the process of forming the source 117 window and drain 118 window, the passivation layer 116 is etched to form a gate trench on the passivation layer 116. The gate trench is located between the source 117 and drain 118, and then the gate is fabricated in the gate trench.

[0064] The lateral field-effect transistor (FET) has an active region 101 and a passive region 102. The passive region 102 has a first side portion located on one side of the active region 101. A first slot 105 and a second slot 107 formed on the device functional layer of the passive region 102 are both located on the first side portion. This prevents the first slot 105 and the second slot 107 from being blocked by the active region 101, thus limiting the increase in the device's gate-source capacitance C. For example, in some embodiments, such as... Figure 1 As shown, the passive region 102 surrounds the outer periphery of the active region 101, and the first side portion of the passive region 102 is located on one side of the active region 101. Figure 1 When the first trench 105 and the second trench 107 are formed on the device functional layer in the first side of the passive region 102 (below the middle), the positions of the first trench 105 and the second trench 107 can be located in the first side of the passive region 102. In this way, the second trench 107 and the first trench 105 can be avoided from being blocked by the active region 101, which would limit the increase of the gate-source capacitance C of the device.

[0065] In some implementations, combined Figure 6 As shown, a gate pad 104 and a source pad 106 are disposed within the passive region 102, as follows: Figure 7As shown, the lateral field-effect transistor also includes a gate, a source 117, and a drain 118 disposed in the active region 101. The gate pad 104 is electrically connected to the gate, and the source pad 106 is electrically connected to the source 117. When the lateral field-effect transistor is configured such that the gate pad 104 is connected in series with the gate driving circuit, the resistance of the circuit structure formed by the gate, gate pad 104, and gate driving circuit is R, and the parasitic inductance of the circuit structure formed by the gate, gate pad 104, and gate driving circuit is L. The lateral field-effect transistor has... The gate-source capacitance C is increased by the gate pad 104 and source pad 106, which are disposed in the passive region 102, extending from the first surface of the device functional layer to the surface of the substrate 108. The gate pad 104 is insulated from both the device functional layer and the substrate 108, while the source pad 106 is short-circuited to the substrate 108. This allows the gate pad 104 to form a capacitor structure through the source pad 106 short-circuited to the substrate 108, thereby increasing the gate-source capacitance C formed between the gate pad 104 and the source pad 106. In some embodiments, such as... Figure 8 As shown, the parasitic parameter distribution of a transverse field-effect transistor is illustrated, under the condition that... At this time, the lateral field-effect transistor can operate in an overdamped state, which can further alleviate gate oscillation, reduce device losses, and prevent false turn-on through the RLC series resonant circuit. In some implementations, such as Figure 1 As shown, a drain pad 103 is also provided on the device functional layer in the passive region 102. The drain pad 103 can be connected to the drain 118 of the active device in the active region 101.

[0066] In some implementations, the source pad 106 is configured to be grounded and the drain 118 is configured to be connected to a power supply.

[0067] In some embodiments, since the dielectric layer 113 acts as the dielectric for the capacitor formed by the gate pad 104 and the source pad 106 shorted to the substrate 108, the size of the device gate-source capacitance C can be adjusted by changing the thickness and material of the dielectric layer 113. For example, when it is necessary to adjust the device gate-source capacitance C to a certain value, the device gate-source capacitance C can be adjusted to a certain value by changing one or a combination of the thickness and material.

[0068] In some implementations, the breakdown voltage of the capacitor formed by the gate pad 104 and the source pad 106 shorted to the substrate 108 should be higher than the actual operating voltage of the lateral field-effect transistor, thereby effectively improving the stability of the device.

[0069] In some embodiments, the thickness and material of the dielectric layer 113 should be reasonably selected in view of the breakdown voltage requirements of the capacitor formed by the gate pad 104 and the source pad 106 and the requirements of the device gate-source capacitance C.

[0070] In some implementations, the depth of the first trench 105 and / or the second trench 107 is greater than the thickness of the functional layer of the device. For example, the typical epitaxial thickness of a 650V GaN HEMT is 5μm, and the depth of the first trench 105 and / or the second trench 107 needs to be greater than 5μm to be etched onto the surface of the substrate 108.

[0071] In some implementations, the thickness of the dielectric layer 113 can be greater than 5 nm, such as 5 nm, 10 nm, or 15 nm, to meet the requirements for breakdown voltage and the gate-source capacitance C of the device. For example, if the GaN E-HEMT gate operating voltage is 6 V, the dielectric material is SiO2, and the typical breakdown electric field is 6 MV / cm, then the thickness of the dielectric layer 113 needs to be greater than 10 nm.

[0072] In some embodiments, the dielectric layer 113 may be made of one of SiO2, Si3N4, and Al2O3. In some embodiments, the dielectric layer 113 may be a Si3N4 / Al2O3 stack, meaning that the dielectric layer 113 is a dielectric stack, that is, a Si3N4 layer is first deposited and then an Al2O3 layer is deposited on the Si3N4 layer.

[0073] In some embodiments, the lateral field-effect transistor is a HEMT device, which includes a substrate 108 and a device functional layer on the substrate 108. Both the substrate 108 and the device functional layer include a portion located in an active region 101 and a portion located in a passive region 102.

[0074] In some embodiments, the device functional layer may include a plurality of active semiconductor layers formed on the substrate 108, all of which are located in the active region 101 and the passive region 102. A two-dimensional electron gas is present at the heterojunction formed between the two active semiconductor layers in the active region 101, while a two-dimensional electron gas is not present at the heterojunction formed between the two active semiconductor layers in the passive region 102 (the absence of a two-dimensional electron gas can be achieved by removing it using processes such as ion implantation).

[0075] In some embodiments, when the lateral field-effect transistor is a HEMT device, the HEMT device includes a substrate 108 and a device functional layer formed on the substrate 108, wherein, for example Figure 7As shown, the multiple active semiconductor layers included in the device functional layer can be: a nucleation layer (not shown) formed on the substrate 108, which can reduce the lattice mismatch between the substrate 108 and the next active semiconductor layer; a buffer layer 109 and a channel layer 110 formed sequentially on the nucleation layer; a barrier layer 111 formed on the channel layer 110, forming a two-dimensional electron gas between the channel layer 110 and the barrier layer 111 (the portion located in the passive region 102 is removed); a passivation layer 116 formed on the barrier layer 111; a source 117 and a drain 118 in contact with the barrier layer 111 formed on the passivation layer 116, and a gate in contact with the barrier layer 111 formed between the source 117 and the drain 118.

[0076] In some implementations, such as Figure 7 As shown, the gate may include a P-type doped layer 119 formed on the barrier layer 111 and a gate metal 120 formed on the P-type doped layer 119.

[0077] In some embodiments, the substrate 108 is made of silicon carbide, sapphire, spinel, zinc oxide, silicon, gallium nitride, aluminum nitride, or any other material capable of supporting the growth of group III nitride materials.

[0078] In some implementations, the nucleation layer may include a variety of different materials, such as Al. x Ga 1-x N (0≤x≤1). A nucleation layer can be formed on substrate 108 using known semiconductor growth techniques such as metal oxide chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0079] In some embodiments, the buffer layer 109 and the channel layer 110 may be made of materials such as Al x Ga y In (1-x-y) The buffer layer 109 and the channel layer 110 are fabricated using group III nitride materials such as N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the buffer layer 109 and the channel layer 110 are GaN layers, and in some other embodiments, Fe can be doped into the GaN layer. The buffer layer 109 and the channel layer 110 can be fabricated using the same methods used to grow nucleation layers.

[0080] In some embodiments, each of the barrier layer 111 and the channel layer 110 may comprise a doped or undoped group III nitride material. The barrier layer 111 may comprise one or more layers of different materials such as InGaN, AlGaN, AlN, or combinations thereof. The barrier layer 111 may be fabricated using the same methods used to grow nucleation layers.

[0081] In some embodiments, the source pad 106 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of titanium, aluminum, gold, and nickel; in some embodiments, the gate pad 104 is made of one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or an alloy of several of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide; in some embodiments, the drain pad 103 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of titanium, aluminum, gold, and nickel.

[0082] In some embodiments, the source electrode 117 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of titanium, aluminum, gold, and nickel; in some embodiments, the gate electrode is made of one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or an alloy of several of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide; in some embodiments, the drain electrode 118 is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of titanium, aluminum, gold, and nickel.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A lateral field-effect transistor, characterized in that, include: Substrate; A device functional layer is disposed on the substrate and has a first surface away from the substrate; The lateral field-effect transistor is provided with an active region and a passive region. The passive region is provided with a gate pad that extends from the first surface to the substrate surface and is insulated from the substrate and the device functional layer. The passive region is provided with a source pad that extends from the first surface to the substrate surface. The source pad is shorted to the substrate.

2. The lateral field-effect transistor as described in claim 1, characterized in that, The lateral field-effect transistor further includes: a first trench extending from the first surface to the substrate surface; the gate pad is composed of a first part and a second part, the first part of the gate pad being located on the first surface surrounding the first trench; and the second part of the gate pad filling the first trench. A dielectric layer, comprising a first part and a second part, wherein the first part of the dielectric layer is disposed on the peripheral wall and bottom wall of the first groove; and the second part of the dielectric layer is disposed on the first surface. The second trench extends from the first surface to the substrate surface. The source pad is composed of a first part and a second part. The first part of the source pad is located on the first surface at the edge of the second trench, and the second part of the source pad fills the second part of the second trench.

3. The lateral field-effect transistor as described in claim 2, characterized in that, The passive region has a first side portion disposed on one side of the active region, and both the first groove and the second groove are located on the first side portion.

4. The lateral field-effect transistor as described in any one of claims 1 to 3, characterized in that, The lateral field-effect transistor further includes a gate, a source, and a drain disposed in the active region. The gate pad is electrically connected to the gate, and the source pad is electrically connected to the source. When the lateral field-effect transistor is configured such that the gate pad and the gate driving circuit are connected in series, the resistance of the circuit structure formed by the gate, the gate pad, and the gate driving circuit is R, and the parasitic inductance of the circuit structure formed by the gate, the gate pad, and the gate driving circuit is L. The lateral field-effect transistor has a gate-source capacitance C. .

5. The lateral field-effect transistor as described in claim 4, characterized in that, The source pad can be configured to be grounded, and the drain can be configured to be connected to a power source.

6. The lateral field-effect transistor as described in any one of claims 1 to 3, characterized in that, The lateral field-effect transistor is a HEMT device, and the functional layer of the device includes a plurality of active semiconductor layers formed on the substrate, wherein a two-dimensional electron gas is present at the heterojunction between at least two of the plurality of active semiconductor layers.

7. The lateral field-effect transistor as described in claim 6, characterized in that, The active semiconductor layer is made of a III-V group compound.

8. The lateral field-effect transistor as described in claim 2, characterized in that, The thickness of the dielectric layer is greater than 5 nm; and / or, the dielectric layer is one of SiO2, Si3N4 and Al2O3, or, the dielectric layer is a stack of Si3N4 and Al2O3.

9. The lateral field-effect transistor as described in claim 2, characterized in that, The depth of the first trench is greater than the thickness of the device functional layer; and / or, the depth of the second trench is greater than the thickness of the device functional layer.

10. The lateral field-effect transistor as claimed in claim 1, characterized in that, The source pad is made of one of titanium, aluminum, gold, and nickel, or an alloy of several of these materials; and / or, The gate pad is made of one of nickel, gold, platinum, titanium, chromium and tungsten, or an alloy of several of nickel, gold, platinum, titanium, chromium and tungsten, or platinum silicide.

11. A method for fabricating a lateral field-effect transistor, characterized in that, Includes the following steps: A device structure is provided, the device structure including a substrate and a device functional layer, the device functional layer being disposed on the substrate and having a first surface remote from the substrate; The device structure is provided with a first region for fabricating an active region and a second region for fabricating a passive region; A first trench and a second trench are formed in the second region, extending from the first surface to the substrate; A dielectric layer is fabricated, the dielectric layer being composed of a first part and a second part, the first part of the dielectric layer being disposed on the peripheral wall and bottom wall of the first groove, and the second part of the dielectric layer being disposed on the first surface; A gate pad is fabricated, the gate pad being composed of a first part and a second part, the first part of the gate pad being located above the second part of the dielectric layer, and the second part of the gate pad filling the first trench; A source pad is fabricated, the source pad being composed of a first part and a second part, the first part of the source pad being located on a first surface at the edge of the second groove, and the second part of the source pad filling the second groove; The source pad is shorted to the substrate.

12. The method for fabricating a lateral field-effect transistor as described in claim 11, characterized in that, The lateral field-effect transistor is a HEMT device. The functional layer of the device includes multiple active semiconductor layers formed on a substrate. A two-dimensional electron gas is present at the heterojunction between two of the multiple active semiconductor layers. The material of the active semiconductor layers is a III-V compound.

13. The method for fabricating a lateral field-effect transistor as described in claim 11, characterized in that, The thickness of the dielectric layer is greater than 5 nm; and / or the dielectric layer is one of SiO2, Si3N4 and Al2O3, or a stack of Si3N4 and Al2O3.

14. The method for fabricating a lateral field-effect transistor according to claim 11, characterized in that, The depth of the first trench is greater than the thickness of the device functional layer; and / or, the depth of the second trench is greater than the thickness of the device functional layer.

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