A three-node flip self-recovery latch based on loop feedback C unit

Abstract

The present invention relates to a three-node flip self-recovery latch based on a loop feedback C unit, including a dual-loop structure storage module and four transmission gates. The dual-loop structure storage module is composed of twelve two-input C units, including a first C unit CE1 to a twelfth C unit CE12; the four transmission gates include a first transmission gate TG1 to a fourth transmission gate TG4; the signal input ends of the four transmission gates are all used as data input ends D of the latch, and the output end of the fifth C unit CE5 is used as the data output end of the latch. The present invention has high reliability, can tolerate any three-node flip and can self-recover; uses fewer MOS tubes, reduces area and power consumption, and improves latch tolerance, with more superior performance; has low latency, because in transparent mode, there is only one transmission gate between the input end and the input end, so the present invention establishes a more efficient path, so the transmission delay is low.

Description

Technical Field

[0001] The present invention relates to the technical field of anti-interference reinforcement latches for nano-integrated circuits, in particular to a three-node flip self-recovery latch based on a cyclic feedback C unit. Background Art

[0002] Recent advances in microelectronics manufacturing have ushered integrated circuits into the nanoscale era. This technology, coupled with the continuous reduction in transistor feature size, has resulted in improved power consumption and performance. However, this also makes integrated circuits more susceptible to interference from space radiation, creating a greater risk of soft errors. A soft error occurs when the logical state of a circuit node changes due to external interference, even when the hardware circuitry is intact. Soft errors primarily arise from interference from high-energy particles in space radiation, such as neutrons, alpha particles, protons, heavy ions, and electrons. Consequently, circuit hardening technology is widely used in aerospace applications.

[0003] When it comes to radiation hardening integrated circuit units, researchers are focusing on the design of latches and flip-flops. Due to their simple structure, unhardened latches are highly susceptible to node logic flips, or even multiple node flips, in the complex and highly interfering space radiation environment of nanoscale processes. This poses significant challenges to the design and application of nanoscale latches. Consequently, the design of multi-node hardened latches should be prioritized.

[0004] At present, many latch designs that are resistant to multi-node flips have been launched, but most of these latches have the following problems: First, the latch cannot self-recover from dual-node flips, that is, when dual nodes of the latch undergo logical flipping at the same time, although the correct value can be output, at least one of the flipped nodes cannot be restored to the original correct value; second, the latch cannot tolerate three nodes flipping at the same time, that is, the latch cannot output the correct value; third, the latch cannot self-recover from three-node flips, that is, when three latch nodes flip at the same time, although the correct logical value can be output in the end, the flipped node cannot be restored to its original state; fourth, latches that can tolerate multi-node flips and self-recover have poor performance, high power consumption, area, and delay. Summary of the Invention

[0005] The purpose of the present invention is to provide a three-node flip self-recovery latch based on a loop feedback C unit with low area overhead, low latency and high reliability requirements that can achieve complete self-recovery of any three nodes.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions: a three-node flip self-recovery latch based on cyclic feedback C-cells, comprising a dual-loop structure storage module and four transmission gates, wherein the dual-loop structure storage module is composed of twelve two-input C-cells, the twelve two-input C-cells including a first C-cell CE1, a second C-cell CE2, a third C-cell CE3, a fourth C-cell CE4, a fifth C-cell CE5, a sixth C-cell CE6, a seventh C-cell CE7, an eighth C-cell CE8, a ninth C-cell CE9, a tenth C-cell CE10, an eleventh C-cell CE11, and a twelfth C-cell CE12; the four transmission gates include a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, and a fourth transmission gate TG4; the signal input ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 all serve as data input ends D of the latch, and the output end of the fifth C-cell CE5 serves as the data output end of the latch.

[0007] The first signal input terminal of the first C-unit CE1 is connected to the output terminal N6 of the sixth C-unit CE6, the second signal input terminal of the first C-unit CE1 is connected to the output terminal N8 of the eighth C-unit CE8, the output terminal N1 of the first C-unit CE1 is connected to the first input terminal of the second C-unit CE2 and the second input terminal of the twelfth C-unit CE12; the second signal input terminal of the second C-unit CE2 is connected to the output terminal N9 of the ninth C-unit CE9, the output terminal N2 of the second C-unit CE2 is connected to the first input terminal of the third C-unit CE3 and the first input terminal of the seventh C-unit CE7; the second signal input terminal of the third C-unit CE3 is connected to the output terminal N10 of the tenth C-unit CE10, the output terminal N3 of the third C-unit CE3 is connected to the first input terminal of the fourth C-unit CE4 and the first input terminal of the eighth C-unit CE8; the second signal input terminal of the fourth C-unit CE4 is connected to the output terminal N11 of the eleventh C-unit CE11, the output terminal N4 of the fourth C-unit CE4 is connected to the first input terminal of the fifth C-unit CE5 and the second input terminal of the ninth C-unit CE9; the first signal input terminal of the fifth C-unit CE5 is connected to the output terminal N10 of the tenth C-unit CE10, the output terminal N3 of the third C-unit CE3 is connected to the first input terminal of the fourth C-unit CE4 and the first input terminal of the eighth C-unit CE8; the second signal input terminal of the fourth C-unit CE4 is connected to the output terminal N11 of the eleventh C-unit CE11, the output terminal N4 of the fourth C-unit CE4 is connected to the first input terminal of the fifth C-unit CE5 and the second input terminal of the ninth C-unit The second signal input terminal is connected to the output terminal N12 of the twelfth C-unit CE12, the output terminal N5 of the fifth C-unit CE5 is connected to the first input terminal of the sixth C-unit CE6 and the first input terminal of the tenth C-unit CE10; the second signal input terminal of the sixth C-unit CE6 is connected to the output terminal N7 of the seventh C-unit CE7, and the output terminal N6 of the sixth C-unit CE6 is connected to the first input terminal of the eleventh C-unit CE11; the second signal input terminal of the seventh C-unit CE7 is connected to the output terminal N12 of the twelfth C-unit CE12, and the output terminal N7 of the seventh C-unit CE7 is connected to the second input terminal of the sixth C-unit CE6 and the second input terminal of the eighth C-unit CE8; the first signal input terminal of the ninth C-unit CE9 is connected to the output terminal N8 of the eighth C-unit CE8; the second signal input terminal of the tenth C-unit CE10 is connected to the output terminal N9 of the ninth C-unit CE9; the second signal input terminal of the eleventh C-unit CE11 is connected to the output terminal N10 of the tenth C-unit CE10; and the first signal input terminal of the twelfth C-unit CE12 is connected to the output terminal N11 of the eleventh C-unit CE11.

[0008] The signal output end of the first transmission gate TG1 is respectively connected to the first input end of the fourth C-unit CE4 and the first input end of the eighth C-unit CE8; the signal output end of the second transmission gate TG2 is respectively connected to the first signal input end of the sixth C-unit and the first input end of the tenth C-unit CE10; the signal output end of the third transmission gate TG3 is respectively connected to the second input end of the sixth C-unit CE6 and the second input end of the eighth C-unit CE8; the signal output end of the fourth transmission gate TG4 is respectively connected to the second input end of the second C-unit CE2 and the second input end of the tenth C-unit CE10.

[0009] The first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are each composed of a PMOS transistor and an NMOS transistor. The sources of the PMOS transistor and the NMOS transistor are connected together as the input of the transmission gate; the drains of the PMOS transistor and the NMOS transistor are connected together as the output of the transmission gate; the gate of the NMOS transistor is connected to the system clock signal CLK, and the gate of the PMOS transistor is connected to the reverse system clock signal NCK.

[0010] The twelve two-input C units have the same structure. The first C unit CE1 is composed of two PMOS transistors and two NMOS transistors. The two PMOS transistors include a first PMOS transistor MP11 and a second PMOS transistor MP12. The two NMOS transistors include a first NMOS transistor MN11 and a second NMOS transistor MN12.

[0011] The gate of the first PMOS transistor MP11 is connected to the gate of the first NMOS transistor MN11, and the connection point is the first signal input terminal of the first C unit CE1; the gate of the second PMOS transistor MP12 is connected to the gate of the second NMOS transistor MN12, and the connection point is the second signal input terminal of the first C unit CE1; the drain of the first PMOS transistor MP11 is connected to the source of the second PMOS transistor MP12; the drain of the second PMOS transistor MP12 is connected to the drain of the first NMOS transistor MN11; the source of the first NMOS transistor MN11 is connected to the drain of the second NMOS transistor MN12; the source of the first PMOS transistor MP11, the substrate of the first PMOS transistor MP11, and the substrate of the second PMOS transistor MP12 are all connected to the power supply VDD; the substrate of the first NMOS transistor MN11, the substrate of the second NMOS transistor MN12, and the source of the second NMOS transistor MN12 are all grounded.

[0012] When the system clock signal CLK = 0 and the inverse system clock signal NCK = 1, the signal output terminal N5 of the fifth C unit CE5 serves as the data output terminal of the latch; when the system clock signal CLK = 1 and the inverse system clock signal NCK = 0, the signal output terminal of the second transmission gate TG2 serves as the data output terminal of the latch.

[0013] It can be seen from the above technical solution that the beneficial effects of the present invention are: first, high reliability, can tolerate any three-node flip and can self-recover; second, it uses fewer MOS tubes, which reduces the area and power consumption compared with existing latches, and improves the latch tolerance, with more superior performance; third, it has low latency. Since there is only one transmission gate between the input and output ends in transparent mode, the present invention establishes a more efficient path, so the transmission delay is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the circuit of the present invention.

[0015] Figure 2 Schematic diagram of the circuit of four transmission gates in the present invention.

[0016] Figure 3 for Figure 1 Schematic diagram of the circuit of the first C unit CE1. DETAILED DESCRIPTION

[0017] like Figure 1 As shown, a three-node flip self-recovery latch based on a loop feedback C unit includes a dual-loop structure storage module and four transmission gates. The dual-loop structure storage module is composed of twelve two-input C units, and the twelve two-input C units include a first C unit CE1, a second C unit CE2, a third C unit CE3, a fourth C unit CE4, a fifth C unit CE5, a sixth C unit CE6, a seventh C unit CE7, an eighth C unit CE8, a ninth C unit CE9, a tenth C unit CE10, an eleventh C unit CE11, and a twelfth C unit CE12; the four transmission gates include a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, and a fourth transmission gate TG4; the signal input ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 all serve as the data input end D of the latch, and the output end of the fifth C unit CE5 serves as the data output end of the latch.

[0018] The first signal input terminal of the first C-unit CE1 is connected to the output terminal N6 of the sixth C-unit CE6, the second signal input terminal of the first C-unit CE1 is connected to the output terminal N8 of the eighth C-unit CE8, the output terminal N1 of the first C-unit CE1 is connected to the first input terminal of the second C-unit CE2 and the second input terminal of the twelfth C-unit CE12; the second signal input terminal of the second C-unit CE2 is connected to the output terminal N9 of the ninth C-unit CE9, the output terminal N2 of the second C-unit CE2 is connected to the first input terminal of the third C-unit CE3 and the first input terminal of the seventh C-unit CE7; the second signal input terminal of the third C-unit CE3 is connected to the output terminal N10 of the tenth C-unit CE10, the output terminal N3 of the third C-unit CE3 is connected to the first input terminal of the fourth C-unit CE4 and the first input terminal of the eighth C-unit CE8; the second signal input terminal of the fourth C-unit CE4 is connected to the output terminal N11 of the eleventh C-unit CE11, the output terminal N4 of the fourth C-unit CE4 is connected to the first input terminal of the fifth C-unit CE5 and the second input terminal of the ninth C-unit CE9; the first signal input terminal of the fifth C-unit CE5 is connected to the output terminal N10 of the tenth C-unit CE10, the output terminal N3 of the third C-unit CE3 is connected to the first input terminal of the fourth C-unit CE4 and the first input terminal of the eighth C-unit CE8; the second signal input terminal of the fourth C-unit CE4 is connected to the output terminal N11 of the eleventh C-unit CE11, the output terminal N4 of the fourth C-unit CE4 is connected to the first input terminal of the fifth C-unit CE5 and the second input terminal of the ninth C-unit The second signal input terminal is connected to the output terminal N12 of the twelfth C-unit CE12, the output terminal N5 of the fifth C-unit CE5 is connected to the first input terminal of the sixth C-unit CE6 and the first input terminal of the tenth C-unit CE10; the second signal input terminal of the sixth C-unit CE6 is connected to the output terminal N7 of the seventh C-unit CE7, and the output terminal N6 of the sixth C-unit CE6 is connected to the first input terminal of the eleventh C-unit CE11; the second signal input terminal of the seventh C-unit CE7 is connected to the output terminal N12 of the twelfth C-unit CE12, and the output terminal N7 of the seventh C-unit CE7 is connected to the second input terminal of the sixth C-unit CE6 and the second input terminal of the eighth C-unit CE8; the first signal input terminal of the ninth C-unit CE9 is connected to the output terminal N8 of the eighth C-unit CE8; the second signal input terminal of the tenth C-unit CE10 is connected to the output terminal N9 of the ninth C-unit CE9; the second signal input terminal of the eleventh C-unit CE11 is connected to the output terminal N10 of the tenth C-unit CE10; and the first signal input terminal of the twelfth C-unit CE12 is connected to the output terminal N11 of the eleventh C-unit CE11.

[0019] like Figure 1 、 2As shown, the signal output end of the first transmission gate TG1 is respectively connected to the first input end of the fourth C-unit CE4 and the first input end of the eighth C-unit CE8; the signal output end of the second transmission gate TG2 is respectively connected to the first signal input end of the sixth C-unit and the first input end of the tenth C-unit CE10; the signal output end of the third transmission gate TG3 is respectively connected to the second input end of the sixth C-unit CE6 and the second input end of the eighth C-unit CE8; the signal output end of the fourth transmission gate TG4 is respectively connected to the second input end of the second C-unit CE2 and the second input end of the tenth C-unit CE10.

[0020] The first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are each composed of a PMOS transistor and an NMOS transistor. The sources of the PMOS transistor and the NMOS transistor are connected together as the input of the transmission gate; the drains of the PMOS transistor and the NMOS transistor are connected together as the output of the transmission gate; the gate of the NMOS transistor is connected to the system clock signal CLK, and the gate of the PMOS transistor is connected to the reverse system clock signal NCK.

[0021] For the dual-loop structure storage module, for each C unit in the ring, if the input end of the next C unit connected to it has not been fed back, the output end of the C unit will be fed back to these input ends to be fed back until the corresponding input ends of all C units in the ring have been fed back.

[0022] Finally, all input terminals of all C units receive feedback, achieving loop interlocking.

[0023] like Figure 3 As shown, the twelve two-input C units have the same structure. The first C unit CE1 is composed of two PMOS transistors and two NMOS transistors. The two PMOS transistors include a first PMOS transistor MP11 and a second PMOS transistor MP12. The two NMOS transistors include a first NMOS transistor MN11 and a second NMOS transistor MN12.

[0024] The gate of the first PMOS transistor MP11 is connected to the gate of the first NMOS transistor MN11, and the connection point is the first signal input terminal of the first C unit CE1; the gate of the second PMOS transistor MP12 is connected to the gate of the second NMOS transistor MN12, and the connection point is the second signal input terminal of the first C unit CE1; the drain of the first PMOS transistor MP11 is connected to the source of the second PMOS transistor MP12; the drain of the second PMOS transistor MP12 is connected to the drain of the first NMOS transistor MN11; the source of the first NMOS transistor MN11 is connected to the drain of the second NMOS transistor MN12; the source of the first PMOS transistor MP11, the substrate of the first PMOS transistor MP11, and the substrate of the second PMOS transistor MP12 are all connected to the power supply VDD; the substrate of the first NMOS transistor MN11, the substrate of the second NMOS transistor MN12, and the source of the second NMOS transistor MN12 are all grounded.

[0025] When the system clock signal CLK = 0 and the inverse system clock signal NCK = 1, the signal output terminal N5 of the fifth C unit CE5 serves as the data output terminal of the latch; when the system clock signal CLK = 1 and the inverse system clock signal NCK = 0, the signal output terminal of the second transmission gate TG2 serves as the data output terminal of the latch.

[0026] The truth table of the two-input C-cell (the first C-cell CE1 to the twelfth C-cell CE12) is shown in Table 1 below:

[0027]

[0028] Table 1 above is the truth table for a two-input C-cell. As can be seen from this table, when the logic values ​​of the first and second signal inputs are the same, the signal output will output a logic value opposite to the input. When the logic values ​​of the first and second signal inputs are different, the signal output will enter a hold state and output the logic value of the previous state. This shows that the two-input C-cell (first C-cell CE1 through twelfth C-cell CE12) can be used to shield node logic value flips, preventing partial logic value flips at the signal inputs from propagating to the signal outputs. When the logic values ​​of both signal inputs flip, the logic value of the output will also flip. Therefore, the logic value of the output will only return to its original value when the logic values ​​of both signal inputs return to their original values.

[0029] The normal operating principle of the latch proposed in the present invention is described below.

[0030] When CLK = 1, NCK = 0, the structure works in transparent mode. At this time, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are turned on, and Q (N5), N3, N7, and N9 are initialized to the value of D. The above initialized nodes are then determined by the C unit. Figure 1 The values ​​of nodes N1, N2, N4, N6, N8, N10, N11, and N12, that is, all nodes are initialized.

[0031] When CLK = 0 and NCK = 1, the latch operates in latch mode, and the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are closed. Therefore, at this time, N3 is determined by the output end of the third C unit CE3, Q (N5) is determined by the output end of the fifth C unit CE5, N7 is determined by the output end of the seventh C unit CE7, and N9 is determined by the output end of the ninth C unit CE9. Because the values ​​of nodes N1, N2, N4, N6, N8, N10, N11, and N12 are initialized in transparent mode, in the cyclic storage module, nodes N3, Q (N5), N7, and N9 feed back to nodes N6, N8, and N10 via three two-input C-cells. Nodes N6, N8, and N10 feed back to nodes N1 and N11 via two two-input C-cells. Nodes N1, N3, N9, and N11 feed back to nodes N2, N4, and N12 via three two-input C-cells. Nodes N2, N4, N8, N10, and N12 then feed back to nodes N3, Q (N5), N7, and N9 via four two-input C-cells. This cyclic feedback loop forms several feedback loops. Therefore, the latch can effectively store data. In summary, the latch functions properly.

[0032] The fault-tolerant working principle of the latch proposed in the present invention is described below. First, the case of internal three-node upside-down (TNU) is discussed. According to the symmetry and loop feedback rule of the latch, it can be seen from analysis that the outer ring and the inner ring can be regarded as the same type, and each node in the ring has the same status. Therefore, only the following two representative cases need to be considered: (1) Three nodes simultaneously experience TNU on a ring; (2) Three nodes simultaneously experience TNU, two of which are on the same ring and the other is a single node on a ring;

[0033] Before analyzing the fault tolerance principle, we first introduce three properties:

[0034] Property 1: For any two-input C unit, when all its inputs are correct values, it will output the correct value regardless of whether its output is affected.

[0035] Property 2: For any two-input C unit, when one of its inputs is flipped and its output is not flipped, it will still output the correct value.

[0036] Property 3: For any two-input C-unit, if both inputs are flipped, it will output an incorrect value. If one input and output are flipped simultaneously, it will maintain the incorrect output. In this case, the flipped input must be restored first, and then it will output the correct value.

[0037] For the case (1), due to the cyclic characteristics of the cyclic storage module, the key TNU sequence can be selected<N1,N2,N3> ,<N1,N2,N4> ,<N1,N3,N5> .

[0038] when<N1,N2,N3> When a TNU occurs, the second C-cell CE2 and the third C-cell CE3 satisfy Property 3, the fourth C-cell CE4 satisfies Property 2, and the remaining C-cells satisfy Property 1. Therefore, all CEs except the second C-cell CE2 and the third C-cell CE3 can output correct values. Obviously, the sixth C-cell CE6 and the eighth C-cell CE8 will output correct values, so N1 is restored to its original value first. Subsequently, the inputs of the second C-cell CE2 are all restored to their original values, and N2 is restored to its original value. Similarly, N3 is also restored to its original value, that is,<N1,N2,N3> It is possible to recover from TNU.

[0039] when<N1,N2,N4> When a TNU occurs, the second C-cell CE2 satisfies Property 3, the third and fifth C-cells CE3 and CE5 satisfy Property 2, and the remaining C-cells satisfy Property 1. Therefore, all CEs except the second C-cell CE2 can output correct values. Obviously, the sixth and eighth C-cells CE6 and CE8 will also output correct values, so N1 is restored to its original value first. Similarly, N4 can also be restored to its original value. Subsequently, the inputs of the second C-cell CE2 are all restored to their original values, and N2 is restored to its original value, that is,<N1,N2,N4> It is possible to recover from TNU.

[0040] when<N1,N3,N5> When TNU occurs, the second C cell CE2, the fourth C cell, the sixth C cell, the eighth C cell, the tenth C cell, and the twelfth C cell satisfy Property 2, and all other C cells satisfy Property 1. Obviously, the sixth C cell CE6 and the eighth C cell CE8 will output the correct value, so N1 is restored to its original value first. Similarly, N3 and N5 are restored to their original values, that is,<N1,N2,N3> It can be recovered from TNU. After analysis, it can be seen that the latch can realize the TNU self-recovery function in this situation.

[0041] For the case (2), due to the cyclic characteristics of the cyclic storage module, the key TNU sequence can be selected<N1,N2, N8> ,<N1, N2, N9> ,<N1, N3, N10> ,<N1, N3, N9> .

[0042] when<N1,N2, N8> When a TNU occurs, the first C-cell CE1 and the second C-cell CE2 satisfy Property 3, the twelfth C-cell CE12, the third C-cell CE3, and the ninth C-cell CE9 satisfy Property 2, and the remaining C-cells satisfy Property 1. Therefore, all CEs except the first C-cell CE1 and the second C-cell can output correct values. Obviously, the outputs of the third C-cell CE3 and the seventh C-cell CE7 remain at their original values, and N8 is restored to its original value. Subsequently, the input of the first C-cell is restored to its original value, N1 is restored to its original value, and similarly, N2 is restored to its original value, that is,<N1,N2, N8> Can recover from TNU

[0043] when<N1, N2, N9> When a TNU occurs, the second C-unit CE2 satisfies Property 3, the third C-unit CE3, the fourth C-unit CE4, the eighth C-unit CE8, the tenth C-unit CE10, and the twelfth C-unit CE12 satisfy Property 2, and the remaining C-units satisfy Property 1. Therefore, all CEs except the second C-unit CE2 can output correct values. Obviously, the outputs of the sixth C-unit CE6 and the eighth C-unit CE8 remain at their original values, so N1 is restored to its original value, and similarly, N9 is restored to its original value. The outputs of the first C-unit CE1 and the ninth C-unit CE9 are all restored to their original values, and N2 is restored to its original value, that is,<N1, N2, N9> It is possible to recover from TNU.

[0044] when<N1, N3, N10> When a TNU occurs, the third C-cell CE3 satisfies Property 3, the second C-cell CE2, the fourth C-cell CE4, the eighth C-cell CE8, the eleventh C-cell CE11, and the twelfth C-cell CE12 satisfy Property 2, and the remaining C-cells satisfy Property 1. Therefore, all CEs except the third C-cell CE3 can output correct values. Obviously, the input to the first C-cell CE1 remains at its original value, so N1 is restored to its original value. Similarly, if N10 is restored to its original value, the input to the third C-cell CE3 is restored to its original value, and N3 is restored to its original value. In other words, <N1, N3, N10> can recover from TNU.

[0045] when<N1, N3, N9> When TNU occurs, the second C unit CE2 satisfies property 3, N2 flips and outputs an incorrect value, the fourth C unit CE4, the eighth C unit CE8, the tenth C unit CE10 and the twelfth C unit CE12 satisfy property 2, and the other C units satisfy property 1. Therefore, all CEs except the second C unit CE2 can output correct values. Obviously, the input of the first C unit CE1 is still the original value, so N1 is restored to the original value, and similarly, N9 is restored to the original value. If the input of the second C unit CE2 input terminal all changes to the original value, then N2 is restored to the original value. If the input of the third C unit CE3 input terminal all changes to the original value, then N3 is restored to the original value, that is,<N1, N3, N9> It can be recovered from TNU. After analysis, it can be seen that the latch can realize the TNU self-recovery function in this situation.

[0046] From the above analysis, we can see that the latch is completely self-recoverable when any three nodes are flipped. Obviously, single-node flip and double-node flip must also be self-recoverable.

[0047] In summary, the present invention improves the reliability of latch circuits. Compared to existing latches, the present invention reduces area and power consumption, improves latch tolerance, and offers superior performance. Furthermore, since there is only one transmission gate between the input terminals in transparent mode, the present invention establishes a more efficient path, resulting in low transmission delay. The present invention is suitable for integrated circuits and systems with high reliability requirements in strong radiation environments and can be widely used in fields such as nuclear testing and aerospace, where high latch reliability is required.

Claims

1. A three-node flip self-recovery latch based on a loop feedback C unit, characterized in that: It comprises a dual-loop structure storage module and four transmission gates, wherein the dual-loop structure storage module is composed of twelve two-input C units, the twelve two-input C units include a first C unit CE1, a second C unit CE2, a third C unit CE3, a fourth C unit CE4, a fifth C unit CE5, a sixth C unit CE6, a seventh C unit CE7, an eighth C unit CE8, a ninth C unit CE9, a tenth C unit CE10, an eleventh C unit CE11 and a twelfth C unit CE12; the four transmission gates include a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3 and a fourth transmission gate TG4; the signal input ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are all used as data input ends D of the latch, and the output end of the fifth C unit CE5 is used as the data output end of the latch; The signal output end of the first transmission gate TG1 is respectively connected to the first input end of the fourth C unit CE4 and the first input end of the eighth C unit CE8; the signal output end of the second transmission gate TG2 is respectively connected to the first signal input end of the sixth C unit and the first input end of the tenth C unit CE10; the signal output end of the third transmission gate TG3 is respectively connected to the second input end of the sixth C unit CE6 and the second input end of the eighth C unit CE8; the signal output end of the fourth transmission gate TG4 is respectively connected to the second input end of the second C unit CE2 and the second input end of the tenth C unit CE10; The first signal input terminal of the first C unit CE1 is connected to the output terminal N6 of the sixth C unit CE6, the second signal input terminal of the first C unit CE1 is connected to the output terminal N8 of the eighth C unit CE8, the output terminal N1 of the first C unit CE1 is connected to the first input terminal of the second C unit CE2 and the second input terminal of the twelfth C unit CE12; the second signal input terminal of the second C unit CE2 is connected to the output terminal N9 of the ninth C unit CE9, the output terminal N2 of the second C unit CE2 is connected to the first input terminal of the third C unit CE3 and the first input terminal of the seventh C unit CE7; the second signal input terminal of the third C unit CE3 is connected to the output terminal N10 of the tenth C unit CE10, the output terminal N3 of the third C unit CE3 is connected to the first input terminal of the fourth C unit CE4 and the first input terminal of the eighth C unit CE8; the second signal input terminal of the fourth C unit CE4 is connected to the output terminal N11 of the eleventh C unit CE11, the output terminal N4 of the fourth C unit CE4 is connected to the first input terminal of the fifth C unit CE5 and the second input terminal of the ninth C unit CE9; The second signal input terminal is connected to the output terminal N12 of the twelfth C unit CE12, the output terminal N5 of the fifth C unit CE5 is connected to the first input terminal of the sixth C unit CE6 and the first input terminal of the tenth C unit CE10; the second signal input terminal of the sixth C unit CE6 is connected to the output terminal N7 of the seventh C unit CE7, and the output terminal N6 of the sixth C unit CE6 is connected to the first input terminal of the eleventh C unit CE11; the second signal input terminal of the seventh C unit CE7 is connected to the output terminal N12 of the twelfth C unit CE12, and the output terminal N7 of the seventh C unit CE7 is connected to the second input terminal of the sixth C unit CE6 and the second input terminal of the eighth C unit CE8; the first signal input terminal of the ninth C unit CE9 is connected to the output terminal N8 of the eighth C unit CE8; the second signal input terminal of the tenth C unit CE10 is connected to the output terminal N9 of the ninth C unit CE9; the second signal input terminal of the eleventh C unit CE11 is connected to the output terminal N10 of the tenth C unit CE10; the first signal input terminal of the twelfth C unit CE12 is connected to the output terminal N11 of the eleventh C unit CE11.

2. The three-node flip self-recovery latch based on the loop feedback C unit according to claim 1, characterized in that: The first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are each composed of a PMOS transistor and an NMOS transistor, the sources of the PMOS transistor and the NMOS transistor are connected together as the input of the transmission gate; the drains of the PMOS transistor and the NMOS transistor are connected together as the output of the transmission gate; the gate of the NMOS transistor is connected to the system clock signal CLK, and the gate of the PMOS transistor is connected to the reverse system clock signal NCK.

3. The three-node flip self-recovery latch based on the loop feedback C unit according to claim 1, characterized in that: The twelve two-input C units have the same structure. The first C unit CE1 is composed of two PMOS tubes and two NMOS tubes. The two PMOS tubes include a first PMOS tube MP11 and a second PMOS tube MP12. The two NMOS tubes include a first NMOS tube MN11 and a second NMOS tube MN12. Among them, the gate of the first PMOS tube MP11 is connected to the gate of the first NMOS tube MN11, and the connection point is the first signal input terminal of the first C unit CE1; the gate of the second PMOS tube MP12 is connected to the gate of the second NMOS tube MN12, and the connection point is the second signal input terminal of the first C unit CE1; the drain of the first PMOS tube MP11 is connected to the source of the second PMOS tube MP12; the drain of the second PMOS tube MP12 is connected to the drain of the first NMOS tube MN11; the source of the first NMOS tube MN11 is connected to the drain of the second NMOS tube MN12; the source of the first PMOS tube MP11, the substrate of the first PMOS tube MP11, and the substrate of the second PMOS tube MP12 are all connected to the power supply VDD; the substrate of the first NMOS tube MN11, the substrate of the second NMOS tube MN12, and the source of the second NMOS tube MN12 are all grounded.

4. The three-node flip self-recovery latch based on the loop feedback C unit according to claim 1, characterized in that: When the system clock signal CLK = 0 and the reverse system clock signal NCK = 1, the signal output terminal N5 of the fifth C unit CE5 serves as the data output terminal of the latch; When the system clock signal CLK=1 and the inverse system clock signal NCK=0, the signal output end of the second transmission gate TG2 serves as the data output end of the latch.

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