A comparator and analog-to-digital converter based on a pre-amplification stage structure

Abstract

This invention relates to the field of integrated circuit technology and provides a comparator and analog-to-digital converter based on a pre-amplification stage structure. The comparator includes: a first pre-amplification stage, whose input terminal is connected to a differential input signal, amplifying the differential input signal and outputting a first differential output signal; a second pre-amplification stage, whose input terminal is connected to the first differential output signal, amplifying the first differential output signal and outputting a second differential output signal, and a positive feedback unit is provided between its output terminal and its input terminal to improve the voltage gain of the second pre-amplification stage; and a latch, whose input terminal is connected to the second differential output signal. By improving the voltage gain of the second pre-amplification stage through the positive feedback unit, especially improving the voltage gain of small signals, the equivalent input noise of the comparator can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a comparator and analog-to-digital converter based on a pre-amplification stage structure. Background Technology

[0002] In recent years, with the continuous development of integrated circuit manufacturing technology, the feature size of CMOS devices has been continuously reduced, and the operating voltage of integrated circuits has also been continuously lowered. Under deep submicron processes, the operating speed of analog-to-digital converters (ADCs) has been greatly improved, while power consumption has been further reduced. However, as a core component of ADCs, the performance of comparators has become a bottleneck in high-speed, low-power design. Traditional comparator structures struggle to simultaneously meet the requirements of speed, power consumption, and low supply voltage.

[0003] In applications with lower precision requirements, a single-stage latch structure can be used as the comparator structure. The advantages of this structure are high speed and low power consumption, but its disadvantages include relatively high noise and offset. In applications with higher precision requirements, to mitigate the high noise and high offset of the single-stage latch structure, the comparator is typically composed of multiple cascaded preamplifier stages connected to the latch stage. However, the disadvantage of using a structure with multiple cascaded preamplifier stages connected to the latch stage is that, during the comparator's reset process, the presence of capacitors at the output of the preamplifier stages significantly reduces the comparator's reset speed and increases its power consumption. Summary of the Invention

[0004] This invention provides a comparator and analog-to-digital converter based on a pre-amplification stage structure to solve the problem of high noise in comparators in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a comparator based on a pre-amplification stage structure, comprising:

[0006] The first pre-amplifier stage has a differential input signal connected to its input terminal, amplifies the differential input signal, and outputs a first differential output signal.

[0007] The second pre-amplifier stage has its input terminal connected to the first differential output signal, amplifies the first differential output signal, outputs the second differential output signal, and has a positive feedback unit between its output terminal and its input terminal to improve the voltage gain of the second pre-amplifier stage.

[0008] A latch, the input of which is connected to the second differential output signal.

[0009] Optionally, the comparator based on the pre-amplification stage structure further includes a pre-amplification stage, which is connected in series between the first pre-amplification stage and the second pre-amplification stage.

[0010] Optionally, the comparator based on the pre-amplification stage structure further includes N pre-amplification stages, where N is an integer greater than or equal to 2. The N pre-amplification stages are cascaded and connected in series between the first pre-amplification stage and the second pre-amplification stage.

[0011] Optionally, the structure of the N pre-amplification stages is the same as that of the second pre-amplification stage.

[0012] Optionally, the first pre-amplification stage includes:

[0013] First NMOS transistor, second NMOS transistor, third NMOS transistor, first PMOS transistor, and second PMOS transistor;

[0014] The source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the first control signal, and the drain of the first NMOS transistor is connected to the first node.

[0015] The source of the second NMOS transistor is connected to the first node, the gate of the second NMOS transistor is connected to the differential input signal, and the drain of the second NMOS transistor is connected to the second node.

[0016] The source of the third NMOS transistor is connected to the first node, the gate of the third NMOS transistor is connected to the differential input signal, and the drain of the third NMOS transistor is connected to the third node.

[0017] The drain of the first PMOS transistor is connected to the second node, the gate of the first PMOS transistor is connected to the first control signal, and the source of the first PMOS transistor is connected to the operating voltage.

[0018] The drain of the second PMOS transistor is connected to the third node, the gate of the second PMOS transistor is connected to the first control signal, and the source of the second PMOS transistor is connected to the operating voltage.

[0019] The first differential output signal is output through the second node and the third node.

[0020] Optionally, the second pre-amplification stage includes a pre-amplification stage main unit and the positive feedback unit, wherein the positive feedback unit includes:

[0021] The fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor;

[0022] The gate of the fourth NMOS transistor is connected to the fourth node, the source of the fourth NMOS transistor is connected to the fifth node, and the drain of the fourth NMOS transistor is connected to the gate of the seventh NMOS transistor.

[0023] The source of the fifth NMOS transistor is connected to the fifth node, the gate of the fifth NMOS transistor is connected to the sixth node, and the drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor.

[0024] The source of the sixth NMOS transistor is connected to the sixth node, and the drain of the sixth NMOS transistor is connected to the seventh node.

[0025] The source of the seventh NMOS transistor is connected to the fourth node, and the drain of the seventh NMOS transistor is connected to the eighth node.

[0026] Optionally, the pre-amplification stage main unit includes:

[0027] The eighth NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor;

[0028] The source of the eighth NMOS transistor is grounded, and the drain of the eighth NMOS transistor is connected to the fifth node;

[0029] The second control signal is connected to the gate of the eighth NMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor, respectively, and the operating voltage is connected to the source of the third PMOS transistor, the source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor, respectively.

[0030] The drain of the third PMOS transistor is connected to the eighth node, the drain of the fourth PMOS transistor is connected to the seventh node, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor.

[0031] The first differential output signal is connected to the fourth node and the sixth node respectively, and the second differential output signal is output through the seventh node and the eighth node.

[0032] Optionally, the latch includes a sampling unit and a holding unit;

[0033] The input terminal of the sampling unit is connected to the sixth node and the eighth node respectively, and the sampling unit samples the second differential output signal;

[0034] The output of the sampling unit is connected to the holding unit, and the holding unit holds the second differential output signal.

[0035] Optionally, the first control signal and the second control signal are the same control signal.

[0036] To achieve the above and other related objectives, the present invention provides an analog-to-digital converter, which includes the comparator based on the pre-amplification stage structure described above.

[0037] The beneficial effects of the present invention are as follows: The comparator based on the pre-amplification stage structure in the present invention includes a first pre-amplification stage and a second pre-amplification stage. By setting a positive feedback unit between the input and output terminals of the second pre-amplification stage, the voltage gain of the second pre-amplification stage is improved, especially the voltage gain of small signals, thereby effectively reducing the equivalent input noise of the comparator. Attached Figure Description

[0038] Figure 1 The diagram shows the principle of a multi-stage cascaded comparator.

[0039] Figure 2 The circuit diagram shown is a traditional cascaded comparator consisting of a preamplifier stage and a latch stage.

[0040] Figure 3 The circuit diagram shows a high-precision comparator cascaded with a traditional first-stage preamplifier and a first-stage latch.

[0041] Figure 4 This is shown as a comparator based on a pre-amplification stage structure in this invention;

[0042] Figure 5 The diagram shown is the input impedance circuit diagram of the second pre-amplification stage in this invention and its small-signal circuit equivalent diagram.

[0043] Figure 6 The diagram shown is the output impedance circuit diagram of the second pre-amplification stage in this invention and its small-signal circuit equivalent diagram.

[0044] Figure 7 The diagram shows the noise equivalent circuit of the first and second pre-amplification stage half circuits in this invention.

[0045] Figure 8 The graph shows a comparison of the equivalent input noise of the three comparators in this invention as a function of temperature. Detailed Implementation

[0046] As mentioned in the background section, in applications requiring high precision, to suppress the high noise and high offset drawbacks of single-stage latch structures, comparators are typically composed of multiple cascaded preamplifier stages connected to the latch stage. The preamplifier stages provide higher gain to suppress the equivalent input noise of the comparator; and the slower change in the output signal of the preamplifier stages suppresses the comparator's offset. Figure 1As shown, the first input signal Vip and the second input signal Vin are amplified by multiple preamplification stages (Preamp-1, Preamp-2, ..., Preamp-n) before being input to the latch, so that the large noise and large offset of the latch will not affect the comparison accuracy of the comparator.

[0047] To describe the above issues in more detail, we will take the cascade of a preamplifier stage and a latch stage as an example to analyze the working principle and advantages and disadvantages of the two traditional comparator structures.

[0048] Figure 2 The circuit diagram shown is a traditional cascaded comparator consisting of a preamplifier stage and a latch stage, as follows: Figure 2 As shown, NMOS transistors N1, N2, N3, PMOS transistors P1 and P2 constitute the pre-amplifier stage. NMOS transistor N1 is the tail current transistor, NMOS transistors N2 and N3 are the input transistors, and PMOS transistors P1 and P2 are the load transistors. NMOS transistors N4, N5, N6, N7, N8, N9, PMOS transistors P3, P4, P5, and P6 constitute the latch. When the comparator is in the reset state, the control signal clk is 0 (low level), which turns off NMOS transistors N1, N4, and N7, resulting in no static power consumption for the entire comparator. When the comparator is in the comparison state, the control signal clk is 1 (high level), and the DC gain A of the pre-amplifier stage can be expressed as:

[0049] A = g m ·(r oN2,N3 ||r oP1,P2 (1)

[0050] Where gm represents the transconductance of NMOS transistors N2 and NMOS transistor N3, r oN2,N3 r represents the small-signal equivalent output impedance of NMOS transistors N2 and N3. oP1,P2 This represents the small-signal equivalent output impedance of PMOS transistors P1 and P2.

[0051] At this point, the dominant pole p of the preamplification stage can be expressed as:

[0052] p = 1 / (r oN2,N3 ||r oP1,P2 (2)

[0053] Where Cp represents the load capacitance at the output of the pre-amplifier stage.

[0054] The advantages of this comparator are its high speed and low power consumption, but its disadvantages are its large noise and offset. According to the calculation formula of the equivalent input noise of the preamplifier stage, the equivalent input noise of the preamplifier stage can be reduced by increasing the DC gain A of the preamplifier stage or decreasing the bandwidth of the preamplifier stage. As shown in equation (1), after the design of the preamplifier stage is completed, the transconductance gm of the input tube, the small-signal equivalent output impedance roN2,N3 of the input tube and the small-signal equivalent output impedance roP1,P2 of the load tube are all fixed, and it is difficult to increase the DC gain A of the preamplifier stage. At the same time, since the bandwidth of the preamplifier stage is related to the dominant pole p, reducing the dominant pole p can reduce the bandwidth accordingly. Therefore, if the equivalent input noise of the preamplifier stage is to be reduced, it can be achieved by reducing the dominant pole p of the preamplifier stage. As shown in equation (2), the load capacitance Cp of the preamplifier stage needs to be increased.

[0055] Based on the above analysis, a high-precision comparator is proposed, such as... Figure 3 As shown, in Figure 2 Based on the cascaded comparator structure of a preamplifier stage and a latch stage shown, a capacitor C is added at the output of the preamplifier stage (at nodes 1 and 2), thereby increasing the load capacitance Cp of the preamplifier stage, reducing its bandwidth, and effectively suppressing the equivalent input noise of the preamplifier stage. However, after the output voltage of the preamplifier stage is amplified, noise is no longer the main factor limiting the comparator's performance. Furthermore, during the comparator's reset process, the presence of capacitor C at the output of the preamplifier stage significantly reduces the comparator's reset speed and increases its power consumption.

[0056] Therefore, the inventors proposed a new concept: a comparator based on a pre-amplification stage structure includes a first pre-amplification stage and a second pre-amplification stage. By setting a positive feedback unit between the input and output of the second pre-amplification stage, the voltage gain of the second pre-amplification stage is improved, especially the voltage gain of small signals, so as to reduce the equivalent input noise of the comparator.

[0057] Specifically, the present invention provides a comparator based on a pre-amplification stage structure, comprising: a first pre-amplification stage, the input of which is connected to a differential input signal, amplifying the differential input signal and outputting a first differential output signal; a second pre-amplification stage, the input of which is connected to the first differential output signal, amplifying the first differential output signal and outputting a second differential output signal, wherein a positive feedback unit is provided between the output and input of the second pre-amplification stage, thereby increasing the voltage gain of the second pre-amplification stage; and a latch, the input of which is connected to the second differential output signal.

[0058] Optionally, the comparator based on the pre-amplification stage structure further includes a pre-amplification stage connected in series between the first and second pre-amplification stages. Optionally, the structure of the pre-amplification stage is the same as that of the second pre-amplification stage. Optionally, the structure of the pre-amplification stage is the same as that of the first pre-amplification stage.

[0059] Optionally, the comparator based on the pre-amplification stage structure further includes N pre-amplification stages, where N is an integer greater than or equal to 2. The N pre-amplification stages are cascaded and connected in series between the first and second pre-amplification stages. Optionally, the structure of the N pre-amplification stages is the same as the structure of the second pre-amplification stage. Optionally, the structure of the N pre-amplification stages is the same as the structure of the first pre-amplification stage.

[0060] Furthermore, the present invention also provides an analog-to-digital converter, which includes the comparator based on the pre-amplification stage structure, thereby improving the working efficiency of the analog-to-digital converter through fast and accurate comparison by the comparator based on the pre-amplification stage structure.

[0061] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0062] Please see Figures 4 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0063] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0064] Please see Figure 4 The first preamplifier stage includes a first NMOS transistor M0, a second NMOS transistor M1, a third NMOS transistor M2, a first PMOS transistor M3, and a second PMOS transistor M4. The source of the first NMOS transistor M0 is grounded, its gate is connected to the first control signal Clk, and its drain is connected to the first node a. The source of the second NMOS transistor M1 is connected to the first node a, its gate is connected to the positive terminal Vinp of the differential input signal, and its drain is connected to the second node b. The source of the third NMOS transistor M2 is connected to the first node a, and its gate is connected to the positive terminal Vinp of the differential input signal. The negative terminal Vinn of the input signal is connected, and the drain of the third NMOS transistor M2 is connected to the third node c; the drain of the first PMOS transistor M3 is connected to the second node b, the gate of the first PMOS transistor M3 is connected to the first control signal Clk, and the source of the first PMOS transistor M3 is connected to the working voltage Vdd; the drain of the second PMOS transistor M4 is connected to the third node c, the gate of the second PMOS transistor M4 is connected to the first control signal Clk, and the source of the second PMOS transistor M4 is connected to the working voltage Vdd; the first differential output signal is output through the second node b and the third node c, with the second node b serving as the negative terminal of the first differential output signal and the third node c serving as the positive terminal of the first differential output signal.

[0065] The second preamplifier stage includes a preamplifier stage main unit and a positive feedback unit. The positive feedback unit includes: a fourth NMOS transistor M6, a fifth NMOS transistor M7, a sixth NMOS transistor M8, and a seventh NMOS transistor M9. The gate of the fourth NMOS transistor M6 is connected to the fourth node d, the source of the fourth NMOS transistor M6 is connected to the fifth node e, and the drain of the fourth NMOS transistor M6 is connected to the gate of the seventh NMOS transistor M9. The source of the fifth NMOS transistor M7 is connected to the fifth node e, the gate of the fifth NMOS transistor M7 is connected to the sixth node f, and the drain of the fifth NMOS transistor M7 is connected to the gate of the sixth NMOS transistor M8. The source of the sixth NMOS transistor M8 is connected to the sixth node f, and the drain of the sixth NMOS transistor M8 is connected to the seventh node g. The source of the seventh NMOS transistor M9 is connected to the fourth node d, and the drain of the seventh NMOS transistor M9 is connected to the eighth node h. The preamplification stage main unit includes: an eighth NMOS transistor M5, a third PMOS transistor M10, a fourth PMOS transistor M11, a fifth PMOS transistor M12, and a sixth PMOS transistor M13; the source of the eighth NMOS transistor M5 is grounded, and the drain of the eighth NMOS transistor M5 is connected to the fifth node e; the second control signal Clk is connected to the gates of the eighth NMOS transistor M5, the third PMOS transistor M10, the fourth PMOS transistor M11, the fifth PMOS transistor M12, and the sixth PMOS transistor M13, respectively; and the operating voltage Vdd is connected to the sources of the third PMOS transistor M10, the fourth PMOS transistor M11, the fifth PMOS transistor M12, and the sixth PMOS transistor M13, respectively. The source of transistor M13 is connected; the drain of the third PMOS transistor M10 is connected to the eighth node h, the drain of the fourth PMOS transistor M11 is connected to the seventh node g, the drain of the fifth PMOS transistor M12 is connected to the drain of the fourth NMOS transistor M6, and the drain of the sixth PMOS transistor M13 is connected to the drain of the fifth NMOS transistor; the first differential output signal is connected to the fourth node d and the sixth node f respectively, wherein the negative terminal Vn of the first differential output signal is connected to the sixth node f, and the positive terminal Vp of the first differential output signal is connected to the fourth node d; the second differential output signal is output through the seventh node g and the eighth node h, wherein the positive terminal Vop of the second differential output signal is connected to the eighth node h, and the negative terminal Von of the second differential output signal is connected to the seventh node g. The positive terminal Vop and the negative terminal Von of the second differential output signal are connected to the input terminal of the latch, and the latch outputs the third differential output signals Voutp and Voutn. The output terminals Voutp and Voutn of the latch structure are the output terminals of the entire comparator.

[0066] Optionally, the first control signal and the second control signal are the same control signal. Optionally, the latch includes a sampling unit and a holding unit; the input terminals of the sampling unit are connected to the sixth node and the eighth node respectively, and the sampling unit samples the second differential output signal; the output terminal of the sampling unit is connected to the holding unit, and the holding unit holds the second differential output signal.

[0067] Please see Figure 5 , Figure 6 and Figure 7 First, calculate the input impedance of the second pre-amplifier stage. The input stage circuit diagram of the second pre-amplifier stage and its small-signal equivalent circuit are as follows: Figure 5 As shown. According to Kirchhoff's current law for the gate of the seventh NMOS transistor M9:

[0068]

[0069] Among them, i x For the input current of this stage, g m9 For the gate transconductance of M9, v mb9 For the substrate transconductance of M9, v x For the input voltage, r o9 The small-signal output impedance of M9;

[0070]

[0071] Among them, g m6 For the gate transconductance of M6, r o6 for;

[0072] Therefore, the input impedance of the second preamplifier stage can be expressed as the small-signal output impedance of M6:

[0073]

[0074] Among them, R in,2 This is the input impedance of the second pre-amplification stage;

[0075] Since the gain of the first preamplifier stage can be expressed as:

[0076]

[0077] Among them, A v1 For the gain of the first preamplification stage, g m2 The gate transconductance of M2;

[0078] To calculate the small-signal voltage gain of the second pre-amplification stage, it is necessary to calculate the transconductance G of the second pre-amplification stage. m,1 Regarding the output impedance, Kirchhoff's current law for the drain of M9 indicates that:

[0079]

[0080] Among them, i out This is the output current of this stage, v gs9 The gate-source voltage of M9, v bs9 The substrate-source voltage of M9;

[0081]

[0082]

[0083] Among them, G m,2 It is the transconductance of the second stage;

[0084] As can be seen from equation (9), the transconductance of the second preamplifier stage is very large. By comparing equations (5) and (9), the input impedance and transconductance of the second preamplifier stage are inversely related, which can be expressed as:

[0085]

[0086] Next, the total transconductance of the first and second pre-amplification stages needs to be calculated, from... Figure 5 It can be known that:

[0087]

[0088] Among them, v id This is the input current for this stage;

[0089]

[0090] Among them, G m,total This represents the total transconductance of the first and second pre-amplification stages.

[0091]

[0092] From equations (10) and (13), the total transconductance can be expressed as:

[0093]

[0094] Among them, i out,dif The output current for this level is a small signal current.

[0095] To calculate the equivalent output impedance of the second pre-amplifier stage, its small-signal equivalent circuit is as follows: Figure 6 As shown, according to Kirchhoff's law for the drain of M9:

[0096]

[0097] Among them, v gs6 for;

[0098]

[0099] Therefore, the equivalent output impedance of the second pre-amplification stage can be expressed as:

[0100] R out,2 =g m9 r o9 g m6 r o6 r o2 +(g m9 +g mb9 )r o9 r o2 +r o9 +r o2 (17)

[0101] Where Rout,2 is the equivalent output impedance of the second pre-amplification stage;

[0102] Therefore, the gain of the second preamplifier stage can be expressed as:

[0103]

[0104] Among them, A v2 This is the gain of the second pre-amplification stage;

[0105] It can be obtained that the total gain of the first preamplifier stage and the second preamplifier stage can be expressed as:

[0106]

[0107] Among them, A v,total This is the total gain of the first and second pre-amplification stages;

[0108] As can be seen from equation (19), the first two pre-amplification stages proposed in this invention can provide a large small signal voltage gain. Therefore, the pre-amplification stage of this structure can provide high accuracy.

[0109] The noise performance of this structure is analyzed below, with calculations performed using half-circuit as an example. The noise equivalent circuits for the first and second pre-amplifier stages are shown below. Figure 7 As shown.

[0110] v n1 =(I n2 +I n9 )(r o2 ||R in,2 )≈(I n2 +I n9 )R in,2 (20)

[0111] Among them, v n1 I is the output noise voltage of M2.n2 I is the output noise current of M2. n9 This refers to the output noise current of M9.

[0112] r o2 R is the small-signal output impedance of M2. in,2 This is the equivalent impedance of the gate of M6;

[0113] v n2 =I n6 r o6 +v n1 g m6 r o6 =I n6 r o6 +(I n2 +I n9 )R in,2 g m6 r o6 (twenty one)

[0114] Among them, v n2 I is the output noise voltage of this stage. n6 r is the output noise current of this stage. o6 For the small-signal output impedance of M6, g m6 For the gate transconductance of M6, R in,2 This is the equivalent impedance of the gate of M6;

[0115] Therefore, we can obtain:

[0116] v n,out =I n9 r o9 +g m9 r o9 I n6 r o6 +r o9 (I n2 +I n9 )R in,2 (g m9 +g mb9 +g m9 g m6 r o6 ) (twenty two)

[0117] Among them, v n,out The output noise voltage of this stage, g m9 For the gate transconductance of M9, r o9 For the small-signal output resistor of M9, g mb9 The substrate transconductance of M9;

[0118] Substituting equation (5) into equation (22), we get:

[0119]

[0120] in, γ is the equivalent output noise of the first two pre-amplification stages, k is the Boltzmann constant, T is the temperature, and γ is a constant.

[0121] Therefore, the equivalent input noise of the first two pre-amplification stages can be expressed as:

[0122]

[0123] in, This is the equivalent input noise for the first two pre-amplification stages.

[0124] As can be seen from equation (24), due to the existence of a large small signal voltage gain, the equivalent input noise of the preamplifier stage of this structure is significantly reduced.

[0125] Please see Figure 8 In one specific embodiment, using a 180nm CMOS process, the above... Figure 2 , Figure 3 and Figure 4 The structure was carefully designed, using the same input / output transistor dimensions for all three structures, as well as the same latch structure dimensions, and a load capacitance of 10fF for all. The clock frequency is 1.8GHz, the power supply voltage is 1.8V, and the common-mode voltage is 0.9V. The comparator is considered to have completed the comparison when |Dp-Dn|=0.9V. The comparison curves of the three comparator structures as a function of the input differential signal ΔVin are shown below. Figure 8 As shown. The clock frequency is 40MHz, the power supply voltage is 1.8V, and the comparator is considered to have completed the comparison when |Dp-Dn|=0.9V. Through transient noise simulation, the equivalent input noise of the above three comparator structures as a function of temperature is compared as shown in the graph. Figure 8 As shown in the simulation results, the low-noise comparator based on the load adjustment technology proposed in this invention reduces the equivalent input noise by at least 60% compared to several traditional structures. The simulation results demonstrate that this technology achieves an improvement in the accuracy of high-speed comparators. Figure 8 [1] is Figure 2 The structure, [2] is Figure 3 The structure of this technology is Figure 4 The structure.

[0126] Therefore, the comparator based on the pre-amplification stage structure introduces a positive feedback unit on the basis of the pre-amplification stage. The positive feedback unit improves the voltage gain of the second pre-amplification stage, especially the voltage gain of small signals, thereby effectively reducing the equivalent input noise of the comparator.

[0127] The present invention also provides an analog-to-digital converter, which includes the comparator based on the pre-amplification stage structure described above.

[0128] The present invention also provides an electronic device, which includes the analog-to-digital converter described above.

[0129] In summary, the comparator based on the pre-amplification stage structure of the present invention improves the voltage gain of the second pre-amplification stage, especially the voltage gain of small signals, by setting a positive feedback unit between the input and output terminals of the second pre-amplification stage, thereby effectively reducing the equivalent input noise of the comparator.

[0130] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A comparator based on a pre-amplification stage structure, characterized in that, At least including: The first pre-amplifier stage has a differential input signal connected to its input terminal, amplifies the differential input signal, and outputs a first differential output signal. The second pre-amplifier stage has its input terminal connected to the first differential output signal, amplifies the first differential output signal, outputs the second differential output signal, and has a positive feedback unit between its output terminal and its input terminal to improve the voltage gain of the second pre-amplifier stage. A latch, the input of which is connected to the second differential output signal; The first pre-amplification stage includes: First NMOS transistor, second NMOS transistor, third NMOS transistor, first PMOS transistor, and second PMOS transistor; The source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the first control signal, and the drain of the first NMOS transistor is connected to the first node. The source of the second NMOS transistor is connected to the first node, the gate of the second NMOS transistor is connected to the differential input signal, and the drain of the second NMOS transistor is connected to the second node. The source of the third NMOS transistor is connected to the first node, the gate of the third NMOS transistor is connected to the differential input signal, and the drain of the third NMOS transistor is connected to the third node. The drain of the first PMOS transistor is connected to the second node, and the gate of the first PMOS transistor is connected to the first control signal. The source of the first PMOS transistor is connected to the operating voltage; The drain of the second PMOS transistor is connected to the third node, and the gate of the second PMOS transistor is connected to the first control signal. The source of the second PMOS transistor is connected to the operating voltage; The first differential output signal is output through the second node and the third node; The second pre-amplification stage includes a pre-amplification stage main unit and the positive feedback unit, wherein the positive feedback unit includes: The fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor; The gate of the fourth NMOS transistor is connected to the fourth node, the source of the fourth NMOS transistor is connected to the fifth node, and the drain of the fourth NMOS transistor is connected to the gate of the seventh NMOS transistor. The source of the fifth NMOS transistor is connected to the fifth node, the gate of the fifth NMOS transistor is connected to the sixth node, and the drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor. The source of the sixth NMOS transistor is connected to the sixth node, and the drain of the sixth NMOS transistor is connected to the seventh node. The source of the seventh NMOS transistor is connected to the fourth node, and the drain of the seventh NMOS transistor is connected to the eighth node.

2. The comparator based on the pre-amplification stage structure according to claim 1, characterized in that, The comparator based on the pre-amplification stage structure further includes a pre-amplification stage, which is connected in series between the first pre-amplification stage and the second pre-amplification stage.

3. The comparator based on the pre-amplification stage structure according to claim 1, characterized in that, The comparator based on the pre-amplification stage structure further includes N pre-amplification stages, where N is an integer greater than or equal to 2. The N pre-amplification stages are cascaded and connected in series between the first pre-amplification stage and the second pre-amplification stage.

4. The comparator based on the pre-amplification stage structure according to claim 3, characterized in that, The structures of the N pre-amplification stages are the same as those of the second pre-amplification stage.

5. The comparator based on the pre-amplification stage structure according to claim 1, characterized in that, The pre-amplification stage main unit includes: The eighth NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor; The source of the eighth NMOS transistor is grounded, and the drain of the eighth NMOS transistor is connected to the fifth node; The second control signal is connected to the gate of the eighth NMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor, respectively, and the operating voltage is connected to the source of the third PMOS transistor, the source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor, respectively. The drain of the third PMOS transistor is connected to the eighth node, the drain of the fourth PMOS transistor is connected to the seventh node, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor. The first differential output signal is connected to the fourth node and the sixth node respectively, and the second differential output signal is output through the seventh node and the eighth node.

6. The comparator based on the pre-amplification stage structure according to claim 5, characterized in that, The latch includes a sampling unit and a holding unit; The input terminal of the sampling unit is connected to the sixth node and the eighth node respectively, and the sampling unit samples the second differential output signal; The output of the sampling unit is connected to the holding unit, and the holding unit holds the second differential output signal.

7. The comparator based on the pre-amplification stage structure according to claim 5, characterized in that, The first control signal and the second control signal are the same control signal.

8. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes a comparator based on a pre-amplification stage structure as described in any one of claims 1-7.

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