Chip reset circuit, chip and electronic device

Abstract

The present invention discloses a chip reset circuit, a chip and an electronic device, wherein the chip reset circuit comprises: a first detection unit, which is used to output a first trigger signal when detecting at least one reset signal triggering inside the chip; a first logic circuit; a second logic circuit; and a second detection unit, wherein when multiple chips are cascaded, the first logic circuit is used to output a first trigger signal when receiving a first trigger signal of a chip at the same level; the second logic circuit is used to output a second trigger signal when receiving a first trigger signal output by other chips; and the second detection unit is used to reset the chip at the same level when receiving at least one of the first trigger signal and the second trigger signal. The present invention can realize simultaneous reset of all cascaded chips when any chip in multiple cascaded chips triggers reset, can effectively prevent problems such as system freezing due to untimely synchronization of abnormal events, and has flexible applications.

Description

Technical Field

[0001] The present invention relates to the technical field of chip reset, and in particular to a chip reset circuit, a chip and an electronic device. Background Art

[0002] The reset function is to restore the chip to its initial configuration and state after the chip is powered on or encounters an abnormal working state, so that the chip can start working from the initial state.

[0003] For large-sized integrated touch display screens such as tablet computers, since the number of pixels on their screens is far greater than that of mobile phone screens, and since the design of existing mobile phone driver chips is relatively mature, multiple mobile phone driver chips such as TDDI (Touch and Display Driver Integration) chips can be cascaded to drive the tablet computer's display screen, thereby avoiding the complex work and time consumption caused by redesign.

[0004] The touch control circuit in the touch chip of the mobile phone usually has multiple reset sources, including power-on reset, external IO reset, software reset, internal ESD reset, watchdog reset, abnormal power-off reset, etc. When multiple chips are cascaded, it is generally necessary to reset multiple cascaded chips at the same time to ensure the stability of the cascaded drive of multiple chips. Therefore, it is necessary that the reset source triggered inside any chip in the multiple cascaded chips can reset the multiple cascaded chips at the same time to restart the entire system.

[0005] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a chip reset circuit, a chip and an electronic device, which can realize the simultaneous reset of all cascade chips when any chip among multiple cascade chips triggers reset, thereby triggering a rapid reset of the system, which can effectively prevent problems such as system freezing due to untimely synchronization of abnormal events, and can flexibly adapt to the application of various cascade chips.

[0007] According to a first aspect of the present disclosure, a chip reset circuit is provided, comprising: a first detection unit, configured to output a first trigger signal when detecting that at least one reset signal inside the chip is triggered;

[0008] A first logic circuit, comprising a first input terminal and an output terminal, wherein the first input terminal of the first logic circuit is connected to the output terminal of the first detection unit;

[0009] A second logic circuit includes a first input terminal and an output terminal;

[0010] A second detection unit includes a first input terminal and a second input terminal, wherein the first input terminal of the second detection unit is connected to the output terminal of the first detection unit, and the second input terminal of the second detection unit is connected to the output terminal of the second logic circuit.

[0011] Wherein, when multiple chips are cascaded, the output end of the first logic circuit is connected to the first input end of the second logic circuit in other cascaded chips; and

[0012] The first logic circuit is used to output the first trigger signal upon receiving the first trigger signal of the chip at this level; the second logic circuit is used to output the second trigger signal upon receiving the first trigger signal output by other chips; the second detection unit is used to reset the chip at this level upon receiving at least one of the first trigger signal and the second trigger signal.

[0013] Optionally, the first logic circuit and the second logic circuit each include at least one of an AND logic circuit, an OR logic circuit and a NOT logic circuit.

[0014] Optionally, the chip reset circuit further includes:

[0015] A third detection unit, configured to output a third trigger signal when detecting at least one reset signal trigger from outside the chip; and

[0016] The second detection unit also includes a third input terminal, the third input terminal of the second detection unit is connected to the output terminal of the third detection unit, and the second detection unit is used to reset the chip at this level when receiving at least one of the first trigger signal, the second trigger signal and the third trigger signal.

[0017] Optionally, the first detection unit, the second detection unit and the third detection unit each include at least one of an AND logic circuit, an OR logic circuit and a NO logic circuit.

[0018] Optionally, the first logic circuit and the second logic circuit each further include a second input terminal for receiving a cascade enable signal, wherein the cascade enable signal is used to simultaneously control output states of the first logic circuit and the second logic circuit.

[0019] Optionally, the first logic circuit further includes a third input terminal for receiving an output enable signal, and the output enable signal is used to control an output state of the first logic circuit.

[0020] Optionally, the second logic circuit further includes a third input terminal for receiving an input enable signal, and the input enable signal is used to control an output state of the second logic circuit.

[0021] Optionally, the at least one reset signal inside the chip includes at least one of a power-on reset signal, a software reset signal, an ESD reset signal, a watchdog reset signal, and an abnormal power-off reset signal.

[0022] According to a second aspect of the present disclosure, a chip is provided, comprising:

[0023] The chip reset circuit as described above is used to implement the reset function of the internal circuit of the chip.

[0024] Optionally, the chip includes:

[0025] Cascade output pin, used to output the first trigger signal of the chip at this level;

[0026] Cascade input pin, used to receive the first trigger signal of other cascade chips.

[0027] Optionally, the chip includes:

[0028] At least one external reset pin is used to receive at least one reset signal from outside the chip.

[0029] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a display panel; and a plurality of cascaded chips as described above, for providing driving and / or touch signals to the display panel.

[0030] Optionally, the display panel includes: a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel or an electrowetting display panel.

[0031] The beneficial effects of the present invention include at least:

[0032] In the chip reset circuit of the embodiment of the present invention, the first logic circuit can output a trigger signal representing the reset signal of a chip when a chip triggers an internal reset, the second logic circuit can enable a chip to receive a reset signal output by other chips, and the second detection unit determines whether the chip needs to be reset by detecting the reset signal from the chip and the reset signal from other chips, thereby realizing simultaneous reset of all cascaded chips when any chip in multiple cascaded chips triggers a reset, and in this process, the number of logic circuits that the signal needs to pass through is small, which can realize rapid reset of the system, thereby effectively preventing problems such as system freezing due to untimely synchronization of abnormal events.

[0033] In a further preferred embodiment, a third detection unit is provided to detect a reset signal from outside the chip, thereby enhancing the reset function of the circuit.

[0034] In a further preferred embodiment, the output states of the first logic circuit and the second logic circuit can be simultaneously controlled by a cascade enable signal, so that the chip can be freely switched between cascade application scenarios and non-cascade application scenarios, thereby improving the flexibility of chip application.

[0035] In a further preferred embodiment, the output state of the first logic circuit and / or the second logic circuit can be controlled by an output enable signal and an input enable signal, so that the chip can freely switch between cascade application scenarios and non-cascade application scenarios, as well as bidirectional reset control and unidirectional reset control, further improving the flexibility of chip application.

[0036] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention is shown;

[0038] Figure 2 A schematic diagram showing the structure of a chip reset circuit inside a chip in a chip cascade application provided in an embodiment of the present invention is shown;

[0039] Figure 3 A schematic diagram of chip pins provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0041] Figure 1 FIG. 2 shows a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention. Figure 1 As shown, the electronic device includes a display panel 100 and a plurality of chips 200. The plurality of chips 200 are cascade-connected and perform data processing and signal transmission with the display panel 100 in a parallel working manner.

[0042] For example, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving. When the display panel 100 in the electronic device is touch-operable, the multiple chips 200 are used to provide driving and / or touch signals to the display panel 100.

[0043] Optionally, the display panel 100 includes: a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel or an electrowetting display panel.

[0044] Figure 2 A schematic diagram showing the structure of a chip reset circuit inside a chip in a chip cascade application provided according to an embodiment of the present invention is shown.

[0045] like Figure 2 As shown, the chip reset circuit includes: a first detection unit 210 , a first logic circuit 220 , a second logic circuit 230 and a second detection unit 240 .

[0046] The first detection unit 210 is used to output a first trigger signal Rst31 when detecting that at least one reset signal (such as Rst11, Rst12, ..., Rst1n) inside the chip is triggered. Optionally, the at least one reset signal inside the chip includes but is not limited to at least one of a power-on reset signal, a software reset signal, an ESD reset signal, a watchdog reset signal, and an abnormal power-off reset signal.

[0047] Optionally, the first detection unit 210 includes at least one of an AND logic circuit, an OR logic circuit, and a non-logic circuit. For example, when the reset signals inside the chip are all low-level resets, the first detection unit 210 can select an AND logic circuit with multiple input terminals, or a combination logic circuit composed of an OR logic circuit and a non-logic circuit; when the reset signals inside the chip are all high-level resets, the first detection unit 210 can select an OR logic circuit with multiple input terminals, or a combination logic circuit composed of an AND logic circuit and a non-logic circuit; when a part of the reset signal inside the chip is a low-level reset and the other part is a high-level reset, the first detection unit 210 can select an AND logic circuit with multiple input terminals to directly receive a reset signal of a low-level reset and a reset signal of a high-level reset through a non-logic circuit, or select an OR logic circuit with multiple input terminals to directly receive a reset signal of a high-level reset and a reset signal of a low-level reset through a non-logic circuit. Of course, other reasonable logic circuit combinations can also be selected according to actual conditions, as long as the detection of any reset signal trigger can be realized.

[0048] The first logic circuit 220 and the second logic circuit 230 both include a first input terminal and an output terminal, and the second detection unit 240 includes a first input terminal and a second input terminal. The first input terminal of the first logic circuit 220 is connected to the output terminal of the first detection unit 210 in the same chip, the output terminal of the second logic circuit 230 is connected to the second input terminal of the second detection unit 240 in the same chip, the first input terminal of the second detection unit 240 is connected to the output terminal of the first detection unit 210 in the same chip, and the output terminal of the second detection unit 240 is connected to the reset terminal RST of the chip internal circuit 260. In this embodiment, the internal circuit 260 is a general term for all circuits / modules / units / devices in the chip that need to be reset.

[0049] When multiple chips 200 are cascaded, the output end of the first logic circuit 220 in each chip is connected to the first input end of the second logic circuit 230 in other cascaded chips. At this time, the first logic circuit 220 is used to output the first trigger signal Rst31 at its output end when receiving the first trigger signal Rst31 of the chip at this level. The second logic circuit 230 is used to output the second trigger signal Rst32 when receiving the first trigger signal Rst31 output by other chips. The second detection unit 240 is used to reset the chip at this level when receiving at least one of the first trigger signal Rst31 and the second trigger signal Rst32.

[0050] Optionally, the second detection unit 240 includes at least one of an AND logic circuit, an OR logic circuit, and a non-logic circuit. For example, when the reset signals inside the chip are all low-level resets, the second detection unit 240 can use an AND logic circuit with multiple input terminals, or a combination logic circuit composed of an OR logic circuit and a non-logic circuit; when the reset signals inside the chip are all high-level resets, the first detection unit 240 can use an OR logic circuit with multiple input terminals, or a combination logic circuit composed of an AND logic circuit and a non-logic circuit. Of course, other reasonable logic circuit combinations can also be selected according to actual conditions, as long as the internal circuit 260 of the chip can be reset when any reset signal is triggered.

[0051] The present invention is attached Figure 2 The structure of the chip reset circuit is illustrated in the example of each reset signal being a low-level reset. It can be understood that based on the connection structure of the first logic circuit 220, the second logic circuit 230 and the second detection unit 240 shown in the present invention, all cascaded chips can be reset simultaneously when any chip in the multiple cascaded chips triggers a reset, and the number of logic circuits that the signal needs to pass through in this process is small, which can achieve a fast reset of the system, and can effectively prevent problems such as system freezing due to untimely synchronization of abnormal events.

[0052] Furthermore, the first logic circuit 220 and the second logic circuit 230 each include a second input terminal for receiving a cascade enable signal CAS, and the cascade enable signal CAS is used to simultaneously control the output states of the first logic circuit 220 and the second logic circuit 230 .

[0053] When the chip 200 needs to be used in cascade, the cascade enable signal CAS can be set to be in an effective level state (the same as the effective reset state of the reset signal), so that the level signal output by the output end of the first logic circuit 220 and the second logic circuit 230 can follow the level state of the signal received by its first input end, so as to realize the effective transmission of the trigger signal representing the reset signal, that is, when the reset of the chip is triggered, the level signal output by the output end of the first logic circuit 220 and the second logic circuit 230 can trigger the second detection unit 240 in each cascade chip to reset the internal circuit 260. When the chip 200 does not need to be used in cascade, the cascade enable signal CAS can be set to be in an invalid level state (opposite to the effective reset state of the reset signal), so that the level signal output by the output end of the first logic circuit 220 and the second logic circuit 230 is fixed at the level state opposite to the effective reset state of the reset signal, that is, when the reset of the chip is triggered, the level signal output by the output end of the first logic circuit 220 and the second logic circuit 230 will not trigger the second detection unit 240 to reset the internal circuit 260. In this way, the chip can switch freely between cascade application scenarios and non-cascade application scenarios, thereby improving the flexibility of chip application.

[0054] Furthermore, the first logic circuit 220 further includes a third input terminal for receiving an output enable signal orst, and the output enable signal orst is used to control the output state of the first logic circuit 220. And the second logic circuit 230 further includes a third input terminal for receiving an input enable signal irst, and the input enable signal irst is used to control the output state of the second logic circuit 230.

[0055] When the chip 200 needs to be used in cascade, the output enable signal orst and the input enable signal irst can be set to be in a valid level state (the same as the valid reset state of the reset signal, and directly transmitted to the third input terminal of the corresponding OR logic circuit; or opposite to the valid reset state of the reset signal, transmitted to the third input terminal of the corresponding OR logic circuit after passing through a non-logic circuit), so that the level signals output by the output terminals of the first logic circuit 220 and the second logic circuit 230 can both follow the level state of the signals received by their respective first input terminals, thereby realizing effective transmission of the trigger signal, that is, the first logic circuit 220 in a certain chip can transmit the reset signal of the chip at this level to other cascaded chips, and at the same time, the second logic circuit 230 can also receive the reset signal output by other cascaded chips, thereby realizing bidirectional reset control of the cascaded chips. It is also possible to set only one of the output enable signal orst and the input enable signal irst to be in a valid level state, so that the first logic circuit 220 in a certain chip can transmit the reset signal of the chip at this level to other cascaded chips and the second logic circuit 230 cannot receive the reset signal output by other cascaded chips, or the first logic circuit 220 cannot transmit the reset signal of the chip at this level to other cascaded chips and the second logic circuit 230 can receive the reset signal output by other cascaded chips, thereby realizing the unidirectional reset control of the cascaded chips. Of course, it is also possible to set both the output enable signal orst and the input enable signal irst to be in an invalid level state, at which time the same function as when the cascade enable signal CAS is in an invalid level state can be realized. In this way, the chip can be freely switched between cascaded application scenarios and non-cascaded application scenarios, as well as bidirectional reset control and unidirectional reset control, further improving the flexibility of chip application.

[0056] Optionally, the cascade enable signal CAS, the output enable signal orst, and the input enable signal irst may all be provided by a control register inside the chip, but in some embodiments, they may also be provided by other devices outside the chip.

[0057] Optionally, the first logic circuit 220 and the second logic circuit 230 each include at least one of an AND logic circuit, an OR logic circuit, and a NON-logic circuit. For example, when the reset signals inside the chip are all low-level resets, such as Figure 2As shown, the first logic circuit 220 and the second logic circuit 230 can be selected as an OR logic circuit, or a combination logic circuit consisting of an AND logic circuit and a non-logic circuit; when the reset signals inside the chip are all high-level resets, the first logic circuit 220 and the second logic circuit 230 can be selected as an AND logic circuit, or a combination logic circuit consisting of an AND logic circuit and an OR logic circuit. Of course, other reasonable logic circuit combinations can also be selected according to actual conditions, as long as the chip at this level can be controlled to output the corresponding trigger signal only when the input signals of the first logic circuit 220 or the second logic circuit 230 are at the same potential as the reset signal.

[0058] Furthermore, the chip reset circuit also includes: a third detection unit 250. The third detection unit 250 is used to output a third trigger signal Rst33 when it detects that at least one reset signal (such as Rst21, Rst22) from outside the chip is triggered. At this time, the second detection unit 240 also includes a third input terminal, and the third input terminal of the second detection unit 240 is connected to the output terminal of the third detection unit 250, and is used to reset the chip at this level when at least one of the first trigger signal Rst31, the second trigger signal Rst32 and the third trigger signal Rst33 is received.

[0059] It can be understood that the present invention helps to enhance the diversity of the reset function of the chip reset circuit by providing the third detection unit to detect the reset signal from outside the chip.

[0060] Similar to the first detection unit 210, optionally, the third detection unit 250 includes at least one of an AND logic circuit, an OR logic circuit, and a non-logic circuit. For example, when the reset signals outside the chip are all low-level resets, the third detection unit 250 can select an AND logic circuit with multiple input terminals, or a combination logic circuit composed of an OR logic circuit and a non-logic circuit; when the reset signals outside the chip are all high-level resets, the third detection unit 250 can select an OR logic circuit with multiple input terminals, or a combination logic circuit composed of an AND logic circuit and a non-logic circuit; when a part of the reset signal outside the chip is a low-level reset and the other part is a high-level reset, the third detection unit 250 can select an AND logic circuit with multiple input terminals to directly receive a reset signal of a low-level reset and a reset signal of a high-level reset through a non-logic circuit, or select an OR logic circuit with multiple input terminals to directly receive a reset signal of a high-level reset and a reset signal of a low-level reset through a non-logic circuit. Of course, other reasonable logic circuit combinations can also be selected according to actual conditions, as long as the detection of any reset signal trigger can be realized.

[0061] The present invention sets a chip reset circuit composed of two OR logic circuits and corresponding detection units inside the chip, which not only enables the chip to achieve common reset of all cascaded chips by the reset source triggered inside any chip when cascaded, thereby ensuring the stability and safety of the cascaded chips as a whole and the controlled devices, but also the two OR logic circuits can add single-bidirectional reset control and cascade-non-cascade reset control switching functions to the chip reset circuit without adding other logic circuits, thereby improving the application flexibility of the chip, simplifying the circuit structure, requiring a small number of logic circuits, and reducing signal transmission delay.

[0062] It should be noted that the chip reset circuit provided in the embodiment of the present invention is not limited to being set only in Figure 1 The chip 200 of the electronic device shown in FIG. 2 can actually be integrated into any chip with a reset function to realize the reset function of the internal circuit of the chip. The present invention is not limited to this.

[0063] Further, for the chip (IC) 200 provided with a chip reset circuit provided in the embodiment of the present invention, the chip pin diagram is as follows: Figure 3 As shown, it includes: a cascade output pin 1, a cascade input pin 2 and at least one external reset pin 3. Among them, the cascade output pin 1 is used to output the first trigger signal Rst31 of the chip at this level; the cascade input pin 2 is used to receive the first trigger signal Rst31 output by other cascade chips; and the at least one external reset pin 3 is used to receive at least one reset signal Rst21 from outside the chip. The chip 200 can realize simultaneous reset of all cascade chips in cascade applications, and at the same time, the function is more powerful and the application is more flexible.

[0064] In summary, in the chip reset circuit of the embodiment of the present invention, the first logic circuit can output a trigger signal to represent the reset signal of a chip when a chip triggers an internal reset, the second logic circuit can enable a chip to receive a reset signal output by other chips, and the second detection unit determines whether the chip needs to be reset by detecting the reset signal from the chip and the reset signal from other chips, thereby realizing simultaneous reset of all cascaded chips when any chip in multiple cascaded chips triggers a reset, and in this process, the number of logic circuits that the signal needs to pass through is small, which can realize rapid reset of the system, thereby effectively preventing problems such as system freezing due to untimely synchronization of abnormal events.

[0065] In a further preferred embodiment, a third detection unit is provided to detect a reset signal from outside the chip, thereby enhancing the reset function of the circuit.

[0066] In a further preferred embodiment, the output states of the first logic circuit and the second logic circuit can be simultaneously controlled by a cascade enable signal, so that the chip can be freely switched between cascade application scenarios and non-cascade application scenarios, thereby improving the flexibility of chip application.

[0067] In a further preferred embodiment, the output state of the first logic circuit and / or the second logic circuit can be controlled by an output enable signal and an input enable signal, so that the chip can freely switch between cascade application scenarios and non-cascade application scenarios, as well as bidirectional reset control and unidirectional reset control, further improving the flexibility of chip application.

[0068] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A chip reset circuit, wherein: include: A first detection unit, configured to output a first trigger signal when detecting that at least one reset signal inside the chip is triggered; A first logic circuit, comprising a first input terminal and an output terminal, wherein the first input terminal of the first logic circuit is connected to the output terminal of the first detection unit; A second logic circuit includes a first input terminal and an output terminal; A second detection unit includes a first input terminal and a second input terminal, wherein the first input terminal of the second detection unit is connected to the output terminal of the first detection unit, and the second input terminal of the second detection unit is connected to the output terminal of the second logic circuit. Wherein, the first logic circuit and the second logic circuit each further include a second input terminal for receiving a cascade enable signal, and the cascade enable signal is used to simultaneously control the output states of the first logic circuit and the second logic circuit; When multiple chips are cascaded, the output end of the first logic circuit is connected to the first input end of the second logic circuit in other cascaded chips; and The first logic circuit is used to output the first trigger signal upon receiving the first trigger signal of the chip at this level; the second logic circuit is used to output the second trigger signal upon receiving the first trigger signal output by other chips; the second detection unit is used to reset the chip at this level upon receiving at least one of the first trigger signal and the second trigger signal.

2. The chip reset circuit according to claim 1, wherein: The first logic circuit further includes a third input terminal for receiving an output enable signal, where the output enable signal is used to control an output state of the first logic circuit.

3. The chip reset circuit according to claim 1, wherein: The second logic circuit further includes a third input terminal for receiving an input enable signal, where the input enable signal is used to control an output state of the second logic circuit.

4. The chip reset circuit according to any one of claims 1 to 3, wherein: The first logic circuit and the second logic circuit each include at least one of an AND logic circuit, an OR logic circuit, and a NOT logic circuit.

5. The chip reset circuit according to claim 1, wherein: The chip reset circuit also includes: A third detection unit, configured to output a third trigger signal when detecting at least one reset signal trigger from outside the chip; and The second detection unit also includes a third input terminal, and the third input terminal of the second detection unit is connected to the output terminal of the third detection unit. The second detection unit is used to reset the chip at this level when receiving at least one of the first trigger signal, the second trigger signal and the third trigger signal.

6. The chip reset circuit according to claim 5, wherein: The first detection unit, the second detection unit, and the third detection unit each include at least one of an AND logic circuit, an OR logic circuit, and a NOT logic circuit.

7. The chip reset circuit according to claim 1, wherein: The at least one reset signal inside the chip includes at least one of a power-on reset signal, a software reset signal, an ESD reset signal, a watchdog reset signal, and an abnormal power-off reset signal.

8. A chip, wherein: include: The chip reset circuit as described in any one of claims 1-7, wherein the chip reset circuit is used to implement a reset function of an internal circuit of the chip.

9. The chip according to claim 8, wherein: The chip comprises: Cascade output pin, used to output the first trigger signal of the chip at this level; Cascade input pin, used to receive the first trigger signal of other cascade chips.

10. The chip according to claim 9, wherein: The chip comprises: At least one external reset pin is used to receive at least one reset signal from outside the chip.

11. An electronic device, wherein: include: Display panel; as well as A plurality of cascaded chips as claimed in any one of claims 8 to 10 are used to provide driving and / or touch signals to the display panel.

12. The electronic device according to claim 11, wherein: The display panel includes: a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel or an electrowetting display panel.

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