474results about How to "Simple circuit design" patented technology

A wireless communications system optimizes performance by dividing communications functionality between a wireless pacemaker and a wireless monitoring base station according to the design constraints imposed by the system elements. Typical design constraints include high frequency operation, low pacemaker power consumption, reasonable range, high data rate, minimal RF radiation of internal circuitry, small pacemaker antenna system, simple pacemaker RF circuit design, high reliability, low pacemaker cost, and use of existing pacemaker construction methodologies.

System and method for regulating a power converter. The system includes a first signal generator configured to receive a first sensed signal and generate an output signal associated with demagnetization. The first sensed signal is related to a first winding coupled to a secondary winding for a power converter, and the secondary winding is associated with at least an output current for the power converter. Additionally, the system includes a ramping signal generator configured to receive the output signal and generate a ramping signal, and a first comparator configured to receive the ramping signal and a first threshold signal and generate a first comparison signal based on at least information associated with the ramping signal and the first threshold signal. Moreover, the system includes a second comparator configured to receive a second sensed signal and a second threshold signal and generate a second comparison signal.

Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and / or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.

An apparatus and method for video data processing in digital video decoding, such as digital video disk (DVD) decoding, which produces new video data according to main picture data, sub-picture unit (SPU) data, and an aspect ratio. The apparatus includes a sub-picture-unit-decoding and color-determining device, a mixer, a buffer, and an interpolator. The sub-picture-unit-decoding and color-determining device is used for performing sub-picture decoding and color determination on the SPU data, and producing decoded SPU data. The mixer, coupled to the SPU-decoding and color-determining device, is employed to mix the main picture data and the decoded SPU data, and outputting combined video data. The buffer, coupled to the mixer, for storing the combined video data outputted from the mixer. The interpolator is used to receive the combined video data from the mixer and to read previously combined video data from the buffer, and to generate the new video data by performing an interpolation operation according to the aspect ratio, the combined video data, and the previously combined video data.

A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

A group of novel power conversion concept is developed with this invention for LED and OLED drive applications. The concept utilizes a single power conversion stage to fulfill multiple functions, including Power Factor Correction, DC voltage to DC current conversion, or DC voltage to DC voltage conversion etc. that are necessary for driving LED devices from an AC power input. Multiple dimming control schemes have also been developed to facilitate wide range of application requirements and enable the system to work with different input power format including AC mains power and variable AC voltage from the existing AC dimmer installations.

A synchronous rectification circuit for a power converter includes a power switch coupled to a transformer and an output capacitor and a switching control circuit configured to provide a control signal to the power switch in response to a first state and a second state of the voltage across the power switch. In the switching control circuit, the second state is determined prior to the first state is determined. In an embodiment, the switching control circuit includes a voltage comparing unit configured to act in response to the first and second inputs. The voltage comparing unit is also configured to output a logic signal according to the voltage difference between the sensed voltage drop across the power switch and a reference threshold voltage. A logic processing circuit is coupled to the voltage comparing unit and configured to provide the first state and the second state of the voltage across the power switch.

A power supply apparatus has a battery and a temperature detection circuit. The battery has n battery cells, and the temperature detection circuit has m temperature detection units. Each temperature detection units has a temperature sensor that is thermally coupled to one or more of the battery cells and whose electrical resistance decreases as the temperature of the battery cell or battery cells to which it is thermally coupled increases, a serial resistor that is connected in series with the temperature sensor, and a first diode whose cathode is connected to the node between the temperature sensor and the serial resistor. The serial circuit formed by the temperature sensor and the serial resistor receives a predetermined voltage such that, as the electrical resistance of the temperature sensor decreases, the voltage at the node decreases. The first diodes have anodes thereof connected together.

Switching-mode power conversion system and method thereof. The system includes a primary winding configured to receive an input voltage, an a secondary winding coupled to the primary winding and configured to, with one or more first components, generate, at an output terminal, an output voltage and an output current. Additionally, the system includes an auxiliary winding coupled to the secondary winding and configured to, with one or more second components, generate, at a first terminal, a detected voltage. Moreover, the system includes an error amplifier configured to receive the detected voltage and a first reference voltage and generate an amplified voltage based on at least information associated with a difference between the detected voltage and the first reference voltage. Also, the system includes a compensation component configured to receive the amplified voltage and generate a second reference voltage based on at least information associated with the amplified voltage.

A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.

A hot-plug control system and method is applied to a computer device, wherein the computer device is provided with a PCI-E (Peripheral Component Interconnect Express) bus, at least one PCI-E slot having a power switch and an indicator light, a power control unit and a driver. The hot-plug control system at least includes a signal control module for generating an interrupt signal; a detection module for detecting the status of the PCI-E slot and the power switch corresponding to the PCI-E slot in response to the interrupt signal; a control module for allowing power to be provided to the PCI-E slot and the indicator light corresponding to the PCI-E slot to be illuminated when the detection module detects that a new expansion card has been inserted in the PCI-E slot and the corresponding power switch has been actuated; and a drive module for loading the driver to drive the inserted expansion card. According to the present invention, the PCI-E hot-plug function could be achieved in different kinds of computer devices.

Switching-mode power conversion system and method thereof. The system includes a primary winding configured to receive an input voltage, and a secondary winding coupled to the primary winding and configured to, with one or more first components, generate, at an output terminal, an output voltage and an output current. Additionally, the system includes an auxiliary winding coupled to the secondary winding and configured to, with one or more second components, generate, at a first terminal, a detected voltage. Moreover, the system includes an error amplifier configured to receive the detected voltage and a first reference voltage and generate an amplified voltage based on at least information associated with a difference between the detected voltage and the first reference voltage. Also, the system includes a compensation component configured to receive the amplified voltage and generate a second reference voltage based on at least information associated with the amplified voltage.

A switching regulator circuit with improved slope compensation for providing a regulated voltage to a load. The regulator circuit includes a power source and a switch circuit configured to control the coupling of the power source to the load. The operation of the switch circuit is controlled by a control signal generated by a control circuit. A feedback circuit is provided for generating a feedback signal indicative of the regulated voltage provided by the switching regulator circuit to the load. A circuit is provided to generate a sensed signal indicative of the current supplied by the power source. The regulator circuit further includes a timing signal generator for generating a timing signal, a ramp signal generator for generating a ramp signal, and a current source controlled by the ramp signal for generating a compensation signal indicative of the ramp signal. The control circuit generates the control signal based on the compensation signal, the timing signal, the sensed signal and the feedback signal.

A self-calibration circuit for capacitance mismatch is provided. The circuit comprises a sample-and-hold (S / H) circuit, a comparator, and a switch control circuit. The S / H circuit comprises a compensation capacitor array, a target capacitor, and a reference capacitor. The S / H circuit provides an output voltage, wherein the output voltage is an operation result based on the capacitance of the target capacitor and the reference capacitor, and the equivalent capacitance of the compensation capacitor array. The comparator provides a comparison signal according to whether the output voltage of the S / H circuit is positive or negative. The switch control circuit controls the equivalent capacitance of the array according to the comparison signal such that the result of the target capacitance added to the equivalent capacitance of the array gradually approximates the reference capacitance with each cycle of a clock signal.

A battery delivers its rated capacity when the battery is below a temperature when the available battery capacity is limited. The battery includes a heating element, a temperature sensor, and a switch operatively connected to the heating element and temperature sensor and responsive to the temperature sensor for switching on the heating element and raising the temperature of the battery to allow the battery to deliver its rated capacity when a sensed temperature of the battery is below a temperature where available battery capacity is limited.

The invention discloses a method for correcting a blood pressure detection signal. The method comprises the steps of determining posture information and movement state information of a user according to data outputted by a three-axis accelerometer; correcting the pressure wave data outputted by a pressure sensor according to the posture information and the movement state information. According to the method, the pressure wave data measured by the pressure sensor are corrected according to the movement condition, thus the interference of the movement of the user to the blood pressure detection can be avoided, and as a result, the blood pressure detection signal can be accurate. The invention further discloses a blood pressure detection device.

A battery delivers its rated capacity when the battery is below a temperature when the available battery capacity is limited. The battery includes a heating element, a temperature sensor, and a switch operatively connected to the heating element and temperature sensor and responsive to the temperature sensor for switching on the heating element and raising the temperature of the battery to allow the battery to deliver its rated capacity when a sensed temperature of the battery is below a temperature where available battery capacity is limited.

The invention, an improved device and method for the pointer system of a digitizer tablet, is to repetitiously emit signals sequentially from a specific set of inductive loop when the position pointed by the wireless pointer device is located within a range formed by this specific set of inductive loop induced most intensively during a locally scanning process. After a transient energy storage of the wireless pointer device, corresponding resonant signals are emitted out and are received sequentially by several sets of inductive loop located on the digitizer tablet in the neighborhood of this specific set of inductive loop and, by these signals, the wireless pointer device's coordinate position on the digitizer tablet is calculated out relatively. Thereby, the intensities of the resonant signals received by these several sets of inductive loop will be displayed as a linear distribution, such that the calculation formula for coordinate position and the design for relative circuit elements may be simplified greatly, and the production cost and the power consumption may further be lowered down effectively.

The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send / receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send / receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send / receive the signal complied wit the PCIE interface specification.

An input-side protective circuit for protecting an intermediate circuit of an inverter against overvoltages, wherein the input-side protective circuit includes an upstream element for limiting the voltage of the intermediate circuit connected upstream of the intermediate circuit and which is bridgeable by a mechanical switching device that is controllable such that it opens in a feed-in operation of the inverter when an intermediate circuit voltage is greater than a specified voltage limit. The protective circuit also includes an electronic voltage limiter connected downstream of the upstream element and connected in parallel to the intermediate circuit.

A switching regulator circuit with improved slope compensation for providing a regulated voltage to a load. The regulator circuit includes a power source and a switch circuit configured to control the coupling of the power source to the load. The operation of the switch circuit is controlled by a control signal generated by a control circuit. A feedback circuit is provided for generating a feedback signal indicative of the regulated voltage provided by the switching regulator circuit to the load. A circuit is provided to generate a sensed signal indicative of the current supplied by the power source. The regulator circuit further includes a timing signal generator for generating a timing signal, a ramp signal generator for generating a ramp signal, and a current source controlled by the ramp signal for generating a compensation signal indicative of the ramp signal. The control circuit generates the control signal based on the compensation signal, the timing signal, the sensed signal and the feedback signal.

An LED driver and a display device using the same are disclosed. The LED driver is adapted for driving a first set of LEDs and a second set of LEDs. The LED driver includes an inductor, a main switch, a first switch, a second switch, and a controller. The inductor has a first terminal receiving an input voltage. The main switch is coupled between a second terminal of the inductor and a common level for adjusting a current flowing therethrough. The first switch is coupled between the first set of LEDs and the second terminal of the inductor. The second switch is coupled between the second LEDs and the second terminal of the inductor. The controller is coupled to controlling terminals of the main switch, the first switch, and the second switch respectively for controlling conducting statuses of the main switch, the first switch, and the second switch respectively.

The invention discloses a method for outputting the standard frequency of a coherent population beat-frequency atomic clock. The method drives a semiconductor laser through a driving current signal, and the driving current signal is modulated by a microwave signal which is produced by a crystal oscillator and locked in the crystal oscillator, so as to produce two pumping lasers of which the frequency difference equals to the frequency of the microwave signal, and act with the atoms with Lambada three-level system so as to produce a relaxation oscillating signal of which the center frequency equals to the beat frequency of the microwave signal and the hyperfine energy level; then the relaxation oscillating signal is photo-electrically converted and FFT-transformed with DSP chips so as to get an oscillating center frequency; finally, the oscillating center frequency is taken as the control signal of an FPGA to change the frequency-controlled word of the DDS chips and get the standard frequency output. The method simplifies the circuit design of an atomic clock system, improves the stability and reliability of the atomic clock, and benefits the digitalization and miniaturization of the atomic clock.